QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.c

   1 /** @file
   2 Lib function for Pei Quark South Cluster.
   3
   4 Copyright (c) 2013-2016 Intel Corporation.
   5
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9 #include "CommonHeader.h"
  10
  11 /**
  12   Program SVID/SID the same as VID/DID*
  13 **/
  14 EFI_STATUS
  15 EFIAPI
  16 InitializeIohSsvidSsid (
  17    IN UINT8   Bus,
  18    IN UINT8   Device,
  19    IN UINT8   Func
  20    )
  21 {
  22   UINTN       Index;
  23
  24   for (Index = 0; Index <= IOH_PCI_IOSF2AHB_0_MAX_FUNCS; Index++) {
  25     if (((Device == IOH_PCI_IOSF2AHB_1_DEV_NUM) && (Index >= IOH_PCI_IOSF2AHB_1_MAX_FUNCS))) {
  26       continue;
  27     }
  28
  29     IohMmPci32(0, Bus, Device, Index, PCI_REG_SVID0) = IohMmPci32(0, Bus, Device, Index, PCI_REG_VID);
  30   }
  31
  32   return EFI_SUCCESS;
  33 }
  34
  35 /* Enable memory, io, and bus master for USB controller */
  36 VOID
  37 EFIAPI
  38 EnableUsbMemIoBusMaster (
  39   IN UINT8   UsbBusNumber
  40   )
  41 {
  42   UINT16 CmdReg;
  43
  44   CmdReg = PciRead16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_OHCI_DEVICE_NUMBER, IOH_OHCI_FUNCTION_NUMBER, PCI_REG_PCICMD));
  45   CmdReg = (UINT16) (CmdReg | EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_IO_SPACE | EFI_PCI_COMMAND_BUS_MASTER);
  46   PciWrite16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_OHCI_DEVICE_NUMBER, IOH_OHCI_FUNCTION_NUMBER, PCI_REG_PCICMD), CmdReg);
  47
  48   CmdReg = PciRead16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, PCI_REG_PCICMD));
  49   CmdReg = (UINT16) (CmdReg | EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_IO_SPACE | EFI_PCI_COMMAND_BUS_MASTER);
  50   PciWrite16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, PCI_REG_PCICMD), CmdReg);
  51 }
  52
  53 /**
  54   Read south cluster GPIO input from Port A.
  55
  56 **/
  57 UINT32
  58 EFIAPI
  59 ReadIohGpioValues (
  60   VOID
  61   )
  62 {
  63   UINT32  GipData;
  64   UINT32  GipAddr;
  65   UINT32  TempBarAddr;
  66   UINT16  SaveCmdReg;
  67   UINT32  SaveBarReg;
  68
  69   TempBarAddr = (UINT32) PcdGet64(PcdIohGpioMmioBase);
  70
  71   GipAddr = PCI_LIB_ADDRESS(
  72       PcdGet8 (PcdIohGpioBusNumber),
  73       PcdGet8 (PcdIohGpioDevNumber),
  74       PcdGet8 (PcdIohGpioFunctionNumber), 0);
  75
  76   //
  77   // Save current settings for PCI CMD/BAR registers.
  78   //
  79   SaveCmdReg = PciRead16 (GipAddr + PCI_COMMAND_OFFSET);
  80   SaveBarReg = PciRead32 (GipAddr + PcdGet8 (PcdIohGpioBarRegister));
  81
  82   DEBUG ((EFI_D_INFO, "SC GPIO temporary enable  at %08X\n", TempBarAddr));
  83
  84   // Use predefined temporary memory resource.
  85   PciWrite32 ( GipAddr + PcdGet8 (PcdIohGpioBarRegister), TempBarAddr);
  86   PciWrite8 ( GipAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
  87
  88   // Read GPIO configuration
  89   GipData = MmioRead32(TempBarAddr + GPIO_EXT_PORTA);
  90
  91   //
  92   // Restore settings for PCI CMD/BAR registers.
  93   //
  94   PciWrite32 ((GipAddr + PcdGet8 (PcdIohGpioBarRegister)), SaveBarReg);
  95   PciWrite16 (GipAddr + PCI_COMMAND_OFFSET, SaveCmdReg);
  96
  97   // Only 8 bits valid.
  98   return GipData & 0x000000FF;
  99 }