projects / mirror_edk2.git / blame
| Commit | Line | Data |
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| 9b6bbcdb MK |
1 | /** @file\r |
| 2 | This file contains the definination for host controller\r | |
| 3 | register operation routines.\r | |
| 4 | \r | |
| 5 | Copyright (c) 2013-2015 Intel Corporation.\r | |
| 6 | \r | |
| 7 | This program and the accompanying materials\r | |
| 8 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 9 | which accompanies this distribution. The full text of the license may be found at\r | |
| 10 | http://opensource.org/licenses/bsd-license.php\r | |
| 11 | \r | |
| 12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 14 | \r | |
| 15 | **/\r | |
| 16 | \r | |
| 17 | \r | |
| 18 | \r | |
| 19 | #ifndef _OHCI_REGS_H\r | |
| 20 | #define _OHCI_REGS_H\r | |
| 21 | \r | |
| 22 | #define HC_STATE_RESET 0x0\r | |
| 23 | #define HC_STATE_RESUME 0x1\r | |
| 24 | #define HC_STATE_OPERATIONAL 0x2\r | |
| 25 | #define HC_STATE_SUSPEND 0x3\r | |
| 26 | \r | |
| 27 | #define PERIODIC_ENABLE 0x01\r | |
| 28 | #define ISOCHRONOUS_ENABLE 0x02\r | |
| 29 | #define CONTROL_ENABLE 0x04\r | |
| 30 | #define BULK_ENABLE 0x08\r | |
| 31 | #define CONTROL_BULK_RATIO 0x10\r | |
| 32 | \r | |
| 33 | #define HC_FUNCTIONAL_STATE 0x20\r | |
| 34 | #define INTERRUPT_ROUTING 0x40\r | |
| 35 | \r | |
| 36 | #define HC_RESET 0x01\r | |
| 37 | #define CONTROL_LIST_FILLED 0x02\r | |
| 38 | #define BULK_LIST_FILLED 0x04\r | |
| 39 | #define CHANGE_OWNER_REQUEST 0x08\r | |
| 40 | \r | |
| 41 | #define SCHEDULE_OVERRUN_COUNT 0x10\r | |
| 42 | \r | |
| 43 | #define SCHEDULE_OVERRUN 0x00001\r | |
| 44 | #define WRITEBACK_DONE_HEAD 0x00002\r | |
| 45 | #define START_OF_FRAME 0x00004\r | |
| 46 | #define RESUME_DETECT 0x00008\r | |
| 47 | #define UNRECOVERABLE_ERROR 0x00010\r | |
| 48 | #define FRAME_NUMBER_OVERFLOW 0x00020\r | |
| 49 | #define ROOTHUB_STATUS_CHANGE 0x00040\r | |
| 50 | #define OWNERSHIP_CHANGE 0x00080\r | |
| 51 | \r | |
| 52 | #define MASTER_INTERRUPT 0x00400\r | |
| 53 | \r | |
| 54 | #define CONTROL_HEAD 0x001\r | |
| 55 | #define BULK_HEAD 0x002\r | |
| 56 | #define DONE_HEAD 0x004\r | |
| 57 | \r | |
| 58 | #define Hc_HCCA 0x001\r | |
| 59 | #define Hc_PERIODIC_CURRENT 0x002\r | |
| 60 | #define Hc_CONTOL_HEAD 0x004\r | |
| 61 | #define Hc_CONTROL_CURRENT_PTR 0x008\r | |
| 62 | #define Hc_BULK_HEAD 0x010\r | |
| 63 | #define Hc_BULK_CURRENT_PTR 0x020\r | |
| 64 | #define Hc_DONE_HEAD 0x040\r | |
| 65 | \r | |
| 66 | #define FRAME_INTERVAL 0x008\r | |
| 67 | #define FS_LARGEST_DATA_PACKET 0x010\r | |
| 68 | #define FRMINT_TOGGLE 0x020\r | |
| 69 | #define FRAME_REMAINING 0x040\r | |
| 70 | #define FRAME_REMAIN_TOGGLE 0x080\r | |
| 71 | \r | |
| 72 | #define RH_DESC_A 0x00001\r | |
| 73 | #define RH_DESC_B 0x00002\r | |
| 74 | #define RH_NUM_DS_PORTS 0x00004\r | |
| 75 | #define RH_NO_PSWITCH 0x00008\r | |
| 76 | #define RH_PSWITCH_MODE 0x00010\r | |
| 77 | #define RH_DEVICE_TYPE 0x00020\r | |
| 78 | #define RH_OC_PROT_MODE 0x00040\r | |
| 79 | #define RH_NOC_PROT 0x00080\r | |
| 80 | #define RH_POTPGT 0x00100\r | |
| 81 | #define RH_NO_POTPGT 0x00200\r | |
| 82 | #define RH_DEV_REMOVABLE 0x00400\r | |
| 83 | #define RH_PORT_PWR_CTRL_MASK 0x00800\r | |
| 84 | \r | |
| 85 | #define RH_LOCAL_PSTAT 0x00001\r | |
| 86 | #define RH_OC_ID 0x00002\r | |
| 87 | #define RH_REMOTE_WK_ENABLE 0x00004\r | |
| 88 | #define RH_LOCAL_PSTAT_CHANGE 0x00008\r | |
| 89 | #define RH_OC_ID_CHANGE 0x00010\r | |
| 90 | #define RH_CLR_RMT_WK_ENABLE 0x00020\r | |
| 91 | \r | |
| 92 | #define RH_CLEAR_PORT_ENABLE 0x0001\r | |
| 93 | #define RH_SET_PORT_ENABLE 0x0002\r | |
| 94 | #define RH_SET_PORT_SUSPEND 0x0004\r | |
| 95 | #define RH_CLEAR_SUSPEND_STATUS 0x0008\r | |
| 96 | #define RH_SET_PORT_RESET 0x0010\r | |
| 97 | #define RH_SET_PORT_POWER 0x0020\r | |
| 98 | #define RH_CLEAR_PORT_POWER 0x0040\r | |
| 99 | #define RH_CONNECT_STATUS_CHANGE 0x10000\r | |
| 100 | #define RH_PORT_ENABLE_STAT_CHANGE 0x20000\r | |
| 101 | #define RH_PORT_SUSPEND_STAT_CHANGE 0x40000\r | |
| 102 | #define RH_OC_INDICATOR_CHANGE 0x80000\r | |
| 103 | #define RH_PORT_RESET_STAT_CHANGE 0x100000\r | |
| 104 | \r | |
| 105 | #define RH_CURR_CONNECT_STAT 0x0001\r | |
| 106 | #define RH_PORT_ENABLE_STAT 0x0002\r | |
| 107 | #define RH_PORT_SUSPEND_STAT 0x0004\r | |
| 108 | #define RH_PORT_OC_INDICATOR 0x0008\r | |
| 109 | #define RH_PORT_RESET_STAT 0x0010\r | |
| 110 | #define RH_PORT_POWER_STAT 0x0020\r | |
| 111 | #define RH_LSDEVICE_ATTACHED 0x0040\r | |
| 112 | \r | |
| 113 | #define RESET_SYSTEM_BUS (1 << 0)\r | |
| 114 | #define RESET_HOST_CONTROLLER (1 << 1)\r | |
| 115 | #define RESET_CLOCK_GENERATION (1 << 2)\r | |
| 116 | #define RESET_SSE_GLOBAL (1 << 5)\r | |
| 117 | #define RESET_PSPL (1 << 6)\r | |
| 118 | #define RESET_PCPL (1 << 7)\r | |
| 119 | #define RESET_SSEP1 (1 << 9)\r | |
| 120 | #define RESET_SSEP2 (1 << 10)\r | |
| 121 | #define RESET_SSEP3 (1 << 11)\r | |
| 122 | \r | |
| 123 | #define ONE_SECOND 1000000\r | |
| 124 | #define ONE_MILLI_SEC 1000\r | |
| 125 | #define MAX_BYTES_PER_TD 0x1000\r | |
| 126 | #define MAX_RETRY_TIMES 100\r | |
| 127 | #define PORT_NUMBER_ON_MAINSTONE2 1\r | |
| 128 | \r | |
| 129 | \r | |
| 130 | //\r | |
| 131 | // Operational Register Offsets\r | |
| 132 | //\r | |
| 133 | \r | |
| 134 | //\r | |
| 135 | // Command & Status Registers Offsets\r | |
| 136 | //\r | |
| 137 | #define HC_REVISION 0x00\r | |
| 138 | #define HC_CONTROL 0x04\r | |
| 139 | #define HC_COMMAND_STATUS 0x08\r | |
| 140 | #define HC_INTERRUPT_STATUS 0x0C\r | |
| 141 | #define HC_INTERRUPT_ENABLE 0x10\r | |
| 142 | #define HC_INTERRUPT_DISABLE 0x14\r | |
| 143 | \r | |
| 144 | //\r | |
| 145 | // Memory Pointer Offsets\r | |
| 146 | //\r | |
| 147 | #define HC_HCCA 0x18\r | |
| 148 | #define HC_PERIODIC_CURRENT 0x1C\r | |
| 149 | #define HC_CONTROL_HEAD 0x20\r | |
| 150 | #define HC_CONTROL_CURRENT_PTR 0x24\r | |
| 151 | #define HC_BULK_HEAD 0x28\r | |
| 152 | #define HC_BULK_CURRENT_PTR 0x2C\r | |
| 153 | #define HC_DONE_HEAD 0x30\r | |
| 154 | \r | |
| 155 | //\r | |
| 156 | // Frame Register Offsets\r | |
| 157 | //\r | |
| 158 | #define HC_FRM_INTERVAL 0x34\r | |
| 159 | #define HC_FRM_REMAINING 0x38\r | |
| 160 | #define HC_FRM_NUMBER 0x3C\r | |
| 161 | #define HC_PERIODIC_START 0x40\r | |
| 162 | #define HC_LS_THREASHOLD 0x44\r | |
| 163 | \r | |
| 164 | //\r | |
| 165 | // Root Hub Register Offsets\r | |
| 166 | //\r | |
| 167 | #define HC_RH_DESC_A 0x48\r | |
| 168 | #define HC_RH_DESC_B 0x4C\r | |
| 169 | #define HC_RH_STATUS 0x50\r | |
| 170 | #define HC_RH_PORT_STATUS 0x54\r | |
| 171 | \r | |
| 172 | #define USBHOST_OFFSET_UHCHR 0x64 // Usb Host reset register\r | |
| 173 | \r | |
| 174 | #define OHC_BAR_INDEX 0\r | |
| 175 | \r | |
| 176 | //\r | |
| 177 | // Usb Host controller register offset\r | |
| 178 | //\r | |
| 179 | #define USBHOST_OFFSET_UHCREV 0x0 // Usb Host revision register\r | |
| 180 | #define USBHOST_OFFSET_UHCHCON 0x4 // Usb Host control register\r | |
| 181 | #define USBHOST_OFFSET_UHCCOMS 0x8 // Usb Host Command Status register\r | |
| 182 | #define USBHOST_OFFSET_UHCINTS 0xC // Usb Host Interrupt Status register\r | |
| 183 | #define USBHOST_OFFSET_UHCINTE 0x10 // Usb Host Interrupt Enable register\r | |
| 184 | #define USBHOST_OFFSET_UHCINTD 0x14 // Usb Host Interrupt Disable register\r | |
| 185 | #define USBHOST_OFFSET_UHCHCCA 0x18 // Usb Host Controller Communication Area\r | |
| 186 | #define USBHOST_OFFSET_UHCPCED 0x1C // Usb Host Period Current Endpoint Descriptor\r | |
| 187 | #define USBHOST_OFFSET_UHCCHED 0x20 // Usb Host Control Head Endpoint Descriptor\r | |
| 188 | #define USBHOST_OFFSET_UHCCCED 0x24 // Usb Host Control Current Endpoint Descriptor\r | |
| 189 | #define USBHOST_OFFSET_UHCBHED 0x28 // Usb Host Bulk Head Endpoint Descriptor\r | |
| 190 | #define USBHOST_OFFSET_UHCBCED 0x2C // Usb Host Bulk Current Endpoint Descriptor\r | |
| 191 | #define USBHOST_OFFSET_UHCDHEAD 0x30 // Usb Host Done Head register\r | |
| 192 | #define USBHOST_OFFSET_UHCFMI 0x34 // Usb Host Frame Interval register\r | |
| 193 | #define USBHOST_OFFSET_UHCFMR 0x38 // Usb Host Frame Remaining register\r | |
| 194 | #define USBHOST_OFFSET_UHCFMN 0x3C // Usb Host Frame Number register\r | |
| 195 | #define USBHOST_OFFSET_UHCPERS 0x40 // Usb Host Periodic Start register\r | |
| 196 | #define USBHOST_OFFSET_UHCLST 0x44 // Usb Host Low-Speed Threshold register\r | |
| 197 | #define USBHOST_OFFSET_UHCRHDA 0x48 // Usb Host Root Hub Descriptor A register\r | |
| 198 | #define USBHOST_OFFSET_UHCRHDB 0x4C // Usb Host Root Hub Descriptor B register\r | |
| 199 | #define USBHOST_OFFSET_UHCRHS 0x50 // Usb Host Root Hub Status register\r | |
| 200 | #define USBHOST_OFFSET_UHCRHPS1 0x54 // Usb Host Root Hub Port Status 1 register\r | |
| 201 | \r | |
| 202 | //\r | |
| 203 | // Usb Host controller register bit fields\r | |
| 204 | //\r | |
| 205 | #pragma pack(1)\r | |
| 206 | \r | |
| 207 | typedef struct {\r | |
| 208 | UINT8 ProgInterface;\r | |
| 209 | UINT8 SubClassCode;\r | |
| 210 | UINT8 BaseCode;\r | |
| 211 | } USB_CLASSC;\r | |
| 212 | \r | |
| 213 | typedef struct {\r | |
| 214 | UINT32 Revision:8;\r | |
| 215 | UINT32 Rsvd:24;\r | |
| 216 | } HcREVISION;\r | |
| 217 | \r | |
| 218 | typedef struct {\r | |
| 219 | UINT32 ControlBulkRatio:2;\r | |
| 220 | UINT32 PeriodicEnable:1;\r | |
| 221 | UINT32 IsochronousEnable:1;\r | |
| 222 | UINT32 ControlEnable:1;\r | |
| 223 | UINT32 BulkEnable:1;\r | |
| 224 | UINT32 FunctionalState:2;\r | |
| 225 | UINT32 InterruptRouting:1;\r | |
| 226 | UINT32 RemoteWakeup:1;\r | |
| 227 | UINT32 RemoteWakeupEnable:1;\r | |
| 228 | UINT32 Reserved:21;\r | |
| 229 | } HcCONTROL;\r | |
| 230 | \r | |
| 231 | typedef struct {\r | |
| 232 | UINT32 HcReset:1;\r | |
| 233 | UINT32 ControlListFilled:1;\r | |
| 234 | UINT32 BulkListFilled:1;\r | |
| 235 | UINT32 ChangeOwnerRequest:1;\r | |
| 236 | UINT32 Reserved1:12;\r | |
| 237 | UINT32 ScheduleOverrunCount:2;\r | |
| 238 | UINT32 Reserved:14;\r | |
| 239 | } HcCOMMAND_STATUS;\r | |
| 240 | \r | |
| 241 | typedef struct {\r | |
| 242 | UINT32 SchedulingOverrun:1;\r | |
| 243 | UINT32 WriteBackDone:1;\r | |
| 244 | UINT32 Sof:1;\r | |
| 245 | UINT32 ResumeDetected:1;\r | |
| 246 | UINT32 UnrecoverableError:1;\r | |
| 247 | UINT32 FrameNumOverflow:1;\r | |
| 248 | UINT32 RHStatusChange:1;\r | |
| 249 | UINT32 Reserved1:23;\r | |
| 250 | UINT32 OwnerChange:1;\r | |
| 251 | UINT32 Reserved2:1;\r | |
| 252 | } HcINTERRUPT_STATUS;\r | |
| 253 | \r | |
| 254 | typedef struct {\r | |
| 255 | UINT32 SchedulingOverrunInt:1;\r | |
| 256 | UINT32 WriteBackDoneInt:1;\r | |
| 257 | UINT32 SofInt:1;\r | |
| 258 | UINT32 ResumeDetectedInt:1;\r | |
| 259 | UINT32 UnrecoverableErrorInt:1;\r | |
| 260 | UINT32 FrameNumOverflowInt:1;\r | |
| 261 | UINT32 RHStatusChangeInt:1;\r | |
| 262 | UINT32 Reserved:23;\r | |
| 263 | UINT32 OwnerChangedInt:1;\r | |
| 264 | UINT32 MasterInterruptEnable:1;\r | |
| 265 | } HcINTERRUPT_CONTROL;\r | |
| 266 | \r | |
| 267 | typedef struct {\r | |
| 268 | UINT32 Rerserved:8;\r | |
| 269 | UINT32 Hcca:24;\r | |
| 270 | } HcHCCA;\r | |
| 271 | \r | |
| 272 | typedef struct {\r | |
| 273 | UINT32 Reserved:4;\r | |
| 274 | UINT32 MemoryPtr:28;\r | |
| 275 | } HcMEMORY_PTR;\r | |
| 276 | \r | |
| 277 | typedef struct {\r | |
| 278 | UINT32 FrameInterval:14;\r | |
| 279 | UINT32 Reserved:2;\r | |
| 280 | UINT32 FSMaxDataPacket:15;\r | |
| 281 | UINT32 FrmIntervalToggle:1;\r | |
| 282 | } HcFRM_INTERVAL;\r | |
| 283 | \r | |
| 284 | typedef struct {\r | |
| 285 | UINT32 FrameRemaining:14;\r | |
| 286 | UINT32 Reserved:17;\r | |
| 287 | UINT32 FrameRemainingToggle:1;\r | |
| 288 | } HcFRAME_REMAINING;\r | |
| 289 | \r | |
| 290 | typedef struct {\r | |
| 291 | UINT32 FrameNumber:16;\r | |
| 292 | UINT32 Reserved:16;\r | |
| 293 | } HcFRAME_NUMBER;\r | |
| 294 | \r | |
| 295 | typedef struct {\r | |
| 296 | UINT32 PeriodicStart:14;\r | |
| 297 | UINT32 Reserved:18;\r | |
| 298 | } HcPERIODIC_START;\r | |
| 299 | \r | |
| 300 | typedef struct {\r | |
| 301 | UINT32 LsThreshold:12;\r | |
| 302 | UINT32 Reserved:20;\r | |
| 303 | } HcLS_THRESHOLD;\r | |
| 304 | \r | |
| 305 | typedef struct {\r | |
| 306 | UINT32 NumDownStrmPorts:8;\r | |
| 307 | UINT32 PowerSwitchMode:1;\r | |
| 308 | UINT32 NoPowerSwitch:1;\r | |
| 309 | UINT32 DeviceType:1;\r | |
| 310 | UINT32 OverCurrentProtMode:1;\r | |
| 311 | UINT32 NoOverCurrentProtMode:1;\r | |
| 312 | UINT32 Reserved:11;\r | |
| 313 | UINT32 PowerOnToPowerGoodTime:8;\r | |
| 314 | } HcRH_DESC_A;\r | |
| 315 | \r | |
| 316 | typedef struct {\r | |
| 317 | UINT32 DeviceRemovable:16;\r | |
| 318 | UINT32 PortPowerControlMask:16;\r | |
| 319 | } HcRH_DESC_B;\r | |
| 320 | \r | |
| 321 | typedef struct {\r | |
| 322 | UINT32 LocalPowerStat:1;\r | |
| 323 | UINT32 OverCurrentIndicator:1;\r | |
| 324 | UINT32 Reserved1:13;\r | |
| 325 | UINT32 DevRemoteWakeupEnable:1;\r | |
| 326 | UINT32 LocalPowerStatChange:1;\r | |
| 327 | UINT32 OverCurrentIndicatorChange:1;\r | |
| 328 | UINT32 Reserved2:13;\r | |
| 329 | UINT32 ClearRemoteWakeupEnable:1;\r | |
| 330 | } HcRH_STATUS;\r | |
| 331 | \r | |
| 332 | typedef struct {\r | |
| 333 | UINT32 CurrentConnectStat:1;\r | |
| 334 | UINT32 EnableStat:1;\r | |
| 335 | UINT32 SuspendStat:1;\r | |
| 336 | UINT32 OCIndicator:1;\r | |
| 337 | UINT32 ResetStat:1;\r | |
| 338 | UINT32 Reserved1:3;\r | |
| 339 | UINT32 PowerStat:1;\r | |
| 340 | UINT32 LsDeviceAttached:1;\r | |
| 341 | UINT32 Reserved2:6;\r | |
| 342 | UINT32 ConnectStatChange:1;\r | |
| 343 | UINT32 EnableStatChange:1;\r | |
| 344 | UINT32 SuspendStatChange:1;\r | |
| 345 | UINT32 OCIndicatorChange:1;\r | |
| 346 | UINT32 ResetStatChange:1;\r | |
| 347 | UINT32 Reserved3:11;\r | |
| 348 | } HcRHPORT_STATUS;\r | |
| 349 | \r | |
| 350 | typedef struct {\r | |
| 351 | UINT32 FSBIR:1;\r | |
| 352 | UINT32 FHR:1;\r | |
| 353 | UINT32 CGR:1;\r | |
| 354 | UINT32 SSDC:1;\r | |
| 355 | UINT32 UIT:1;\r | |
| 356 | UINT32 SSE:1;\r | |
| 357 | UINT32 PSPL:1;\r | |
| 358 | UINT32 PCPL:1;\r | |
| 359 | UINT32 Reserved0:1;\r | |
| 360 | UINT32 SSEP1:1;\r | |
| 361 | UINT32 SSEP2:1;\r | |
| 362 | UINT32 SSEP3:1;\r | |
| 363 | UINT32 Reserved1:20;\r | |
| 364 | } HcRESET;\r | |
| 365 | \r | |
| 366 | #pragma pack()\r | |
| 367 | \r | |
| 368 | //\r | |
| 369 | // Func List\r | |
| 370 | //\r | |
| 371 | /**\r | |
| 372 | \r | |
| 373 | Get OHCI operational reg value\r | |
| 374 | \r | |
| 375 | @param Ohc UHC private data\r | |
| 376 | @param Offset Offset of the operational reg\r | |
| 377 | \r | |
| 378 | @retval Value of the register\r | |
| 379 | \r | |
| 380 | **/\r | |
| 381 | UINT32\r | |
| 382 | OhciGetOperationalReg (\r | |
| 383 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 384 | IN UINT32 Offset\r | |
| 385 | );\r | |
| 386 | /**\r | |
| 387 | \r | |
| 388 | Set OHCI operational reg value\r | |
| 389 | \r | |
| 390 | @param Ohc UHC private data\r | |
| 391 | @param Offset Offset of the operational reg\r | |
| 392 | @param Value Value to set\r | |
| 393 | \r | |
| 394 | @retval EFI_SUCCESS Value set to the reg\r | |
| 395 | \r | |
| 396 | **/\r | |
| 397 | EFI_STATUS\r | |
| 398 | OhciSetOperationalReg (\r | |
| 399 | USB_OHCI_HC_DEV *Ohc,\r | |
| 400 | IN UINT32 Offset,\r | |
| 401 | IN UINT32 *Value\r | |
| 402 | );\r | |
| 403 | /**\r | |
| 404 | \r | |
| 405 | Get HcRevision reg value\r | |
| 406 | \r | |
| 407 | @param Ohc UHC private data\r | |
| 408 | \r | |
| 409 | @retval Value of the register\r | |
| 410 | \r | |
| 411 | **/\r | |
| 412 | \r | |
| 413 | \r | |
| 414 | UINT32\r | |
| 415 | OhciGetHcRevision (\r | |
| 416 | USB_OHCI_HC_DEV *Ohc\r | |
| 417 | );\r | |
| 418 | \r | |
| 419 | /**\r | |
| 420 | \r | |
| 421 | Set HcReset reg value\r | |
| 422 | \r | |
| 423 | @param Ohc UHC private data\r | |
| 424 | @param Field Field to set\r | |
| 425 | @param Value Value to set\r | |
| 426 | \r | |
| 427 | @retval EFI_SUCCESS Value set\r | |
| 428 | \r | |
| 429 | **/\r | |
| 430 | \r | |
| 431 | EFI_STATUS\r | |
| 432 | OhciSetHcReset (\r | |
| 433 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 434 | IN UINT32 Field,\r | |
| 435 | IN UINT32 Value\r | |
| 436 | );\r | |
| 437 | /**\r | |
| 438 | \r | |
| 439 | Get specific field of HcReset reg value\r | |
| 440 | \r | |
| 441 | @param Ohc UHC private data\r | |
| 442 | @param Field Field to get\r | |
| 443 | \r | |
| 444 | @retval Value of the field\r | |
| 445 | \r | |
| 446 | **/\r | |
| 447 | \r | |
| 448 | UINT32\r | |
| 449 | OhciGetHcReset (\r | |
| 450 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 451 | IN UINT32 Field\r | |
| 452 | );\r | |
| 453 | /**\r | |
| 454 | \r | |
| 455 | Set HcControl reg value\r | |
| 456 | \r | |
| 457 | @param Ohc UHC private data\r | |
| 458 | @param Field Field to set\r | |
| 459 | @param Value Value to set\r | |
| 460 | \r | |
| 461 | @retval EFI_SUCCESS Value set\r | |
| 462 | \r | |
| 463 | **/\r | |
| 464 | \r | |
| 465 | EFI_STATUS\r | |
| 466 | OhciSetHcControl (\r | |
| 467 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 468 | IN UINTN Field,\r | |
| 469 | IN UINT32 Value\r | |
| 470 | );\r | |
| 471 | /**\r | |
| 472 | \r | |
| 473 | Get specific field of HcControl reg value\r | |
| 474 | \r | |
| 475 | @param Ohc UHC private data\r | |
| 476 | @param Field Field to get\r | |
| 477 | \r | |
| 478 | @retval Value of the field\r | |
| 479 | \r | |
| 480 | **/\r | |
| 481 | \r | |
| 482 | \r | |
| 483 | UINT32\r | |
| 484 | OhciGetHcControl (\r | |
| 485 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 486 | IN UINTN Field\r | |
| 487 | );\r | |
| 488 | /**\r | |
| 489 | \r | |
| 490 | Set HcCommand reg value\r | |
| 491 | \r | |
| 492 | @param Ohc UHC private data\r | |
| 493 | @param Field Field to set\r | |
| 494 | @param Value Value to set\r | |
| 495 | \r | |
| 496 | @retval EFI_SUCCESS Value set\r | |
| 497 | \r | |
| 498 | **/\r | |
| 499 | \r | |
| 500 | EFI_STATUS\r | |
| 501 | OhciSetHcCommandStatus (\r | |
| 502 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 503 | IN UINTN Field,\r | |
| 504 | IN UINT32 Value\r | |
| 505 | );\r | |
| 506 | /**\r | |
| 507 | \r | |
| 508 | Get specific field of HcCommand reg value\r | |
| 509 | \r | |
| 510 | @param Ohc UHC private data\r | |
| 511 | @param Field Field to get\r | |
| 512 | \r | |
| 513 | @retval Value of the field\r | |
| 514 | \r | |
| 515 | **/\r | |
| 516 | \r | |
| 517 | UINT32\r | |
| 518 | OhciGetHcCommandStatus (\r | |
| 519 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 520 | IN UINTN Field\r | |
| 521 | );\r | |
| 522 | /**\r | |
| 523 | \r | |
| 524 | Clear specific fields of Interrupt Status\r | |
| 525 | \r | |
| 526 | @param Ohc UHC private data\r | |
| 527 | @param Field Field to clear\r | |
| 528 | \r | |
| 529 | @retval EFI_SUCCESS Fields cleared\r | |
| 530 | \r | |
| 531 | **/\r | |
| 532 | \r | |
| 533 | EFI_STATUS\r | |
| 534 | OhciClearInterruptStatus (\r | |
| 535 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 536 | IN UINTN Field\r | |
| 537 | );\r | |
| 538 | /**\r | |
| 539 | \r | |
| 540 | Get fields of HcInterrupt reg value\r | |
| 541 | \r | |
| 542 | @param Ohc UHC private data\r | |
| 543 | @param Field Field to get\r | |
| 544 | \r | |
| 545 | @retval Value of the field\r | |
| 546 | \r | |
| 547 | **/\r | |
| 548 | \r | |
| 549 | UINT32\r | |
| 550 | OhciGetHcInterruptStatus (\r | |
| 551 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 552 | IN UINTN Field\r | |
| 553 | );\r | |
| 554 | /**\r | |
| 555 | \r | |
| 556 | Set Interrupt Control reg value\r | |
| 557 | \r | |
| 558 | @param Ohc UHC private data\r | |
| 559 | @param StatEnable Enable or Disable\r | |
| 560 | @param Field Field to set\r | |
| 561 | @param Value Value to set\r | |
| 562 | \r | |
| 563 | @retval EFI_SUCCESS Value set\r | |
| 564 | \r | |
| 565 | **/\r | |
| 566 | \r | |
| 567 | EFI_STATUS\r | |
| 568 | OhciSetInterruptControl (\r | |
| 569 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 570 | IN BOOLEAN StatEnable,\r | |
| 571 | IN UINTN Field,\r | |
| 572 | IN UINT32 Value\r | |
| 573 | );\r | |
| 574 | /**\r | |
| 575 | \r | |
| 576 | Get field of HcInterruptControl reg value\r | |
| 577 | \r | |
| 578 | @param Ohc UHC private data\r | |
| 579 | @param Field Field to get\r | |
| 580 | \r | |
| 581 | @retval Value of the field\r | |
| 582 | \r | |
| 583 | **/\r | |
| 584 | \r | |
| 585 | UINT32\r | |
| 586 | OhciGetHcInterruptControl (\r | |
| 587 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 588 | IN UINTN Field\r | |
| 589 | );\r | |
| 590 | /**\r | |
| 591 | \r | |
| 592 | Set memory pointer of specific type\r | |
| 593 | \r | |
| 594 | @param Ohc UHC private data\r | |
| 595 | @param PointerType Type of the pointer to set\r | |
| 596 | @param Value Value to set\r | |
| 597 | \r | |
| 598 | @retval EFI_SUCCESS Memory pointer set\r | |
| 599 | \r | |
| 600 | **/\r | |
| 601 | \r | |
| 602 | EFI_STATUS\r | |
| 603 | OhciSetMemoryPointer(\r | |
| 604 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 605 | IN UINTN PointerType,\r | |
| 606 | IN VOID *Value\r | |
| 607 | );\r | |
| 608 | /**\r | |
| 609 | \r | |
| 610 | Get memory pointer of specific type\r | |
| 611 | \r | |
| 612 | @param Ohc UHC private data\r | |
| 613 | @param PointerType Type of pointer\r | |
| 614 | \r | |
| 615 | @retval Memory pointer of the specific type\r | |
| 616 | \r | |
| 617 | **/\r | |
| 618 | \r | |
| 619 | VOID *\r | |
| 620 | OhciGetMemoryPointer (\r | |
| 621 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 622 | IN UINTN PointerType\r | |
| 623 | );\r | |
| 624 | /**\r | |
| 625 | \r | |
| 626 | Set Frame Interval value\r | |
| 627 | \r | |
| 628 | @param Ohc UHC private data\r | |
| 629 | @param Field Field to set\r | |
| 630 | @param Value Value to set\r | |
| 631 | \r | |
| 632 | @retval EFI_SUCCESS Value set\r | |
| 633 | \r | |
| 634 | **/\r | |
| 635 | \r | |
| 636 | EFI_STATUS\r | |
| 637 | OhciSetFrameInterval (\r | |
| 638 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 639 | IN UINTN Field,\r | |
| 640 | IN UINT32 Value\r | |
| 641 | );\r | |
| 642 | /**\r | |
| 643 | \r | |
| 644 | Get field of frame interval reg value\r | |
| 645 | \r | |
| 646 | @param Ohc UHC private data\r | |
| 647 | @param Field Field to get\r | |
| 648 | \r | |
| 649 | @retval Value of the field\r | |
| 650 | \r | |
| 651 | **/\r | |
| 652 | \r | |
| 653 | UINT32\r | |
| 654 | OhciGetFrameInterval (\r | |
| 655 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 656 | IN UINTN Field\r | |
| 657 | );\r | |
| 658 | /**\r | |
| 659 | \r | |
| 660 | Set Frame Remaining reg value\r | |
| 661 | \r | |
| 662 | @param Ohc UHC private data\r | |
| 663 | @param Value Value to set\r | |
| 664 | \r | |
| 665 | @retval EFI_SUCCESS Value set\r | |
| 666 | \r | |
| 667 | **/\r | |
| 668 | \r | |
| 669 | EFI_STATUS\r | |
| 670 | OhciSetFrameRemaining (\r | |
| 671 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 672 | IN UINT32 Value\r | |
| 673 | );\r | |
| 674 | /**\r | |
| 675 | \r | |
| 676 | Get value of frame remaining reg\r | |
| 677 | \r | |
| 678 | @param Ohc UHC private data\r | |
| 679 | @param Field Field to get\r | |
| 680 | \r | |
| 681 | @retval Value of frame remaining reg\r | |
| 682 | \r | |
| 683 | **/\r | |
| 684 | UINT32\r | |
| 685 | OhciGetFrameRemaining (\r | |
| 686 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 687 | IN UINTN Field\r | |
| 688 | );\r | |
| 689 | /**\r | |
| 690 | \r | |
| 691 | Set frame number reg value\r | |
| 692 | \r | |
| 693 | @param Ohc UHC private data\r | |
| 694 | @param Value Value to set\r | |
| 695 | \r | |
| 696 | @retval EFI_SUCCESS Value set\r | |
| 697 | \r | |
| 698 | **/\r | |
| 699 | \r | |
| 700 | EFI_STATUS\r | |
| 701 | OhciSetFrameNumber(\r | |
| 702 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 703 | IN UINT32 Value\r | |
| 704 | );\r | |
| 705 | /**\r | |
| 706 | \r | |
| 707 | Get frame number reg value\r | |
| 708 | \r | |
| 709 | @param Ohc UHC private data\r | |
| 710 | \r | |
| 711 | @retval Value of frame number reg\r | |
| 712 | \r | |
| 713 | **/\r | |
| 714 | \r | |
| 715 | UINT32\r | |
| 716 | OhciGetFrameNumber (\r | |
| 717 | IN USB_OHCI_HC_DEV *Ohc\r | |
| 718 | );\r | |
| 719 | /**\r | |
| 720 | \r | |
| 721 | Set period start reg value\r | |
| 722 | \r | |
| 723 | @param Ohc UHC private data\r | |
| 724 | @param Value Value to set\r | |
| 725 | \r | |
| 726 | @retval EFI_SUCCESS Value set\r | |
| 727 | \r | |
| 728 | **/\r | |
| 729 | \r | |
| 730 | EFI_STATUS\r | |
| 731 | OhciSetPeriodicStart (\r | |
| 732 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 733 | IN UINT32 Value\r | |
| 734 | );\r | |
| 735 | /**\r | |
| 736 | \r | |
| 737 | Get periodic start reg value\r | |
| 738 | \r | |
| 739 | @param Ohc UHC private data\r | |
| 740 | \r | |
| 741 | @param Value of periodic start reg\r | |
| 742 | \r | |
| 743 | **/\r | |
| 744 | \r | |
| 745 | UINT32\r | |
| 746 | OhciGetPeriodicStart (\r | |
| 747 | IN USB_OHCI_HC_DEV *Ohc\r | |
| 748 | );\r | |
| 749 | /**\r | |
| 750 | \r | |
| 751 | Set Ls Threshold reg value\r | |
| 752 | \r | |
| 753 | @param Ohc UHC private data\r | |
| 754 | @param Value Value to set\r | |
| 755 | \r | |
| 756 | @retval EFI_SUCCESS Value set\r | |
| 757 | \r | |
| 758 | **/\r | |
| 759 | \r | |
| 760 | EFI_STATUS\r | |
| 761 | OhciSetLsThreshold (\r | |
| 762 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 763 | IN UINT32 Value\r | |
| 764 | );\r | |
| 765 | /**\r | |
| 766 | \r | |
| 767 | Get Ls Threshold reg value\r | |
| 768 | \r | |
| 769 | @param Ohc UHC private data\r | |
| 770 | \r | |
| 771 | @retval Value of Ls Threshold reg\r | |
| 772 | \r | |
| 773 | **/\r | |
| 774 | \r | |
| 775 | UINT32\r | |
| 776 | OhciGetLsThreshold (\r | |
| 777 | IN USB_OHCI_HC_DEV *Ohc\r | |
| 778 | );\r | |
| 779 | /**\r | |
| 780 | \r | |
| 781 | Set Root Hub Descriptor reg value\r | |
| 782 | \r | |
| 783 | @param Ohc UHC private data\r | |
| 784 | @param Field Field to set\r | |
| 785 | @param Value Value to set\r | |
| 786 | \r | |
| 787 | @retval EFI_SUCCESS Value set\r | |
| 788 | \r | |
| 789 | **/\r | |
| 790 | EFI_STATUS\r | |
| 791 | OhciSetRootHubDescriptor (\r | |
| 792 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 793 | IN UINTN Field,\r | |
| 794 | IN UINT32 Value\r | |
| 795 | );\r | |
| 796 | /**\r | |
| 797 | \r | |
| 798 | Get Root Hub Descriptor reg value\r | |
| 799 | \r | |
| 800 | @param Ohc UHC private data\r | |
| 801 | @param Field Field to get\r | |
| 802 | \r | |
| 803 | @retval Value of the field\r | |
| 804 | \r | |
| 805 | **/\r | |
| 806 | \r | |
| 807 | UINT32\r | |
| 808 | OhciGetRootHubDescriptor (\r | |
| 809 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 810 | IN UINTN Field\r | |
| 811 | );\r | |
| 812 | /**\r | |
| 813 | \r | |
| 814 | Set Root Hub Status reg value\r | |
| 815 | \r | |
| 816 | @param Ohc UHC private data\r | |
| 817 | @param Field Field to set\r | |
| 818 | \r | |
| 819 | @retval EFI_SUCCESS Value set\r | |
| 820 | \r | |
| 821 | **/\r | |
| 822 | \r | |
| 823 | EFI_STATUS\r | |
| 824 | OhciSetRootHubStatus (\r | |
| 825 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 826 | IN UINTN Field\r | |
| 827 | );\r | |
| 828 | /**\r | |
| 829 | \r | |
| 830 | Get Root Hub Status reg value\r | |
| 831 | \r | |
| 832 | @param Ohc UHC private data\r | |
| 833 | @param Field Field to get\r | |
| 834 | \r | |
| 835 | @retval Value of the field\r | |
| 836 | \r | |
| 837 | **/\r | |
| 838 | \r | |
| 839 | UINT32\r | |
| 840 | OhciGetRootHubStatus (\r | |
| 841 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 842 | IN UINTN Field\r | |
| 843 | );\r | |
| 844 | /**\r | |
| 845 | \r | |
| 846 | Set Root Hub Port Status reg value\r | |
| 847 | \r | |
| 848 | @param Ohc UHC private data\r | |
| 849 | @param Index Index of the port\r | |
| 850 | @param Field Field to set\r | |
| 851 | \r | |
| 852 | @retval EFI_SUCCESS Value set\r | |
| 853 | \r | |
| 854 | **/\r | |
| 855 | \r | |
| 856 | EFI_STATUS\r | |
| 857 | OhciSetRootHubPortStatus (\r | |
| 858 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 859 | IN UINT32 Index,\r | |
| 860 | IN UINTN Field\r | |
| 861 | );\r | |
| 862 | /**\r | |
| 863 | \r | |
| 864 | Get Root Hub Port Status reg value\r | |
| 865 | \r | |
| 866 | @param Ohc UHC private data\r | |
| 867 | @param Index Index of the port\r | |
| 868 | @param Field Field to get\r | |
| 869 | \r | |
| 870 | @retval Value of the field and index\r | |
| 871 | \r | |
| 872 | **/\r | |
| 873 | \r | |
| 874 | UINT32\r | |
| 875 | OhciReadRootHubPortStatus (\r | |
| 876 | IN USB_OHCI_HC_DEV *Ohc,\r | |
| 877 | IN UINT32 Index,\r | |
| 878 | IN UINTN Field\r | |
| 879 | );\r | |
| 880 | \r | |
| 881 | #endif\r |