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cb274a27
ED		 1/** @file\r
2 Header file for Registers and Structure definitions\r
3\r
4Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
5This program and the accompanying materials\r
6are licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14#ifndef __OPAL_PASSWORD_NVME_REG_H__\r
15#define __OPAL_PASSWORD_NVME_REG_H__\r
16\r
17//\r
18// PCI Header for PCIe root port configuration\r
19//\r
20#define NVME_PCIE_PCICMD 0x04\r
21#define NVME_PCIE_BNUM 0x18\r
22#define NVME_PCIE_SEC_BNUM 0x19\r
23#define NVME_PCIE_IOBL 0x1C\r
24#define NVME_PCIE_MBL 0x20\r
25#define NVME_PCIE_PMBL 0x24\r
26#define NVME_PCIE_PMBU32 0x28\r
27#define NVME_PCIE_PMLU32 0x2C\r
28#define NVME_PCIE_INTR 0x3C\r
29\r
30//\r
31// NVMe related definitions\r
32//\r
33#define PCI_CLASS_MASS_STORAGE_NVM 0x08 // mass storage sub-class non-volatile memory.\r
34#define PCI_IF_NVMHCI 0x02 // mass storage programming interface NVMHCI.\r
35\r
36#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based\r
37#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based\r
38\r
39#define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based\r
40#define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based\r
41\r
42#define NVME_MAX_IO_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ\r
43\r
44#define NVME_CSQ_DEPTH (NVME_CSQ_SIZE+1)\r
45#define NVME_CCQ_DEPTH (NVME_CCQ_SIZE+1)\r
46#define NVME_PRP_SIZE (4) // Pages of PRP list\r
47\r
48#define NVME_CONTROLLER_ID 0\r
49\r
50//\r
51// Time out Value for Nvme transaction execution\r
52//\r
53#define NVME_GENERIC_TIMEOUT 5000000 ///< us\r
54#define NVME_CMD_WAIT 100 ///< us\r
55#define NVME_CMD_TIMEOUT 20000000 ///< us\r
56\r
57\r
58\r
59#define NVME_MEM_MAX_SIZE \\r
60 (( \\r
61 1 /* Controller Data */ + \\r
62 1 /* Identify Data */ + \\r
63 1 /* ASQ */ + \\r
64 1 /* ACQ */ + \\r
65 1 /* SQs */ + \\r
66 1 /* CQs */ + \\r
67 NVME_PRP_SIZE * NVME_CSQ_DEPTH /* PRPs */ \\r
68 ) * EFI_PAGE_SIZE)\r
69\r
70\r
71//\r
72// controller register offsets\r
73//\r
74#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities\r
75#define NVME_VER_OFFSET 0x0008 // Version\r
76#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set\r
77#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear\r
78#define NVME_CC_OFFSET 0x0014 // Controller Configuration\r
79#define NVME_CSTS_OFFSET 0x001c // Controller Status\r
80#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes\r
81#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address\r
82#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address\r
83#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell\r
84#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell\r
85\r
86//\r
87// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))\r
88// Get the doorbell stride bit shift Value from the controller capabilities.\r
89//\r
90#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell\r
91#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell\r
92\r
93\r
94#pragma pack(1)\r
95\r
96//\r
97// 3.1.1 Offset 00h: CAP - Controller Capabilities\r
98//\r
99typedef struct {\r
100 UINT16 Mqes; // Maximum Queue Entries Supported\r
101 UINT8 Cqr:1; // Contiguous Queues Required\r
102 UINT8 Ams:2; // Arbitration Mechanism Supported\r
103 UINT8 Rsvd1:5;\r
104 UINT8 To; // Timeout\r
105 UINT16 Dstrd:4;\r
106 UINT16 Rsvd2:1;\r
107 UINT16 Css:4; // Command Sets Supported\r
108 UINT16 Rsvd3:7;\r
109 UINT8 Mpsmin:4;\r
110 UINT8 Mpsmax:4;\r
111 UINT8 Rsvd4;\r
112} NVME_CAP;\r
113\r
114//\r
115// 3.1.2 Offset 08h: VS - Version\r
116//\r
117typedef struct {\r
118 UINT16 Mnr; // Minor version number\r
119 UINT16 Mjr; // Major version number\r
120} NVME_VER;\r
121\r
122//\r
123// 3.1.5 Offset 14h: CC - Controller Configuration\r
124//\r
125typedef struct {\r
126 UINT16 En:1; // Enable\r
127 UINT16 Rsvd1:3;\r
128 UINT16 Css:3; // Command Set Selected\r
129 UINT16 Mps:4; // Memory Page Size\r
130 UINT16 Ams:3; // Arbitration Mechanism Selected\r
131 UINT16 Shn:2; // Shutdown Notification\r
132 UINT8 Iosqes:4; // I/O Submission Queue Entry Size\r
133 UINT8 Iocqes:4; // I/O Completion Queue Entry Size\r
134 UINT8 Rsvd2;\r
135} NVME_CC;\r
136\r
137//\r
138// 3.1.6 Offset 1Ch: CSTS - Controller Status\r
139//\r
140typedef struct {\r
141 UINT32 Rdy:1; // Ready\r
142 UINT32 Cfs:1; // Controller Fatal Status\r
143 UINT32 Shst:2; // Shutdown Status\r
144 UINT32 Nssro:1; // NVM Subsystem Reset Occurred\r
145 UINT32 Rsvd1:27;\r
146} NVME_CSTS;\r
147\r
148//\r
149// 3.1.8 Offset 24h: AQA - Admin Queue Attributes\r
150//\r
151typedef struct {\r
152 UINT16 Asqs:12; // Submission Queue Size\r
153 UINT16 Rsvd1:4;\r
154 UINT16 Acqs:12; // Completion Queue Size\r
155 UINT16 Rsvd2:4;\r
156} NVME_AQA;\r
157\r
158//\r
159// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address\r
160//\r
161#define NVME_ASQ UINT64\r
162\r
163//\r
164// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address\r
165//\r
166#define NVME_ACQ UINT64\r
167\r
168//\r
169// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell\r
170//\r
171typedef struct {\r
172 UINT16 Sqt;\r
173 UINT16 Rsvd1;\r
174} NVME_SQTDBL;\r
175\r
176//\r
177// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell\r
178//\r
179typedef struct {\r
180 UINT16 Cqh;\r
181 UINT16 Rsvd1;\r
182} NVME_CQHDBL;\r
183\r
184//\r
185// NVM command set structures\r
186//\r
187// Read Command\r
188//\r
189typedef struct {\r
190 //\r
191 // CDW 10, 11\r
192 //\r
193 UINT64 Slba; /* Starting Sector Address */\r
194 //\r
195 // CDW 12\r
196 //\r
197 UINT16 Nlb; /* Number of Sectors */\r
198 UINT16 Rsvd1:10;\r
199 UINT16 Prinfo:4; /* Protection Info Check */\r
200 UINT16 Fua:1; /* Force Unit Access */\r
201 UINT16 Lr:1; /* Limited Retry */\r
202 //\r
203 // CDW 13\r
204 //\r
205 UINT32 Af:4; /* Access Frequency */\r
206 UINT32 Al:2; /* Access Latency */\r
207 UINT32 Sr:1; /* Sequential Request */\r
208 UINT32 In:1; /* Incompressible */\r
209 UINT32 Rsvd2:24;\r
210 //\r
211 // CDW 14\r
212 //\r
213 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
214 //\r
215 // CDW 15\r
216 //\r
217 UINT16 Elbat; /* Expected Logical Block Application Tag */\r
218 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
219} NVME_READ;\r
220\r
221//\r
222// Write Command\r
223//\r
224typedef struct {\r
225 //\r
226 // CDW 10, 11\r
227 //\r
228 UINT64 Slba; /* Starting Sector Address */\r
229 //\r
230 // CDW 12\r
231 //\r
232 UINT16 Nlb; /* Number of Sectors */\r
233 UINT16 Rsvd1:10;\r
234 UINT16 Prinfo:4; /* Protection Info Check */\r
235 UINT16 Fua:1; /* Force Unit Access */\r
236 UINT16 Lr:1; /* Limited Retry */\r
237 //\r
238 // CDW 13\r
239 //\r
240 UINT32 Af:4; /* Access Frequency */\r
241 UINT32 Al:2; /* Access Latency */\r
242 UINT32 Sr:1; /* Sequential Request */\r
243 UINT32 In:1; /* Incompressible */\r
244 UINT32 Rsvd2:24;\r
245 //\r
246 // CDW 14\r
247 //\r
248 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
249 //\r
250 // CDW 15\r
251 //\r
252 UINT16 Lbat; /* Logical Block Application Tag */\r
253 UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
254} NVME_WRITE;\r
255\r
256//\r
257// Flush\r
258//\r
259typedef struct {\r
260 //\r
261 // CDW 10\r
262 //\r
263 UINT32 Flush; /* Flush */\r
264} NVME_FLUSH;\r
265\r
266//\r
267// Write Uncorrectable command\r
268//\r
269typedef struct {\r
270 //\r
271 // CDW 10, 11\r
272 //\r
273 UINT64 Slba; /* Starting LBA */\r
274 //\r
275 // CDW 12\r
276 //\r
277 UINT32 Nlb:16; /* Number of Logical Blocks */\r
278 UINT32 Rsvd1:16;\r
279} NVME_WRITE_UNCORRECTABLE;\r
280\r
281//\r
282// Write Zeroes command\r
283//\r
284typedef struct {\r
285 //\r
286 // CDW 10, 11\r
287 //\r
288 UINT64 Slba; /* Starting LBA */\r
289 //\r
290 // CDW 12\r
291 //\r
292 UINT16 Nlb; /* Number of Logical Blocks */\r
293 UINT16 Rsvd1:10;\r
294 UINT16 Prinfo:4; /* Protection Info Check */\r
295 UINT16 Fua:1; /* Force Unit Access */\r
296 UINT16 Lr:1; /* Limited Retry */\r
297 //\r
298 // CDW 13\r
299 //\r
300 UINT32 Rsvd2;\r
301 //\r
302 // CDW 14\r
303 //\r
304 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
305 //\r
306 // CDW 15\r
307 //\r
308 UINT16 Lbat; /* Logical Block Application Tag */\r
309 UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
310} NVME_WRITE_ZEROES;\r
311\r
312//\r
313// Compare command\r
314//\r
315typedef struct {\r
316 //\r
317 // CDW 10, 11\r
318 //\r
319 UINT64 Slba; /* Starting LBA */\r
320 //\r
321 // CDW 12\r
322 //\r
323 UINT16 Nlb; /* Number of Logical Blocks */\r
324 UINT16 Rsvd1:10;\r
325 UINT16 Prinfo:4; /* Protection Info Check */\r
326 UINT16 Fua:1; /* Force Unit Access */\r
327 UINT16 Lr:1; /* Limited Retry */\r
328 //\r
329 // CDW 13\r
330 //\r
331 UINT32 Rsvd2;\r
332 //\r
333 // CDW 14\r
334 //\r
335 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
336 //\r
337 // CDW 15\r
338 //\r
339 UINT16 Elbat; /* Expected Logical Block Application Tag */\r
340 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
341} NVME_COMPARE;\r
342\r
343typedef union {\r
344 NVME_READ Read;\r
345 NVME_WRITE Write;\r
346 NVME_FLUSH Flush;\r
347 NVME_WRITE_UNCORRECTABLE WriteUncorrectable;\r
348 NVME_WRITE_ZEROES WriteZeros;\r
349 NVME_COMPARE Compare;\r
350} NVME_CMD;\r
351\r
352typedef struct {\r
353 UINT16 Mp; /* Maximum Power */\r
354 UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */\r
355 UINT8 Mps:1; /* Max Power Scale */\r
356 UINT8 Nops:1; /* Non-Operational State */\r
357 UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */\r
358 UINT32 Enlat; /* Entry Latency */\r
359 UINT32 Exlat; /* Exit Latency */\r
360 UINT8 Rrt:5; /* Relative Read Throughput */\r
361 UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */\r
362 UINT8 Rrl:5; /* Relative Read Leatency */\r
363 UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */\r
364 UINT8 Rwt:5; /* Relative Write Throughput */\r
365 UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */\r
366 UINT8 Rwl:5; /* Relative Write Leatency */\r
367 UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */\r
368 UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */\r
369} NVME_PSDESCRIPTOR;\r
370\r
371//\r
372// Identify Controller Data\r
373//\r
374typedef struct {\r
375 //\r
376 // Controller Capabilities and Features 0-255\r
377 //\r
378 UINT16 Vid; /* PCI Vendor ID */\r
379 UINT16 Ssvid; /* PCI sub-system vendor ID */\r
380 UINT8 Sn[20]; /* Produce serial number */\r
381\r
382 UINT8 Mn[40]; /* Proeduct model number */\r
383 UINT8 Fr[8]; /* Firmware Revision */\r
384 UINT8 Rab; /* Recommended Arbitration Burst */\r
385 UINT8 Ieee_oiu[3]; /* Organization Unique Identifier */\r
386 UINT8 Cmic; /* Multi-interface Capabilities */\r
387 UINT8 Mdts; /* Maximum Data Transfer Size */\r
388 UINT8 Cntlid[2]; /* Controller ID */\r
389 UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */\r
390 //\r
391 // Admin Command Set Attributes\r
392 //\r
393 UINT16 Oacs; /* Optional Admin Command Support */\r
394 UINT8 Acl; /* Abort Command Limit */\r
395 UINT8 Aerl; /* Async Event Request Limit */\r
396 UINT8 Frmw; /* Firmware updates */\r
397 UINT8 Lpa; /* Log Page Attributes */\r
398 UINT8 Elpe; /* Error Log Page Entries */\r
399 UINT8 Npss; /* Number of Power States Support */\r
400 UINT8 Avscc; /* Admin Vendor Specific Command Configuration */\r
401 UINT8 Apsta; /* Autonomous Power State Transition Attributes */\r
402 UINT8 Rsvd2[246]; /* Reserved as of Nvm Express 1.1 Spec */\r
403 //\r
404 // NVM Command Set Attributes\r
405 //\r
406 UINT8 Sqes; /* Submission Queue Entry Size */\r
407 UINT8 Cqes; /* Completion Queue Entry Size */\r
408 UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */\r
409 UINT32 Nn; /* Number of Namespaces */\r
410 UINT16 Oncs; /* Optional NVM Command Support */\r
411 UINT16 Fuses; /* Fused Operation Support */\r
412 UINT8 Fna; /* Format NVM Attributes */\r
413 UINT8 Vwc; /* Volatile Write Cache */\r
414 UINT16 Awun; /* Atomic Write Unit Normal */\r
415 UINT16 Awupf; /* Atomic Write Unit Power Fail */\r
416 UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */\r
417 UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */\r
418 UINT16 Acwu; /* Atomic Compare & Write Unit */\r
419 UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */\r
420 UINT32 Sgls; /* SGL Support */\r
421 UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */\r
422 //\r
423 // I/O Command set Attributes\r
424 //\r
425 UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */\r
426 //\r
427 // Power State Descriptors\r
428 //\r
429 NVME_PSDESCRIPTOR PsDescriptor[32];\r
430\r
431 UINT8 VendorData[1024]; /* Vendor specific Data */\r
432} NVME_ADMIN_CONTROLLER_DATA;\r
433\r
434typedef struct {\r
435 UINT16 Security : 1; /* supports security send/receive commands */\r
436 UINT16 Format : 1; /* supports format nvm command */\r
437 UINT16 Firmware : 1; /* supports firmware activate/download commands */\r
438 UINT16 Oacs_rsvd : 13;\r
439 } OACS; // optional admin command support: NVME_ADMIN_CONTROLLER_DATA.Oacs\r
440\r
441typedef struct {\r
442 UINT16 Ms; /* Metadata Size */\r
443 UINT8 Lbads; /* LBA Data Size */\r
444 UINT8 Rp:2; /* Relative Performance */\r
445 #define LBAF_RP_BEST 00b\r
446 #define LBAF_RP_BETTER 01b\r
447 #define LBAF_RP_GOOD 10b\r
448 #define LBAF_RP_DEGRADED 11b\r
449 UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */\r
450} NVME_LBAFORMAT;\r
451\r
452//\r
453// Identify Namespace Data\r
454//\r
455typedef struct {\r
456 //\r
457 // NVM Command Set Specific\r
458 //\r
459 UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */\r
460 UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */\r
461 UINT64 Nuse; /* Namespace Utilization */\r
462 UINT8 Nsfeat; /* Namespace Features */\r
463 UINT8 Nlbaf; /* Number of LBA Formats */\r
464 UINT8 Flbas; /* Formatted LBA Size */\r
465 UINT8 Mc; /* Metadata Capabilities */\r
466 UINT8 Dpc; /* End-to-end Data Protection capabilities */\r
467 UINT8 Dps; /* End-to-end Data Protection Type Settings */\r
468 UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */\r
469 UINT8 Rescap; /* Reservation Capabilities */\r
470 UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */\r
471 UINT64 Eui64; /* IEEE Extended Unique Identifier */\r
472 //\r
473 // LBA Format\r
474 //\r
475 NVME_LBAFORMAT LbaFormat[16];\r
476\r
477 UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */\r
478 UINT8 VendorData[3712]; /* Vendor specific Data */\r
479} NVME_ADMIN_NAMESPACE_DATA;\r
480\r
481//\r
482// NvmExpress Admin Identify Cmd\r
483//\r
484typedef struct {\r
485 //\r
486 // CDW 10\r
487 //\r
488 UINT32 Cns:2;\r
489 UINT32 Rsvd1:30;\r
490} NVME_ADMIN_IDENTIFY;\r
491\r
492//\r
493// NvmExpress Admin Create I/O Completion Queue\r
494//\r
495typedef struct {\r
496 //\r
497 // CDW 10\r
498 //\r
499 UINT32 Qid:16; /* Queue Identifier */\r
500 UINT32 Qsize:16; /* Queue Size */\r
501\r
502 //\r
503 // CDW 11\r
504 //\r
505 UINT32 Pc:1; /* Physically Contiguous */\r
506 UINT32 Ien:1; /* Interrupts Enabled */\r
507 UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */\r
508 UINT32 Iv:16; /* Interrupt Vector */\r
509} NVME_ADMIN_CRIOCQ;\r
510\r
511//\r
512// NvmExpress Admin Create I/O Submission Queue\r
513//\r
514typedef struct {\r
515 //\r
516 // CDW 10\r
517 //\r
518 UINT32 Qid:16; /* Queue Identifier */\r
519 UINT32 Qsize:16; /* Queue Size */\r
520\r
521 //\r
522 // CDW 11\r
523 //\r
524 UINT32 Pc:1; /* Physically Contiguous */\r
525 UINT32 Qprio:2; /* Queue Priority */\r
526 UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */\r
527 UINT32 Cqid:16; /* Completion Queue ID */\r
528} NVME_ADMIN_CRIOSQ;\r
529\r
530//\r
531// NvmExpress Admin Delete I/O Completion Queue\r
532//\r
533typedef struct {\r
534 //\r
535 // CDW 10\r
536 //\r
537 UINT16 Qid;\r
538 UINT16 Rsvd1;\r
539} NVME_ADMIN_DEIOCQ;\r
540\r
541//\r
542// NvmExpress Admin Delete I/O Submission Queue\r
543//\r
544typedef struct {\r
545 //\r
546 // CDW 10\r
547 //\r
548 UINT16 Qid;\r
549 UINT16 Rsvd1;\r
550} NVME_ADMIN_DEIOSQ;\r
551\r
552//\r
553// NvmExpress Admin Security Send\r
554//\r
555typedef struct {\r
556 //\r
557 // CDW 10\r
558 //\r
559 UINT32 Resv:8; /* Reserve */\r
560 UINT32 Spsp:16; /* SP Specific */\r
561 UINT32 Secp:8; /* Security Protocol */\r
562\r
563 //\r
564 // CDW 11\r
565 //\r
566 UINT32 Tl; /* Transfer Length */\r
567} NVME_ADMIN_SECSEND;\r
568\r
569//\r
570// NvmExpress Admin Abort Command\r
571//\r
572typedef struct {\r
573 //\r
574 // CDW 10\r
575 //\r
576 UINT32 Sqid:16; /* Submission Queue identifier */\r
577 UINT32 Cid:16; /* Command Identifier */\r
578} NVME_ADMIN_ABORT;\r
579\r
580//\r
581// NvmExpress Admin Firmware Activate Command\r
582//\r
583typedef struct {\r
584 //\r
585 // CDW 10\r
586 //\r
587 UINT32 Fs:3; /* Submission Queue identifier */\r
588 UINT32 Aa:2; /* Command Identifier */\r
589 UINT32 Rsvd1:27;\r
590} NVME_ADMIN_FIRMWARE_ACTIVATE;\r
591\r
592//\r
593// NvmExpress Admin Firmware Image Download Command\r
594//\r
595typedef struct {\r
596 //\r
597 // CDW 10\r
598 //\r
599 UINT32 Numd; /* Number of Dwords */\r
600 //\r
601 // CDW 11\r
602 //\r
603 UINT32 Ofst; /* Offset */\r
604} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;\r
605\r
606//\r
607// NvmExpress Admin Get Features Command\r
608//\r
609typedef struct {\r
610 //\r
611 // CDW 10\r
612 //\r
613 UINT32 Fid:8; /* Feature Identifier */\r
614 UINT32 Sel:3; /* Select */\r
615 UINT32 Rsvd1:21;\r
616} NVME_ADMIN_GET_FEATURES;\r
617\r
618//\r
619// NvmExpress Admin Get Log Page Command\r
620//\r
621typedef struct {\r
622 //\r
623 // CDW 10\r
624 //\r
625 UINT32 Lid:8; /* Log Page Identifier */\r
626 #define LID_ERROR_INFO\r
627 #define LID_SMART_INFO\r
628 #define LID_FW_SLOT_INFO\r
629 UINT32 Rsvd1:8;\r
630 UINT32 Numd:12; /* Number of Dwords */\r
631 UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */\r
632} NVME_ADMIN_GET_LOG_PAGE;\r
633\r
634//\r
635// NvmExpress Admin Set Features Command\r
636//\r
637typedef struct {\r
638 //\r
639 // CDW 10\r
640 //\r
641 UINT32 Fid:8; /* Feature Identifier */\r
642 UINT32 Rsvd1:23;\r
643 UINT32 Sv:1; /* Save */\r
644} NVME_ADMIN_SET_FEATURES;\r
645\r
646//\r
647// NvmExpress Admin Format NVM Command\r
648//\r
649typedef struct {\r
650 //\r
651 // CDW 10\r
652 //\r
653 UINT32 Lbaf:4; /* LBA Format */\r
654 UINT32 Ms:1; /* Metadata Settings */\r
655 UINT32 Pi:3; /* Protection Information */\r
656 UINT32 Pil:1; /* Protection Information Location */\r
657 UINT32 Ses:3; /* Secure Erase Settings */\r
658 UINT32 Rsvd1:20;\r
659} NVME_ADMIN_FORMAT_NVM;\r
660\r
661//\r
662// NvmExpress Admin Security Receive Command\r
663//\r
664typedef struct {\r
665 //\r
666 // CDW 10\r
667 //\r
668 UINT32 Rsvd1:8;\r
669 UINT32 Spsp:16; /* SP Specific */\r
670 UINT32 Secp:8; /* Security Protocol */\r
671 //\r
672 // CDW 11\r
673 //\r
674 UINT32 Al; /* Allocation Length */\r
675} NVME_ADMIN_SECURITY_RECEIVE;\r
676\r
677//\r
678// NvmExpress Admin Security Send Command\r
679//\r
680typedef struct {\r
681 //\r
682 // CDW 10\r
683 //\r
684 UINT32 Rsvd1:8;\r
685 UINT32 Spsp:16; /* SP Specific */\r
686 UINT32 Secp:8; /* Security Protocol */\r
687 //\r
688 // CDW 11\r
689 //\r
690 UINT32 Tl; /* Transfer Length */\r
691} NVME_ADMIN_SECURITY_SEND;\r
692\r
693typedef union {\r
694 NVME_ADMIN_IDENTIFY Identify;\r
695 NVME_ADMIN_CRIOCQ CrIoCq;\r
696 NVME_ADMIN_CRIOSQ CrIoSq;\r
697 NVME_ADMIN_DEIOCQ DeIoCq;\r
698 NVME_ADMIN_DEIOSQ DeIoSq;\r
699 NVME_ADMIN_ABORT Abort;\r
700 NVME_ADMIN_FIRMWARE_ACTIVATE Activate;\r
701 NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;\r
702 NVME_ADMIN_GET_FEATURES GetFeatures;\r
703 NVME_ADMIN_GET_LOG_PAGE GetLogPage;\r
704 NVME_ADMIN_SET_FEATURES SetFeatures;\r
705 NVME_ADMIN_FORMAT_NVM FormatNvm;\r
706 NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;\r
707 NVME_ADMIN_SECURITY_SEND SecuritySend;\r
708} NVME_ADMIN_CMD;\r
709\r
710typedef struct {\r
711 UINT32 Cdw10;\r
712 UINT32 Cdw11;\r
713 UINT32 Cdw12;\r
714 UINT32 Cdw13;\r
715 UINT32 Cdw14;\r
716 UINT32 Cdw15;\r
717} NVME_RAW;\r
718\r
719typedef union {\r
720 NVME_ADMIN_CMD Admin; // Union of Admin commands\r
721 NVME_CMD Nvm; // Union of Nvm commands\r
722 NVME_RAW Raw;\r
723} NVME_PAYLOAD;\r
724\r
725//\r
726// Submission Queue\r
727//\r
728typedef struct {\r
729 //\r
730 // CDW 0, Common to all comnmands\r
731 //\r
732 UINT8 Opc; // Opcode\r
733 UINT8 Fuse:2; // Fused Operation\r
734 UINT8 Rsvd1:5;\r
735 UINT8 Psdt:1; // PRP or SGL for Data Transfer\r
736 UINT16 Cid; // Command Identifier\r
737\r
738 //\r
739 // CDW 1\r
740 //\r
741 UINT32 Nsid; // Namespace Identifier\r
742\r
743 //\r
744 // CDW 2,3\r
745 //\r
746 UINT64 Rsvd2;\r
747\r
748 //\r
749 // CDW 4,5\r
750 //\r
751 UINT64 Mptr; // Metadata Pointer\r
752\r
753 //\r
754 // CDW 6-9\r
755 //\r
756 UINT64 Prp[2]; // First and second PRP entries\r
757\r
758 NVME_PAYLOAD Payload;\r
759\r
760} NVME_SQ;\r
761\r
762//\r
763// Completion Queue\r
764//\r
765typedef struct {\r
766 //\r
767 // CDW 0\r
768 //\r
769 UINT32 Dword0;\r
770 //\r
771 // CDW 1\r
772 //\r
773 UINT32 Rsvd1;\r
774 //\r
775 // CDW 2\r
776 //\r
777 UINT16 Sqhd; // Submission Queue Head Pointer\r
778 UINT16 Sqid; // Submission Queue Identifier\r
779 //\r
780 // CDW 3\r
781 //\r
782 UINT16 Cid; // Command Identifier\r
783 UINT16 Pt:1; // Phase Tag\r
784 UINT16 Sc:8; // Status Code\r
785 UINT16 Sct:3; // Status Code Type\r
786 UINT16 Rsvd2:2;\r
787 UINT16 Mo:1; // More\r
788 UINT16 Dnr:1; // Retry\r
789} NVME_CQ;\r
790\r
791//\r
792// Nvm Express Admin cmd opcodes\r
793//\r
794#define NVME_ADMIN_DELIOSQ_OPC 0\r
795#define NVME_ADMIN_CRIOSQ_OPC 1\r
796#define NVME_ADMIN_DELIOCQ_OPC 4\r
797#define NVME_ADMIN_CRIOCQ_OPC 5\r
798#define NVME_ADMIN_IDENTIFY_OPC 6\r
799#define NVME_ADMIN_SECURITY_SEND_OPC 0x81\r
800#define NVME_ADMIN_SECURITY_RECV_OPC 0x82\r
801\r
802#define NVME_IO_FLUSH_OPC 0\r
803#define NVME_IO_WRITE_OPC 1\r
804#define NVME_IO_READ_OPC 2\r
805\r
806//\r
807// Offset from the beginning of private Data queue Buffer\r
808//\r
809#define NVME_ASQ_BUF_OFFSET EFI_PAGE_SIZE\r
810\r
811#pragma pack()\r
812\r
813#endif\r
814\r
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