[mirror_edk2.git] / SourceLevelDebugPkg / Library / DebugAgent / DebugAgentCommon / Ia32 / ArchRegisters.h

/** @file\r
  IA32 register defintions needed by debug transfer protocol.\r
\r
  Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _ARCH_REGISTERS_H_\r
#define _ARCH_REGISTERS_H_\r
\r
///\r
/// FXSAVE_STATE\r
/// FP / MMX / XMM registers (see fxrstor instruction definition)\r
///\r
typedef struct {\r
  UINT16  Fcw;\r
  UINT16  Fsw;\r
  UINT16  Ftw;\r
  UINT16  Opcode;\r
  UINT32  Eip;\r
  UINT16  Cs;\r
  UINT16  Reserved1;\r
  UINT32  DataOffset;\r
  UINT16  Ds;\r
  UINT8   Reserved2[2];\r
  UINT32  Mxcsr;\r
  UINT32  Mxcsr_Mask;\r
  UINT8   St0Mm0[10];\r
  UINT8   Reserved3[6];\r
  UINT8   St1Mm1[10];\r
  UINT8   Reserved4[6];\r
  UINT8   St2Mm2[10];\r
  UINT8   Reserved5[6];\r
  UINT8   St3Mm3[10];\r
  UINT8   Reserved6[6];\r
  UINT8   St4Mm4[10];\r
  UINT8   Reserved7[6];\r
  UINT8   St5Mm5[10];\r
  UINT8   Reserved8[6];\r
  UINT8   St6Mm6[10];\r
  UINT8   Reserved9[6];\r
  UINT8   St7Mm7[10];\r
  UINT8   Reserved10[6];\r
  UINT8   Xmm0[16];\r
  UINT8   Xmm1[16];\r
  UINT8   Xmm2[16];\r
  UINT8   Xmm3[16];\r
  UINT8   Xmm4[16];\r
  UINT8   Xmm5[16];\r
  UINT8   Xmm6[16];\r
  UINT8   Xmm7[16];\r
  UINT8   Reserved11[14 * 16];\r
} DEBUG_DATA_IA32_FX_SAVE_STATE;\r
\r
///\r
///  IA-32 processor context definition\r
///\r
typedef struct {\r
  DEBUG_DATA_IA32_FX_SAVE_STATE  FxSaveState;\r
  UINT32                         Dr0;\r
  UINT32                         Dr1;\r
  UINT32                         Dr2;\r
  UINT32                         Dr3;\r
  UINT32                         Dr6;\r
  UINT32                         Dr7;\r
  UINT32                         Eflags;\r
  UINT32                         Ldtr;\r
  UINT32                         Tr;\r
  UINT32                         Gdtr[2];\r
  UINT32                         Idtr[2];\r
  UINT32                         Eip;\r
  UINT32                         Gs;\r
  UINT32                         Fs;\r
  UINT32                         Es;\r
  UINT32                         Ds;\r
  UINT32                         Cs;\r
  UINT32                         Ss;\r
  UINT32                         Cr0;\r
  UINT32                         Cr1;  ///< Reserved\r
  UINT32                         Cr2;\r
  UINT32                         Cr3;\r
  UINT32                         Cr4;\r
  UINT32                         Edi;\r
  UINT32                         Esi;\r
  UINT32                         Ebp;\r
  UINT32                         Esp;\r
  UINT32                         Edx;\r
  UINT32                         Ecx;\r
  UINT32                         Ebx;\r
  UINT32                         Eax;\r
} DEBUG_DATA_IA32_SYSTEM_CONTEXT;\r
\r
///\r
///  IA32 GROUP register\r
///\r
typedef struct {\r
  UINT16         Cs;\r
  UINT16         Ds;\r
  UINT16         Es;\r
  UINT16         Fs;\r
  UINT16         Gs;\r
  UINT16         Ss;\r
  UINT32         Eflags;\r
  UINT32         Ebp;\r
  UINT32         Eip;\r
  UINT32         Esp;\r
  UINT32         Eax;\r
  UINT32         Ebx;\r
  UINT32         Ecx;\r
  UINT32         Edx;\r
  UINT32         Esi;\r
  UINT32         Edi;\r
  UINT32         Dr0;\r
  UINT32         Dr1;\r
  UINT32         Dr2;\r
  UINT32         Dr3;\r
  UINT32         Dr6;\r
  UINT32         Dr7;\r
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_IA32;\r
\r
///\r
///  IA32 Segment Limit GROUP register\r
///\r
typedef struct {\r
  UINT32         CsLim;\r
  UINT32         SsLim;\r
  UINT32         GsLim;\r
  UINT32         FsLim;\r
  UINT32         EsLim;\r
  UINT32         DsLim;\r
  UINT32         LdtLim;\r
  UINT32         TssLim;\r
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM_IA32;\r
\r
///\r
///  IA32 Segment Base GROUP register\r
///\r
typedef struct {\r
  UINT32         CsBas;\r
  UINT32         SsBas;\r
  UINT32         GsBas;\r
  UINT32         FsBas;\r
  UINT32         EsBas;\r
  UINT32         DsBas;\r
  UINT32         LdtBas;\r
  UINT32         TssBas;\r
} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE_IA32;\r
\r
#endif\r
Commit	Line	Data
18b144ea	1	/** @file\r
	2	IA32 register defintions needed by debug transfer protocol.\r
	3	\r
	4	Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
	5	This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php.\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	#ifndef _ARCH_REGISTERS_H_\r
	16	#define _ARCH_REGISTERS_H_\r
	17	\r
	18	///\r
	19	/// FXSAVE_STATE\r
	20	/// FP / MMX / XMM registers (see fxrstor instruction definition)\r
	21	///\r
	22	typedef struct {\r
	23	UINT16 Fcw;\r
	24	UINT16 Fsw;\r
	25	UINT16 Ftw;\r
	26	UINT16 Opcode;\r
	27	UINT32 Eip;\r
	28	UINT16 Cs;\r
	29	UINT16 Reserved1;\r
	30	UINT32 DataOffset;\r
	31	UINT16 Ds;\r
	32	UINT8 Reserved2[2];\r
	33	UINT32 Mxcsr;\r
	34	UINT32 Mxcsr_Mask;\r
	35	UINT8 St0Mm0[10];\r
	36	UINT8 Reserved3[6];\r
	37	UINT8 St1Mm1[10];\r
	38	UINT8 Reserved4[6];\r
	39	UINT8 St2Mm2[10];\r
	40	UINT8 Reserved5[6];\r
	41	UINT8 St3Mm3[10];\r
	42	UINT8 Reserved6[6];\r
	43	UINT8 St4Mm4[10];\r
	44	UINT8 Reserved7[6];\r
	45	UINT8 St5Mm5[10];\r
	46	UINT8 Reserved8[6];\r
	47	UINT8 St6Mm6[10];\r
	48	UINT8 Reserved9[6];\r
	49	UINT8 St7Mm7[10];\r
	50	UINT8 Reserved10[6];\r
	51	UINT8 Xmm0[16];\r
	52	UINT8 Xmm1[16];\r
	53	UINT8 Xmm2[16];\r
	54	UINT8 Xmm3[16];\r
	55	UINT8 Xmm4[16];\r
	56	UINT8 Xmm5[16];\r
	57	UINT8 Xmm6[16];\r
	58	UINT8 Xmm7[16];\r
	59	UINT8 Reserved11[14 * 16];\r
	60	} DEBUG_DATA_IA32_FX_SAVE_STATE;\r
	61	\r
	62	///\r
	63	/// IA-32 processor context definition\r
	64	///\r
65	typedef struct {\r
66	DEBUG_DATA_IA32_FX_SAVE_STATE FxSaveState;\r
67	UINT32 Dr0;\r
68	UINT32 Dr1;\r
69	UINT32 Dr2;\r
70	UINT32 Dr3;\r
71	UINT32 Dr6;\r
72	UINT32 Dr7;\r
73	UINT32 Eflags;\r
74	UINT32 Ldtr;\r
75	UINT32 Tr;\r
76	UINT32 Gdtr[2];\r
77	UINT32 Idtr[2];\r
78	UINT32 Eip;\r
79	UINT32 Gs;\r
80	UINT32 Fs;\r
81	UINT32 Es;\r
82	UINT32 Ds;\r
83	UINT32 Cs;\r
84	UINT32 Ss;\r
85	UINT32 Cr0;\r
86	UINT32 Cr1; ///< Reserved\r
87	UINT32 Cr2;\r
88	UINT32 Cr3;\r
89	UINT32 Cr4;\r
90	UINT32 Edi;\r
91	UINT32 Esi;\r
92	UINT32 Ebp;\r
93	UINT32 Esp;\r
94	UINT32 Edx;\r
95	UINT32 Ecx;\r
96	UINT32 Ebx;\r
97	UINT32 Eax;\r
98	} DEBUG_DATA_IA32_SYSTEM_CONTEXT;\r
99	\r
100	///\r
101	/// IA32 GROUP register\r
102	///\r
103	typedef struct {\r
104	UINT16 Cs;\r
105	UINT16 Ds;\r
106	UINT16 Es;\r
107	UINT16 Fs;\r
108	UINT16 Gs;\r
109	UINT16 Ss;\r
110	UINT32 Eflags;\r
111	UINT32 Ebp;\r
112	UINT32 Eip;\r
113	UINT32 Esp;\r
114	UINT32 Eax;\r
115	UINT32 Ebx;\r
116	UINT32 Ecx;\r
117	UINT32 Edx;\r
118	UINT32 Esi;\r
119	UINT32 Edi;\r
120	UINT32 Dr0;\r
121	UINT32 Dr1;\r
122	UINT32 Dr2;\r
123	UINT32 Dr3;\r
124	UINT32 Dr6;\r
125	UINT32 Dr7;\r
126	} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_IA32;\r
127	\r
128	///\r
129	/// IA32 Segment Limit GROUP register\r
130	///\r
131	typedef struct {\r
132	UINT32 CsLim;\r
133	UINT32 SsLim;\r
134	UINT32 GsLim;\r
135	UINT32 FsLim;\r
136	UINT32 EsLim;\r
137	UINT32 DsLim;\r
138	UINT32 LdtLim;\r
139	UINT32 TssLim;\r
140	} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGLIM_IA32;\r
141	\r
142	///\r
143	/// IA32 Segment Base GROUP register\r
144	///\r
145	typedef struct {\r
146	UINT32 CsBas;\r
147	UINT32 SsBas;\r
148	UINT32 GsBas;\r
149	UINT32 FsBas;\r
150	UINT32 EsBas;\r
151	UINT32 DsBas;\r
152	UINT32 LdtBas;\r
153	UINT32 TssBas;\r
154	} DEBUG_DATA_REPONSE_READ_REGISTER_GROUP_SEGBASE_IA32;\r
155	\r
156	#endif\r