[mirror_edk2.git] / SourceLevelDebugPkg / Library / DebugCommunicationLibUsb3 / DebugCommunicationLibUsb3Internal.h

/** @file\r
  Debug Port Library implementation based on usb3 debug port.\r
\r
  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __USB3_DEBUG_PORT_LIB_INTERNAL__\r
#define __USB3_DEBUG_PORT_LIB_INTERNAL__\r
\r
#include <Uefi.h>\r
#include <Base.h>\r
#include <IndustryStandard/Usb.h>\r
#include <Library/IoLib.h>\r
#include <IndustryStandard/Pci.h>\r
#include <Library/PcdLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/TimerLib.h>\r
#include <Library/DebugCommunicationLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/SerialPortLib.h>      // Todo: remove in future\r
\r
//\r
// Internal serial debug - remove finally\r
//\r
#include <Library/SerialPortLib.h>\r
#include <Library/PrintLib.h>\r
\r
//\r
// USB Debug GUID value\r
//\r
#define USB3_DBG_GUID \\r
    { \\r
      0xb2a56f4d, 0x9177, 0x4fc8, { 0xa6, 0x77, 0xdd, 0x96, 0x3e, 0xb4, 0xcb, 0x1b } \\r
    }\r
\r
//\r
// The state machine of usb debug port\r
//\r
#define USB3DBG_NO_DBG_CAB    0   // The XHCI host controller does not support debug capability\r
#define USB3DBG_DBG_CAB       1   // The XHCI host controller supports debug capability\r
#define USB3DBG_ENABLED       2   // The XHCI debug device is enabled\r
#define USB3DBG_NOT_ENABLED   4   // The XHCI debug device is not enabled\r
\r
#define USB3_DEBUG_PORT_MAX_PACKET_SIZE 0x08\r
\r
#define XHCI_DEBUG_DEVICE_VENDOR_ID   0x0525\r
#define XHCI_DEBUG_DEVICE_PRODUCT_ID  0x127A\r
#define XHCI_DEBUG_DEVICE_PROTOCOL    0xFF\r
#define XHCI_DEBUG_DEVICE_REVISION    0x00\r
\r
#define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL\r
#define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000\r
\r
#define PCI_CAPABILITY_ID_DEBUG_PORT  0x0A\r
#define XHC_HCCPARAMS_OFFSET          0x10\r
#define XHC_CAPABILITY_ID_MASK        0xFF\r
#define XHC_NEXT_CAPABILITY_MASK      0xFF00\r
\r
#define XHC_HCSPARAMS1_OFFSET         0x4    // Structural Parameters 1\r
#define XHC_USBCMD_OFFSET             0x0    // USB Command Register Offset\r
#define XHC_USBSTS_OFFSET             0x4    // USB Status Register Offset\r
#define XHC_PORTSC_OFFSET             0x400  // Port Status and Control Register Offset\r
\r
#define XHC_USBCMD_RUN                BIT0  // Run/Stop\r
#define XHC_USBCMD_RESET              BIT1  // Host Controller Reset\r
\r
#define XHC_USBSTS_HALT               BIT0\r
\r
//\r
// Transfer the data of 8 bytes each time\r
//\r
#define XHC_DEBUG_PORT_DATA_LENGTH   8\r
\r
//\r
// Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.\r
//\r
#define DATA_TRANSFER_WRITE_TIMEOUT      0\r
#define DATA_TRANSFER_READ_TIMEOUT       50000\r
#define DATA_TRANSFER_POLL_TIMEOUT       1000\r
\r
//\r
// XHCI port power off/on delay\r
//\r
#define XHC_DEBUG_PORT_ON_OFF_DELAY    100000\r
\r
//\r
// USB debug device string descritpor (header size + unicode string length)\r
//\r
#define STRING0_DESC_LEN      4\r
#define MANU_DESC_LEN         12\r
#define PRODUCT_DESC_LEN      40\r
#define SERIAL_DESC_LEN       4\r
\r
//\r
// Debug Capability Register Offset\r
//\r
#define XHC_DC_DCID                  0x0\r
#define XHC_DC_DCDB                  0x4\r
#define XHC_DC_DCERSTSZ              0x8\r
#define XHC_DC_DCERSTBA              0x10\r
#define XHC_DC_DCERDP                0x18\r
#define XHC_DC_DCCTRL                0x20\r
#define XHC_DC_DCST                  0x24\r
#define XHC_DC_DCPORTSC              0x28\r
#define XHC_DC_DCCP                  0x30\r
#define XHC_DC_DCDDI1                0x38\r
#define XHC_DC_DCDDI2                0x3C\r
\r
#define TRB_TYPE_LINK                6\r
\r
#define ERST_NUMBER                  0x01\r
#define TR_RING_TRB_NUMBER           0x100\r
#define EVENT_RING_TRB_NUMBER        0x200\r
\r
#define ED_BULK_OUT                  2\r
#define ED_BULK_IN                   6\r
\r
#define XHC_LOW_32BIT(Addr64)          ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))\r
#define XHC_HIGH_32BIT(Addr64)         ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))\r
#define XHC_BIT_IS_SET(Data, Bit)      ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
\r
//\r
// Endpoint Type (EP Type).\r
//\r
#define ED_NOT_VALID                          0\r
#define ED_ISOCH_OUT                          1\r
#define ED_BULK_OUT                           2\r
#define ED_INTERRUPT_OUT                      3\r
#define ED_CONTROL_BIDIR                      4\r
#define ED_ISOCH_IN                           5\r
#define ED_BULK_IN                            6\r
#define ED_INTERRUPT_IN                       7\r
\r
//\r
// 6.4.5 TRB Completion Codes\r
//\r
#define TRB_COMPLETION_INVALID                0\r
#define TRB_COMPLETION_SUCCESS                1\r
#define TRB_COMPLETION_DATA_BUFFER_ERROR      2\r
#define TRB_COMPLETION_BABBLE_ERROR           3\r
#define TRB_COMPLETION_USB_TRANSACTION_ERROR  4\r
#define TRB_COMPLETION_TRB_ERROR              5\r
#define TRB_COMPLETION_STALL_ERROR            6\r
#define TRB_COMPLETION_SHORT_PACKET           13\r
\r
//\r
// 6.4.6 TRB Types\r
//\r
#define TRB_TYPE_NORMAL                       1\r
#define TRB_TYPE_SETUP_STAGE                  2\r
#define TRB_TYPE_DATA_STAGE                   3\r
#define TRB_TYPE_STATUS_STAGE                 4\r
#define TRB_TYPE_ISOCH                        5\r
#define TRB_TYPE_LINK                         6\r
#define TRB_TYPE_EVENT_DATA                   7\r
#define TRB_TYPE_NO_OP                        8\r
#define TRB_TYPE_EN_SLOT                      9\r
#define TRB_TYPE_DIS_SLOT                     10\r
#define TRB_TYPE_ADDRESS_DEV                  11\r
#define TRB_TYPE_CON_ENDPOINT                 12\r
#define TRB_TYPE_EVALU_CONTXT                 13\r
#define TRB_TYPE_RESET_ENDPOINT               14\r
#define TRB_TYPE_STOP_ENDPOINT                15\r
#define TRB_TYPE_SET_TR_DEQUE                 16\r
#define TRB_TYPE_RESET_DEV                    17\r
#define TRB_TYPE_GET_PORT_BANW                21\r
#define TRB_TYPE_FORCE_HEADER                 22\r
#define TRB_TYPE_NO_OP_COMMAND                23\r
#define TRB_TYPE_TRANS_EVENT                  32\r
#define TRB_TYPE_COMMAND_COMPLT_EVENT         33\r
#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT     34\r
#define TRB_TYPE_HOST_CONTROLLER_EVENT        37\r
#define TRB_TYPE_DEVICE_NOTIFI_EVENT          38\r
#define TRB_TYPE_MFINDEX_WRAP_EVENT           39\r
\r
//\r
// Convert millisecond to microsecond.\r
//\r
#define XHC_1_MILLISECOND                     (1000)\r
#define XHC_POLL_DELAY                        (1000)\r
#define XHC_GENERIC_TIMEOUT                   (10 * 1000)\r
\r
#define EFI_USB_SPEED_FULL                    0x0000  ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.\r
#define EFI_USB_SPEED_LOW                     0x0001  ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.\r
#define EFI_USB_SPEED_HIGH                    0x0002  ///< 480 Mb/s, USB 2.0 EHCI HC.\r
#define EFI_USB_SPEED_SUPER                   0x0003  ///< 4.8 Gb/s, USB 3.0 XHCI HC.\r
\r
//\r
// Transfer types, used in URB to identify the transfer type\r
//\r
#define XHC_CTRL_TRANSFER                     0x01\r
#define XHC_BULK_TRANSFER                     0x02\r
#define XHC_INT_TRANSFER_SYNC                 0x04\r
#define XHC_INT_TRANSFER_ASYNC                0x08\r
#define XHC_INT_ONLY_TRANSFER_ASYNC           0x10\r
\r
//\r
// USB Transfer Results\r
//\r
#define EFI_USB_NOERROR             0x00\r
#define EFI_USB_ERR_NOTEXECUTE      0x01\r
#define EFI_USB_ERR_STALL           0x02\r
#define EFI_USB_ERR_BUFFER          0x04\r
#define EFI_USB_ERR_BABBLE          0x08\r
#define EFI_USB_ERR_NAK             0x10\r
#define EFI_USB_ERR_CRC             0x20\r
#define EFI_USB_ERR_TIMEOUT         0x40\r
#define EFI_USB_ERR_BITSTUFF        0x80\r
#define EFI_USB_ERR_SYSTEM          0x100\r
\r
#pragma pack(1)\r
\r
//\r
// 7.6.9 OUT/IN EP Context: 64 bytes\r
// 7.6.9.2 When used by the DbC it is always a 64 byte data structure\r
//\r
typedef struct _ENDPOINT_CONTEXT_64 {\r
  UINT32                  EPState:3;\r
  UINT32                  RsvdZ1:5;\r
  UINT32                  Mult:2;         // set to 0\r
  UINT32                  MaxPStreams:5;  // set to 0\r
  UINT32                  LSA:1;          // set to 0\r
  UINT32                  Interval:8;     // set to 0\r
  UINT32                  RsvdZ2:8;\r
\r
  UINT32                  RsvdZ3:1;\r
  UINT32                  CErr:2;\r
  UINT32                  EPType:3;\r
  UINT32                  RsvdZ4:1;\r
  UINT32                  HID:1;          // set to 0\r
  UINT32                  MaxBurstSize:8;\r
  UINT32                  MaxPacketSize:16;\r
\r
  UINT32                  PtrLo;\r
\r
  UINT32                  PtrHi;\r
\r
  UINT32                  AverageTRBLength:16;\r
  UINT32                  MaxESITPayload:16;  // set to 0\r
\r
  UINT32                  RsvdZ5;             // Reserved\r
  UINT32                  RsvdZ6;\r
  UINT32                  RsvdZ7;\r
  \r
  UINT32                  RsvdZ8;\r
  UINT32                  RsvdZ9;\r
  UINT32                  RsvdZ10;\r
  UINT32                  RsvdZ11;\r
  \r
  UINT32                  RsvdZ12;\r
  UINT32                  RsvdZ13;\r
  UINT32                  RsvdZ14;\r
  UINT32                  RsvdZ15;\r
} ENDPOINT_CONTEXT_64;\r
\r
//\r
// 6.4.1.1 Normal TRB: 16 bytes\r
// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r
// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r
// Rings, and to define the Data stage information for Control Transfer Rings.\r
//\r
typedef struct _TRANSFER_TRB_NORMAL {\r
  UINT32                  TRBPtrLo;\r
\r
  UINT32                  TRBPtrHi;\r
\r
  UINT32                  Length:17;\r
  UINT32                  TDSize:5;\r
  UINT32                  IntTarget:10;\r
\r
  UINT32                  CycleBit:1;\r
  UINT32                  ENT:1;\r
  UINT32                  ISP:1;\r
  UINT32                  NS:1;\r
  UINT32                  CH:1;\r
  UINT32                  IOC:1;\r
  UINT32                  IDT:1;\r
  UINT32                  RsvdZ1:2;\r
  UINT32                  BEI:1;\r
  UINT32                  Type:6;\r
  UINT32                  RsvdZ2:16;\r
} TRANSFER_TRB_NORMAL;\r
\r
//\r
// 6.4.2.1 Transfer Event TRB: 16 bytes\r
// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r
// for more information on the use and operation of Transfer Events.\r
//\r
typedef struct _EVT_TRB_TRANSFER {\r
  UINT32                  TRBPtrLo;\r
\r
  UINT32                  TRBPtrHi;\r
\r
  UINT32                  Length:24;\r
  UINT32                  Completecode:8;\r
\r
  UINT32                  CycleBit:1;\r
  UINT32                  RsvdZ1:1;\r
  UINT32                  ED:1;\r
  UINT32                  RsvdZ2:7;\r
  UINT32                  Type:6;\r
  UINT32                  EndpointId:5;\r
  UINT32                  RsvdZ3:3;\r
  UINT32                  SlotId:8;\r
} EVT_TRB_TRANSFER;\r
\r
//\r
// 6.4.4.1 Link TRB: 16 bytes\r
// A Link TRB provides support for non-contiguous TRB Rings.\r
//\r
typedef struct _LINK_TRB {\r
  UINT32                  PtrLo;\r
\r
  UINT32                  PtrHi;\r
\r
  UINT32                  RsvdZ1:22;\r
  UINT32                  InterTarget:10;\r
\r
  UINT32                  CycleBit:1;\r
  UINT32                  TC:1;\r
  UINT32                  RsvdZ2:2;\r
  UINT32                  CH:1;\r
  UINT32                  IOC:1;\r
  UINT32                  RsvdZ3:4;\r
  UINT32                  Type:6;\r
  UINT32                  RsvdZ4:16;\r
} LINK_TRB;\r
\r
//\r
// TRB Template: 16 bytes\r
//\r
typedef struct _TRB_TEMPLATE {\r
  UINT32                    Parameter1;\r
\r
  UINT32                    Parameter2;\r
\r
  UINT32                    Status;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    RsvdZ1:9;\r
  UINT32                    Type:6;\r
  UINT32                    Control:16;\r
} TRB_TEMPLATE;\r
\r
//\r
// Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes\r
//\r
typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r
  UINT32                  PtrLo;\r
  UINT32                  PtrHi;\r
  UINT32                  RingTrbSize:16;\r
  UINT32                  RsvdZ1:16;\r
  UINT32                  RsvdZ2;\r
} EVENT_RING_SEG_TABLE_ENTRY;\r
\r
//\r
// Size: 40 bytes\r
//\r
typedef struct _EVENT_RING {\r
  EFI_PHYSICAL_ADDRESS      ERSTBase;\r
  EFI_PHYSICAL_ADDRESS      EventRingSeg0;\r
  UINT32                    TrbNumber;\r
  EFI_PHYSICAL_ADDRESS      EventRingEnqueue;\r
  EFI_PHYSICAL_ADDRESS      EventRingDequeue;\r
  UINT32                    EventRingCCS;\r
} EVENT_RING;\r
\r
// Size: 32 bytes\r
typedef struct _TRANSFER_RING {\r
  EFI_PHYSICAL_ADDRESS      RingSeg0;\r
  UINT32                    TrbNumber;\r
  EFI_PHYSICAL_ADDRESS      RingEnqueue;\r
  EFI_PHYSICAL_ADDRESS      RingDequeue;\r
  UINT32                    RingPCS;\r
} TRANSFER_RING;\r
\r
//\r
// Size: 64 bytes\r
//\r
typedef struct _DBC_INFO_CONTEXT {\r
  UINT64        String0DescAddress;\r
  UINT64        ManufacturerStrDescAddress;\r
  UINT64        ProductStrDescAddress;\r
  UINT64        SerialNumberStrDescAddress;\r
  UINT64        String0Length:8;\r
  UINT64        ManufacturerStrLength:8;\r
  UINT64        ProductStrLength:8;\r
  UINT64        SerialNumberStrLength:8;\r
  UINT64        RsvdZ1:32;\r
  UINT64        RsvdZ2;\r
  UINT64        RsvdZ3;\r
  UINT64        RsvdZ4;  \r
} DBC_INFO_CONTEXT;\r
\r
//\r
// Debug Capability Context Data Structure: 192 bytes\r
//\r
typedef struct _XHC_DC_CONTEXT {\r
  DBC_INFO_CONTEXT      DbcInfoContext;\r
  ENDPOINT_CONTEXT_64   EpOutContext;\r
  ENDPOINT_CONTEXT_64   EpInContext;\r
} XHC_DC_CONTEXT;\r
\r
//\r
// Size: 16 bytes\r
//\r
typedef union _TRB {\r
  TRB_TEMPLATE                TrbTemplate;\r
  TRANSFER_TRB_NORMAL         TrbNormal;\r
} TRB;\r
\r
///\r
/// USB data transfer direction\r
///\r
typedef enum {\r
  EfiUsbDataIn,\r
  EfiUsbDataOut,\r
  EfiUsbNoData\r
} EFI_USB_DATA_DIRECTION;\r
\r
//\r
// URB (Usb Request Block) contains information for all kinds of\r
// usb requests.\r
//\r
typedef struct _URB {\r
  //\r
  // Transfer data buffer\r
  //\r
  EFI_PHYSICAL_ADDRESS            Data;\r
  UINT32                          DataLen;\r
\r
  //\r
  // Execute result\r
  //\r
  UINT32                          Result;\r
  //\r
  // Completed data length\r
  //\r
  UINT32                          Completed;\r
  //\r
  // Tranfer Ring info\r
  //\r
  EFI_PHYSICAL_ADDRESS            Ring;\r
  EFI_PHYSICAL_ADDRESS            Trb;\r
  BOOLEAN                         Finished;\r
  EFI_USB_DATA_DIRECTION          Direction;\r
} URB;\r
\r
typedef struct _USB3_DEBUG_PORT_INSTANCE {\r
  UINT8                                   Initialized;\r
\r
  //\r
  // The flag indicates debug device is ready\r
  //\r
  BOOLEAN                                 DebugSupport;\r
  \r
  //\r
  // The flag indicates debug device is ready\r
  //\r
  BOOLEAN                                 Ready;\r
\r
  //\r
  // The flag indicates if USB 3.0 ports has been turn off/on power\r
  //  \r
  BOOLEAN                                 ChangePortPower;\r
\r
  //\r
  // XHCI MMIO Base address\r
  //\r
  EFI_PHYSICAL_ADDRESS                    XhciMmioBase;\r
\r
  //\r
  // XHCI OP RegisterBase address\r
  //  \r
  EFI_PHYSICAL_ADDRESS                    XhciOpRegister;\r
  \r
  //\r
  // XHCI Debug Register Base Address\r
  //\r
  EFI_PHYSICAL_ADDRESS                    DebugCapabilityBase;\r
  \r
  //\r
  // XHCI Debug Capability offset\r
  //\r
  UINT64                                  DebugCapabilityOffset;  \r
  \r
  //\r
  // XHCI Debug Context Address\r
  //\r
  EFI_PHYSICAL_ADDRESS                    DebugCapabilityContext;\r
  \r
  //\r
  // Transfer Ring\r
  //\r
  TRANSFER_RING                           TransferRingOut;\r
  TRANSFER_RING                           TransferRingIn;\r
\r
  //\r
  // EventRing\r
  //\r
  EVENT_RING                              EventRing;\r
  \r
  //\r
  // URB - Read\r
  //\r
  URB                                     UrbOut;\r
\r
  //\r
  // URB - Write\r
  //\r
  URB                                     UrbIn;\r
\r
  //\r
  // The available data length in the following data buffer.\r
  //\r
  UINT8                                   DataCount;\r
  //\r
  // The data buffer. Maximum length is 8 bytes.\r
  //\r
  UINT8                                   Data[8];\r
  //\r
  // Timter settings\r
  //\r
  UINT64                                  TimerFrequency;\r
  UINT64                                  TimerCycle;\r
  BOOLEAN                                 TimerCountDown;\r
\r
} USB3_DEBUG_PORT_HANDLE;\r
\r
#pragma pack()\r
\r
/**\r
  Read XHCI debug register.\r
\r
 @param  Handle        Debug port handle.\r
  @param  Offset       The offset of the debug register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadDebugReg (\r
  IN  USB3_DEBUG_PORT_HANDLE    *Handle,\r
  IN  UINT32                      Offset\r
  );\r
\r
/**\r
  Set one bit of the debug register while keeping other bits.\r
\r
  @param  Handle       Debug port handle.\r
  @param  Offset       The offset of the debug register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetDebugRegBit (\r
  IN USB3_DEBUG_PORT_HANDLE  *Handle,\r
  IN UINT32                   Offset,\r
  IN UINT32                   Bit\r
  );\r
  \r
/**\r
  Write the data to the debug register.\r
\r
  @param  Handle       Debug port handle.\r
  @param  Offset       The offset of the debug register.\r
  @param  Data         The data to write.\r
\r
**/  \r
VOID\r
XhcWriteDebugReg (\r
  IN USB3_DEBUG_PORT_HANDLE     *Handle,\r
  IN UINT32                     Offset,\r
  IN UINT32                     Data\r
  );\r
\r
/**\r
  Discover the USB3 debug device.\r
  \r
  @param  Handle                Debug port handle.\r
  \r
  @retval RETURN_SUCCESS        The serial device was initialized.\r
  @retval RETURN_DEVICE_ERROR   The serial device could not be initialized.\r
\r
**/\r
RETURN_STATUS\r
DiscoverUsb3DebugPort(\r
  USB3_DEBUG_PORT_HANDLE  *Handle\r
  );\r
  \r
/**\r
  Initialize the Serial Device hardware.\r
  \r
  @param  Handle            Debug port handle.\r
\r
  @retval RETURN_SUCCESS    The serial device was initialized successfully.\r
  @retval !RETURN_SUCCESS   Error.\r
\r
**/\r
RETURN_STATUS\r
InitializeUsb3DebugPort (\r
  USB3_DEBUG_PORT_HANDLE  *Handle\r
  );\r
\r
/**\r
  Return XHCI MMIO base address.\r
\r
**/\r
EFI_PHYSICAL_ADDRESS\r
GetXhciBaseAddress (\r
  VOID\r
  );\r
\r
/**\r
  Verifies if the bit positions specified by a mask are set in a register.\r
\r
  @param[in, out] Register    UNITN register\r
  @param[in]      BitMask     32-bit mask\r
\r
  @return  BOOLEAN  - TRUE  if all bits specified by the mask are enabled.\r
                    - FALSE even if one of the bits specified by the mask \r
                            is not enabled.\r
**/\r
BOOLEAN\r
XhcIsBitSet(\r
  UINTN   Register, \r
  UINT32  BitMask\r
  );\r
\r
/**\r
  Sets bits as per the enabled bit positions in the mask.\r
\r
  @param[in, out] Register    UINTN register\r
  @param[in]      BitMask     32-bit mask\r
**/\r
VOID\r
XhcSetR32Bit(\r
  UINTN   Register, \r
  UINT32  BitMask\r
  );\r
\r
/**\r
  Clears bits as per the enabled bit positions in the mask.\r
\r
  @param[in, out] Register    UINTN register\r
  @param[in]      BitMask     32-bit mask\r
**/\r
VOID\r
XhcClearR32Bit(\r
  IN OUT  UINTN  Register, \r
  IN      UINT32 BitMask\r
  );\r
\r
/**\r
  Initialize USB3 debug port.\r
  \r
  This method invokes various internal functions to facilitate\r
  detection and initialization of USB3 debug port.\r
\r
  @retval RETURN_SUCCESS        The serial device was initialized.\r
**/\r
RETURN_STATUS\r
EFIAPI\r
USB3Initialize (\r
  VOID\r
  );\r
\r
/**\r
  Return command register value in XHCI controller.\r
\r
**/\r
UINT16\r
GetXhciPciCommand (\r
  VOID\r
  );\r
\r
/**\r
  Allocate aligned memory for XHC's usage.\r
\r
  @param  BufferSize      The size, in bytes, of the Buffer.\r
  \r
  @return A pointer to the allocated buffer or NULL if allocation fails.\r
\r
**/\r
VOID*\r
AllocateAlignBuffer (\r
  IN UINTN                    BufferSize\r
  );\r
\r
/**\r
  The real function to initialize USB3 debug port.\r
  \r
  This method invokes various internal functions to facilitate\r
  detection and initialization of USB3 debug port.\r
\r
  @retval RETURN_SUCCESS        The serial device was initialized.\r
**/\r
RETURN_STATUS\r
EFIAPI\r
USB3InitializeReal (\r
  VOID\r
  );\r
\r
/**\r
  Submits bulk transfer to a bulk endpoint of a USB device.\r
\r
  @param  Handle                The instance of debug device.\r
  @param  Direction             The direction of data transfer.\r
  @param  Data                  Array of pointers to the buffers of data to transmit\r
                                from or receive into.\r
  @param  DataLength            The lenght of the data buffer.\r
  @param  Timeout               Indicates the maximum time, in millisecond, which\r
                                the transfer is allowed to complete.\r
\r
  @retval EFI_SUCCESS           The transfer was completed successfully.\r
  @retval EFI_OUT_OF_RESOURCES  The transfer failed due to lack of resource.\r
  @retval EFI_INVALID_PARAMETER Some parameters are invalid.\r
  @retval EFI_TIMEOUT           The transfer failed due to timeout.\r
  @retval EFI_DEVICE_ERROR      The transfer failed due to host controller error.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
XhcDataTransfer (\r
  IN     USB3_DEBUG_PORT_HANDLE              *Handle,\r
  IN     EFI_USB_DATA_DIRECTION              Direction,\r
  IN OUT VOID                                *Data,\r
  IN OUT UINTN                               *DataLength,\r
  IN     UINTN                               Timeout\r
  );\r
\r
/**\r
  Check if the timer is timeout.\r
  \r
  @param[in] UsbDebugPortHandle  Pointer to USB Debug port handle\r
  @param[in] Timer               The start timer from the begin.\r
  @param[in] TimeoutTicker       Ticker number need time out.\r
\r
  @return TRUE  Timer time out occurs.\r
  @retval FALSE Timer does not time out.\r
\r
**/\r
BOOLEAN\r
IsTimerTimeout (\r
  IN USB3_DEBUG_PORT_HANDLE  *UsbDebugPortHandle,\r
  IN UINT64                  Timer,\r
  IN UINT64                  TimeoutTicker\r
  );\r
\r
#endif //__SERIAL_PORT_LIB_USB__\r
Commit	Line	Data
2cb6eabe EL	1	/** @file\r
	2	Debug Port Library implementation based on usb3 debug port.\r
	3	\r
	4	Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
	5	This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php.\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	#ifndef __USB3_DEBUG_PORT_LIB_INTERNAL__\r
	16	#define __USB3_DEBUG_PORT_LIB_INTERNAL__\r
	17	\r
	18	#include <Uefi.h>\r
	19	#include <Base.h>\r
	20	#include <IndustryStandard/Usb.h>\r
	21	#include <Library/IoLib.h>\r
	22	#include <IndustryStandard/Pci.h>\r
	23	#include <Library/PcdLib.h>\r
	24	#include <Library/UefiLib.h>\r
	25	#include <Library/UefiBootServicesTableLib.h>\r
	26	#include <Library/MemoryAllocationLib.h>\r
	27	#include <Library/DebugLib.h>\r
	28	#include <Library/BaseMemoryLib.h>\r
	29	#include <Library/BaseLib.h>\r
	30	#include <Library/TimerLib.h>\r
	31	#include <Library/DebugCommunicationLib.h>\r
	32	#include <Library/PciLib.h>\r
	33	#include <Library/SerialPortLib.h> // Todo: remove in future\r
	34	\r
	35	//\r
	36	// Internal serial debug - remove finally\r
	37	//\r
	38	#include <Library/SerialPortLib.h>\r
	39	#include <Library/PrintLib.h>\r
	40	\r
	41	//\r
	42	// USB Debug GUID value\r
	43	//\r
	44	#define USB3_DBG_GUID \\r
	45	{ \\r
	46	0xb2a56f4d, 0x9177, 0x4fc8, { 0xa6, 0x77, 0xdd, 0x96, 0x3e, 0xb4, 0xcb, 0x1b } \\r
	47	}\r
	48	\r
	49	//\r
	50	// The state machine of usb debug port\r
	51	//\r
	52	#define USB3DBG_NO_DBG_CAB 0 // The XHCI host controller does not support debug capability\r
	53	#define USB3DBG_DBG_CAB 1 // The XHCI host controller supports debug capability\r
	54	#define USB3DBG_ENABLED 2 // The XHCI debug device is enabled\r
	55	#define USB3DBG_NOT_ENABLED 4 // The XHCI debug device is not enabled\r
	56	\r
	57	#define USB3_DEBUG_PORT_MAX_PACKET_SIZE 0x08\r
	58	\r
	59	#define XHCI_DEBUG_DEVICE_VENDOR_ID 0x0525\r
	60	#define XHCI_DEBUG_DEVICE_PRODUCT_ID 0x127A\r
	61	#define XHCI_DEBUG_DEVICE_PROTOCOL 0xFF\r
	62	#define XHCI_DEBUG_DEVICE_REVISION 0x00\r
	63	\r
	64	#define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL\r
65	#define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000\r
66	\r
67	#define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A\r
68	#define XHC_HCCPARAMS_OFFSET 0x10\r
69	#define XHC_CAPABILITY_ID_MASK 0xFF\r
70	#define XHC_NEXT_CAPABILITY_MASK 0xFF00\r
71	\r
72	#define XHC_HCSPARAMS1_OFFSET 0x4 // Structural Parameters 1\r
73	#define XHC_USBCMD_OFFSET 0x0 // USB Command Register Offset\r
74	#define XHC_USBSTS_OFFSET 0x4 // USB Status Register Offset\r
75	#define XHC_PORTSC_OFFSET 0x400 // Port Status and Control Register Offset\r
76	\r
77	#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
78	#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
79	\r
80	#define XHC_USBSTS_HALT BIT0\r
81	\r
82	//\r
83	// Transfer the data of 8 bytes each time\r
84	//\r
85	#define XHC_DEBUG_PORT_DATA_LENGTH 8\r
86	\r
87	//\r
88	// Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.\r
89	//\r
90	#define DATA_TRANSFER_WRITE_TIMEOUT 0\r
91	#define DATA_TRANSFER_READ_TIMEOUT 50000\r
92	#define DATA_TRANSFER_POLL_TIMEOUT 1000\r
93	\r
94	//\r
95	// XHCI port power off/on delay\r
96	//\r
97	#define XHC_DEBUG_PORT_ON_OFF_DELAY 100000\r
98	\r
99	//\r
100	// USB debug device string descritpor (header size + unicode string length)\r
101	//\r
102	#define STRING0_DESC_LEN 4\r
103	#define MANU_DESC_LEN 12\r
104	#define PRODUCT_DESC_LEN 40\r
105	#define SERIAL_DESC_LEN 4\r
106	\r
107	//\r
108	// Debug Capability Register Offset\r
109	//\r
110	#define XHC_DC_DCID 0x0\r
111	#define XHC_DC_DCDB 0x4\r
112	#define XHC_DC_DCERSTSZ 0x8\r
113	#define XHC_DC_DCERSTBA 0x10\r
114	#define XHC_DC_DCERDP 0x18\r
115	#define XHC_DC_DCCTRL 0x20\r
116	#define XHC_DC_DCST 0x24\r
117	#define XHC_DC_DCPORTSC 0x28\r
118	#define XHC_DC_DCCP 0x30\r
119	#define XHC_DC_DCDDI1 0x38\r
120	#define XHC_DC_DCDDI2 0x3C\r
121	\r
122	#define TRB_TYPE_LINK 6\r
123	\r
124	#define ERST_NUMBER 0x01\r
125	#define TR_RING_TRB_NUMBER 0x100\r
126	#define EVENT_RING_TRB_NUMBER 0x200\r
127	\r
128	#define ED_BULK_OUT 2\r
129	#define ED_BULK_IN 6\r
130	\r
131	#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))\r
132	#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))\r
133	#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
134	\r
135	//\r
136	// Endpoint Type (EP Type).\r
137	//\r
138	#define ED_NOT_VALID 0\r
139	#define ED_ISOCH_OUT 1\r
140	#define ED_BULK_OUT 2\r
141	#define ED_INTERRUPT_OUT 3\r
142	#define ED_CONTROL_BIDIR 4\r
143	#define ED_ISOCH_IN 5\r
144	#define ED_BULK_IN 6\r
145	#define ED_INTERRUPT_IN 7\r
146	\r
147	//\r
148	// 6.4.5 TRB Completion Codes\r
149	//\r
150	#define TRB_COMPLETION_INVALID 0\r
151	#define TRB_COMPLETION_SUCCESS 1\r
152	#define TRB_COMPLETION_DATA_BUFFER_ERROR 2\r
153	#define TRB_COMPLETION_BABBLE_ERROR 3\r
154	#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4\r
155	#define TRB_COMPLETION_TRB_ERROR 5\r
156	#define TRB_COMPLETION_STALL_ERROR 6\r
157	#define TRB_COMPLETION_SHORT_PACKET 13\r
158	\r
159	//\r
160	// 6.4.6 TRB Types\r
161	//\r
162	#define TRB_TYPE_NORMAL 1\r
163	#define TRB_TYPE_SETUP_STAGE 2\r
164	#define TRB_TYPE_DATA_STAGE 3\r
165	#define TRB_TYPE_STATUS_STAGE 4\r
166	#define TRB_TYPE_ISOCH 5\r
167	#define TRB_TYPE_LINK 6\r
168	#define TRB_TYPE_EVENT_DATA 7\r
169	#define TRB_TYPE_NO_OP 8\r
170	#define TRB_TYPE_EN_SLOT 9\r
171	#define TRB_TYPE_DIS_SLOT 10\r
172	#define TRB_TYPE_ADDRESS_DEV 11\r
173	#define TRB_TYPE_CON_ENDPOINT 12\r
174	#define TRB_TYPE_EVALU_CONTXT 13\r
175	#define TRB_TYPE_RESET_ENDPOINT 14\r
176	#define TRB_TYPE_STOP_ENDPOINT 15\r
177	#define TRB_TYPE_SET_TR_DEQUE 16\r
178	#define TRB_TYPE_RESET_DEV 17\r
179	#define TRB_TYPE_GET_PORT_BANW 21\r
180	#define TRB_TYPE_FORCE_HEADER 22\r
181	#define TRB_TYPE_NO_OP_COMMAND 23\r
182	#define TRB_TYPE_TRANS_EVENT 32\r
183	#define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r
184	#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r
185	#define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r
186	#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r
187	#define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r
188	\r
189	//\r
190	// Convert millisecond to microsecond.\r
191	//\r
192	#define XHC_1_MILLISECOND (1000)\r
193	#define XHC_POLL_DELAY (1000)\r
194	#define XHC_GENERIC_TIMEOUT (10 * 1000)\r
195	\r
196	#define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.\r
197	#define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.\r
198	#define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.\r
199	#define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.\r
200	\r
201	//\r
202	// Transfer types, used in URB to identify the transfer type\r
203	//\r
204	#define XHC_CTRL_TRANSFER 0x01\r
205	#define XHC_BULK_TRANSFER 0x02\r
206	#define XHC_INT_TRANSFER_SYNC 0x04\r
207	#define XHC_INT_TRANSFER_ASYNC 0x08\r
208	#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10\r
209	\r
210	//\r
211	// USB Transfer Results\r
212	//\r
213	#define EFI_USB_NOERROR 0x00\r
214	#define EFI_USB_ERR_NOTEXECUTE 0x01\r
215	#define EFI_USB_ERR_STALL 0x02\r
216	#define EFI_USB_ERR_BUFFER 0x04\r
217	#define EFI_USB_ERR_BABBLE 0x08\r
218	#define EFI_USB_ERR_NAK 0x10\r
219	#define EFI_USB_ERR_CRC 0x20\r
220	#define EFI_USB_ERR_TIMEOUT 0x40\r
221	#define EFI_USB_ERR_BITSTUFF 0x80\r
222	#define EFI_USB_ERR_SYSTEM 0x100\r
223	\r
224	#pragma pack(1)\r
225	\r
226	//\r
227	// 7.6.9 OUT/IN EP Context: 64 bytes\r
228	// 7.6.9.2 When used by the DbC it is always a 64 byte data structure\r
229	//\r
230	typedef struct _ENDPOINT_CONTEXT_64 {\r
231	UINT32 EPState:3;\r
232	UINT32 RsvdZ1:5;\r
233	UINT32 Mult:2; // set to 0\r
234	UINT32 MaxPStreams:5; // set to 0\r
235	UINT32 LSA:1; // set to 0\r
236	UINT32 Interval:8; // set to 0\r
237	UINT32 RsvdZ2:8;\r
238	\r
239	UINT32 RsvdZ3:1;\r
240	UINT32 CErr:2;\r
241	UINT32 EPType:3;\r
242	UINT32 RsvdZ4:1;\r
243	UINT32 HID:1; // set to 0\r
244	UINT32 MaxBurstSize:8;\r
245	UINT32 MaxPacketSize:16;\r
246	\r
247	UINT32 PtrLo;\r
248	\r
249	UINT32 PtrHi;\r
250	\r
251	UINT32 AverageTRBLength:16;\r
252	UINT32 MaxESITPayload:16; // set to 0\r
253	\r
254	UINT32 RsvdZ5; // Reserved\r
255	UINT32 RsvdZ6;\r
256	UINT32 RsvdZ7;\r
257	\r
258	UINT32 RsvdZ8;\r
259	UINT32 RsvdZ9;\r
260	UINT32 RsvdZ10;\r
261	UINT32 RsvdZ11;\r
262	\r
263	UINT32 RsvdZ12;\r
264	UINT32 RsvdZ13;\r
265	UINT32 RsvdZ14;\r
266	UINT32 RsvdZ15;\r
267	} ENDPOINT_CONTEXT_64;\r
268	\r
269	//\r
270	// 6.4.1.1 Normal TRB: 16 bytes\r
271	// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r
272	// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r
273	// Rings, and to define the Data stage information for Control Transfer Rings.\r
274	//\r
275	typedef struct _TRANSFER_TRB_NORMAL {\r
276	UINT32 TRBPtrLo;\r
277	\r
278	UINT32 TRBPtrHi;\r
279	\r
280	UINT32 Length:17;\r
281	UINT32 TDSize:5;\r
282	UINT32 IntTarget:10;\r
283	\r
284	UINT32 CycleBit:1;\r
285	UINT32 ENT:1;\r
286	UINT32 ISP:1;\r
287	UINT32 NS:1;\r
288	UINT32 CH:1;\r
289	UINT32 IOC:1;\r
290	UINT32 IDT:1;\r
291	UINT32 RsvdZ1:2;\r
292	UINT32 BEI:1;\r
293	UINT32 Type:6;\r
294	UINT32 RsvdZ2:16;\r
295	} TRANSFER_TRB_NORMAL;\r
296	\r
297	//\r
298	// 6.4.2.1 Transfer Event TRB: 16 bytes\r
299	// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r
300	// for more information on the use and operation of Transfer Events.\r
301	//\r
302	typedef struct _EVT_TRB_TRANSFER {\r
303	UINT32 TRBPtrLo;\r
304	\r
305	UINT32 TRBPtrHi;\r
306	\r
307	UINT32 Length:24;\r
308	UINT32 Completecode:8;\r
309	\r
310	UINT32 CycleBit:1;\r
311	UINT32 RsvdZ1:1;\r
312	UINT32 ED:1;\r
313	UINT32 RsvdZ2:7;\r
314	UINT32 Type:6;\r
315	UINT32 EndpointId:5;\r
316	UINT32 RsvdZ3:3;\r
317	UINT32 SlotId:8;\r
318	} EVT_TRB_TRANSFER;\r
319	\r
320	//\r
321	// 6.4.4.1 Link TRB: 16 bytes\r
322	// A Link TRB provides support for non-contiguous TRB Rings.\r
323	//\r
324	typedef struct _LINK_TRB {\r
325	UINT32 PtrLo;\r
326	\r
327	UINT32 PtrHi;\r
328	\r
329	UINT32 RsvdZ1:22;\r
330	UINT32 InterTarget:10;\r
331	\r
332	UINT32 CycleBit:1;\r
333	UINT32 TC:1;\r
334	UINT32 RsvdZ2:2;\r
335	UINT32 CH:1;\r
336	UINT32 IOC:1;\r
337	UINT32 RsvdZ3:4;\r
338	UINT32 Type:6;\r
339	UINT32 RsvdZ4:16;\r
340	} LINK_TRB;\r
341	\r
342	//\r
343	// TRB Template: 16 bytes\r
344	//\r
345	typedef struct _TRB_TEMPLATE {\r
346	UINT32 Parameter1;\r
347	\r
348	UINT32 Parameter2;\r
349	\r
350	UINT32 Status;\r
351	\r
352	UINT32 CycleBit:1;\r
353	UINT32 RsvdZ1:9;\r
354	UINT32 Type:6;\r
355	UINT32 Control:16;\r
356	} TRB_TEMPLATE;\r
357	\r
358	//\r
359	// Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes\r
360	//\r
361	typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r
362	UINT32 PtrLo;\r
363	UINT32 PtrHi;\r
364	UINT32 RingTrbSize:16;\r
365	UINT32 RsvdZ1:16;\r
366	UINT32 RsvdZ2;\r
367	} EVENT_RING_SEG_TABLE_ENTRY;\r
368	\r
369	//\r
370	// Size: 40 bytes\r
371	//\r
372	typedef struct _EVENT_RING {\r
373	EFI_PHYSICAL_ADDRESS ERSTBase;\r
374	EFI_PHYSICAL_ADDRESS EventRingSeg0;\r
375	UINT32 TrbNumber;\r
376	EFI_PHYSICAL_ADDRESS EventRingEnqueue;\r
377	EFI_PHYSICAL_ADDRESS EventRingDequeue;\r
378	UINT32 EventRingCCS;\r
379	} EVENT_RING;\r
380	\r
381	// Size: 32 bytes\r
382	typedef struct _TRANSFER_RING {\r
383	EFI_PHYSICAL_ADDRESS RingSeg0;\r
384	UINT32 TrbNumber;\r
385	EFI_PHYSICAL_ADDRESS RingEnqueue;\r
386	EFI_PHYSICAL_ADDRESS RingDequeue;\r
387	UINT32 RingPCS;\r
388	} TRANSFER_RING;\r
389	\r
390	//\r
391	// Size: 64 bytes\r
392	//\r
393	typedef struct _DBC_INFO_CONTEXT {\r
394	UINT64 String0DescAddress;\r
395	UINT64 ManufacturerStrDescAddress;\r
396	UINT64 ProductStrDescAddress;\r
397	UINT64 SerialNumberStrDescAddress;\r
398	UINT64 String0Length:8;\r
399	UINT64 ManufacturerStrLength:8;\r
400	UINT64 ProductStrLength:8;\r
401	UINT64 SerialNumberStrLength:8;\r
402	UINT64 RsvdZ1:32;\r
403	UINT64 RsvdZ2;\r
404	UINT64 RsvdZ3;\r
405	UINT64 RsvdZ4; \r
406	} DBC_INFO_CONTEXT;\r
407	\r
408	//\r
409	// Debug Capability Context Data Structure: 192 bytes\r
410	//\r
411	typedef struct _XHC_DC_CONTEXT {\r
412	DBC_INFO_CONTEXT DbcInfoContext;\r
413	ENDPOINT_CONTEXT_64 EpOutContext;\r
414	ENDPOINT_CONTEXT_64 EpInContext;\r
415	} XHC_DC_CONTEXT;\r
416	\r
417	//\r
418	// Size: 16 bytes\r
419	//\r
420	typedef union _TRB {\r
421	TRB_TEMPLATE TrbTemplate;\r
422	TRANSFER_TRB_NORMAL TrbNormal;\r
423	} TRB;\r
424	\r
425	///\r
426	/// USB data transfer direction\r
427	///\r
428	typedef enum {\r
429	EfiUsbDataIn,\r
430	EfiUsbDataOut,\r
431	EfiUsbNoData\r
432	} EFI_USB_DATA_DIRECTION;\r
433	\r
434	//\r
435	// URB (Usb Request Block) contains information for all kinds of\r
436	// usb requests.\r
437	//\r
438	typedef struct _URB {\r
439	//\r
440	// Transfer data buffer\r
441	//\r
442	EFI_PHYSICAL_ADDRESS Data;\r
443	UINT32 DataLen;\r
444	\r
445	//\r
446	// Execute result\r
447	//\r
448	UINT32 Result;\r
449	//\r
450	// Completed data length\r
451	//\r
452	UINT32 Completed;\r
453	//\r
454	// Tranfer Ring info\r
455	//\r
456	EFI_PHYSICAL_ADDRESS Ring;\r
457	EFI_PHYSICAL_ADDRESS Trb;\r
458	BOOLEAN Finished;\r
459	EFI_USB_DATA_DIRECTION Direction;\r
460	} URB;\r
461	\r
462	typedef struct _USB3_DEBUG_PORT_INSTANCE {\r
463	UINT8 Initialized;\r
464	\r
465	//\r
466	// The flag indicates debug device is ready\r
467	//\r
468	BOOLEAN DebugSupport;\r
469	\r
470	//\r
471	// The flag indicates debug device is ready\r
472	//\r
473	BOOLEAN Ready;\r
474	\r
475	//\r
476	// The flag indicates if USB 3.0 ports has been turn off/on power\r
477	// \r
478	BOOLEAN ChangePortPower;\r
479	\r
480	//\r
481	// XHCI MMIO Base address\r
482	//\r
483	EFI_PHYSICAL_ADDRESS XhciMmioBase;\r
484	\r
485	//\r
486	// XHCI OP RegisterBase address\r
487	// \r
488	EFI_PHYSICAL_ADDRESS XhciOpRegister;\r
489	\r
490	//\r
491	// XHCI Debug Register Base Address\r
492	//\r
493	EFI_PHYSICAL_ADDRESS DebugCapabilityBase;\r
494	\r
495	//\r
496	// XHCI Debug Capability offset\r
497	//\r
498	UINT64 DebugCapabilityOffset; \r
499	\r
500	//\r
501	// XHCI Debug Context Address\r
502	//\r
503	EFI_PHYSICAL_ADDRESS DebugCapabilityContext;\r
504	\r
505	//\r
506	// Transfer Ring\r
507	//\r
508	TRANSFER_RING TransferRingOut;\r
509	TRANSFER_RING TransferRingIn;\r
510	\r
511	//\r
512	// EventRing\r
513	//\r
514	EVENT_RING EventRing;\r
515	\r
516	//\r
517	// URB - Read\r
518	//\r
519	URB UrbOut;\r
520	\r
521	//\r
522	// URB - Write\r
523	//\r
524	URB UrbIn;\r
525	\r
526	//\r
527	// The available data length in the following data buffer.\r
528	//\r
529	UINT8 DataCount;\r
530	//\r
531	// The data buffer. Maximum length is 8 bytes.\r
532	//\r
533	UINT8 Data[8];\r
534	//\r
535	// Timter settings\r
536	//\r
537	UINT64 TimerFrequency;\r
538	UINT64 TimerCycle;\r
539	BOOLEAN TimerCountDown;\r
540	\r
541	} USB3_DEBUG_PORT_HANDLE;\r
542	\r
543	#pragma pack()\r
544	\r
545	/**\r
546	Read XHCI debug register.\r
547	\r
548	@param Handle Debug port handle.\r
549	@param Offset The offset of the debug register.\r
550	\r
551	@return The register content read\r
552	\r
553	**/\r
554	UINT32\r
555	XhcReadDebugReg (\r
556	IN USB3_DEBUG_PORT_HANDLE *Handle,\r
557	IN UINT32 Offset\r
558	);\r
559	\r
560	/**\r
561	Set one bit of the debug register while keeping other bits.\r
562	\r
563	@param Handle Debug port handle.\r
564	@param Offset The offset of the debug register.\r
565	@param Bit The bit mask of the register to set.\r
566	\r
567	**/\r
568	VOID\r
569	XhcSetDebugRegBit (\r
570	IN USB3_DEBUG_PORT_HANDLE *Handle,\r
571	IN UINT32 Offset,\r
572	IN UINT32 Bit\r
573	);\r
574	\r
575	/**\r
576	Write the data to the debug register.\r
577	\r
578	@param Handle Debug port handle.\r
579	@param Offset The offset of the debug register.\r
580	@param Data The data to write.\r
581	\r
582	**/ \r
583	VOID\r
584	XhcWriteDebugReg (\r
585	IN USB3_DEBUG_PORT_HANDLE *Handle,\r
586	IN UINT32 Offset,\r
587	IN UINT32 Data\r
588	);\r
589	\r
590	/**\r
591	Discover the USB3 debug device.\r
592	\r
593	@param Handle Debug port handle.\r
594	\r
595	@retval RETURN_SUCCESS The serial device was initialized.\r
596	@retval RETURN_DEVICE_ERROR The serial device could not be initialized.\r
597	\r
598	**/\r
599	RETURN_STATUS\r
600	DiscoverUsb3DebugPort(\r
601	USB3_DEBUG_PORT_HANDLE *Handle\r
602	);\r
603	\r
604	/**\r
605	Initialize the Serial Device hardware.\r
606	\r
607	@param Handle Debug port handle.\r
608	\r
609	@retval RETURN_SUCCESS The serial device was initialized successfully.\r
610	@retval !RETURN_SUCCESS Error.\r
611	\r
612	**/\r
613	RETURN_STATUS\r
614	InitializeUsb3DebugPort (\r
615	USB3_DEBUG_PORT_HANDLE *Handle\r
616	);\r
617	\r
618	/**\r
619	Return XHCI MMIO base address.\r
620	\r
621	**/\r
622	EFI_PHYSICAL_ADDRESS\r
623	GetXhciBaseAddress (\r
624	VOID\r
625	);\r
626	\r
627	/**\r
628	Verifies if the bit positions specified by a mask are set in a register.\r
629	\r
630	@param[in, out] Register UNITN register\r
631	@param[in] BitMask 32-bit mask\r
632	\r
633	@return BOOLEAN - TRUE if all bits specified by the mask are enabled.\r
634	- FALSE even if one of the bits specified by the mask \r
635	is not enabled.\r
636	**/\r
637	BOOLEAN\r
638	XhcIsBitSet(\r
639	UINTN Register, \r
640	UINT32 BitMask\r
641	);\r
642	\r
643	/**\r
644	Sets bits as per the enabled bit positions in the mask.\r
645	\r
646	@param[in, out] Register UINTN register\r
647	@param[in] BitMask 32-bit mask\r
648	**/\r
649	VOID\r
650	XhcSetR32Bit(\r
651	UINTN Register, \r
652	UINT32 BitMask\r
653	);\r
654	\r
655	/**\r
656	Clears bits as per the enabled bit positions in the mask.\r
657	\r
658	@param[in, out] Register UINTN register\r
659	@param[in] BitMask 32-bit mask\r
660	**/\r
661	VOID\r
662	XhcClearR32Bit(\r
663	IN OUT UINTN Register, \r
664	IN UINT32 BitMask\r
665	);\r
666	\r
667	/**\r
668	Initialize USB3 debug port.\r
669	\r
670	This method invokes various internal functions to facilitate\r
671	detection and initialization of USB3 debug port.\r
672	\r
673	@retval RETURN_SUCCESS The serial device was initialized.\r
674	**/\r
675	RETURN_STATUS\r
676	EFIAPI\r
677	USB3Initialize (\r
678	VOID\r
679	);\r
680	\r
681	/**\r
682	Return command register value in XHCI controller.\r
683	\r
684	**/\r
685	UINT16\r
686	GetXhciPciCommand (\r
687	VOID\r
688	);\r
689	\r
690	/**\r
691	Allocate aligned memory for XHC's usage.\r
692	\r
693	@param BufferSize The size, in bytes, of the Buffer.\r
694	\r
695	@return A pointer to the allocated buffer or NULL if allocation fails.\r
696	\r
697	**/\r
698	VOID*\r
699	AllocateAlignBuffer (\r
700	IN UINTN BufferSize\r
701	);\r
702	\r
703	/**\r
704	The real function to initialize USB3 debug port.\r
705	\r
706	This method invokes various internal functions to facilitate\r
707	detection and initialization of USB3 debug port.\r
708	\r
709	@retval RETURN_SUCCESS The serial device was initialized.\r
710	**/\r
711	RETURN_STATUS\r
712	EFIAPI\r
713	USB3InitializeReal (\r
714	VOID\r
715	);\r
716	\r
717	/**\r
718	Submits bulk transfer to a bulk endpoint of a USB device.\r
719	\r
720	@param Handle The instance of debug device.\r
721	@param Direction The direction of data transfer.\r
722	@param Data Array of pointers to the buffers of data to transmit\r
723	from or receive into.\r
724	@param DataLength The lenght of the data buffer.\r
725	@param Timeout Indicates the maximum time, in millisecond, which\r
726	the transfer is allowed to complete.\r
727	\r
728	@retval EFI_SUCCESS The transfer was completed successfully.\r
729	@retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.\r
730	@retval EFI_INVALID_PARAMETER Some parameters are invalid.\r
731	@retval EFI_TIMEOUT The transfer failed due to timeout.\r
732	@retval EFI_DEVICE_ERROR The transfer failed due to host controller error.\r
733	\r
734	**/\r
735	EFI_STATUS\r
736	EFIAPI\r
737	XhcDataTransfer (\r
738	IN USB3_DEBUG_PORT_HANDLE *Handle,\r
739	IN EFI_USB_DATA_DIRECTION Direction,\r
740	IN OUT VOID *Data,\r
741	IN OUT UINTN *DataLength,\r
742	IN UINTN Timeout\r
743	);\r
744	\r
745	/**\r
746	Check if the timer is timeout.\r
747	\r
748	@param[in] UsbDebugPortHandle Pointer to USB Debug port handle\r
749	@param[in] Timer The start timer from the begin.\r
750	@param[in] TimeoutTicker Ticker number need time out.\r
751	\r
752	@return TRUE Timer time out occurs.\r
753	@retval FALSE Timer does not time out.\r
754	\r
755	**/\r
756	BOOLEAN\r
757	IsTimerTimeout (\r
758	IN USB3_DEBUG_PORT_HANDLE *UsbDebugPortHandle,\r
759	IN UINT64 Timer,\r
760	IN UINT64 TimeoutTicker\r
761	);\r
762	\r
763	#endif //__SERIAL_PORT_LIB_USB__\r