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[mirror_edk2.git] / SourceLevelDebugPkg / Library / DebugCommunicationLibUsb3 / DebugCommunicationLibUsb3Internal.h
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2cb6eabe
EL		 1/** @file\r
2 Debug Port Library implementation based on usb3 debug port.\r
3\r
f0c56276 4 Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
85f7e110 5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
2cb6eabe
EL		 6\r
7**/\r
8\r
9#ifndef __USB3_DEBUG_PORT_LIB_INTERNAL__\r
10#define __USB3_DEBUG_PORT_LIB_INTERNAL__\r
11\r
12#include <Uefi.h>\r
13#include <Base.h>\r
14#include <IndustryStandard/Usb.h>\r
15#include <Library/IoLib.h>\r
16#include <IndustryStandard/Pci.h>\r
17#include <Library/PcdLib.h>\r
18#include <Library/UefiLib.h>\r
19#include <Library/UefiBootServicesTableLib.h>\r
20#include <Library/MemoryAllocationLib.h>\r
21#include <Library/DebugLib.h>\r
22#include <Library/BaseMemoryLib.h>\r
23#include <Library/BaseLib.h>\r
24#include <Library/TimerLib.h>\r
25#include <Library/DebugCommunicationLib.h>\r
26#include <Library/PciLib.h>\r
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EL		 27\r
28//\r
29// USB Debug GUID value\r
30//\r
31#define USB3_DBG_GUID \\r
32 { \\r
33 0xb2a56f4d, 0x9177, 0x4fc8, { 0xa6, 0x77, 0xdd, 0x96, 0x3e, 0xb4, 0xcb, 0x1b } \\r
34 }\r
35\r
36//\r
37// The state machine of usb debug port\r
38//\r
c1e126b1
MK		 39#define USB3DBG_NO_DBG_CAB 0 // The XHCI host controller does not support debug capability\r
40#define USB3DBG_DBG_CAB 1 // The XHCI host controller supports debug capability\r
41#define USB3DBG_ENABLED 2 // The XHCI debug device is enabled\r
42#define USB3DBG_NOT_ENABLED 4 // The XHCI debug device is not enabled\r
43#define USB3DBG_UNINITIALIZED 255 // The XHCI debug device is uninitialized\r
2cb6eabe 44\r
c1e126b1 45#define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08\r
5d6507a1
EL		 46\r
47//\r
48// MaxPacketSize for DbC Endpoint Descriptor IN and OUT\r
49//\r
c1e126b1 50#define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE 0x400\r
2cb6eabe
EL		 51\r
52#define XHCI_DEBUG_DEVICE_VENDOR_ID 0x0525\r
53#define XHCI_DEBUG_DEVICE_PRODUCT_ID 0x127A\r
54#define XHCI_DEBUG_DEVICE_PROTOCOL 0xFF\r
55#define XHCI_DEBUG_DEVICE_REVISION 0x00\r
56\r
c1e126b1
MK		 57#define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL\r
58#define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000\r
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EL		 59\r
60#define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A\r
61#define XHC_HCCPARAMS_OFFSET 0x10\r
62#define XHC_CAPABILITY_ID_MASK 0xFF\r
63#define XHC_NEXT_CAPABILITY_MASK 0xFF00\r
64\r
c1e126b1
MK		 65#define XHC_HCSPARAMS1_OFFSET 0x4 // Structural Parameters 1\r
66#define XHC_USBCMD_OFFSET 0x0 // USB Command Register Offset\r
67#define XHC_USBSTS_OFFSET 0x4 // USB Status Register Offset\r
68#define XHC_PORTSC_OFFSET 0x400 // Port Status and Control Register Offset\r
2cb6eabe 69\r
c1e126b1
MK		 70#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
71#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
2cb6eabe 72\r
c1e126b1 73#define XHC_USBSTS_HALT BIT0\r
2cb6eabe 74\r
2cb6eabe
EL		 75//\r
76// Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.\r
77//\r
c1e126b1
MK		 78#define DATA_TRANSFER_WRITE_TIMEOUT 0\r
79#define DATA_TRANSFER_READ_TIMEOUT 50000\r
80#define DATA_TRANSFER_POLL_TIMEOUT 1000\r
81#define XHC_DEBUG_PORT_1_MILLISECOND 1000\r
2cb6eabe
EL		 82//\r
83// XHCI port power off/on delay\r
84//\r
c1e126b1 85#define XHC_DEBUG_PORT_ON_OFF_DELAY 100000\r
2cb6eabe
EL		 86\r
87//\r
1825c24f 88// USB debug device string descriptor (header size + unicode string length)\r
2cb6eabe 89//\r
c1e126b1
MK		 90#define STRING0_DESC_LEN 4\r
91#define MANU_DESC_LEN 12\r
92#define PRODUCT_DESC_LEN 40\r
93#define SERIAL_DESC_LEN 4\r
2cb6eabe
EL		 94\r
95//\r
96// Debug Capability Register Offset\r
97//\r
c1e126b1
MK		 98#define XHC_DC_DCID 0x0\r
99#define XHC_DC_DCDB 0x4\r
100#define XHC_DC_DCERSTSZ 0x8\r
101#define XHC_DC_DCERSTBA 0x10\r
102#define XHC_DC_DCERDP 0x18\r
103#define XHC_DC_DCCTRL 0x20\r
104#define XHC_DC_DCST 0x24\r
105#define XHC_DC_DCPORTSC 0x28\r
106#define XHC_DC_DCCP 0x30\r
107#define XHC_DC_DCDDI1 0x38\r
108#define XHC_DC_DCDDI2 0x3C\r
2cb6eabe 109\r
c1e126b1 110#define TRB_TYPE_LINK 6\r
2cb6eabe 111\r
c1e126b1
MK		 112#define ERST_NUMBER 0x01\r
113#define TR_RING_TRB_NUMBER 0x100\r
114#define EVENT_RING_TRB_NUMBER 0x200\r
2cb6eabe 115\r
c1e126b1
MK		 116#define ED_BULK_OUT 2\r
117#define ED_BULK_IN 6\r
2cb6eabe 118\r
c1e126b1
MK		 119#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))\r
120#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))\r
121#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
2cb6eabe
EL		 122\r
123//\r
124// Endpoint Type (EP Type).\r
125//\r
c1e126b1
MK		 126#define ED_NOT_VALID 0\r
127#define ED_ISOCH_OUT 1\r
128#define ED_BULK_OUT 2\r
129#define ED_INTERRUPT_OUT 3\r
130#define ED_CONTROL_BIDIR 4\r
131#define ED_ISOCH_IN 5\r
132#define ED_BULK_IN 6\r
133#define ED_INTERRUPT_IN 7\r
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EL		 134\r
135//\r
136// 6.4.5 TRB Completion Codes\r
137//\r
138#define TRB_COMPLETION_INVALID 0\r
139#define TRB_COMPLETION_SUCCESS 1\r
140#define TRB_COMPLETION_DATA_BUFFER_ERROR 2\r
141#define TRB_COMPLETION_BABBLE_ERROR 3\r
142#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4\r
143#define TRB_COMPLETION_TRB_ERROR 5\r
144#define TRB_COMPLETION_STALL_ERROR 6\r
145#define TRB_COMPLETION_SHORT_PACKET 13\r
146\r
147//\r
148// 6.4.6 TRB Types\r
149//\r
c1e126b1
MK		 150#define TRB_TYPE_NORMAL 1\r
151#define TRB_TYPE_SETUP_STAGE 2\r
152#define TRB_TYPE_DATA_STAGE 3\r
153#define TRB_TYPE_STATUS_STAGE 4\r
154#define TRB_TYPE_ISOCH 5\r
155#define TRB_TYPE_LINK 6\r
156#define TRB_TYPE_EVENT_DATA 7\r
157#define TRB_TYPE_NO_OP 8\r
158#define TRB_TYPE_EN_SLOT 9\r
159#define TRB_TYPE_DIS_SLOT 10\r
160#define TRB_TYPE_ADDRESS_DEV 11\r
161#define TRB_TYPE_CON_ENDPOINT 12\r
162#define TRB_TYPE_EVALU_CONTXT 13\r
163#define TRB_TYPE_RESET_ENDPOINT 14\r
164#define TRB_TYPE_STOP_ENDPOINT 15\r
165#define TRB_TYPE_SET_TR_DEQUE 16\r
166#define TRB_TYPE_RESET_DEV 17\r
167#define TRB_TYPE_GET_PORT_BANW 21\r
168#define TRB_TYPE_FORCE_HEADER 22\r
169#define TRB_TYPE_NO_OP_COMMAND 23\r
170#define TRB_TYPE_TRANS_EVENT 32\r
171#define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r
172#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r
173#define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r
174#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r
175#define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r
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EL		 176\r
177//\r
178// Convert millisecond to microsecond.\r
179//\r
c1e126b1
MK		 180#define XHC_1_MILLISECOND (1000)\r
181#define XHC_POLL_DELAY (1000)\r
182#define XHC_GENERIC_TIMEOUT (10 * 1000)\r
2cb6eabe 183\r
c1e126b1
MK		 184#define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.\r
185#define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.\r
186#define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.\r
187#define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.\r
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EL		 188\r
189//\r
190// Transfer types, used in URB to identify the transfer type\r
191//\r
c1e126b1
MK		 192#define XHC_CTRL_TRANSFER 0x01\r
193#define XHC_BULK_TRANSFER 0x02\r
194#define XHC_INT_TRANSFER_SYNC 0x04\r
195#define XHC_INT_TRANSFER_ASYNC 0x08\r
196#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10\r
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EL		 197\r
198//\r
199// USB Transfer Results\r
200//\r
c1e126b1
MK		 201#define EFI_USB_NOERROR 0x00\r
202#define EFI_USB_ERR_NOTEXECUTE 0x01\r
203#define EFI_USB_ERR_STALL 0x02\r
204#define EFI_USB_ERR_BUFFER 0x04\r
205#define EFI_USB_ERR_BABBLE 0x08\r
206#define EFI_USB_ERR_NAK 0x10\r
207#define EFI_USB_ERR_CRC 0x20\r
208#define EFI_USB_ERR_TIMEOUT 0x40\r
209#define EFI_USB_ERR_BITSTUFF 0x80\r
210#define EFI_USB_ERR_SYSTEM 0x100\r
2cb6eabe
EL		 211\r
212#pragma pack(1)\r
213\r
214//\r
215// 7.6.9 OUT/IN EP Context: 64 bytes\r
216// 7.6.9.2 When used by the DbC it is always a 64 byte data structure\r
217//\r
218typedef struct _ENDPOINT_CONTEXT_64 {\r
c1e126b1
MK		 219 UINT32 EPState : 3;\r
220 UINT32 RsvdZ1 : 5;\r
221 UINT32 Mult : 2; // set to 0\r
222 UINT32 MaxPStreams : 5; // set to 0\r
223 UINT32 LSA : 1; // set to 0\r
224 UINT32 Interval : 8; // set to 0\r
225 UINT32 RsvdZ2 : 8;\r
226\r
227 UINT32 RsvdZ3 : 1;\r
228 UINT32 CErr : 2;\r
229 UINT32 EPType : 3;\r
230 UINT32 RsvdZ4 : 1;\r
231 UINT32 HID : 1; // set to 0\r
232 UINT32 MaxBurstSize : 8;\r
233 UINT32 MaxPacketSize : 16;\r
234\r
235 UINT32 PtrLo;\r
236\r
237 UINT32 PtrHi;\r
238\r
239 UINT32 AverageTRBLength : 16;\r
240 UINT32 MaxESITPayload : 16; // set to 0\r
241\r
242 UINT32 RsvdZ5; // Reserved\r
243 UINT32 RsvdZ6;\r
244 UINT32 RsvdZ7;\r
245\r
246 UINT32 RsvdZ8;\r
247 UINT32 RsvdZ9;\r
248 UINT32 RsvdZ10;\r
249 UINT32 RsvdZ11;\r
250\r
251 UINT32 RsvdZ12;\r
252 UINT32 RsvdZ13;\r
253 UINT32 RsvdZ14;\r
254 UINT32 RsvdZ15;\r
2cb6eabe
EL		 255} ENDPOINT_CONTEXT_64;\r
256\r
257//\r
258// 6.4.1.1 Normal TRB: 16 bytes\r
259// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r
260// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r
261// Rings, and to define the Data stage information for Control Transfer Rings.\r
262//\r
263typedef struct _TRANSFER_TRB_NORMAL {\r
c1e126b1
MK		 264 UINT32 TRBPtrLo;\r
265\r
266 UINT32 TRBPtrHi;\r
267\r
268 UINT32 Length : 17;\r
269 UINT32 TDSize : 5;\r
270 UINT32 IntTarget : 10;\r
271\r
272 UINT32 CycleBit : 1;\r
273 UINT32 ENT : 1;\r
274 UINT32 ISP : 1;\r
275 UINT32 NS : 1;\r
276 UINT32 CH : 1;\r
277 UINT32 IOC : 1;\r
278 UINT32 IDT : 1;\r
279 UINT32 RsvdZ1 : 2;\r
280 UINT32 BEI : 1;\r
281 UINT32 Type : 6;\r
282 UINT32 RsvdZ2 : 16;\r
2cb6eabe
EL		 283} TRANSFER_TRB_NORMAL;\r
284\r
285//\r
286// 6.4.2.1 Transfer Event TRB: 16 bytes\r
287// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r
288// for more information on the use and operation of Transfer Events.\r
289//\r
290typedef struct _EVT_TRB_TRANSFER {\r
c1e126b1 291 UINT32 TRBPtrLo;\r
2cb6eabe 292\r
c1e126b1 293 UINT32 TRBPtrHi;\r
2cb6eabe 294\r
c1e126b1
MK		 295 UINT32 Length : 24;\r
296 UINT32 Completecode : 8;\r
2cb6eabe 297\r
c1e126b1
MK		 298 UINT32 CycleBit : 1;\r
299 UINT32 RsvdZ1 : 1;\r
300 UINT32 ED : 1;\r
301 UINT32 RsvdZ2 : 7;\r
302 UINT32 Type : 6;\r
303 UINT32 EndpointId : 5;\r
304 UINT32 RsvdZ3 : 3;\r
305 UINT32 SlotId : 8;\r
2cb6eabe
EL		 306} EVT_TRB_TRANSFER;\r
307\r
308//\r
309// 6.4.4.1 Link TRB: 16 bytes\r
310// A Link TRB provides support for non-contiguous TRB Rings.\r
311//\r
312typedef struct _LINK_TRB {\r
c1e126b1 313 UINT32 PtrLo;\r
2cb6eabe 314\r
c1e126b1 315 UINT32 PtrHi;\r
2cb6eabe 316\r
c1e126b1
MK		 317 UINT32 RsvdZ1 : 22;\r
318 UINT32 InterTarget : 10;\r
2cb6eabe 319\r
c1e126b1
MK		 320 UINT32 CycleBit : 1;\r
321 UINT32 TC : 1;\r
322 UINT32 RsvdZ2 : 2;\r
323 UINT32 CH : 1;\r
324 UINT32 IOC : 1;\r
325 UINT32 RsvdZ3 : 4;\r
326 UINT32 Type : 6;\r
327 UINT32 RsvdZ4 : 16;\r
2cb6eabe
EL		 328} LINK_TRB;\r
329\r
330//\r
331// TRB Template: 16 bytes\r
332//\r
333typedef struct _TRB_TEMPLATE {\r
c1e126b1 334 UINT32 Parameter1;\r
2cb6eabe 335\r
c1e126b1 336 UINT32 Parameter2;\r
2cb6eabe 337\r
c1e126b1 338 UINT32 Status;\r
2cb6eabe 339\r
c1e126b1
MK		 340 UINT32 CycleBit : 1;\r
341 UINT32 RsvdZ1 : 9;\r
342 UINT32 Type : 6;\r
343 UINT32 Control : 16;\r
2cb6eabe
EL		 344} TRB_TEMPLATE;\r
345\r
346//\r
347// Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes\r
348//\r
349typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r
c1e126b1
MK		 350 UINT32 PtrLo;\r
351 UINT32 PtrHi;\r
352 UINT32 RingTrbSize : 16;\r
353 UINT32 RsvdZ1 : 16;\r
354 UINT32 RsvdZ2;\r
2cb6eabe
EL		 355} EVENT_RING_SEG_TABLE_ENTRY;\r
356\r
357//\r
358// Size: 40 bytes\r
359//\r
360typedef struct _EVENT_RING {\r
c1e126b1
MK		 361 EFI_PHYSICAL_ADDRESS ERSTBase;\r
362 EFI_PHYSICAL_ADDRESS EventRingSeg0;\r
363 UINT32 TrbNumber;\r
364 EFI_PHYSICAL_ADDRESS EventRingEnqueue;\r
365 EFI_PHYSICAL_ADDRESS EventRingDequeue;\r
366 UINT32 EventRingCCS;\r
2cb6eabe
EL		 367} EVENT_RING;\r
368\r
369// Size: 32 bytes\r
370typedef struct _TRANSFER_RING {\r
c1e126b1
MK		 371 EFI_PHYSICAL_ADDRESS RingSeg0;\r
372 UINT32 TrbNumber;\r
373 EFI_PHYSICAL_ADDRESS RingEnqueue;\r
374 EFI_PHYSICAL_ADDRESS RingDequeue;\r
375 UINT32 RingPCS;\r
2cb6eabe
EL		 376} TRANSFER_RING;\r
377\r
378//\r
379// Size: 64 bytes\r
380//\r
381typedef struct _DBC_INFO_CONTEXT {\r
c1e126b1
MK		 382 UINT64 String0DescAddress;\r
383 UINT64 ManufacturerStrDescAddress;\r
384 UINT64 ProductStrDescAddress;\r
385 UINT64 SerialNumberStrDescAddress;\r
386 UINT64 String0Length : 8;\r
387 UINT64 ManufacturerStrLength : 8;\r
388 UINT64 ProductStrLength : 8;\r
389 UINT64 SerialNumberStrLength : 8;\r
390 UINT64 RsvdZ1 : 32;\r
391 UINT64 RsvdZ2;\r
392 UINT64 RsvdZ3;\r
393 UINT64 RsvdZ4;\r
2cb6eabe
EL		 394} DBC_INFO_CONTEXT;\r
395\r
396//\r
397// Debug Capability Context Data Structure: 192 bytes\r
398//\r
399typedef struct _XHC_DC_CONTEXT {\r
c1e126b1
MK		 400 DBC_INFO_CONTEXT DbcInfoContext;\r
401 ENDPOINT_CONTEXT_64 EpOutContext;\r
402 ENDPOINT_CONTEXT_64 EpInContext;\r
2cb6eabe
EL		 403} XHC_DC_CONTEXT;\r
404\r
405//\r
406// Size: 16 bytes\r
407//\r
408typedef union _TRB {\r
c1e126b1
MK		 409 TRB_TEMPLATE TrbTemplate;\r
410 TRANSFER_TRB_NORMAL TrbNormal;\r
2cb6eabe
EL		 411} TRB;\r
412\r
413///\r
414/// USB data transfer direction\r
415///\r
416typedef enum {\r
417 EfiUsbDataIn,\r
418 EfiUsbDataOut,\r
419 EfiUsbNoData\r
420} EFI_USB_DATA_DIRECTION;\r
421\r
422//\r
423// URB (Usb Request Block) contains information for all kinds of\r
424// usb requests.\r
425//\r
426typedef struct _URB {\r
427 //\r
428 // Transfer data buffer\r
429 //\r
c1e126b1
MK		 430 EFI_PHYSICAL_ADDRESS Data;\r
431 UINT32 DataLen;\r
2cb6eabe
EL		 432\r
433 //\r
434 // Execute result\r
435 //\r
c1e126b1 436 UINT32 Result;\r
2cb6eabe
EL		 437 //\r
438 // Completed data length\r
439 //\r
c1e126b1 440 UINT32 Completed;\r
2cb6eabe
EL		 441 //\r
442 // Tranfer Ring info\r
443 //\r
c1e126b1
MK		 444 EFI_PHYSICAL_ADDRESS Ring;\r
445 EFI_PHYSICAL_ADDRESS Trb;\r
446 BOOLEAN Finished;\r
447 EFI_USB_DATA_DIRECTION Direction;\r
2cb6eabe
EL		 448} URB;\r
449\r
450typedef struct _USB3_DEBUG_PORT_INSTANCE {\r
c1e126b1 451 UINT8 Initialized;\r
2cb6eabe
EL		 452\r
453 //\r
75787f65 454 // The flag indicates debug capability is supported\r
2cb6eabe 455 //\r
c1e126b1 456 BOOLEAN DebugSupport;\r
77695f4d 457\r
2cb6eabe
EL		 458 //\r
459 // The flag indicates debug device is ready\r
460 //\r
c1e126b1 461 BOOLEAN Ready;\r
2cb6eabe 462\r
75787f65
SZ		 463 //\r
464 // The flag indicates the instance is from HOB\r
465 //\r
c1e126b1 466 BOOLEAN FromHob;\r
75787f65
SZ		 467\r
468 //\r
469 // Prevent notification being interrupted by debug timer\r
470 //\r
c1e126b1 471 BOOLEAN InNotify;\r
75787f65
SZ		 472\r
473 //\r
474 // PciIo protocol event\r
475 //\r
c1e126b1 476 EFI_PHYSICAL_ADDRESS PciIoEvent;\r
75787f65 477\r
2cb6eabe
EL		 478 //\r
479 // The flag indicates if USB 3.0 ports has been turn off/on power\r
77695f4d 480 //\r
c1e126b1 481 BOOLEAN ChangePortPower;\r
2cb6eabe
EL		 482\r
483 //\r
484 // XHCI MMIO Base address\r
485 //\r
c1e126b1 486 EFI_PHYSICAL_ADDRESS XhciMmioBase;\r
2cb6eabe
EL		 487\r
488 //\r
489 // XHCI OP RegisterBase address\r
77695f4d 490 //\r
c1e126b1 491 EFI_PHYSICAL_ADDRESS XhciOpRegister;\r
77695f4d 492\r
2cb6eabe
EL		 493 //\r
494 // XHCI Debug Register Base Address\r
495 //\r
c1e126b1 496 EFI_PHYSICAL_ADDRESS DebugCapabilityBase;\r
77695f4d 497\r
2cb6eabe
EL		 498 //\r
499 // XHCI Debug Capability offset\r
500 //\r
c1e126b1 501 UINT64 DebugCapabilityOffset;\r
77695f4d 502\r
2cb6eabe
EL		 503 //\r
504 // XHCI Debug Context Address\r
505 //\r
c1e126b1 506 EFI_PHYSICAL_ADDRESS DebugCapabilityContext;\r
77695f4d 507\r
2cb6eabe
EL		 508 //\r
509 // Transfer Ring\r
510 //\r
c1e126b1
MK		 511 TRANSFER_RING TransferRingOut;\r
512 TRANSFER_RING TransferRingIn;\r
2cb6eabe
EL		 513\r
514 //\r
515 // EventRing\r
516 //\r
c1e126b1 517 EVENT_RING EventRing;\r
77695f4d 518\r
2cb6eabe
EL		 519 //\r
520 // URB - Read\r
521 //\r
c1e126b1 522 URB UrbOut;\r
2cb6eabe
EL		 523\r
524 //\r
525 // URB - Write\r
526 //\r
c1e126b1 527 URB UrbIn;\r
2cb6eabe
EL		 528\r
529 //\r
530 // The available data length in the following data buffer.\r
531 //\r
c1e126b1 532 UINT8 DataCount;\r
2cb6eabe 533 //\r
5d6507a1 534 // The data buffer address for data read and poll.\r
2cb6eabe 535 //\r
c1e126b1 536 EFI_PHYSICAL_ADDRESS Data;\r
2cb6eabe
EL		 537} USB3_DEBUG_PORT_HANDLE;\r
538\r
539#pragma pack()\r
540\r
541/**\r
542 Read XHCI debug register.\r
543\r
544 @param Handle Debug port handle.\r
545 @param Offset The offset of the debug register.\r
546\r
547 @return The register content read\r
548\r
549**/\r
550UINT32\r
551XhcReadDebugReg (\r
c1e126b1
MK		 552 IN USB3_DEBUG_PORT_HANDLE *Handle,\r
553 IN UINT32 Offset\r
2cb6eabe
EL		 554 );\r
555\r
556/**\r
557 Set one bit of the debug register while keeping other bits.\r
558\r
559 @param Handle Debug port handle.\r
560 @param Offset The offset of the debug register.\r
561 @param Bit The bit mask of the register to set.\r
562\r
563**/\r
564VOID\r
565XhcSetDebugRegBit (\r
566 IN USB3_DEBUG_PORT_HANDLE *Handle,\r
f0c56276
SZ		 567 IN UINT32 Offset,\r
568 IN UINT32 Bit\r
2cb6eabe 569 );\r
77695f4d 570\r
2cb6eabe
EL		 571/**\r
572 Write the data to the debug register.\r
573\r
574 @param Handle Debug port handle.\r
575 @param Offset The offset of the debug register.\r
576 @param Data The data to write.\r
577\r
77695f4d 578**/\r
2cb6eabe
EL		 579VOID\r
580XhcWriteDebugReg (\r
c1e126b1
MK		 581 IN USB3_DEBUG_PORT_HANDLE *Handle,\r
582 IN UINT32 Offset,\r
583 IN UINT32 Data\r
2cb6eabe
EL		 584 );\r
585\r
2cb6eabe
EL		 586/**\r
587 Verifies if the bit positions specified by a mask are set in a register.\r
588\r
d6d4a81f 589 @param[in, out] Register UINTN register\r
2cb6eabe
EL		 590 @param[in] BitMask 32-bit mask\r
591\r
592 @return BOOLEAN - TRUE if all bits specified by the mask are enabled.\r
77695f4d 593 - FALSE even if one of the bits specified by the mask\r
2cb6eabe
EL		 594 is not enabled.\r
595**/\r
596BOOLEAN\r
c1e126b1 597XhcIsBitSet (\r
77695f4d 598 UINTN Register,\r
2cb6eabe
EL		 599 UINT32 BitMask\r
600 );\r
601\r
602/**\r
603 Sets bits as per the enabled bit positions in the mask.\r
604\r
605 @param[in, out] Register UINTN register\r
606 @param[in] BitMask 32-bit mask\r
607**/\r
608VOID\r
c1e126b1 609XhcSetR32Bit (\r
77695f4d 610 UINTN Register,\r
2cb6eabe
EL		 611 UINT32 BitMask\r
612 );\r
613\r
614/**\r
615 Clears bits as per the enabled bit positions in the mask.\r
616\r
617 @param[in, out] Register UINTN register\r
618 @param[in] BitMask 32-bit mask\r
619**/\r
620VOID\r
c1e126b1
MK		 621XhcClearR32Bit (\r
622 IN OUT UINTN Register,\r
623 IN UINT32 BitMask\r
2cb6eabe
EL		 624 );\r
625\r
626/**\r
627 Initialize USB3 debug port.\r
77695f4d 628\r
2cb6eabe
EL		 629 This method invokes various internal functions to facilitate\r
630 detection and initialization of USB3 debug port.\r
631\r
632 @retval RETURN_SUCCESS The serial device was initialized.\r
633**/\r
634RETURN_STATUS\r
635EFIAPI\r
636USB3Initialize (\r
637 VOID\r
638 );\r
639\r
640/**\r
641 Return command register value in XHCI controller.\r
642\r
643**/\r
644UINT16\r
645GetXhciPciCommand (\r
646 VOID\r
647 );\r
648\r
649/**\r
650 Allocate aligned memory for XHC's usage.\r
651\r
652 @param BufferSize The size, in bytes, of the Buffer.\r
77695f4d 653\r
2cb6eabe
EL		 654 @return A pointer to the allocated buffer or NULL if allocation fails.\r
655\r
656**/\r
c1e126b1 657VOID *\r
2cb6eabe 658AllocateAlignBuffer (\r
c1e126b1 659 IN UINTN BufferSize\r
2cb6eabe
EL		 660 );\r
661\r
662/**\r
663 The real function to initialize USB3 debug port.\r
77695f4d 664\r
2cb6eabe
EL		 665 This method invokes various internal functions to facilitate\r
666 detection and initialization of USB3 debug port.\r
667\r
668 @retval RETURN_SUCCESS The serial device was initialized.\r
669**/\r
670RETURN_STATUS\r
671EFIAPI\r
672USB3InitializeReal (\r
673 VOID\r
674 );\r
675\r
676/**\r
677 Submits bulk transfer to a bulk endpoint of a USB device.\r
678\r
679 @param Handle The instance of debug device.\r
680 @param Direction The direction of data transfer.\r
681 @param Data Array of pointers to the buffers of data to transmit\r
682 from or receive into.\r
1825c24f 683 @param DataLength The length of the data buffer.\r
2cb6eabe
EL		 684 @param Timeout Indicates the maximum time, in millisecond, which\r
685 the transfer is allowed to complete.\r
686\r
687 @retval EFI_SUCCESS The transfer was completed successfully.\r
688 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.\r
689 @retval EFI_INVALID_PARAMETER Some parameters are invalid.\r
690 @retval EFI_TIMEOUT The transfer failed due to timeout.\r
691 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.\r
692\r
693**/\r
694EFI_STATUS\r
695EFIAPI\r
696XhcDataTransfer (\r
c1e126b1
MK		 697 IN USB3_DEBUG_PORT_HANDLE *Handle,\r
698 IN EFI_USB_DATA_DIRECTION Direction,\r
699 IN OUT VOID *Data,\r
700 IN OUT UINTN *DataLength,\r
701 IN UINTN Timeout\r
2cb6eabe
EL		 702 );\r
703\r
75787f65
SZ		 704/**\r
705 Initialize usb debug port hardware.\r
706\r
707 @param Handle Debug port handle.\r
708\r
709 @retval TRUE The usb debug port hardware configuration is changed.\r
710 @retval FALSE The usb debug port hardware configuration is not changed.\r
711\r
712**/\r
713RETURN_STATUS\r
714EFIAPI\r
715InitializeUsbDebugHardware (\r
c1e126b1 716 IN USB3_DEBUG_PORT_HANDLE *Handle\r
75787f65
SZ		 717 );\r
718\r
719/**\r
720 Return USB3 debug instance address pointer.\r
721\r
77695f4d 722**/\r
75787f65
SZ		 723EFI_PHYSICAL_ADDRESS *\r
724GetUsb3DebugPortInstanceAddrPtr (\r
725 VOID\r
726 );\r
727\r
728/**\r
729 Return USB3 debug instance address.\r
730\r
77695f4d 731**/\r
75787f65
SZ		 732USB3_DEBUG_PORT_HANDLE *\r
733GetUsb3DebugPortInstance (\r
734 VOID\r
735 );\r
736\r
737#endif //__SERIAL_PORT_LIB_USB__\r
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