[mirror_edk2.git] / StandaloneMmPkg / Library / StandaloneMmCoreEntryPoint / AArch64 / CreateHobList.c

/** @file\r
  Creates HOB during Standalone MM Foundation entry point\r
  on ARM platforms.\r
\r
Copyright (c) 2017 - 2021, Arm Ltd. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
\r
#include <PiMm.h>\r
\r
#include <PiPei.h>\r
#include <Guid/MmramMemoryReserve.h>\r
#include <Guid/MpInformation.h>\r
\r
#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>\r
#include <Library/ArmMmuLib.h>\r
#include <Library/ArmSvcLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/SerialPortLib.h>\r
\r
#include <IndustryStandard/ArmStdSmc.h>\r
\r
extern EFI_HOB_HANDOFF_INFO_TABLE*\r
HobConstructor (\r
  IN VOID   *EfiMemoryBegin,\r
  IN UINTN  EfiMemoryLength,\r
  IN VOID   *EfiFreeMemoryBottom,\r
  IN VOID   *EfiFreeMemoryTop\r
  );\r
\r
// GUID to identify HOB with whereabouts of communication buffer with Normal\r
// World\r
extern EFI_GUID gEfiStandaloneMmNonSecureBufferGuid;\r
\r
// GUID to identify HOB where the entry point of the CPU driver will be\r
// populated to allow this entry point driver to invoke it upon receipt of an\r
// event\r
extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;\r
\r
/**\r
  Use the boot information passed by privileged firmware to populate a HOB list\r
  suitable for consumption by the MM Core and drivers.\r
\r
  @param  [in, out] CpuDriverEntryPoint   Address of MM CPU driver entrypoint\r
  @param  [in]      PayloadBootInfo       Boot information passed by privileged\r
                                          firmware\r
\r
**/\r
VOID *\r
CreateHobListFromBootInfo (\r
  IN  OUT  PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,\r
  IN       EFI_SECURE_PARTITION_BOOT_INFO     *PayloadBootInfo\r
)\r
{\r
  EFI_HOB_HANDOFF_INFO_TABLE      *HobStart;\r
  EFI_RESOURCE_ATTRIBUTE_TYPE     Attributes;\r
  UINT32                          Index;\r
  UINT32                          BufferSize;\r
  UINT32                          Flags;\r
  EFI_MMRAM_HOB_DESCRIPTOR_BLOCK  *MmramRangesHob;\r
  EFI_MMRAM_DESCRIPTOR            *MmramRanges;\r
  EFI_MMRAM_DESCRIPTOR            *NsCommBufMmramRange;\r
  MP_INFORMATION_HOB_DATA         *MpInformationHobData;\r
  EFI_PROCESSOR_INFORMATION       *ProcInfoBuffer;\r
  EFI_SECURE_PARTITION_CPU_INFO   *CpuInfo;\r
  ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *CpuDriverEntryPointDesc;\r
\r
  // Create a hoblist with a PHIT and EOH\r
  HobStart = HobConstructor (\r
               (VOID *) (UINTN) PayloadBootInfo->SpMemBase,\r
               (UINTN)  PayloadBootInfo->SpMemLimit - PayloadBootInfo->SpMemBase,\r
               (VOID *) (UINTN) PayloadBootInfo->SpHeapBase,\r
               (VOID *) (UINTN) (PayloadBootInfo->SpHeapBase + PayloadBootInfo->SpHeapSize)\r
               );\r
\r
  // Check that the Hoblist starts at the bottom of the Heap\r
  ASSERT (HobStart == (VOID *) (UINTN) PayloadBootInfo->SpHeapBase);\r
\r
  // Build a Boot Firmware Volume HOB\r
  BuildFvHob (PayloadBootInfo->SpImageBase, PayloadBootInfo->SpImageSize);\r
\r
  // Build a resource descriptor Hob that describes the available physical\r
  // memory range\r
  Attributes = (\r
    EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
    EFI_RESOURCE_ATTRIBUTE_TESTED |\r
    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
    EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
    EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
    EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE\r
  );\r
\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_SYSTEM_MEMORY,\r
    Attributes,\r
    (UINTN) PayloadBootInfo->SpMemBase,\r
    PayloadBootInfo->SpMemLimit - PayloadBootInfo->SpMemBase\r
    );\r
\r
  // Find the size of the GUIDed HOB with MP information\r
  BufferSize = sizeof (MP_INFORMATION_HOB_DATA);\r
  BufferSize += sizeof (EFI_PROCESSOR_INFORMATION) * PayloadBootInfo->NumCpus;\r
\r
  // Create a Guided MP information HOB to enable the ARM TF CPU driver to\r
  // perform per-cpu allocations.\r
  MpInformationHobData = BuildGuidHob (&gMpInformationHobGuid, BufferSize);\r
\r
  // Populate the MP information HOB with the topology information passed by\r
  // privileged firmware\r
  MpInformationHobData->NumberOfProcessors = PayloadBootInfo->NumCpus;\r
  MpInformationHobData->NumberOfEnabledProcessors = PayloadBootInfo->NumCpus;\r
  ProcInfoBuffer = MpInformationHobData->ProcessorInfoBuffer;\r
  CpuInfo = PayloadBootInfo->CpuInfo;\r
\r
  for (Index = 0; Index < PayloadBootInfo->NumCpus; Index++) {\r
    ProcInfoBuffer[Index].ProcessorId      = CpuInfo[Index].Mpidr;\r
    ProcInfoBuffer[Index].Location.Package = GET_CLUSTER_ID(CpuInfo[Index].Mpidr);\r
    ProcInfoBuffer[Index].Location.Core    = GET_CORE_ID(CpuInfo[Index].Mpidr);\r
    ProcInfoBuffer[Index].Location.Thread  = GET_CORE_ID(CpuInfo[Index].Mpidr);\r
\r
    Flags = PROCESSOR_ENABLED_BIT | PROCESSOR_HEALTH_STATUS_BIT;\r
    if (CpuInfo[Index].Flags & CPU_INFO_FLAG_PRIMARY_CPU) {\r
      Flags |= PROCESSOR_AS_BSP_BIT;\r
    }\r
    ProcInfoBuffer[Index].StatusFlag = Flags;\r
  }\r
\r
  // Create a Guided HOB to tell the ARM TF CPU driver the location and length\r
  // of the communication buffer shared with the Normal world.\r
  NsCommBufMmramRange = (EFI_MMRAM_DESCRIPTOR *) BuildGuidHob (\r
                                                   &gEfiStandaloneMmNonSecureBufferGuid,\r
                                                   sizeof (EFI_MMRAM_DESCRIPTOR)\r
                                                   );\r
  NsCommBufMmramRange->PhysicalStart = PayloadBootInfo->SpNsCommBufBase;\r
  NsCommBufMmramRange->CpuStart      = PayloadBootInfo->SpNsCommBufBase;\r
  NsCommBufMmramRange->PhysicalSize  = PayloadBootInfo->SpNsCommBufSize;\r
  NsCommBufMmramRange->RegionState   = EFI_CACHEABLE | EFI_ALLOCATED;\r
\r
  // Create a Guided HOB to enable the ARM TF CPU driver to share its entry\r
  // point and populate it with the address of the shared buffer\r
  CpuDriverEntryPointDesc = (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *) BuildGuidHob (\r
                                                                  &gEfiArmTfCpuDriverEpDescriptorGuid,\r
                                                                  sizeof (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR)\r
                                                                  );\r
\r
  *CpuDriverEntryPoint = NULL;\r
  CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr = CpuDriverEntryPoint;\r
\r
  // Find the size of the GUIDed HOB with SRAM ranges\r
  BufferSize = sizeof (EFI_MMRAM_HOB_DESCRIPTOR_BLOCK);\r
  BufferSize += PayloadBootInfo->NumSpMemRegions * sizeof (EFI_MMRAM_DESCRIPTOR);\r
\r
  // Create a GUIDed HOB with SRAM ranges\r
  MmramRangesHob = BuildGuidHob (&gEfiMmPeiMmramMemoryReserveGuid, BufferSize);\r
\r
  // Fill up the number of MMRAM memory regions\r
  MmramRangesHob->NumberOfMmReservedRegions = PayloadBootInfo->NumSpMemRegions;\r
  // Fill up the MMRAM ranges\r
  MmramRanges = &MmramRangesHob->Descriptor[0];\r
\r
  // Base and size of memory occupied by the Standalone MM image\r
  MmramRanges[0].PhysicalStart = PayloadBootInfo->SpImageBase;\r
  MmramRanges[0].CpuStart      = PayloadBootInfo->SpImageBase;\r
  MmramRanges[0].PhysicalSize  = PayloadBootInfo->SpImageSize;\r
  MmramRanges[0].RegionState   = EFI_CACHEABLE | EFI_ALLOCATED;\r
\r
  // Base and size of buffer shared with privileged Secure world software\r
  MmramRanges[1].PhysicalStart = PayloadBootInfo->SpSharedBufBase;\r
  MmramRanges[1].CpuStart      = PayloadBootInfo->SpSharedBufBase;\r
  MmramRanges[1].PhysicalSize  = PayloadBootInfo->SpPcpuSharedBufSize * PayloadBootInfo->NumCpus;\r
  MmramRanges[1].RegionState   = EFI_CACHEABLE | EFI_ALLOCATED;\r
\r
  // Base and size of buffer used for synchronous communication with Normal\r
  // world software\r
  MmramRanges[2].PhysicalStart = PayloadBootInfo->SpNsCommBufBase;\r
  MmramRanges[2].CpuStart      = PayloadBootInfo->SpNsCommBufBase;\r
  MmramRanges[2].PhysicalSize  = PayloadBootInfo->SpNsCommBufSize;\r
  MmramRanges[2].RegionState   = EFI_CACHEABLE | EFI_ALLOCATED;\r
\r
  // Base and size of memory allocated for stacks for all cpus\r
  MmramRanges[3].PhysicalStart = PayloadBootInfo->SpStackBase;\r
  MmramRanges[3].CpuStart      = PayloadBootInfo->SpStackBase;\r
  MmramRanges[3].PhysicalSize  = PayloadBootInfo->SpPcpuStackSize * PayloadBootInfo->NumCpus;\r
  MmramRanges[3].RegionState   = EFI_CACHEABLE | EFI_ALLOCATED;\r
\r
  // Base and size of heap memory shared by all cpus\r
  MmramRanges[4].PhysicalStart = (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;\r
  MmramRanges[4].CpuStart      = (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;\r
  MmramRanges[4].PhysicalSize  = HobStart->EfiFreeMemoryBottom - (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;\r
  MmramRanges[4].RegionState   = EFI_CACHEABLE | EFI_ALLOCATED;\r
\r
  // Base and size of heap memory shared by all cpus\r
  MmramRanges[5].PhysicalStart = HobStart->EfiFreeMemoryBottom;\r
  MmramRanges[5].CpuStart      = HobStart->EfiFreeMemoryBottom;\r
  MmramRanges[5].PhysicalSize  = HobStart->EfiFreeMemoryTop - HobStart->EfiFreeMemoryBottom;\r
  MmramRanges[5].RegionState   = EFI_CACHEABLE;\r
\r
  return HobStart;\r
}\r
Commit	Line	Data
184558d0 SV	1	/** @file\r
	2	Creates HOB during Standalone MM Foundation entry point\r
	3	on ARM platforms.\r
	4	\r
4779bc6c	5	Copyright (c) 2017 - 2021, Arm Ltd. All rights reserved.<BR>\r
86094561	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
184558d0 SV	7	\r
	8	**/\r
	9	\r
	10	\r
	11	#include <PiMm.h>\r
	12	\r
	13	#include <PiPei.h>\r
	14	#include <Guid/MmramMemoryReserve.h>\r
	15	#include <Guid/MpInformation.h>\r
	16	\r
	17	#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>\r
	18	#include <Library/ArmMmuLib.h>\r
	19	#include <Library/ArmSvcLib.h>\r
	20	#include <Library/DebugLib.h>\r
	21	#include <Library/HobLib.h>\r
	22	#include <Library/BaseLib.h>\r
	23	#include <Library/BaseMemoryLib.h>\r
	24	#include <Library/SerialPortLib.h>\r
	25	\r
	26	#include <IndustryStandard/ArmStdSmc.h>\r
	27	\r
	28	extern EFI_HOB_HANDOFF_INFO_TABLE*\r
	29	HobConstructor (\r
	30	IN VOID *EfiMemoryBegin,\r
	31	IN UINTN EfiMemoryLength,\r
	32	IN VOID *EfiFreeMemoryBottom,\r
	33	IN VOID *EfiFreeMemoryTop\r
	34	);\r
	35	\r
	36	// GUID to identify HOB with whereabouts of communication buffer with Normal\r
	37	// World\r
	38	extern EFI_GUID gEfiStandaloneMmNonSecureBufferGuid;\r
	39	\r
	40	// GUID to identify HOB where the entry point of the CPU driver will be\r
	41	// populated to allow this entry point driver to invoke it upon receipt of an\r
	42	// event\r
	43	extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;\r
	44	\r
	45	/**\r
	46	Use the boot information passed by privileged firmware to populate a HOB list\r
	47	suitable for consumption by the MM Core and drivers.\r
	48	\r
4779bc6c SM	49	@param [in, out] CpuDriverEntryPoint Address of MM CPU driver entrypoint\r
	50	@param [in] PayloadBootInfo Boot information passed by privileged\r
	51	firmware\r
184558d0 SV	52	\r
	53	**/\r
	54	VOID *\r
	55	CreateHobListFromBootInfo (\r
	56	IN OUT PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,\r
	57	IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo\r
	58	)\r
	59	{\r
	60	EFI_HOB_HANDOFF_INFO_TABLE *HobStart;\r
	61	EFI_RESOURCE_ATTRIBUTE_TYPE Attributes;\r
	62	UINT32 Index;\r
	63	UINT32 BufferSize;\r
	64	UINT32 Flags;\r
	65	EFI_MMRAM_HOB_DESCRIPTOR_BLOCK *MmramRangesHob;\r
	66	EFI_MMRAM_DESCRIPTOR *MmramRanges;\r
	67	EFI_MMRAM_DESCRIPTOR *NsCommBufMmramRange;\r
	68	MP_INFORMATION_HOB_DATA *MpInformationHobData;\r
	69	EFI_PROCESSOR_INFORMATION *ProcInfoBuffer;\r
	70	EFI_SECURE_PARTITION_CPU_INFO *CpuInfo;\r
	71	ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *CpuDriverEntryPointDesc;\r
	72	\r
	73	// Create a hoblist with a PHIT and EOH\r
	74	HobStart = HobConstructor (\r
b7f0226a	75	(VOID *) (UINTN) PayloadBootInfo->SpMemBase,\r
184558d0	76	(UINTN) PayloadBootInfo->SpMemLimit - PayloadBootInfo->SpMemBase,\r
b7f0226a EC	77	(VOID *) (UINTN) PayloadBootInfo->SpHeapBase,\r
b7f0226a EC	78	(VOID *) (UINTN) (PayloadBootInfo->SpHeapBase + PayloadBootInfo->SpHeapSize)\r
184558d0 SV	79	);\r
	80	\r
	81	// Check that the Hoblist starts at the bottom of the Heap\r
b7f0226a	82	ASSERT (HobStart == (VOID *) (UINTN) PayloadBootInfo->SpHeapBase);\r
184558d0 SV	83	\r
	84	// Build a Boot Firmware Volume HOB\r
	85	BuildFvHob (PayloadBootInfo->SpImageBase, PayloadBootInfo->SpImageSize);\r
	86	\r
	87	// Build a resource descriptor Hob that describes the available physical\r
	88	// memory range\r
	89	Attributes = (\r
	90	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	91	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	92	EFI_RESOURCE_ATTRIBUTE_TESTED \|\r
	93	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
	94	EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE \|\r
	95	EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE \|\r
	96	EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE\r
	97	);\r
	98	\r
	99	BuildResourceDescriptorHob (\r
	100	EFI_RESOURCE_SYSTEM_MEMORY,\r
	101	Attributes,\r
	102	(UINTN) PayloadBootInfo->SpMemBase,\r
	103	PayloadBootInfo->SpMemLimit - PayloadBootInfo->SpMemBase\r
	104	);\r
	105	\r
	106	// Find the size of the GUIDed HOB with MP information\r
	107	BufferSize = sizeof (MP_INFORMATION_HOB_DATA);\r
	108	BufferSize += sizeof (EFI_PROCESSOR_INFORMATION) * PayloadBootInfo->NumCpus;\r
	109	\r
	110	// Create a Guided MP information HOB to enable the ARM TF CPU driver to\r
	111	// perform per-cpu allocations.\r
	112	MpInformationHobData = BuildGuidHob (&gMpInformationHobGuid, BufferSize);\r
	113	\r
	114	// Populate the MP information HOB with the topology information passed by\r
	115	// privileged firmware\r
	116	MpInformationHobData->NumberOfProcessors = PayloadBootInfo->NumCpus;\r
	117	MpInformationHobData->NumberOfEnabledProcessors = PayloadBootInfo->NumCpus;\r
	118	ProcInfoBuffer = MpInformationHobData->ProcessorInfoBuffer;\r
	119	CpuInfo = PayloadBootInfo->CpuInfo;\r
	120	\r
	121	for (Index = 0; Index < PayloadBootInfo->NumCpus; Index++) {\r
	122	ProcInfoBuffer[Index].ProcessorId = CpuInfo[Index].Mpidr;\r
	123	ProcInfoBuffer[Index].Location.Package = GET_CLUSTER_ID(CpuInfo[Index].Mpidr);\r
	124	ProcInfoBuffer[Index].Location.Core = GET_CORE_ID(CpuInfo[Index].Mpidr);\r
	125	ProcInfoBuffer[Index].Location.Thread = GET_CORE_ID(CpuInfo[Index].Mpidr);\r
	126	\r
	127	Flags = PROCESSOR_ENABLED_BIT \| PROCESSOR_HEALTH_STATUS_BIT;\r
	128	if (CpuInfo[Index].Flags & CPU_INFO_FLAG_PRIMARY_CPU) {\r
	129	Flags \|= PROCESSOR_AS_BSP_BIT;\r
	130	}\r
	131	ProcInfoBuffer[Index].StatusFlag = Flags;\r
	132	}\r
	133	\r
	134	// Create a Guided HOB to tell the ARM TF CPU driver the location and length\r
	135	// of the communication buffer shared with the Normal world.\r
	136	NsCommBufMmramRange = (EFI_MMRAM_DESCRIPTOR *) BuildGuidHob (\r
	137	&gEfiStandaloneMmNonSecureBufferGuid,\r
	138	sizeof (EFI_MMRAM_DESCRIPTOR)\r
	139	);\r
	140	NsCommBufMmramRange->PhysicalStart = PayloadBootInfo->SpNsCommBufBase;\r
	141	NsCommBufMmramRange->CpuStart = PayloadBootInfo->SpNsCommBufBase;\r
	142	NsCommBufMmramRange->PhysicalSize = PayloadBootInfo->SpNsCommBufSize;\r
	143	NsCommBufMmramRange->RegionState = EFI_CACHEABLE \| EFI_ALLOCATED;\r
	144	\r
	145	// Create a Guided HOB to enable the ARM TF CPU driver to share its entry\r
	146	// point and populate it with the address of the shared buffer\r
147	CpuDriverEntryPointDesc = (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *) BuildGuidHob (\r
148	&gEfiArmTfCpuDriverEpDescriptorGuid,\r
149	sizeof (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR)\r
150	);\r
151	\r
152	*CpuDriverEntryPoint = NULL;\r
153	CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr = CpuDriverEntryPoint;\r
154	\r
155	// Find the size of the GUIDed HOB with SRAM ranges\r
156	BufferSize = sizeof (EFI_MMRAM_HOB_DESCRIPTOR_BLOCK);\r
157	BufferSize += PayloadBootInfo->NumSpMemRegions * sizeof (EFI_MMRAM_DESCRIPTOR);\r
158	\r
159	// Create a GUIDed HOB with SRAM ranges\r
160	MmramRangesHob = BuildGuidHob (&gEfiMmPeiMmramMemoryReserveGuid, BufferSize);\r
161	\r
162	// Fill up the number of MMRAM memory regions\r
163	MmramRangesHob->NumberOfMmReservedRegions = PayloadBootInfo->NumSpMemRegions;\r
164	// Fill up the MMRAM ranges\r
165	MmramRanges = &MmramRangesHob->Descriptor[0];\r
166	\r
167	// Base and size of memory occupied by the Standalone MM image\r
168	MmramRanges[0].PhysicalStart = PayloadBootInfo->SpImageBase;\r
169	MmramRanges[0].CpuStart = PayloadBootInfo->SpImageBase;\r
170	MmramRanges[0].PhysicalSize = PayloadBootInfo->SpImageSize;\r
171	MmramRanges[0].RegionState = EFI_CACHEABLE \| EFI_ALLOCATED;\r
172	\r
173	// Base and size of buffer shared with privileged Secure world software\r
174	MmramRanges[1].PhysicalStart = PayloadBootInfo->SpSharedBufBase;\r
175	MmramRanges[1].CpuStart = PayloadBootInfo->SpSharedBufBase;\r
176	MmramRanges[1].PhysicalSize = PayloadBootInfo->SpPcpuSharedBufSize * PayloadBootInfo->NumCpus;\r
177	MmramRanges[1].RegionState = EFI_CACHEABLE \| EFI_ALLOCATED;\r
178	\r
179	// Base and size of buffer used for synchronous communication with Normal\r
180	// world software\r
181	MmramRanges[2].PhysicalStart = PayloadBootInfo->SpNsCommBufBase;\r
182	MmramRanges[2].CpuStart = PayloadBootInfo->SpNsCommBufBase;\r
183	MmramRanges[2].PhysicalSize = PayloadBootInfo->SpNsCommBufSize;\r
184	MmramRanges[2].RegionState = EFI_CACHEABLE \| EFI_ALLOCATED;\r
185	\r
186	// Base and size of memory allocated for stacks for all cpus\r
187	MmramRanges[3].PhysicalStart = PayloadBootInfo->SpStackBase;\r
188	MmramRanges[3].CpuStart = PayloadBootInfo->SpStackBase;\r
189	MmramRanges[3].PhysicalSize = PayloadBootInfo->SpPcpuStackSize * PayloadBootInfo->NumCpus;\r
190	MmramRanges[3].RegionState = EFI_CACHEABLE \| EFI_ALLOCATED;\r
191	\r
192	// Base and size of heap memory shared by all cpus\r
b7f0226a EC	193	MmramRanges[4].PhysicalStart = (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;\r
	194	MmramRanges[4].CpuStart = (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;\r
	195	MmramRanges[4].PhysicalSize = HobStart->EfiFreeMemoryBottom - (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;\r
184558d0 SV	196	MmramRanges[4].RegionState = EFI_CACHEABLE \| EFI_ALLOCATED;\r
	197	\r
	198	// Base and size of heap memory shared by all cpus\r
	199	MmramRanges[5].PhysicalStart = HobStart->EfiFreeMemoryBottom;\r
	200	MmramRanges[5].CpuStart = HobStart->EfiFreeMemoryBottom;\r
	201	MmramRanges[5].PhysicalSize = HobStart->EfiFreeMemoryTop - HobStart->EfiFreeMemoryBottom;\r
	202	MmramRanges[5].RegionState = EFI_CACHEABLE;\r
	203	\r
	204	return HobStart;\r
	205	}\r