[mirror_edk2.git] / StdLib / Include / Ipf / machine / mca_machdep.h

/*	$NetBSD: mca_machdep.h,v 1.1 2006/04/07 14:21:18 cherry Exp $	*/\r
\r
/*-\r
 * Copyright (c) 2002 Marcel Moolenaar\r
 * All rights reserved.\r
 *\r
 * Redistribution and use in source and binary forms, with or without\r
 * modification, are permitted provided that the following conditions\r
 * are met:\r
 *\r
 * 1. Redistributions of source code must retain the above copyright\r
 *    notice, this list of conditions and the following disclaimer.\r
 * 2. Redistributions in binary form must reproduce the above copyright\r
 *    notice, this list of conditions and the following disclaimer in the\r
 *    documentation and/or other materials provided with the distribution.\r
 *\r
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\r
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\r
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\r
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
 *\r
 * $FreeBSD$\r
 */\r
\r
#ifndef _MACHINE_MCA_H_\r
#define _MACHINE_MCA_H_\r
\r
struct mca_record_header {\r
	uint64_t	rh_seqnr;		/* Record id. */\r
	uint8_t		rh_major;		/* BCD (=02). */\r
	uint8_t		rh_minor;		/* BCD (=00). */\r
	uint8_t		rh_error;		/* Error severity. */\r
#define	MCA_RH_ERROR_RECOVERABLE	0\r
#define	MCA_RH_ERROR_FATAL		1\r
#define	MCA_RH_ERROR_CORRECTED		2\r
	uint8_t		rh_flags;\r
#define	MCA_RH_FLAGS_PLATFORM_ID	0x01	/* Platform_id present. */\r
	uint32_t	rh_length;		/* Size including header. */\r
	uint8_t		rh_time[8];\r
#define	MCA_RH_TIME_SEC		0\r
#define	MCA_RH_TIME_MIN		1\r
#define	MCA_RH_TIME_HOUR	2\r
#define	MCA_RH_TIME_MDAY	4\r
#define	MCA_RH_TIME_MON		5\r
#define	MCA_RH_TIME_YEAR	6\r
#define	MCA_RH_TIME_CENT	7\r
	struct uuid	rh_platform;\r
};\r
\r
struct mca_section_header {\r
	struct uuid	sh_uuid;\r
	uint8_t		sh_major;		/* BCD (=02). */\r
	uint8_t		sh_minor;		/* BCD (=00). */\r
	uint8_t		sh_flags;\r
#define	MCA_SH_FLAGS_CORRECTED	0x01		/* Error has been corrected. */\r
#define	MCA_SH_FLAGS_PROPAGATE	0x02		/* Possible propagation. */\r
#define	MCA_SH_FLAGS_RESET	0x04		/* Reset device before use. */\r
#define	MCA_SH_FLAGS_VALID	0x80		/* Flags are valid. */\r
	uint8_t		__reserved;\r
	uint32_t	sh_length;		/* Size including header. */\r
};\r
\r
struct mca_cpu_record {\r
	uint64_t	cpu_flags;\r
#define	MCA_CPU_FLAGS_ERRMAP		(1ULL << 0)\r
#define	MCA_CPU_FLAGS_STATE		(1ULL << 1)\r
#define	MCA_CPU_FLAGS_CR_LID		(1ULL << 2)\r
#define	MCA_CPU_FLAGS_PSI_STRUCT	(1ULL << 3)\r
#define	MCA_CPU_FLAGS_CACHE(x)		(((x) >> 4) & 15)\r
#define	MCA_CPU_FLAGS_TLB(x)		(((x) >> 8) & 15)\r
#define	MCA_CPU_FLAGS_BUS(x)		(((x) >> 12) & 15)\r
#define	MCA_CPU_FLAGS_REG(x)		(((x) >> 16) & 15)\r
#define	MCA_CPU_FLAGS_MS(x)		(((x) >> 20) & 15)\r
#define	MCA_CPU_FLAGS_CPUID		(1ULL << 24)\r
	uint64_t	cpu_errmap;\r
	uint64_t	cpu_state;\r
	uint64_t	cpu_cr_lid;\r
	/* Nx cpu_mod (cache). */\r
	/* Nx cpu_mod (TLB). */\r
	/* Nx cpu_mod (bus). */\r
	/* Nx cpu_mod (reg). */\r
	/* Nx cpu_mod (MS). */\r
	/* cpu_cpuid. */\r
	/* cpu_psi. */\r
};\r
\r
struct mca_cpu_cpuid {\r
	uint64_t	cpuid[6];\r
};\r
\r
struct mca_cpu_mod {\r
	uint64_t	cpu_mod_flags;\r
#define	MCA_CPU_MOD_FLAGS_INFO	(1ULL << 0)\r
#define	MCA_CPU_MOD_FLAGS_REQID	(1ULL << 1)\r
#define	MCA_CPU_MOD_FLAGS_RSPID	(1ULL << 2)\r
#define	MCA_CPU_MOD_FLAGS_TGTID	(1ULL << 3)\r
#define	MCA_CPU_MOD_FLAGS_IP	(1ULL << 4)\r
	uint64_t	cpu_mod_info;\r
	uint64_t	cpu_mod_reqid;\r
	uint64_t	cpu_mod_rspid;\r
	uint64_t	cpu_mod_tgtid;\r
	uint64_t	cpu_mod_ip;\r
};\r
\r
struct mca_cpu_psi {\r
	uint64_t	cpu_psi_flags;\r
#define	MCA_CPU_PSI_FLAGS_STATE	(1ULL << 0)\r
#define	MCA_CPU_PSI_FLAGS_BR	(1ULL << 1)\r
#define	MCA_CPU_PSI_FLAGS_CR	(1ULL << 2)\r
#define	MCA_CPU_PSI_FLAGS_AR	(1ULL << 3)\r
#define	MCA_CPU_PSI_FLAGS_RR	(1ULL << 4)\r
#define	MCA_CPU_PSI_FLAGS_FR	(1ULL << 5)\r
	uint8_t		cpu_psi_state[1024];	/* XXX variable? */\r
	uint64_t	cpu_psi_br[8];\r
	uint64_t	cpu_psi_cr[128];	/* XXX variable? */\r
	uint64_t	cpu_psi_ar[128];	/* XXX variable? */\r
	uint64_t	cpu_psi_rr[8];\r
	uint64_t	cpu_psi_fr[256];	/* 16 bytes per register! */\r
};\r
\r
struct mca_mem_record {\r
	uint64_t	mem_flags;\r
#define	MCA_MEM_FLAGS_STATUS		(1ULL << 0)\r
#define	MCA_MEM_FLAGS_ADDR		(1ULL << 1)\r
#define	MCA_MEM_FLAGS_ADDRMASK		(1ULL << 2)\r
#define	MCA_MEM_FLAGS_NODE		(1ULL << 3)\r
#define	MCA_MEM_FLAGS_CARD		(1ULL << 4)\r
#define	MCA_MEM_FLAGS_MODULE		(1ULL << 5)\r
#define	MCA_MEM_FLAGS_BANK		(1ULL << 6)\r
#define	MCA_MEM_FLAGS_DEVICE		(1ULL << 7)\r
#define	MCA_MEM_FLAGS_ROW		(1ULL << 8)\r
#define	MCA_MEM_FLAGS_COLUMN		(1ULL << 9)\r
#define	MCA_MEM_FLAGS_BITPOS		(1ULL << 10)\r
#define	MCA_MEM_FLAGS_REQID		(1ULL << 11)\r
#define	MCA_MEM_FLAGS_RSPID		(1ULL << 12)\r
#define	MCA_MEM_FLAGS_TGTID		(1ULL << 13)\r
#define	MCA_MEM_FLAGS_BUSDATA		(1ULL << 14)\r
#define	MCA_MEM_FLAGS_OEM_ID		(1ULL << 15)\r
#define	MCA_MEM_FLAGS_OEM_DATA		(1ULL << 16)\r
	uint64_t	mem_status;\r
	uint64_t	mem_addr;\r
	uint64_t	mem_addrmask;\r
	uint16_t	mem_node;\r
	uint16_t	mem_card;\r
	uint16_t	mem_module;\r
	uint16_t	mem_bank;\r
	uint16_t	mem_device;\r
	uint16_t	mem_row;\r
	uint16_t	mem_column;\r
	uint16_t	mem_bitpos;\r
	uint64_t	mem_reqid;\r
	uint64_t	mem_rspid;\r
	uint64_t	mem_tgtid;\r
	uint64_t	mem_busdata;\r
	struct uuid	mem_oem_id;\r
	uint16_t	mem_oem_length;		/* Size of OEM data. */\r
	/* N bytes of OEM platform data. */\r
};\r
\r
struct mca_pcibus_record {\r
	uint64_t	pcibus_flags;\r
#define	MCA_PCIBUS_FLAGS_STATUS		(1ULL << 0)\r
#define	MCA_PCIBUS_FLAGS_ERROR		(1ULL << 1)\r
#define	MCA_PCIBUS_FLAGS_BUS		(1ULL << 2)\r
#define	MCA_PCIBUS_FLAGS_ADDR		(1ULL << 3)\r
#define	MCA_PCIBUS_FLAGS_DATA		(1ULL << 4)\r
#define	MCA_PCIBUS_FLAGS_CMD		(1ULL << 5)\r
#define	MCA_PCIBUS_FLAGS_REQID		(1ULL << 6)\r
#define	MCA_PCIBUS_FLAGS_RSPID		(1ULL << 7)\r
#define	MCA_PCIBUS_FLAGS_TGTID		(1ULL << 8)\r
#define	MCA_PCIBUS_FLAGS_OEM_ID		(1ULL << 9)\r
#define	MCA_PCIBUS_FLAGS_OEM_DATA	(1ULL << 10)\r
	uint64_t	pcibus_status;\r
	uint16_t	pcibus_error;\r
	uint16_t	pcibus_bus;\r
	uint32_t	__reserved;\r
	uint64_t	pcibus_addr;\r
	uint64_t	pcibus_data;\r
	uint64_t	pcibus_cmd;\r
	uint64_t	pcibus_reqid;\r
	uint64_t	pcibus_rspid;\r
	uint64_t	pcibus_tgtid;\r
	struct uuid	pcibus_oem_id;\r
	uint16_t	pcibus_oem_length;	/* Size of OEM data. */\r
	/* N bytes of OEM platform data. */\r
};\r
\r
struct mca_pcidev_record {\r
	uint64_t	pcidev_flags;\r
#define	MCA_PCIDEV_FLAGS_STATUS		(1ULL << 0)\r
#define	MCA_PCIDEV_FLAGS_INFO		(1ULL << 1)\r
#define	MCA_PCIDEV_FLAGS_REG_MEM	(1ULL << 2)\r
#define	MCA_PCIDEV_FLAGS_REG_IO		(1ULL << 3)\r
#define	MCA_PCIDEV_FLAGS_REG_DATA	(1ULL << 4)\r
#define	MCA_PCIDEV_FLAGS_OEM_DATA	(1ULL << 5)\r
	uint64_t	pcidev_status;\r
	struct {\r
		uint16_t	info_vendor;\r
		uint16_t	info_device;\r
		uint32_t	info_ccfn;	/* Class code & funct. nr. */\r
#define	MCA_PCIDEV_INFO_CLASS(x)	((x) & 0xffffff)\r
#define	MCA_PCIDEV_INFO_FUNCTION(x)	(((x) >> 24) & 0xff)\r
		uint8_t		info_slot;\r
		uint8_t		info_bus;\r
		uint8_t		info_segment;\r
		uint8_t		__res0;\r
		uint32_t	__res1;\r
	} pcidev_info;\r
	uint32_t	pcidev_reg_mem;\r
	uint32_t	pcidev_reg_io;\r
	/* Nx pcidev_reg. */\r
	/* M bytes of OEM platform data. */\r
};\r
\r
struct mca_pcidev_reg {\r
	uint64_t	pcidev_reg_addr;\r
	uint64_t	pcidev_reg_data;\r
};\r
\r
#define	MCA_UUID_CPU		\\r
	{0xe429faf1,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}\r
#define	MCA_UUID_MEMORY		\\r
	{0xe429faf2,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}\r
#define	MCA_UUID_SEL		\\r
	{0xe429faf3,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}\r
#define	MCA_UUID_PCI_BUS	\\r
	{0xe429faf4,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}\r
#define	MCA_UUID_SMBIOS		\\r
	{0xe429faf5,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}\r
#define	MCA_UUID_PCI_DEV	\\r
	{0xe429faf6,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}\r
#define	MCA_UUID_GENERIC	\\r
	{0xe429faf7,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}\r
\r
#ifdef _KERNEL\r
\r
void ia64_mca_init(void);\r
void ia64_mca_save_state(int);\r
\r
#endif /* _KERNEL */\r
\r
#endif /* _MACHINE_MCA_H_ */\r
Commit	Line	Data
2aa62f2b	1	/* $NetBSD: mca_machdep.h,v 1.1 2006/04/07 14:21:18 cherry Exp $ */\r
	2	\r
	3	/*-\r
	4	* Copyright (c) 2002 Marcel Moolenaar\r
	5	* All rights reserved.\r
	6	*\r
	7	* Redistribution and use in source and binary forms, with or without\r
	8	* modification, are permitted provided that the following conditions\r
	9	* are met:\r
	10	*\r
	11	* 1. Redistributions of source code must retain the above copyright\r
	12	* notice, this list of conditions and the following disclaimer.\r
	13	* 2. Redistributions in binary form must reproduce the above copyright\r
	14	* notice, this list of conditions and the following disclaimer in the\r
	15	* documentation and/or other materials provided with the distribution.\r
	16	*\r
	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\r
	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\r
	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\r
	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
	27	*\r
	28	* $FreeBSD$\r
	29	*/\r
	30	\r
	31	#ifndef _MACHINE_MCA_H_\r
	32	#define _MACHINE_MCA_H_\r
	33	\r
	34	struct mca_record_header {\r
	35	uint64_t rh_seqnr; /* Record id. */\r
	36	uint8_t rh_major; /* BCD (=02). */\r
	37	uint8_t rh_minor; /* BCD (=00). */\r
	38	uint8_t rh_error; /* Error severity. */\r
	39	#define MCA_RH_ERROR_RECOVERABLE 0\r
	40	#define MCA_RH_ERROR_FATAL 1\r
	41	#define MCA_RH_ERROR_CORRECTED 2\r
	42	uint8_t rh_flags;\r
	43	#define MCA_RH_FLAGS_PLATFORM_ID 0x01 /* Platform_id present. */\r
	44	uint32_t rh_length; /* Size including header. */\r
	45	uint8_t rh_time[8];\r
	46	#define MCA_RH_TIME_SEC 0\r
	47	#define MCA_RH_TIME_MIN 1\r
	48	#define MCA_RH_TIME_HOUR 2\r
	49	#define MCA_RH_TIME_MDAY 4\r
	50	#define MCA_RH_TIME_MON 5\r
	51	#define MCA_RH_TIME_YEAR 6\r
	52	#define MCA_RH_TIME_CENT 7\r
	53	struct uuid rh_platform;\r
	54	};\r
	55	\r
	56	struct mca_section_header {\r
	57	struct uuid sh_uuid;\r
	58	uint8_t sh_major; /* BCD (=02). */\r
	59	uint8_t sh_minor; /* BCD (=00). */\r
	60	uint8_t sh_flags;\r
	61	#define MCA_SH_FLAGS_CORRECTED 0x01 /* Error has been corrected. */\r
	62	#define MCA_SH_FLAGS_PROPAGATE 0x02 /* Possible propagation. */\r
	63	#define MCA_SH_FLAGS_RESET 0x04 /* Reset device before use. */\r
	64	#define MCA_SH_FLAGS_VALID 0x80 /* Flags are valid. */\r
65	uint8_t __reserved;\r
66	uint32_t sh_length; /* Size including header. */\r
67	};\r
68	\r
69	struct mca_cpu_record {\r
70	uint64_t cpu_flags;\r
71	#define MCA_CPU_FLAGS_ERRMAP (1ULL << 0)\r
72	#define MCA_CPU_FLAGS_STATE (1ULL << 1)\r
73	#define MCA_CPU_FLAGS_CR_LID (1ULL << 2)\r
74	#define MCA_CPU_FLAGS_PSI_STRUCT (1ULL << 3)\r
75	#define MCA_CPU_FLAGS_CACHE(x) (((x) >> 4) & 15)\r
76	#define MCA_CPU_FLAGS_TLB(x) (((x) >> 8) & 15)\r
77	#define MCA_CPU_FLAGS_BUS(x) (((x) >> 12) & 15)\r
78	#define MCA_CPU_FLAGS_REG(x) (((x) >> 16) & 15)\r
79	#define MCA_CPU_FLAGS_MS(x) (((x) >> 20) & 15)\r
80	#define MCA_CPU_FLAGS_CPUID (1ULL << 24)\r
81	uint64_t cpu_errmap;\r
82	uint64_t cpu_state;\r
83	uint64_t cpu_cr_lid;\r
84	/* Nx cpu_mod (cache). */\r
85	/* Nx cpu_mod (TLB). */\r
86	/* Nx cpu_mod (bus). */\r
87	/* Nx cpu_mod (reg). */\r
88	/* Nx cpu_mod (MS). */\r
89	/* cpu_cpuid. */\r
90	/* cpu_psi. */\r
91	};\r
92	\r
93	struct mca_cpu_cpuid {\r
94	uint64_t cpuid[6];\r
95	};\r
96	\r
97	struct mca_cpu_mod {\r
98	uint64_t cpu_mod_flags;\r
99	#define MCA_CPU_MOD_FLAGS_INFO (1ULL << 0)\r
100	#define MCA_CPU_MOD_FLAGS_REQID (1ULL << 1)\r
101	#define MCA_CPU_MOD_FLAGS_RSPID (1ULL << 2)\r
102	#define MCA_CPU_MOD_FLAGS_TGTID (1ULL << 3)\r
103	#define MCA_CPU_MOD_FLAGS_IP (1ULL << 4)\r
104	uint64_t cpu_mod_info;\r
105	uint64_t cpu_mod_reqid;\r
106	uint64_t cpu_mod_rspid;\r
107	uint64_t cpu_mod_tgtid;\r
108	uint64_t cpu_mod_ip;\r
109	};\r
110	\r
111	struct mca_cpu_psi {\r
112	uint64_t cpu_psi_flags;\r
113	#define MCA_CPU_PSI_FLAGS_STATE (1ULL << 0)\r
114	#define MCA_CPU_PSI_FLAGS_BR (1ULL << 1)\r
115	#define MCA_CPU_PSI_FLAGS_CR (1ULL << 2)\r
116	#define MCA_CPU_PSI_FLAGS_AR (1ULL << 3)\r
117	#define MCA_CPU_PSI_FLAGS_RR (1ULL << 4)\r
118	#define MCA_CPU_PSI_FLAGS_FR (1ULL << 5)\r
119	uint8_t cpu_psi_state[1024]; /* XXX variable? */\r
120	uint64_t cpu_psi_br[8];\r
121	uint64_t cpu_psi_cr[128]; /* XXX variable? */\r
122	uint64_t cpu_psi_ar[128]; /* XXX variable? */\r
123	uint64_t cpu_psi_rr[8];\r
124	uint64_t cpu_psi_fr[256]; /* 16 bytes per register! */\r
125	};\r
126	\r
127	struct mca_mem_record {\r
128	uint64_t mem_flags;\r
129	#define MCA_MEM_FLAGS_STATUS (1ULL << 0)\r
130	#define MCA_MEM_FLAGS_ADDR (1ULL << 1)\r
131	#define MCA_MEM_FLAGS_ADDRMASK (1ULL << 2)\r
132	#define MCA_MEM_FLAGS_NODE (1ULL << 3)\r
133	#define MCA_MEM_FLAGS_CARD (1ULL << 4)\r
134	#define MCA_MEM_FLAGS_MODULE (1ULL << 5)\r
135	#define MCA_MEM_FLAGS_BANK (1ULL << 6)\r
136	#define MCA_MEM_FLAGS_DEVICE (1ULL << 7)\r
137	#define MCA_MEM_FLAGS_ROW (1ULL << 8)\r
138	#define MCA_MEM_FLAGS_COLUMN (1ULL << 9)\r
139	#define MCA_MEM_FLAGS_BITPOS (1ULL << 10)\r
140	#define MCA_MEM_FLAGS_REQID (1ULL << 11)\r
141	#define MCA_MEM_FLAGS_RSPID (1ULL << 12)\r
142	#define MCA_MEM_FLAGS_TGTID (1ULL << 13)\r
143	#define MCA_MEM_FLAGS_BUSDATA (1ULL << 14)\r
144	#define MCA_MEM_FLAGS_OEM_ID (1ULL << 15)\r
145	#define MCA_MEM_FLAGS_OEM_DATA (1ULL << 16)\r
146	uint64_t mem_status;\r
147	uint64_t mem_addr;\r
148	uint64_t mem_addrmask;\r
149	uint16_t mem_node;\r
150	uint16_t mem_card;\r
151	uint16_t mem_module;\r
152	uint16_t mem_bank;\r
153	uint16_t mem_device;\r
154	uint16_t mem_row;\r
155	uint16_t mem_column;\r
156	uint16_t mem_bitpos;\r
157	uint64_t mem_reqid;\r
158	uint64_t mem_rspid;\r
159	uint64_t mem_tgtid;\r
160	uint64_t mem_busdata;\r
161	struct uuid mem_oem_id;\r
162	uint16_t mem_oem_length; /* Size of OEM data. */\r
163	/* N bytes of OEM platform data. */\r
164	};\r
165	\r
166	struct mca_pcibus_record {\r
167	uint64_t pcibus_flags;\r
168	#define MCA_PCIBUS_FLAGS_STATUS (1ULL << 0)\r
169	#define MCA_PCIBUS_FLAGS_ERROR (1ULL << 1)\r
170	#define MCA_PCIBUS_FLAGS_BUS (1ULL << 2)\r
171	#define MCA_PCIBUS_FLAGS_ADDR (1ULL << 3)\r
172	#define MCA_PCIBUS_FLAGS_DATA (1ULL << 4)\r
173	#define MCA_PCIBUS_FLAGS_CMD (1ULL << 5)\r
174	#define MCA_PCIBUS_FLAGS_REQID (1ULL << 6)\r
175	#define MCA_PCIBUS_FLAGS_RSPID (1ULL << 7)\r
176	#define MCA_PCIBUS_FLAGS_TGTID (1ULL << 8)\r
177	#define MCA_PCIBUS_FLAGS_OEM_ID (1ULL << 9)\r
178	#define MCA_PCIBUS_FLAGS_OEM_DATA (1ULL << 10)\r
179	uint64_t pcibus_status;\r
180	uint16_t pcibus_error;\r
181	uint16_t pcibus_bus;\r
182	uint32_t __reserved;\r
183	uint64_t pcibus_addr;\r
184	uint64_t pcibus_data;\r
185	uint64_t pcibus_cmd;\r
186	uint64_t pcibus_reqid;\r
187	uint64_t pcibus_rspid;\r
188	uint64_t pcibus_tgtid;\r
189	struct uuid pcibus_oem_id;\r
190	uint16_t pcibus_oem_length; /* Size of OEM data. */\r
191	/* N bytes of OEM platform data. */\r
192	};\r
193	\r
194	struct mca_pcidev_record {\r
195	uint64_t pcidev_flags;\r
196	#define MCA_PCIDEV_FLAGS_STATUS (1ULL << 0)\r
197	#define MCA_PCIDEV_FLAGS_INFO (1ULL << 1)\r
198	#define MCA_PCIDEV_FLAGS_REG_MEM (1ULL << 2)\r
199	#define MCA_PCIDEV_FLAGS_REG_IO (1ULL << 3)\r
200	#define MCA_PCIDEV_FLAGS_REG_DATA (1ULL << 4)\r
201	#define MCA_PCIDEV_FLAGS_OEM_DATA (1ULL << 5)\r
202	uint64_t pcidev_status;\r
203	struct {\r
204	uint16_t info_vendor;\r
205	uint16_t info_device;\r
206	uint32_t info_ccfn; /* Class code & funct. nr. */\r
207	#define MCA_PCIDEV_INFO_CLASS(x) ((x) & 0xffffff)\r
208	#define MCA_PCIDEV_INFO_FUNCTION(x) (((x) >> 24) & 0xff)\r
209	uint8_t info_slot;\r
210	uint8_t info_bus;\r
211	uint8_t info_segment;\r
212	uint8_t __res0;\r
213	uint32_t __res1;\r
214	} pcidev_info;\r
215	uint32_t pcidev_reg_mem;\r
216	uint32_t pcidev_reg_io;\r
217	/* Nx pcidev_reg. */\r
218	/* M bytes of OEM platform data. */\r
219	};\r
220	\r
221	struct mca_pcidev_reg {\r
222	uint64_t pcidev_reg_addr;\r
223	uint64_t pcidev_reg_data;\r
224	};\r
225	\r
226	#define MCA_UUID_CPU \\r
227	{0xe429faf1,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}\r
228	#define MCA_UUID_MEMORY \\r
229	{0xe429faf2,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}\r
230	#define MCA_UUID_SEL \\r
231	{0xe429faf3,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}\r
232	#define MCA_UUID_PCI_BUS \\r
233	{0xe429faf4,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}\r
234	#define MCA_UUID_SMBIOS \\r
235	{0xe429faf5,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}\r
236	#define MCA_UUID_PCI_DEV \\r
237	{0xe429faf6,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}\r
238	#define MCA_UUID_GENERIC \\r
239	{0xe429faf7,0x3cb7,0x11d4,0xbc,0xa7,{0x00,0x80,0xc7,0x3c,0x88,0x81}}\r
240	\r
241	#ifdef _KERNEL\r
242	\r
243	void ia64_mca_init(void);\r
244	void ia64_mca_save_state(int);\r
245	\r
246	#endif /* _KERNEL */\r
247	\r
248	#endif /* _MACHINE_MCA_H_ */\r