[mirror_edk2.git] / UefiCpuPkg / Include / Library / LocalApicLib.h

/** @file\r
  Public include file for Local APIC library.\r
\r
  Local APIC library assumes local APIC is enabled. It does not\r
  handles cases where local APIC is disabled.\r
\r
  Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __LOCAL_APIC_LIB_H__\r
#define __LOCAL_APIC_LIB_H__\r
\r
#define LOCAL_APIC_MODE_XAPIC   0x1  ///< xAPIC mode.\r
#define LOCAL_APIC_MODE_X2APIC  0x2  ///< x2APIC mode.\r
\r
/**\r
  Retrieve the base address of local APIC.\r
\r
  @return The base address of local APIC.\r
\r
**/\r
UINTN\r
EFIAPI\r
GetLocalApicBaseAddress (\r
  VOID\r
  );\r
\r
/**\r
  Set the base address of local APIC.\r
\r
  If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r
\r
  @param[in] BaseAddress   Local APIC base address to be set.\r
\r
**/\r
VOID\r
EFIAPI\r
SetLocalApicBaseAddress (\r
  IN UINTN                BaseAddress\r
  );\r
\r
/**\r
  Get the current local APIC mode.\r
\r
  If local APIC is disabled, then ASSERT.\r
\r
  @retval LOCAL_APIC_MODE_XAPIC  current APIC mode is xAPIC.\r
  @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r
**/\r
UINTN\r
EFIAPI\r
GetApicMode (\r
  VOID\r
  );\r
\r
/**\r
  Set the current local APIC mode.\r
\r
  If the specified local APIC mode is not valid, then ASSERT.\r
  If the specified local APIC mode can't be set as current, then ASSERT.\r
\r
  @param ApicMode APIC mode to be set.\r
**/\r
VOID\r
EFIAPI\r
SetApicMode (\r
  IN UINTN  ApicMode\r
  );\r
\r
/**\r
  Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
\r
  In xAPIC mode, the initial local APIC ID is 8-bit, and may be different from current APIC ID.\r
  In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
  the 32-bit local APIC ID is returned as initial APIC ID.\r
\r
  @return  32-bit initial local APIC ID of the executing processor.\r
**/\r
UINT32\r
EFIAPI\r
GetInitialApicId (\r
  VOID\r
  );\r
\r
/**\r
  Get the local APIC ID of the executing processor.\r
\r
  @return  32-bit local APIC ID of the executing processor.\r
**/\r
UINT32\r
EFIAPI\r
GetApicId (\r
  VOID\r
  );\r
\r
/**\r
  Get the value of the local APIC version register.\r
\r
  @return  the value of the local APIC version register.\r
**/\r
UINT32\r
EFIAPI\r
GetApicVersion (\r
  VOID\r
  );\r
\r
/**\r
  Send a Fixed IPI to a specified target processor.\r
\r
  This function returns after the IPI has been accepted by the target processor. \r
\r
  @param  ApicId   The local APIC ID of the target processor.\r
  @param  Vector   The vector number of the interrupt being sent.\r
**/\r
VOID\r
EFIAPI\r
SendFixedIpi (\r
  IN UINT32          ApicId,\r
  IN UINT8           Vector\r
  );\r
\r
/**\r
  Send a Fixed IPI to all processors excluding self.\r
\r
  This function returns after the IPI has been accepted by the target processors. \r
\r
  @param  Vector   The vector number of the interrupt being sent.\r
**/\r
VOID\r
EFIAPI\r
SendFixedIpiAllExcludingSelf (\r
  IN UINT8           Vector\r
  );\r
\r
/**\r
  Send a SMI IPI to a specified target processor.\r
\r
  This function returns after the IPI has been accepted by the target processor. \r
\r
  @param  ApicId   Specify the local APIC ID of the target processor.\r
**/\r
VOID\r
EFIAPI\r
SendSmiIpi (\r
  IN UINT32          ApicId\r
  );\r
\r
/**\r
  Send a SMI IPI to all processors excluding self.\r
\r
  This function returns after the IPI has been accepted by the target processors. \r
**/\r
VOID\r
EFIAPI\r
SendSmiIpiAllExcludingSelf (\r
  VOID\r
  );\r
\r
/**\r
  Send an INIT IPI to a specified target processor.\r
\r
  This function returns after the IPI has been accepted by the target processor. \r
\r
  @param  ApicId   Specify the local APIC ID of the target processor.\r
**/\r
VOID\r
EFIAPI\r
SendInitIpi (\r
  IN UINT32          ApicId\r
  );\r
\r
/**\r
  Send an INIT IPI to all processors excluding self.\r
\r
  This function returns after the IPI has been accepted by the target processors. \r
**/\r
VOID\r
EFIAPI\r
SendInitIpiAllExcludingSelf (\r
  VOID\r
  );\r
\r
/**\r
  Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
\r
  This function returns after the IPI has been accepted by the target processor. \r
\r
  if StartupRoutine >= 1M, then ASSERT.\r
  if StartupRoutine is not multiple of 4K, then ASSERT.\r
\r
  @param  ApicId          Specify the local APIC ID of the target processor.\r
  @param  StartupRoutine  Points to a start-up routine which is below 1M physical\r
                          address and 4K aligned.\r
**/\r
VOID\r
EFIAPI\r
SendInitSipiSipi (\r
  IN UINT32          ApicId,\r
  IN UINT32          StartupRoutine\r
  );\r
\r
/**\r
  Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
\r
  This function returns after the IPI has been accepted by the target processors. \r
\r
  if StartupRoutine >= 1M, then ASSERT.\r
  if StartupRoutine is not multiple of 4K, then ASSERT.\r
\r
  @param  StartupRoutine    Points to a start-up routine which is below 1M physical\r
                            address and 4K aligned.\r
**/\r
VOID\r
EFIAPI\r
SendInitSipiSipiAllExcludingSelf (\r
  IN UINT32          StartupRoutine\r
  );\r
\r
/**\r
  Programming Virtual Wire Mode.\r
\r
  This function programs the local APIC for virtual wire mode following\r
  the example described in chapter A.3 of the MP 1.4 spec.\r
\r
  IOxAPIC is not involved in this type of virtual wire mode.\r
**/\r
VOID\r
EFIAPI\r
ProgramVirtualWireMode (\r
  VOID\r
  );\r
\r
/**\r
  Disable LINT0 & LINT1 interrupts.\r
\r
  This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r
**/\r
VOID\r
EFIAPI\r
DisableLvtInterrupts (\r
  VOID\r
  );\r
\r
/**\r
  Read the initial count value from the init-count register.\r
\r
  @return The initial count value read from the init-count register.\r
**/\r
UINT32\r
EFIAPI\r
GetApicTimerInitCount (\r
  VOID\r
  );\r
\r
/**\r
  Read the current count value from the current-count register.\r
\r
  @return The current count value read from the current-count register.\r
**/\r
UINT32\r
EFIAPI\r
GetApicTimerCurrentCount (\r
  VOID\r
  );\r
\r
/**\r
  Initialize the local APIC timer.\r
\r
  The local APIC timer is initialized and enabled.\r
\r
  @param DivideValue   The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
                       If it is 0, then use the current divide value in the DCR.\r
  @param InitCount     The initial count value.\r
  @param PeriodicMode  If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
  @param Vector        The timer interrupt vector number.\r
**/\r
VOID\r
EFIAPI\r
InitializeApicTimer (\r
  IN UINTN   DivideValue,\r
  IN UINT32  InitCount,\r
  IN BOOLEAN PeriodicMode,\r
  IN UINT8   Vector\r
  );\r
\r
/**\r
  Get the state of the local APIC timer.\r
\r
  @param DivideValue   Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
  @param PeriodicMode  Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
  @param Vector        Return the timer interrupt vector number.\r
**/\r
VOID\r
EFIAPI\r
GetApicTimerState (\r
  OUT UINTN    *DivideValue  OPTIONAL,\r
  OUT BOOLEAN  *PeriodicMode  OPTIONAL,\r
  OUT UINT8    *Vector  OPTIONAL\r
  );\r
\r
/**\r
  Enable the local APIC timer interrupt.\r
**/\r
VOID\r
EFIAPI\r
EnableApicTimerInterrupt (\r
  VOID\r
  );\r
\r
/**\r
  Disable the local APIC timer interrupt.\r
**/\r
VOID\r
EFIAPI\r
DisableApicTimerInterrupt (\r
  VOID\r
  );\r
\r
/**\r
  Get the local APIC timer interrupt state.\r
\r
  @retval TRUE  The local APIC timer interrupt is enabled.\r
  @retval FALSE The local APIC timer interrupt is disabled.\r
**/\r
BOOLEAN\r
EFIAPI\r
GetApicTimerInterruptState (\r
  VOID\r
  );\r
\r
/**\r
  Send EOI to the local APIC.\r
**/\r
VOID\r
EFIAPI\r
SendApicEoi (\r
  VOID\r
  );\r
\r
/**\r
  Get the 32-bit address that a device should use to send a Message Signaled \r
  Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
  @return 32-bit address used to send an MSI to the Local APIC.\r
**/\r
UINT32\r
EFIAPI    \r
GetApicMsiAddress (\r
  VOID\r
  );\r
    \r
/**\r
  Get the 64-bit data value that a device should use to send a Message Signaled \r
  Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
  If Vector is not in range 0x10..0xFE, then ASSERT().\r
  If DeliveryMode is not supported, then ASSERT().\r
  \r
  @param  Vector          The 8-bit interrupt vector associated with the MSI.  \r
                          Must be in the range 0x10..0xFE\r
  @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI \r
                          is handled.  The only supported values are:\r
                            0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
                            1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
                            2: LOCAL_APIC_DELIVERY_MODE_SMI\r
                            4: LOCAL_APIC_DELIVERY_MODE_NMI\r
                            5: LOCAL_APIC_DELIVERY_MODE_INIT\r
                            7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
                          \r
  @param  LevelTriggered  TRUE specifies a level triggered interrupt.  \r
                          FALSE specifies an edge triggered interrupt.\r
  @param  AssertionLevel  Ignored if LevelTriggered is FALSE.\r
                          TRUE specifies a level triggered interrupt that active \r
                          when the interrupt line is asserted.\r
                          FALSE specifies a level triggered interrupt that active \r
                          when the interrupt line is deasserted.\r
\r
  @return 64-bit data value used to send an MSI to the Local APIC.\r
**/\r
UINT64\r
EFIAPI    \r
GetApicMsiValue (\r
  IN UINT8    Vector,\r
  IN UINTN    DeliveryMode,\r
  IN BOOLEAN  LevelTriggered,\r
  IN BOOLEAN  AssertionLevel\r
  );\r
  \r
#endif\r
\r
Commit	Line	Data
bf73cc4b	1	/** @file\r
	2	Public include file for Local APIC library.\r
	3	\r
	4	Local APIC library assumes local APIC is enabled. It does not\r
	5	handles cases where local APIC is disabled.\r
	6	\r
a66e0c7d	7	Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>\r
bf73cc4b	8	This program and the accompanying materials\r
	9	are licensed and made available under the terms and conditions of the BSD License\r
	10	which accompanies this distribution. The full text of the license may be found at\r
	11	http://opensource.org/licenses/bsd-license.php\r
	12	\r
	13	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	14	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	15	\r
	16	**/\r
	17	\r
	18	#ifndef __LOCAL_APIC_LIB_H__\r
	19	#define __LOCAL_APIC_LIB_H__\r
	20	\r
	21	#define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode.\r
	22	#define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode.\r
	23	\r
a66e0c7d	24	/**\r
	25	Retrieve the base address of local APIC.\r
	26	\r
	27	@return The base address of local APIC.\r
	28	\r
	29	**/\r
	30	UINTN\r
	31	EFIAPI\r
	32	GetLocalApicBaseAddress (\r
	33	VOID\r
	34	);\r
	35	\r
	36	/**\r
	37	Set the base address of local APIC.\r
	38	\r
	39	If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r
	40	\r
	41	@param[in] BaseAddress Local APIC base address to be set.\r
	42	\r
	43	**/\r
	44	VOID\r
	45	EFIAPI\r
	46	SetLocalApicBaseAddress (\r
	47	IN UINTN BaseAddress\r
	48	);\r
	49	\r
bf73cc4b	50	/**\r
	51	Get the current local APIC mode.\r
	52	\r
	53	If local APIC is disabled, then ASSERT.\r
	54	\r
	55	@retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r
	56	@retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r
	57	**/\r
	58	UINTN\r
	59	EFIAPI\r
	60	GetApicMode (\r
	61	VOID\r
	62	);\r
	63	\r
	64	/**\r
	65	Set the current local APIC mode.\r
	66	\r
	67	If the specified local APIC mode is not valid, then ASSERT.\r
	68	If the specified local APIC mode can't be set as current, then ASSERT.\r
	69	\r
	70	@param ApicMode APIC mode to be set.\r
	71	**/\r
	72	VOID\r
	73	EFIAPI\r
	74	SetApicMode (\r
	75	IN UINTN ApicMode\r
	76	);\r
	77	\r
	78	/**\r
	79	Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
	80	\r
	81	In xAPIC mode, the initial local APIC ID is 8-bit, and may be different from current APIC ID.\r
	82	In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
	83	the 32-bit local APIC ID is returned as initial APIC ID.\r
	84	\r
	85	@return 32-bit initial local APIC ID of the executing processor.\r
	86	**/\r
	87	UINT32\r
	88	EFIAPI\r
	89	GetInitialApicId (\r
	90	VOID\r
	91	);\r
	92	\r
	93	/**\r
	94	Get the local APIC ID of the executing processor.\r
	95	\r
	96	@return 32-bit local APIC ID of the executing processor.\r
	97	**/\r
	98	UINT32\r
	99	EFIAPI\r
	100	GetApicId (\r
	101	VOID\r
	102	);\r
	103	\r
ae40aef1	104	/**\r
	105	Get the value of the local APIC version register.\r
	106	\r
	107	@return the value of the local APIC version register.\r
	108	**/\r
	109	UINT32\r
	110	EFIAPI\r
	111	GetApicVersion (\r
	112	VOID\r
	113	);\r
	114	\r
	115	/**\r
	116	Send a Fixed IPI to a specified target processor.\r
	117	\r
	118	This function returns after the IPI has been accepted by the target processor. \r
	119	\r
	120	@param ApicId The local APIC ID of the target processor.\r
	121	@param Vector The vector number of the interrupt being sent.\r
	122	**/\r
	123	VOID\r
	124	EFIAPI\r
	125	SendFixedIpi (\r
	126	IN UINT32 ApicId,\r
	127	IN UINT8 Vector\r
	128	);\r
	129	\r
	130	/**\r
	131	Send a Fixed IPI to all processors excluding self.\r
	132	\r
	133	This function returns after the IPI has been accepted by the target processors. \r
	134	\r
	135	@param Vector The vector number of the interrupt being sent.\r
	136	**/\r
	137	VOID\r
	138	EFIAPI\r
	139	SendFixedIpiAllExcludingSelf (\r
	140	IN UINT8 Vector\r
	141	);\r
	142	\r
bf73cc4b	143	/**\r
	144	Send a SMI IPI to a specified target processor.\r
	145	\r
	146	This function returns after the IPI has been accepted by the target processor. \r
	147	\r
	148	@param ApicId Specify the local APIC ID of the target processor.\r
	149	**/\r
	150	VOID\r
	151	EFIAPI\r
	152	SendSmiIpi (\r
	153	IN UINT32 ApicId\r
	154	);\r
	155	\r
	156	/**\r
	157	Send a SMI IPI to all processors excluding self.\r
	158	\r
	159	This function returns after the IPI has been accepted by the target processors. \r
	160	**/\r
	161	VOID\r
	162	EFIAPI\r
	163	SendSmiIpiAllExcludingSelf (\r
	164	VOID\r
	165	);\r
	166	\r
	167	/**\r
	168	Send an INIT IPI to a specified target processor.\r
	169	\r
	170	This function returns after the IPI has been accepted by the target processor. \r
	171	\r
	172	@param ApicId Specify the local APIC ID of the target processor.\r
	173	**/\r
	174	VOID\r
	175	EFIAPI\r
	176	SendInitIpi (\r
	177	IN UINT32 ApicId\r
	178	);\r
	179	\r
	180	/**\r
	181	Send an INIT IPI to all processors excluding self.\r
	182	\r
	183	This function returns after the IPI has been accepted by the target processors. \r
	184	**/\r
	185	VOID\r
	186	EFIAPI\r
	187	SendInitIpiAllExcludingSelf (\r
	188	VOID\r
	189	);\r
	190	\r
	191	/**\r
	192	Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
	193	\r
	194	This function returns after the IPI has been accepted by the target processor. \r
	195	\r
	196	if StartupRoutine >= 1M, then ASSERT.\r
	197	if StartupRoutine is not multiple of 4K, then ASSERT.\r
	198	\r
	199	@param ApicId Specify the local APIC ID of the target processor.\r
	200	@param StartupRoutine Points to a start-up routine which is below 1M physical\r
	201	address and 4K aligned.\r
	202	**/\r
	203	VOID\r
	204	EFIAPI\r
	205	SendInitSipiSipi (\r
	206	IN UINT32 ApicId,\r
207	IN UINT32 StartupRoutine\r
208	);\r
209	\r
210	/**\r
211	Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
212	\r
213	This function returns after the IPI has been accepted by the target processors. \r
214	\r
215	if StartupRoutine >= 1M, then ASSERT.\r
216	if StartupRoutine is not multiple of 4K, then ASSERT.\r
217	\r
218	@param StartupRoutine Points to a start-up routine which is below 1M physical\r
219	address and 4K aligned.\r
220	**/\r
221	VOID\r
222	EFIAPI\r
223	SendInitSipiSipiAllExcludingSelf (\r
224	IN UINT32 StartupRoutine\r
225	);\r
226	\r
227	/**\r
228	Programming Virtual Wire Mode.\r
229	\r
230	This function programs the local APIC for virtual wire mode following\r
231	the example described in chapter A.3 of the MP 1.4 spec.\r
232	\r
233	IOxAPIC is not involved in this type of virtual wire mode.\r
234	**/\r
235	VOID\r
236	EFIAPI\r
237	ProgramVirtualWireMode (\r
238	VOID\r
239	);\r
240	\r
b1b8c631	241	/**\r
	242	Disable LINT0 & LINT1 interrupts.\r
	243	\r
	244	This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r
	245	**/\r
	246	VOID\r
	247	EFIAPI\r
	248	DisableLvtInterrupts (\r
	249	VOID\r
	250	);\r
	251	\r
bf73cc4b	252	/**\r
	253	Read the initial count value from the init-count register.\r
	254	\r
	255	@return The initial count value read from the init-count register.\r
	256	**/\r
	257	UINT32\r
	258	EFIAPI\r
	259	GetApicTimerInitCount (\r
	260	VOID\r
	261	);\r
	262	\r
	263	/**\r
	264	Read the current count value from the current-count register.\r
	265	\r
	266	@return The current count value read from the current-count register.\r
	267	**/\r
	268	UINT32\r
	269	EFIAPI\r
	270	GetApicTimerCurrentCount (\r
	271	VOID\r
	272	);\r
	273	\r
	274	/**\r
	275	Initialize the local APIC timer.\r
	276	\r
	277	The local APIC timer is initialized and enabled.\r
	278	\r
	279	@param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
	280	If it is 0, then use the current divide value in the DCR.\r
	281	@param InitCount The initial count value.\r
	282	@param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
	283	@param Vector The timer interrupt vector number.\r
	284	**/\r
	285	VOID\r
	286	EFIAPI\r
	287	InitializeApicTimer (\r
	288	IN UINTN DivideValue,\r
	289	IN UINT32 InitCount,\r
	290	IN BOOLEAN PeriodicMode,\r
	291	IN UINT8 Vector\r
	292	);\r
	293	\r
ae40aef1	294	/**\r
	295	Get the state of the local APIC timer.\r
	296	\r
	297	@param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
	298	@param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
	299	@param Vector Return the timer interrupt vector number.\r
	300	**/\r
	301	VOID\r
	302	EFIAPI\r
	303	GetApicTimerState (\r
	304	OUT UINTN *DivideValue OPTIONAL,\r
	305	OUT BOOLEAN *PeriodicMode OPTIONAL,\r
	306	OUT UINT8 *Vector OPTIONAL\r
	307	);\r
	308	\r
bf73cc4b	309	/**\r
	310	Enable the local APIC timer interrupt.\r
	311	**/\r
	312	VOID\r
	313	EFIAPI\r
	314	EnableApicTimerInterrupt (\r
	315	VOID\r
	316	);\r
	317	\r
	318	/**\r
	319	Disable the local APIC timer interrupt.\r
	320	**/\r
	321	VOID\r
	322	EFIAPI\r
	323	DisableApicTimerInterrupt (\r
	324	VOID\r
	325	);\r
	326	\r
	327	/**\r
	328	Get the local APIC timer interrupt state.\r
	329	\r
	330	@retval TRUE The local APIC timer interrupt is enabled.\r
	331	@retval FALSE The local APIC timer interrupt is disabled.\r
	332	**/\r
	333	BOOLEAN\r
	334	EFIAPI\r
	335	GetApicTimerInterruptState (\r
	336	VOID\r
	337	);\r
	338	\r
	339	/**\r
	340	Send EOI to the local APIC.\r
	341	**/\r
	342	VOID\r
	343	EFIAPI\r
	344	SendApicEoi (\r
	345	VOID\r
	346	);\r
	347	\r
5f867ad0	348	/**\r
	349	Get the 32-bit address that a device should use to send a Message Signaled \r
	350	Interrupt (MSI) to the Local APIC of the currently executing processor.\r
	351	\r
	352	@return 32-bit address used to send an MSI to the Local APIC.\r
	353	**/\r
	354	UINT32\r
	355	EFIAPI \r
	356	GetApicMsiAddress (\r
	357	VOID\r
	358	);\r
	359	\r
	360	/**\r
	361	Get the 64-bit data value that a device should use to send a Message Signaled \r
	362	Interrupt (MSI) to the Local APIC of the currently executing processor.\r
	363	\r
	364	If Vector is not in range 0x10..0xFE, then ASSERT().\r
	365	If DeliveryMode is not supported, then ASSERT().\r
	366	\r
	367	@param Vector The 8-bit interrupt vector associated with the MSI. \r
	368	Must be in the range 0x10..0xFE\r
	369	@param DeliveryMode A 3-bit value that specifies how the recept of the MSI \r
	370	is handled. The only supported values are:\r
	371	0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
	372	1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
	373	2: LOCAL_APIC_DELIVERY_MODE_SMI\r
	374	4: LOCAL_APIC_DELIVERY_MODE_NMI\r
	375	5: LOCAL_APIC_DELIVERY_MODE_INIT\r
	376	7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
	377	\r
	378	@param LevelTriggered TRUE specifies a level triggered interrupt. \r
	379	FALSE specifies an edge triggered interrupt.\r
	380	@param AssertionLevel Ignored if LevelTriggered is FALSE.\r
	381	TRUE specifies a level triggered interrupt that active \r
	382	when the interrupt line is asserted.\r
	383	FALSE specifies a level triggered interrupt that active \r
	384	when the interrupt line is deasserted.\r
	385	\r
	386	@return 64-bit data value used to send an MSI to the Local APIC.\r
	387	**/\r
	388	UINT64\r
	389	EFIAPI \r
	390	GetApicMsiValue (\r
	391	IN UINT8 Vector,\r
	392	IN UINTN DeliveryMode,\r
	393	IN BOOLEAN LevelTriggered,\r
	394	IN BOOLEAN AssertionLevel\r
	395	);\r
	396	\r
bf73cc4b	397	#endif\r
bf73cc4b	398	\r