UefiCpuPkg/MpLib: fix potential overflow issue.

[mirror_edk2.git] / UefiCpuPkg / Include / Register / ArchitecturalMsr.h

/** @file\r
  Architectural MSR Definitions.\r
\r
  Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
  are provided for MSRs that contain one or more bit fields.  If the MSR value\r
  returned is a single 32-bit or 64-bit value, then a data structure is not\r
  provided for that MSR.\r
\r
  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
  @par Specification Reference:\r
  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
  September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.1.\r
\r
  @par Specification Reference:\r
  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
  September 2016, Appendix A VMX Capability Reporting Facility, Section A.1.\r
\r
  @par Specification Reference:\r
  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
  September 2016, Appendix A VMX Capability Reporting Facility, Section A.6.\r
\r
**/\r
\r
#ifndef __ARCHITECTURAL_MSR_H__\r
#define __ARCHITECTURAL_MSR_H__\r
\r
/**\r
  See Section 35.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r
\r
  @param  ECX  MSR_IA32_P5_MC_ADDR (0x00000000)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);\r
  AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);\r
  @endcode\r
  @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.\r
**/\r
#define MSR_IA32_P5_MC_ADDR                      0x00000000\r
\r
\r
/**\r
  See Section 35.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r
\r
  @param  ECX  MSR_IA32_P5_MC_TYPE (0x00000001)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);\r
  AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);\r
  @endcode\r
  @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.\r
**/\r
#define MSR_IA32_P5_MC_TYPE                      0x00000001\r
\r
\r
/**\r
  See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced\r
  at Display Family / Display Model 0F_03H.\r
\r
  @param  ECX  MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);\r
  AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);\r
  @endcode\r
  @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.\r
**/\r
#define MSR_IA32_MONITOR_FILTER_SIZE             0x00000006\r
\r
\r
/**\r
  See Section 17.15, "Time-Stamp Counter.". Introduced at Display Family /\r
  Display Model 05_01H.\r
\r
  @param  ECX  MSR_IA32_TIME_STAMP_COUNTER (0x00000010)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);\r
  AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);\r
  @endcode\r
  @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.\r
**/\r
#define MSR_IA32_TIME_STAMP_COUNTER              0x00000010\r
\r
\r
/**\r
  Platform ID (RO)  The operating system can use this MSR to determine "slot"\r
  information for the processor and the proper microcode update to load.\r
  Introduced at Display Family / Display Model 06_01H.\r
\r
  @param  ECX  MSR_IA32_PLATFORM_ID (0x00000017)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PLATFORM_ID_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);\r
  @endcode\r
  @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.\r
**/\r
#define MSR_IA32_PLATFORM_ID                     0x00000017\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PLATFORM_ID\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32  Reserved1:32;\r
    UINT32  Reserved2:18;\r
    ///\r
    /// [Bits 52:50] Platform Id (RO)  Contains information concerning the\r
    /// intended platform for the processor.\r
    ///   52 51 50\r
    ///   -- -- --\r
    ///    0  0  0  Processor Flag 0.\r
    ///    0  0  1  Processor Flag 1\r
    ///    0  1  0  Processor Flag 2\r
    ///    0  1  1  Processor Flag 3\r
    ///    1  0  0  Processor Flag 4\r
    ///    1  0  1  Processor Flag 5\r
    ///    1  1  0  Processor Flag 6\r
    ///    1  1  1  Processor Flag 7\r
    ///\r
    UINT32  PlatformId:3;\r
    UINT32  Reserved3:11;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PLATFORM_ID_REGISTER;\r
\r
\r
/**\r
  06_01H.\r
\r
  @param  ECX  MSR_IA32_APIC_BASE (0x0000001B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_APIC_BASE_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_APIC_BASE_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_APIC_BASE_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
  AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.\r
**/\r
#define MSR_IA32_APIC_BASE                       0x0000001B\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_APIC_BASE\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32  Reserved1:8;\r
    ///\r
    /// [Bit 8] BSP flag (R/W).\r
    ///\r
    UINT32  BSP:1;\r
    UINT32  Reserved2:1;\r
    ///\r
    /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display\r
    /// Model 06_1AH.\r
    ///\r
    UINT32  EXTD:1;\r
    ///\r
    /// [Bit 11] APIC Global Enable (R/W).\r
    ///\r
    UINT32  EN:1;\r
    ///\r
    /// [Bits 31:12] APIC Base (R/W).\r
    ///\r
    UINT32  ApicBase:20;\r
    ///\r
    /// [Bits 63:32] APIC Base (R/W).\r
    ///\r
    UINT32  ApicBaseHi:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_APIC_BASE_REGISTER;\r
\r
\r
/**\r
  Control Features in Intel 64 Processor (R/W). If any one enumeration\r
  condition for defined bit field holds.\r
\r
  @param  ECX  MSR_IA32_FEATURE_CONTROL (0x0000003A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_FEATURE_CONTROL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);\r
  AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r
**/\r
#define MSR_IA32_FEATURE_CONTROL                 0x0000003A\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from\r
    /// being written, writes to this bit will result in GP(0). Note: Once the\r
    /// Lock bit is set, the contents of this register cannot be modified.\r
    /// Therefore the lock bit must be set after configuring support for Intel\r
    /// Virtualization Technology and prior to transferring control to an\r
    /// option ROM or the OS. Hence, once the Lock bit is set, the entire\r
    /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD\r
    /// is not deasserted. If any one enumeration condition for defined bit\r
    /// field position greater than bit 0 holds.\r
    ///\r
    UINT32  Lock:1;\r
    ///\r
    /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a\r
    /// system executive to use VMX in conjunction with SMX to support\r
    /// Intel(R) Trusted Execution Technology. BIOS must set this bit only\r
    /// when the CPUID function 1 returns VMX feature flag and SMX feature\r
    /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&\r
    /// CPUID.01H:ECX[6] = 1.\r
    ///\r
    UINT32  EnableVmxInsideSmx:1;\r
    ///\r
    /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX\r
    /// for system executive that do not require SMX. BIOS must set this bit\r
    /// only when the CPUID function 1 returns VMX feature flag set (ECX bit\r
    /// 5). If CPUID.01H:ECX[5] = 1.\r
    ///\r
    UINT32  EnableVmxOutsideSmx:1;\r
    UINT32  Reserved1:5;\r
    ///\r
    /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit\r
    /// in the field represents an enable control for a corresponding SENTER\r
    /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If\r
    /// CPUID.01H:ECX[6] = 1.\r
    ///\r
    UINT32  SenterLocalFunctionEnables:7;\r
    ///\r
    /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable\r
    /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit\r
    /// 6] is set. If CPUID.01H:ECX[6] = 1.\r
    ///\r
    UINT32  SenterGlobalEnable:1;\r
    UINT32  Reserved2:1;\r
    ///\r
    /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to\r
    /// enable runtime reconfiguration of SGX Launch Control via\r
    /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.\r
    ///\r
    UINT32  SgxLaunchControlEnable:1;\r
    ///\r
    /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX\r
    /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r
    ///\r
    UINT32  SgxEnable:1;\r
    UINT32  Reserved3:1;\r
    ///\r
    /// [Bit 20] LMCE On (R/WL): When set, system software can program the\r
    /// MSRs associated with LMCE to configure delivery of some machine check\r
    /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.\r
    ///\r
    UINT32  LmceOn:1;\r
    UINT32  Reserved4:11;\r
    UINT32  Reserved5:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_FEATURE_CONTROL_REGISTER;\r
\r
\r
/**\r
  Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,\r
  ECX=0H): EBX[1] = 1. THREAD_ADJUST:  Local offset value of the IA32_TSC for\r
  a logical processor. Reset value is Zero. A write to IA32_TSC will modify\r
  the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does\r
  not affect the internal invariant TSC hardware.\r
\r
  @param  ECX  MSR_IA32_TSC_ADJUST (0x0000003B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);\r
  AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);\r
  @endcode\r
  @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.\r
**/\r
#define MSR_IA32_TSC_ADJUST                      0x0000003B\r
\r
\r
/**\r
  BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a\r
  microcode update to be loaded into the processor. See Section 9.11.6,\r
  "Microcode Update Loader." A processor may prevent writing to this MSR when\r
  loading guest states on VM entries or saving guest states on VM exits.\r
  Introduced at Display Family / Display Model 06_01H.\r
\r
  @param  ECX  MSR_IA32_BIOS_UPDT_TRIG (0x00000079)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = 0;\r
  AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);\r
  @endcode\r
  @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.\r
**/\r
#define MSR_IA32_BIOS_UPDT_TRIG                  0x00000079\r
\r
\r
/**\r
  BIOS Update Signature (RO) Returns the microcode update signature following\r
  the execution of CPUID.01H. A processor may prevent writing to this MSR when\r
  loading guest states on VM entries or saving guest states on VM exits.\r
  Introduced at Display Family / Display Model 06_01H.\r
\r
  @param  ECX  MSR_IA32_BIOS_SIGN_ID (0x0000008B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_BIOS_SIGN_ID_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);\r
  @endcode\r
  @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.\r
**/\r
#define MSR_IA32_BIOS_SIGN_ID                    0x0000008B\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32  Reserved:32;\r
    ///\r
    /// [Bits 63:32] Microcode update signature. This field contains the\r
    /// signature of the currently loaded microcode update when read following\r
    /// the execution of the CPUID instruction, function 1. It is required\r
    /// that this register field be pre-loaded with zero prior to executing\r
    /// the CPUID, function 1. If the field remains equal to zero, then there\r
    /// is no microcode update loaded. Another nonzero value will be the\r
    /// signature.\r
    ///\r
    UINT32  MicrocodeUpdateSignature:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_BIOS_SIGN_ID_REGISTER;\r
\r
\r
/**\r
  IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the\r
  SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the\r
  default value is the digest of Intel's signing key. Read permitted If\r
  CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):\r
  EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.\r
\r
  @param  ECX  MSR_IA32_SGXLEPUBKEYHASHn\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);\r
  AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);\r
  @endcode\r
  @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.\r
        MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.\r
        MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.\r
        MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.\r
  @{\r
**/\r
#define MSR_IA32_SGXLEPUBKEYHASH0                0x0000008C\r
#define MSR_IA32_SGXLEPUBKEYHASH1                0x0000008D\r
#define MSR_IA32_SGXLEPUBKEYHASH2                0x0000008E\r
#define MSR_IA32_SGXLEPUBKEYHASH3                0x0000008F\r
/// @}\r
\r
\r
/**\r
  SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =\r
  1.\r
\r
  @param  ECX  MSR_IA32_SMM_MONITOR_CTL (0x0000009B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_SMM_MONITOR_CTL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);\r
  AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.\r
**/\r
#define MSR_IA32_SMM_MONITOR_CTL                 0x0000009B\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Valid (R/W).  The STM may be invoked using VMCALL only if this\r
    /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment\r
    /// (see Section 34.15.6), the dual-monitor treatment cannot be activated\r
    /// if the bit is 0. This bit is cleared when the logical processor is\r
    /// reset.\r
    ///\r
    UINT32  Valid:1;\r
    UINT32  Reserved1:1;\r
    ///\r
    /// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the\r
    /// default treatment of SMIs and SMM.  Executions of VMXOFF unblock SMIs\r
    /// unless bit 2 is 1 (the value of bit 0 is irrelevant).\r
    ///\r
    UINT32  BlockSmi:1;\r
    UINT32  Reserved2:9;\r
    ///\r
    /// [Bits 31:12] MSEG Base (R/W).\r
    ///\r
    UINT32  MsegBase:20;\r
    UINT32  Reserved3:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_SMM_MONITOR_CTL_REGISTER;\r
\r
/**\r
  MSEG header that is located at the physical address specified by the MsegBase\r
  field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
**/\r
typedef struct {\r
  ///\r
  /// Different processors may use different MSEG revision identifiers. These\r
  /// identifiers enable software to avoid using an MSEG header formatted for\r
  /// one processor on a processor that uses a different format. Software can\r
  /// discover the MSEG revision identifier that a processor uses by reading\r
  /// the VMX capability MSR IA32_VMX_MISC.\r
  //\r
  UINT32  MsegHeaderRevision;\r
  ///\r
  /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field\r
  /// is the IA-32e mode SMM feature bit. It indicates whether the logical\r
  /// processor will be in IA-32e mode after the STM is activated.\r
  ///\r
  UINT32  MonitorFeatures;\r
  UINT32  GdtrLimit;\r
  UINT32  GdtrBaseOffset;\r
  UINT32  CsSelector;\r
  UINT32  EipOffset;\r
  UINT32  EspOffset;\r
  UINT32  Cr3Offset;\r
  ///\r
  /// Pad header so total size is 2KB\r
  ///\r
  UINT8   Reserved[SIZE_2KB - 8 * sizeof (UINT32)];\r
} MSEG_HEADER;\r
\r
///\r
/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER\r
///\r
#define STM_FEATURES_IA32E 0x1\r
///\r
/// @}\r
///\r
\r
/**\r
  Base address of the logical processor's SMRAM image (RO, SMM only). If\r
  IA32_VMX_MISC[15].\r
\r
  @param  ECX  MSR_IA32_SMBASE (0x0000009E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_SMBASE);\r
  @endcode\r
  @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.\r
**/\r
#define MSR_IA32_SMBASE                          0x0000009E\r
\r
\r
/**\r
  General Performance Counters (R/W).\r
  MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.\r
\r
  @param  ECX  MSR_IA32_PMCn\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_PMC0);\r
  AsmWriteMsr64 (MSR_IA32_PMC0, Msr);\r
  @endcode\r
  @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.\r
        MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.\r
        MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.\r
        MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.\r
        MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.\r
        MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.\r
        MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.\r
        MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.\r
  @{\r
**/\r
#define MSR_IA32_PMC0                            0x000000C1\r
#define MSR_IA32_PMC1                            0x000000C2\r
#define MSR_IA32_PMC2                            0x000000C3\r
#define MSR_IA32_PMC3                            0x000000C4\r
#define MSR_IA32_PMC4                            0x000000C5\r
#define MSR_IA32_PMC5                            0x000000C6\r
#define MSR_IA32_PMC6                            0x000000C7\r
#define MSR_IA32_PMC7                            0x000000C8\r
/// @}\r
\r
\r
/**\r
  TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.\r
  C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative\r
  to TSC freq.) when the logical processor is in C0. Cleared upon overflow /\r
  wrap-around of IA32_APERF.\r
\r
  @param  ECX  MSR_IA32_MPERF (0x000000E7)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MPERF);\r
  AsmWriteMsr64 (MSR_IA32_MPERF, Msr);\r
  @endcode\r
  @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.\r
**/\r
#define MSR_IA32_MPERF                           0x000000E7\r
\r
\r
/**\r
  Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =\r
  1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at\r
  the coordinated clock frequency, when the logical processor is in C0.\r
  Cleared upon overflow / wrap-around of IA32_MPERF.\r
\r
  @param  ECX  MSR_IA32_APERF (0x000000E8)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_APERF);\r
  AsmWriteMsr64 (MSR_IA32_APERF, Msr);\r
  @endcode\r
  @note MSR_IA32_APERF is defined as IA32_APERF in SDM.\r
**/\r
#define MSR_IA32_APERF                           0x000000E8\r
\r
\r
/**\r
  MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".\r
  Introduced at Display Family / Display Model 06_01H.\r
\r
  @param  ECX  MSR_IA32_MTRRCAP (0x000000FE)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_MTRRCAP_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_MTRRCAP_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_MTRRCAP_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r
  @endcode\r
  @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.\r
**/\r
#define MSR_IA32_MTRRCAP                         0x000000FE\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_MTRRCAP\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] VCNT: The number of variable memory type ranges in the\r
    /// processor.\r
    ///\r
    UINT32  VCNT:8;\r
    ///\r
    /// [Bit 8] Fixed range MTRRs are supported when set.\r
    ///\r
    UINT32  FIX:1;\r
    UINT32  Reserved1:1;\r
    ///\r
    /// [Bit 10] WC Supported when set.\r
    ///\r
    UINT32  WC:1;\r
    ///\r
    /// [Bit 11] SMRR Supported when set.\r
    ///\r
    UINT32  SMRR:1;\r
    UINT32  Reserved2:20;\r
    UINT32  Reserved3:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_MTRRCAP_REGISTER;\r
\r
\r
/**\r
  SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r
\r
  @param  ECX  MSR_IA32_SYSENTER_CS (0x00000174)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_SYSENTER_CS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);\r
  AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.\r
**/\r
#define MSR_IA32_SYSENTER_CS                     0x00000174\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_SYSENTER_CS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 15:0] CS Selector.\r
    ///\r
    UINT32  CS:16;\r
    UINT32  Reserved1:16;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_SYSENTER_CS_REGISTER;\r
\r
\r
/**\r
  SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r
\r
  @param  ECX  MSR_IA32_SYSENTER_ESP (0x00000175)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);\r
  AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);\r
  @endcode\r
  @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.\r
**/\r
#define MSR_IA32_SYSENTER_ESP                    0x00000175\r
\r
\r
/**\r
  SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r
\r
  @param  ECX  MSR_IA32_SYSENTER_EIP (0x00000176)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);\r
  AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);\r
  @endcode\r
  @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.\r
**/\r
#define MSR_IA32_SYSENTER_EIP                    0x00000176\r
\r
\r
/**\r
  Global Machine Check Capability (RO). Introduced at Display Family / Display\r
  Model 06_01H.\r
\r
  @param  ECX  MSR_IA32_MCG_CAP (0x00000179)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_MCG_CAP_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_MCG_CAP_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_MCG_CAP_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r
  @endcode\r
  @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
**/\r
#define MSR_IA32_MCG_CAP                         0x00000179\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_MCG_CAP\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Count: Number of reporting banks.\r
    ///\r
    UINT32  Count:8;\r
    ///\r
    /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.\r
    ///\r
    UINT32  MCG_CTL_P:1;\r
    ///\r
    /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present\r
    /// if this bit is set.\r
    ///\r
    UINT32  MCG_EXT_P:1;\r
    ///\r
    /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.\r
    /// Introduced at Display Family / Display Model 06_01H.\r
    ///\r
    UINT32  MCP_CMCI_P:1;\r
    ///\r
    /// [Bit 11] MCG_TES_P: Threshold-based error status register are present\r
    /// if this bit is set.\r
    ///\r
    UINT32  MCG_TES_P:1;\r
    UINT32  Reserved1:4;\r
    ///\r
    /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state\r
    /// registers present.\r
    ///\r
    UINT32  MCG_EXT_CNT:8;\r
    ///\r
    /// [Bit 24] MCG_SER_P: The processor supports software error recovery if\r
    /// this bit is set.\r
    ///\r
    UINT32  MCG_SER_P:1;\r
    UINT32  Reserved2:1;\r
    ///\r
    /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform\r
    /// firmware to be invoked when an error is detected so that it may\r
    /// provide additional platform specific information in an ACPI format\r
    /// "Generic Error Data Entry" that augments the data included in machine\r
    /// check bank registers. Introduced at Display Family / Display Model\r
    /// 06_3EH.\r
    ///\r
    UINT32  MCG_ELOG_P:1;\r
    ///\r
    /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended\r
    /// state in IA32_MCG_STATUS and associated MSR necessary to configure\r
    /// Local Machine Check Exception (LMCE). Introduced at Display Family /\r
    /// Display Model 06_3EH.\r
    ///\r
    UINT32  MCG_LMCE_P:1;\r
    UINT32  Reserved3:4;\r
    UINT32  Reserved4:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_MCG_CAP_REGISTER;\r
\r
\r
/**\r
  Global Machine Check Status (R/W0). Introduced at Display Family / Display\r
  Model 06_01H.\r
\r
  @param  ECX  MSR_IA32_MCG_STATUS (0x0000017A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_MCG_STATUS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);\r
  AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.\r
**/\r
#define MSR_IA32_MCG_STATUS                      0x0000017A\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_MCG_STATUS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display\r
    /// Model 06_01H.\r
    ///\r
    UINT32  RIPV:1;\r
    ///\r
    /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display\r
    /// Model 06_01H.\r
    ///\r
    UINT32  EIPV:1;\r
    ///\r
    /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family\r
    /// / Display Model 06_01H.\r
    ///\r
    UINT32  MCIP:1;\r
    ///\r
    /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.\r
    ///\r
    UINT32  LMCE_S:1;\r
    UINT32  Reserved1:28;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_MCG_STATUS_REGISTER;\r
\r
\r
/**\r
  Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.\r
\r
  @param  ECX  MSR_IA32_MCG_CTL (0x0000017B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);\r
  AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);\r
  @endcode\r
  @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.\r
**/\r
#define MSR_IA32_MCG_CTL                         0x0000017B\r
\r
\r
/**\r
  Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.\r
\r
  @param  ECX  MSR_IA32_PERFEVTSELn\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PERFEVTSEL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);\r
  AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.\r
        MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.\r
        MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.\r
        MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r
  @{\r
**/\r
#define MSR_IA32_PERFEVTSEL0                     0x00000186\r
#define MSR_IA32_PERFEVTSEL1                     0x00000187\r
#define MSR_IA32_PERFEVTSEL2                     0x00000188\r
#define MSR_IA32_PERFEVTSEL3                     0x00000189\r
/// @}\r
\r
/**\r
  MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to\r
  #MSR_IA32_PERFEVTSEL3\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r
    ///\r
    UINT32  EventSelect:8;\r
    ///\r
    /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r
    /// detect on the selected event logic.\r
    ///\r
    UINT32  UMASK:8;\r
    ///\r
    /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r
    ///\r
    UINT32  USR:1;\r
    ///\r
    /// [Bit 17] OS: Counts while in privilege level is ring 0.\r
    ///\r
    UINT32  OS:1;\r
    ///\r
    /// [Bit 18] Edge: Enables edge detection if set.\r
    ///\r
    UINT32  E:1;\r
    ///\r
    /// [Bit 19] PC: enables pin control.\r
    ///\r
    UINT32  PC:1;\r
    ///\r
    /// [Bit 20] INT: enables interrupt on counter overflow.\r
    ///\r
    UINT32  INT:1;\r
    ///\r
    /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r
    /// event conditions occurring across all logical processors sharing a\r
    /// processor core. When set to 0, the counter only increments the\r
    /// associated event conditions occurring in the logical processor which\r
    /// programmed the MSR.\r
    ///\r
    UINT32  ANY:1;\r
    ///\r
    /// [Bit 22] EN: enables the corresponding performance counter to commence\r
    /// counting when this bit is set.\r
    ///\r
    UINT32  EN:1;\r
    ///\r
    /// [Bit 23] INV: invert the CMASK.\r
    ///\r
    UINT32  INV:1;\r
    ///\r
    /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r
    /// performance counter increments each cycle if the event count is\r
    /// greater than or equal to the CMASK.\r
    ///\r
    UINT32  CMASK:8;\r
    UINT32  Reserved:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PERFEVTSEL_REGISTER;\r
\r
\r
/**\r
  Current performance state(P-State) operating point (RO). Introduced at\r
  Display Family / Display Model 0F_03H.\r
\r
  @param  ECX  MSR_IA32_PERF_STATUS (0x00000198)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PERF_STATUS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);\r
  @endcode\r
  @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.\r
**/\r
#define MSR_IA32_PERF_STATUS                     0x00000198\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PERF_STATUS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 15:0] Current performance State Value.\r
    ///\r
    UINT32  State:16;\r
    UINT32  Reserved1:16;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PERF_STATUS_REGISTER;\r
\r
\r
/**\r
  (R/W). Introduced at Display Family / Display Model 0F_03H.\r
\r
  @param  ECX  MSR_IA32_PERF_CTL (0x00000199)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_CTL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_CTL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PERF_CTL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);\r
  AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.\r
**/\r
#define MSR_IA32_PERF_CTL                        0x00000199\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PERF_CTL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 15:0] Target performance State Value.\r
    ///\r
    UINT32  TargetState:16;\r
    UINT32  Reserved1:16;\r
    ///\r
    /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH\r
    /// (Mobile only).\r
    ///\r
    UINT32  IDA:1;\r
    UINT32  Reserved2:31;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PERF_CTL_REGISTER;\r
\r
\r
/**\r
  Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled\r
  Clock Modulation.". If CPUID.01H:EDX[22] = 1.\r
\r
  @param  ECX  MSR_IA32_CLOCK_MODULATION (0x0000019A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_CLOCK_MODULATION_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);\r
  AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.\r
**/\r
#define MSR_IA32_CLOCK_MODULATION                0x0000019A\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If\r
    /// CPUID.06H:EAX[5] = 1.\r
    ///\r
    UINT32  ExtendedOnDemandClockModulationDutyCycle:1;\r
    ///\r
    /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded\r
    /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  OnDemandClockModulationDutyCycle:3;\r
    ///\r
    /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.\r
    /// If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  OnDemandClockModulationEnable:1;\r
    UINT32  Reserved1:27;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_CLOCK_MODULATION_REGISTER;\r
\r
\r
/**\r
  Thermal Interrupt Control (R/W) Enables and disables the generation of an\r
  interrupt on temperature transitions detected with the processor's thermal\r
  sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".\r
  If CPUID.01H:EDX[22] = 1\r
\r
  @param  ECX  MSR_IA32_THERM_INTERRUPT (0x0000019B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_THERM_INTERRUPT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);\r
  AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.\r
**/\r
#define MSR_IA32_THERM_INTERRUPT                 0x0000019B\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  HighTempEnable:1;\r
    ///\r
    /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  LowTempEnable:1;\r
    ///\r
    /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  PROCHOT_Enable:1;\r
    ///\r
    /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  FORCEPR_Enable:1;\r
    ///\r
    /// [Bit 4] Critical Temperature Interrupt Enable.\r
    /// If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  CriticalTempEnable:1;\r
    UINT32  Reserved1:3;\r
    ///\r
    /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  Threshold1:7;\r
    ///\r
    /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  Threshold1Enable:1;\r
    ///\r
    /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  Threshold2:7;\r
    ///\r
    /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  Threshold2Enable:1;\r
    ///\r
    /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.\r
    ///\r
    UINT32  PowerLimitNotificationEnable:1;\r
    UINT32  Reserved2:7;\r
    UINT32  Reserved3:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_THERM_INTERRUPT_REGISTER;\r
\r
\r
/**\r
  Thermal Status Information (RO) Contains status information about the\r
  processor's thermal sensor and automatic thermal monitoring facilities. See\r
  Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.\r
\r
  @param  ECX  MSR_IA32_THERM_STATUS (0x0000019C)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_THERM_STATUS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);\r
  @endcode\r
  @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.\r
**/\r
#define MSR_IA32_THERM_STATUS                    0x0000019C\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_THERM_STATUS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  ThermalStatus:1;\r
    ///\r
    /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  ThermalStatusLog:1;\r
    ///\r
    /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  PROCHOT_FORCEPR_Event:1;\r
    ///\r
    /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  PROCHOT_FORCEPR_Log:1;\r
    ///\r
    /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  CriticalTempStatus:1;\r
    ///\r
    /// [Bit 5] Critical Temperature Status log (R/WC0).\r
    /// If CPUID.01H:EDX[22] = 1.\r
    ///\r
    UINT32  CriticalTempStatusLog:1;\r
    ///\r
    /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.\r
    ///\r
    UINT32  ThermalThreshold1Status:1;\r
    ///\r
    /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r
    ///\r
    UINT32  ThermalThreshold1Log:1;\r
    ///\r
    /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.\r
    ///\r
    UINT32  ThermalThreshold2Status:1;\r
    ///\r
    /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r
    ///\r
    UINT32  ThermalThreshold2Log:1;\r
    ///\r
    /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.\r
    ///\r
    UINT32  PowerLimitStatus:1;\r
    ///\r
    /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.\r
    ///\r
    UINT32  PowerLimitLog:1;\r
    ///\r
    /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r
    ///\r
    UINT32  CurrentLimitStatus:1;\r
    ///\r
    /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r
    ///\r
    UINT32  CurrentLimitLog:1;\r
    ///\r
    /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r
    ///\r
    UINT32  CrossDomainLimitStatus:1;\r
    ///\r
    /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r
    ///\r
    UINT32  CrossDomainLimitLog:1;\r
    ///\r
    /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.\r
    ///\r
    UINT32  DigitalReadout:7;\r
    UINT32  Reserved1:4;\r
    ///\r
    /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =\r
    /// 1.\r
    ///\r
    UINT32  ResolutionInDegreesCelsius:4;\r
    ///\r
    /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.\r
    ///\r
    UINT32  ReadingValid:1;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_THERM_STATUS_REGISTER;\r
\r
\r
/**\r
  Enable Misc. Processor Features (R/W)  Allows a variety of processor\r
  functions to be enabled and disabled.\r
\r
  @param  ECX  MSR_IA32_MISC_ENABLE (0x000001A0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_MISC_ENABLE_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);\r
  AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
#define MSR_IA32_MISC_ENABLE                     0x000001A0\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_MISC_ENABLE\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for\r
    /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings\r
    /// are disabled. Introduced at Display Family / Display Model 0F_0H.\r
    ///\r
    UINT32  FastStrings:1;\r
    UINT32  Reserved1:2;\r
    ///\r
    /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W)  1 = Setting\r
    /// this bit enables the thermal control circuit (TCC) portion of the\r
    /// Intel Thermal Monitor feature. This allows the processor to\r
    /// automatically reduce power consumption in response to TCC activation.\r
    /// 0 = Disabled. Note: In some products clearing this bit might be\r
    /// ignored in critical thermal conditions, and TM1, TM2 and adaptive\r
    /// thermal throttling will still be activated. The default value of this\r
    /// field varies with product. See respective tables where default value is\r
    /// listed. Introduced at Display Family / Display Model 0F_0H.\r
    ///\r
    UINT32  AutomaticThermalControlCircuit:1;\r
    UINT32  Reserved2:3;\r
    ///\r
    /// [Bit 7] Performance Monitoring Available (R)  1 = Performance\r
    /// monitoring enabled 0 = Performance monitoring disabled. Introduced at\r
    /// Display Family / Display Model 0F_0H.\r
    ///\r
    UINT32  PerformanceMonitoring:1;\r
    UINT32  Reserved3:3;\r
    ///\r
    /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't\r
    /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at\r
    /// Display Family / Display Model 0F_0H.\r
    ///\r
    UINT32  BTS:1;\r
    ///\r
    /// [Bit 12] Processor Event Based Sampling (PEBS)  Unavailable (RO)  1 =\r
    /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display\r
    /// Family / Display Model 06_0FH.\r
    ///\r
    UINT32  PEBS:1;\r
    UINT32  Reserved4:3;\r
    ///\r
    /// [Bit 16] Enhanced Intel SpeedStep Technology  Enable (R/W) 0= Enhanced\r
    /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep\r
    /// Technology enabled. If CPUID.01H: ECX[7] =1.\r
    ///\r
    UINT32  EIST:1;\r
    UINT32  Reserved5:1;\r
    ///\r
    /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the\r
    /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This\r
    /// indicates that MONITOR/MWAIT are not supported. Software attempts to\r
    /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit\r
    /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit\r
    /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit\r
    /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it\r
    /// in the default state. Writing this bit when the SSE3 feature flag is\r
    /// set to 0 may generate a #GP exception. Introduced at Display Family /\r
    /// Display Model 0F_03H.\r
    ///\r
    UINT32  MONITOR:1;\r
    UINT32  Reserved6:3;\r
    ///\r
    /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H\r
    /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup\r
    /// question that allows users to specify when the installed OS does not\r
    /// support CPUID functions greater than 2. Before setting this bit, BIOS\r
    /// must execute the CPUID.0H and examine the maximum value returned in\r
    /// EAX[7:0]. If the maximum value is greater than 2, this bit is\r
    /// supported. Otherwise, this bit is not supported. Setting this bit when\r
    /// the maximum value is not greater than 2 may generate a #GP exception.\r
    /// Setting this bit may cause unexpected behavior in software that\r
    /// depends on the availability of CPUID leaves greater than 2. Introduced\r
    /// at Display Family / Display Model 0F_03H.\r
    ///\r
    UINT32  LimitCpuidMaxval:1;\r
    ///\r
    /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r
    /// disabled. xTPR messages are optional messages that allow the processor\r
    /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.\r
    ///\r
    UINT32  xTPR_Message_Disable:1;\r
    UINT32  Reserved7:8;\r
    UINT32  Reserved8:2;\r
    ///\r
    /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit\r
    /// feature (XD Bit) is disabled and the XD Bit extended feature flag will\r
    /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the\r
    /// Execute Disable Bit feature (if available) allows the OS to enable PAE\r
    /// paging and take advantage of data only pages. BIOS must not alter the\r
    /// contents of this bit location, if XD bit is not supported. Writing\r
    /// this bit to 1 when the XD Bit extended feature flag is set to 0 may\r
    /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.\r
    ///\r
    UINT32  XD:1;\r
    UINT32  Reserved9:29;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_MISC_ENABLE_REGISTER;\r
\r
\r
/**\r
  Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.\r
\r
  @param  ECX  MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_ENERGY_PERF_BIAS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);\r
  AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r
**/\r
#define MSR_IA32_ENERGY_PERF_BIAS                0x000001B0\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest\r
    /// performance. 15 indicates preference to maximize energy saving.\r
    ///\r
    UINT32  PowerPolicyPreference:4;\r
    UINT32  Reserved1:28;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_ENERGY_PERF_BIAS_REGISTER;\r
\r
\r
/**\r
  Package Thermal Status Information (RO) Contains status information about\r
  the package's thermal sensor. See Section 14.8, "Package Level Thermal\r
  Management.". If CPUID.06H: EAX[6] = 1.\r
\r
  @param  ECX  MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PACKAGE_THERM_STATUS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);\r
  @endcode\r
  @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.\r
**/\r
#define MSR_IA32_PACKAGE_THERM_STATUS            0x000001B1\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Pkg Thermal Status (RO):.\r
    ///\r
    UINT32  ThermalStatus:1;\r
    ///\r
    /// [Bit 1] Pkg Thermal Status Log (R/W):.\r
    ///\r
    UINT32  ThermalStatusLog:1;\r
    ///\r
    /// [Bit 2] Pkg PROCHOT # event (RO).\r
    ///\r
    UINT32  PROCHOT_Event:1;\r
    ///\r
    /// [Bit 3] Pkg PROCHOT # log (R/WC0).\r
    ///\r
    UINT32  PROCHOT_Log:1;\r
    ///\r
    /// [Bit 4] Pkg Critical Temperature Status (RO).\r
    ///\r
    UINT32  CriticalTempStatus:1;\r
    ///\r
    /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).\r
    ///\r
    UINT32  CriticalTempStatusLog:1;\r
    ///\r
    /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).\r
    ///\r
    UINT32  ThermalThreshold1Status:1;\r
    ///\r
    /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).\r
    ///\r
    UINT32  ThermalThreshold1Log:1;\r
    ///\r
    /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).\r
    ///\r
    UINT32  ThermalThreshold2Status:1;\r
    ///\r
    /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).\r
    ///\r
    UINT32  ThermalThreshold2Log:1;\r
    ///\r
    /// [Bit 10] Pkg Power Limitation Status (RO).\r
    ///\r
    UINT32  PowerLimitStatus:1;\r
    ///\r
    /// [Bit 11] Pkg Power Limitation log (R/WC0).\r
    ///\r
    UINT32  PowerLimitLog:1;\r
    UINT32  Reserved1:4;\r
    ///\r
    /// [Bits 22:16] Pkg Digital Readout (RO).\r
    ///\r
    UINT32  DigitalReadout:7;\r
    UINT32  Reserved2:9;\r
    UINT32  Reserved3:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;\r
\r
\r
/**\r
  Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of\r
  an interrupt on temperature transitions detected with the package's thermal\r
  sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:\r
  EAX[6] = 1.\r
\r
  @param  ECX  MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);\r
  AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.\r
**/\r
#define MSR_IA32_PACKAGE_THERM_INTERRUPT         0x000001B2\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Pkg High-Temperature Interrupt Enable.\r
    ///\r
    UINT32  HighTempEnable:1;\r
    ///\r
    /// [Bit 1] Pkg Low-Temperature Interrupt Enable.\r
    ///\r
    UINT32  LowTempEnable:1;\r
    ///\r
    /// [Bit 2] Pkg PROCHOT# Interrupt Enable.\r
    ///\r
    UINT32  PROCHOT_Enable:1;\r
    UINT32  Reserved1:1;\r
    ///\r
    /// [Bit 4] Pkg Overheat Interrupt Enable.\r
    ///\r
    UINT32  OverheatEnable:1;\r
    UINT32  Reserved2:3;\r
    ///\r
    /// [Bits 14:8] Pkg Threshold #1 Value.\r
    ///\r
    UINT32  Threshold1:7;\r
    ///\r
    /// [Bit 15] Pkg Threshold #1 Interrupt Enable.\r
    ///\r
    UINT32  Threshold1Enable:1;\r
    ///\r
    /// [Bits 22:16] Pkg Threshold #2 Value.\r
    ///\r
    UINT32  Threshold2:7;\r
    ///\r
    /// [Bit 23] Pkg Threshold #2 Interrupt Enable.\r
    ///\r
    UINT32  Threshold2Enable:1;\r
    ///\r
    /// [Bit 24] Pkg Power Limit Notification Enable.\r
    ///\r
    UINT32  PowerLimitNotificationEnable:1;\r
    UINT32  Reserved3:7;\r
    UINT32  Reserved4:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;\r
\r
\r
/**\r
  Trace/Profile Resource Control (R/W). Introduced at Display Family / Display\r
  Model 06_0EH.\r
\r
  @param  ECX  MSR_IA32_DEBUGCTL (0x000001D9)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_DEBUGCTL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);\r
  AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.\r
**/\r
#define MSR_IA32_DEBUGCTL                        0x000001D9\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_DEBUGCTL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a\r
    /// running trace of the most recent branches taken by the processor in\r
    /// the LBR stack. Introduced at Display Family / Display Model 06_01H.\r
    ///\r
    UINT32  LBR:1;\r
    ///\r
    /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat\r
    /// EFLAGS.TF as single-step on branches instead of single-step on\r
    /// instructions. Introduced at Display Family / Display Model 06_01H.\r
    ///\r
    UINT32  BTF:1;\r
    UINT32  Reserved1:4;\r
    ///\r
    /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be\r
    /// sent. Introduced at Display Family / Display Model 06_0EH.\r
    ///\r
    UINT32  TR:1;\r
    ///\r
    /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to\r
    /// be logged in a BTS buffer. Introduced at Display Family / Display\r
    /// Model 06_0EH.\r
    ///\r
    UINT32  BTS:1;\r
    ///\r
    /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular\r
    /// fashion. When this bit is set, an interrupt is generated by the BTS\r
    /// facility when the BTS buffer is full. Introduced at Display Family /\r
    /// Display Model 06_0EH.\r
    ///\r
    UINT32  BTINT:1;\r
    ///\r
    /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.\r
    /// Introduced at Display Family / Display Model 06_0FH.\r
    ///\r
    UINT32  BTS_OFF_OS:1;\r
    ///\r
    /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.\r
    /// Introduced at Display Family / Display Model 06_0FH.\r
    ///\r
    UINT32  BTS_OFF_USR:1;\r
    ///\r
    /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a\r
    /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r
    ///\r
    UINT32  FREEZE_LBRS_ON_PMI:1;\r
    ///\r
    /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the\r
    /// global counter control MSR are frozen (address 38FH) on a PMI request.\r
    /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r
    ///\r
    UINT32  FREEZE_PERFMON_ON_PMI:1;\r
    ///\r
    /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to\r
    /// receive and generate PMI on behalf of the uncore. Introduced at\r
    /// Display Family / Display Model 06_1AH.\r
    ///\r
    UINT32  ENABLE_UNCORE_PMI:1;\r
    ///\r
    /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace\r
    /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.\r
    ///\r
    UINT32  FREEZE_WHILE_SMM:1;\r
    ///\r
    /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If\r
    /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).\r
    ///\r
    UINT32  RTM_DEBUG:1;\r
    UINT32  Reserved2:16;\r
    UINT32  Reserved3:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_DEBUGCTL_REGISTER;\r
\r
\r
/**\r
  SMRR Base Address (Writeable only in SMM)  Base address of SMM memory range.\r
  If IA32_MTRRCAP.SMRR[11] = 1.\r
\r
  @param  ECX  MSR_IA32_SMRR_PHYSBASE (0x000001F2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_SMRR_PHYSBASE_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);\r
  AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.\r
**/\r
#define MSR_IA32_SMRR_PHYSBASE                   0x000001F2\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Type. Specifies memory type of the range.\r
    ///\r
    UINT32  Type:8;\r
    UINT32  Reserved1:4;\r
    ///\r
    /// [Bits 31:12] PhysBase.  SMRR physical Base Address.\r
    ///\r
    UINT32  PhysBase:20;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_SMRR_PHYSBASE_REGISTER;\r
\r
\r
/**\r
  SMRR Range Mask. (Writeable only in SMM)  Range Mask of SMM memory range. If\r
  IA32_MTRRCAP[SMRR] = 1.\r
\r
  @param  ECX  MSR_IA32_SMRR_PHYSMASK (0x000001F3)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_SMRR_PHYSMASK_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);\r
  AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.\r
**/\r
#define MSR_IA32_SMRR_PHYSMASK                   0x000001F3\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32  Reserved1:11;\r
    ///\r
    /// [Bit 11] Valid Enable range mask.\r
    ///\r
    UINT32  Valid:1;\r
    ///\r
    /// [Bits 31:12] PhysMask SMRR address range mask.\r
    ///\r
    UINT32  PhysMask:20;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_SMRR_PHYSMASK_REGISTER;\r
\r
\r
/**\r
  DCA Capability (R). If CPUID.01H: ECX[18] = 1.\r
\r
  @param  ECX  MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);\r
  @endcode\r
  @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.\r
**/\r
#define MSR_IA32_PLATFORM_DCA_CAP                0x000001F8\r
\r
\r
/**\r
  If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.\r
\r
  @param  ECX  MSR_IA32_CPU_DCA_CAP (0x000001F9)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);\r
  AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);\r
  @endcode\r
  @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.\r
**/\r
#define MSR_IA32_CPU_DCA_CAP                     0x000001F9\r
\r
\r
/**\r
  DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.\r
\r
  @param  ECX  MSR_IA32_DCA_0_CAP (0x000001FA)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_DCA_0_CAP_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);\r
  AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.\r
**/\r
#define MSR_IA32_DCA_0_CAP                       0x000001FA\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_DCA_0_CAP\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no\r
    /// defeatures are set.\r
    ///\r
    UINT32  DCA_ACTIVE:1;\r
    ///\r
    /// [Bits 2:1] TRANSACTION.\r
    ///\r
    UINT32  TRANSACTION:2;\r
    ///\r
    /// [Bits 6:3] DCA_TYPE.\r
    ///\r
    UINT32  DCA_TYPE:4;\r
    ///\r
    /// [Bits 10:7] DCA_QUEUE_SIZE.\r
    ///\r
    UINT32  DCA_QUEUE_SIZE:4;\r
    UINT32  Reserved1:2;\r
    ///\r
    /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW\r
    /// side-effect.\r
    ///\r
    UINT32  DCA_DELAY:4;\r
    UINT32  Reserved2:7;\r
    ///\r
    /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.\r
    ///\r
    UINT32  SW_BLOCK:1;\r
    UINT32  Reserved3:1;\r
    ///\r
    /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).\r
    ///\r
    UINT32  HW_BLOCK:1;\r
    UINT32  Reserved4:5;\r
    UINT32  Reserved5:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_DCA_0_CAP_REGISTER;\r
\r
\r
/**\r
  MTRRphysBasen.  See Section 11.11.2.3, "Variable Range MTRRs".\r
  If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r
\r
  @param  ECX  MSR_IA32_MTRR_PHYSBASEn\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_MTRR_PHYSBASE_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);\r
  AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.\r
        MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.\r
        MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.\r
        MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.\r
        MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.\r
        MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.\r
        MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.\r
        MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.\r
        MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.\r
        MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.\r
  @{\r
**/\r
#define MSR_IA32_MTRR_PHYSBASE0                  0x00000200\r
#define MSR_IA32_MTRR_PHYSBASE1                  0x00000202\r
#define MSR_IA32_MTRR_PHYSBASE2                  0x00000204\r
#define MSR_IA32_MTRR_PHYSBASE3                  0x00000206\r
#define MSR_IA32_MTRR_PHYSBASE4                  0x00000208\r
#define MSR_IA32_MTRR_PHYSBASE5                  0x0000020A\r
#define MSR_IA32_MTRR_PHYSBASE6                  0x0000020C\r
#define MSR_IA32_MTRR_PHYSBASE7                  0x0000020E\r
#define MSR_IA32_MTRR_PHYSBASE8                  0x00000210\r
#define MSR_IA32_MTRR_PHYSBASE9                  0x00000212\r
/// @}\r
\r
/**\r
  MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to\r
  #MSR_IA32_MTRR_PHYSBASE9\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Type. Specifies memory type of the range.\r
    ///\r
    UINT32  Type:8;\r
    UINT32  Reserved1:4;\r
    ///\r
    /// [Bits 31:12] PhysBase.  MTRR physical Base Address.\r
    ///\r
    UINT32  PhysBase:20;\r
    ///\r
    /// [Bits MAXPHYSADDR:32] PhysBase.  Upper bits of MTRR physical Base Address.\r
    /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r
    /// maximum physical address range supported by the processor. It is\r
    /// reported by CPUID leaf function 80000008H. If CPUID does not support\r
    /// leaf 80000008H, the processor supports 36-bit physical address size,\r
    /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r
    ///\r
    UINT32  PhysBaseHi:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_MTRR_PHYSBASE_REGISTER;\r
\r
\r
/**\r
  MTRRphysMaskn.  See Section 11.11.2.3, "Variable Range MTRRs".\r
  If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r
\r
  @param  ECX  MSR_IA32_MTRR_PHYSMASKn\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_MTRR_PHYSMASK_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);\r
  AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.\r
        MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.\r
        MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.\r
        MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.\r
        MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.\r
        MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.\r
        MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.\r
        MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.\r
        MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.\r
        MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.\r
  @{\r
**/\r
#define MSR_IA32_MTRR_PHYSMASK0                  0x00000201\r
#define MSR_IA32_MTRR_PHYSMASK1                  0x00000203\r
#define MSR_IA32_MTRR_PHYSMASK2                  0x00000205\r
#define MSR_IA32_MTRR_PHYSMASK3                  0x00000207\r
#define MSR_IA32_MTRR_PHYSMASK4                  0x00000209\r
#define MSR_IA32_MTRR_PHYSMASK5                  0x0000020B\r
#define MSR_IA32_MTRR_PHYSMASK6                  0x0000020D\r
#define MSR_IA32_MTRR_PHYSMASK7                  0x0000020F\r
#define MSR_IA32_MTRR_PHYSMASK8                  0x00000211\r
#define MSR_IA32_MTRR_PHYSMASK9                  0x00000213\r
/// @}\r
\r
/**\r
  MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to\r
  #MSR_IA32_MTRR_PHYSMASK9\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32  Reserved1:11;\r
    ///\r
    /// [Bit 11] Valid Enable range mask.\r
    ///\r
    UINT32  V:1;\r
    ///\r
    /// [Bits 31:12] PhysMask.  MTRR address range mask.\r
    ///\r
    UINT32  PhysMask:20;\r
    ///\r
    /// [Bits MAXPHYSADDR:32] PhysMask.  Upper bits of MTRR address range mask.\r
    /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r
    /// maximum physical address range supported by the processor. It is\r
    /// reported by CPUID leaf function 80000008H. If CPUID does not support\r
    /// leaf 80000008H, the processor supports 36-bit physical address size,\r
    /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r
    ///\r
    UINT32  PhysMaskHi:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_MTRR_PHYSMASK_REGISTER;\r
\r
\r
/**\r
  MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.\r
\r
  @param  ECX  MSR_IA32_MTRR_FIX64K_00000 (0x00000250)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);\r
  AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);\r
  @endcode\r
  @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX64K_00000               0x00000250\r
\r
\r
/**\r
  MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.\r
\r
  @param  ECX  MSR_IA32_MTRR_FIX16K_80000 (0x00000258)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);\r
  AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);\r
  @endcode\r
  @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX16K_80000               0x00000258\r
\r
\r
/**\r
  MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.\r
\r
  @param  ECX  MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);\r
  AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);\r
  @endcode\r
  @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX16K_A0000               0x00000259\r
\r
\r
/**\r
  See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.\r
\r
  @param  ECX  MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);\r
  AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);\r
  @endcode\r
  @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX4K_C0000                0x00000268\r
\r
\r
/**\r
  MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.\r
\r
  @param  ECX  MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);\r
  AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);\r
  @endcode\r
  @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX4K_C8000                0x00000269\r
\r
\r
/**\r
  MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.\r
\r
  @param  ECX  MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);\r
  AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);\r
  @endcode\r
  @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX4K_D0000                0x0000026A\r
\r
\r
/**\r
  MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.\r
\r
  @param  ECX  MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);\r
  AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);\r
  @endcode\r
  @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX4K_D8000                0x0000026B\r
\r
\r
/**\r
  MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.\r
\r
  @param  ECX  MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);\r
  AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);\r
  @endcode\r
  @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX4K_E0000                0x0000026C\r
\r
\r
/**\r
  MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.\r
\r
  @param  ECX  MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);\r
  AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);\r
  @endcode\r
  @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX4K_E8000                0x0000026D\r
\r
\r
/**\r
  MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.\r
\r
  @param  ECX  MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);\r
  AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);\r
  @endcode\r
  @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX4K_F0000                0x0000026E\r
\r
\r
/**\r
  MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.\r
\r
  @param  ECX  MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);\r
  AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);\r
  @endcode\r
  @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.\r
**/\r
#define MSR_IA32_MTRR_FIX4K_F8000                0x0000026F\r
\r
\r
/**\r
  IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.\r
\r
  @param  ECX  MSR_IA32_PAT (0x00000277)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PAT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PAT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PAT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);\r
  AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_PAT is defined as IA32_PAT in SDM.\r
**/\r
#define MSR_IA32_PAT                             0x00000277\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PAT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 2:0] PA0.\r
    ///\r
    UINT32  PA0:3;\r
    UINT32  Reserved1:5;\r
    ///\r
    /// [Bits 10:8] PA1.\r
    ///\r
    UINT32  PA1:3;\r
    UINT32  Reserved2:5;\r
    ///\r
    /// [Bits 18:16] PA2.\r
    ///\r
    UINT32  PA2:3;\r
    UINT32  Reserved3:5;\r
    ///\r
    /// [Bits 26:24] PA3.\r
    ///\r
    UINT32  PA3:3;\r
    UINT32  Reserved4:5;\r
    ///\r
    /// [Bits 34:32] PA4.\r
    ///\r
    UINT32  PA4:3;\r
    UINT32  Reserved5:5;\r
    ///\r
    /// [Bits 42:40] PA5.\r
    ///\r
    UINT32  PA5:3;\r
    UINT32  Reserved6:5;\r
    ///\r
    /// [Bits 50:48] PA6.\r
    ///\r
    UINT32  PA6:3;\r
    UINT32  Reserved7:5;\r
    ///\r
    /// [Bits 58:56] PA7.\r
    ///\r
    UINT32  PA7:3;\r
    UINT32  Reserved8:5;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PAT_REGISTER;\r
\r
\r
/**\r
  Provides the programming interface to use corrected MC error signaling\r
  capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.\r
\r
  @param  ECX  MSR_IA32_MCn_CTL2\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_MC_CTL2_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_MC_CTL2_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_MC_CTL2_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);\r
  AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_MC0_CTL2  is defined as IA32_MC0_CTL2  in SDM.\r
        MSR_IA32_MC1_CTL2  is defined as IA32_MC1_CTL2  in SDM.\r
        MSR_IA32_MC2_CTL2  is defined as IA32_MC2_CTL2  in SDM.\r
        MSR_IA32_MC3_CTL2  is defined as IA32_MC3_CTL2  in SDM.\r
        MSR_IA32_MC4_CTL2  is defined as IA32_MC4_CTL2  in SDM.\r
        MSR_IA32_MC5_CTL2  is defined as IA32_MC5_CTL2  in SDM.\r
        MSR_IA32_MC6_CTL2  is defined as IA32_MC6_CTL2  in SDM.\r
        MSR_IA32_MC7_CTL2  is defined as IA32_MC7_CTL2  in SDM.\r
        MSR_IA32_MC8_CTL2  is defined as IA32_MC8_CTL2  in SDM.\r
        MSR_IA32_MC9_CTL2  is defined as IA32_MC9_CTL2  in SDM.\r
        MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.\r
        MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.\r
        MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.\r
        MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.\r
        MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.\r
        MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.\r
        MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.\r
        MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.\r
        MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.\r
        MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.\r
        MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.\r
        MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.\r
        MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.\r
        MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.\r
        MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.\r
        MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.\r
        MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.\r
        MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.\r
        MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.\r
        MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.\r
        MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.\r
        MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.\r
  @{\r
**/\r
#define MSR_IA32_MC0_CTL2                        0x00000280\r
#define MSR_IA32_MC1_CTL2                        0x00000281\r
#define MSR_IA32_MC2_CTL2                        0x00000282\r
#define MSR_IA32_MC3_CTL2                        0x00000283\r
#define MSR_IA32_MC4_CTL2                        0x00000284\r
#define MSR_IA32_MC5_CTL2                        0x00000285\r
#define MSR_IA32_MC6_CTL2                        0x00000286\r
#define MSR_IA32_MC7_CTL2                        0x00000287\r
#define MSR_IA32_MC8_CTL2                        0x00000288\r
#define MSR_IA32_MC9_CTL2                        0x00000289\r
#define MSR_IA32_MC10_CTL2                       0x0000028A\r
#define MSR_IA32_MC11_CTL2                       0x0000028B\r
#define MSR_IA32_MC12_CTL2                       0x0000028C\r
#define MSR_IA32_MC13_CTL2                       0x0000028D\r
#define MSR_IA32_MC14_CTL2                       0x0000028E\r
#define MSR_IA32_MC15_CTL2                       0x0000028F\r
#define MSR_IA32_MC16_CTL2                       0x00000290\r
#define MSR_IA32_MC17_CTL2                       0x00000291\r
#define MSR_IA32_MC18_CTL2                       0x00000292\r
#define MSR_IA32_MC19_CTL2                       0x00000293\r
#define MSR_IA32_MC20_CTL2                       0x00000294\r
#define MSR_IA32_MC21_CTL2                       0x00000295\r
#define MSR_IA32_MC22_CTL2                       0x00000296\r
#define MSR_IA32_MC23_CTL2                       0x00000297\r
#define MSR_IA32_MC24_CTL2                       0x00000298\r
#define MSR_IA32_MC25_CTL2                       0x00000299\r
#define MSR_IA32_MC26_CTL2                       0x0000029A\r
#define MSR_IA32_MC27_CTL2                       0x0000029B\r
#define MSR_IA32_MC28_CTL2                       0x0000029C\r
#define MSR_IA32_MC29_CTL2                       0x0000029D\r
#define MSR_IA32_MC30_CTL2                       0x0000029E\r
#define MSR_IA32_MC31_CTL2                       0x0000029F\r
/// @}\r
\r
/**\r
  MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2\r
  to #MSR_IA32_MC31_CTL2\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 14:0] Corrected error count threshold.\r
    ///\r
    UINT32  CorrectedErrorCountThreshold:15;\r
    UINT32  Reserved1:15;\r
    ///\r
    /// [Bit 30] CMCI_EN.\r
    ///\r
    UINT32  CMCI_EN:1;\r
    UINT32  Reserved2:1;\r
    UINT32  Reserved3:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_MC_CTL2_REGISTER;\r
\r
\r
/**\r
  MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.\r
\r
  @param  ECX  MSR_IA32_MTRR_DEF_TYPE (0x000002FF)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_MTRR_DEF_TYPE_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
  AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.\r
**/\r
#define MSR_IA32_MTRR_DEF_TYPE                   0x000002FF\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 2:0] Default Memory Type.\r
    ///\r
    UINT32  Type:3;\r
    UINT32  Reserved1:7;\r
    ///\r
    /// [Bit 10] Fixed Range MTRR Enable.\r
    ///\r
    UINT32  FE:1;\r
    ///\r
    /// [Bit 11] MTRR Enable.\r
    ///\r
    UINT32  E:1;\r
    UINT32  Reserved2:20;\r
    UINT32  Reserved3:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_MTRR_DEF_TYPE_REGISTER;\r
\r
\r
/**\r
  Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If\r
  CPUID.0AH: EDX[4:0] > 0.\r
\r
  @param  ECX  MSR_IA32_FIXED_CTR0 (0x00000309)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);\r
  AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);\r
  @endcode\r
  @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.\r
**/\r
#define MSR_IA32_FIXED_CTR0                      0x00000309\r
\r
\r
/**\r
  Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If\r
  CPUID.0AH: EDX[4:0] > 1.\r
\r
  @param  ECX  MSR_IA32_FIXED_CTR1 (0x0000030A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);\r
  AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);\r
  @endcode\r
  @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.\r
**/\r
#define MSR_IA32_FIXED_CTR1                      0x0000030A\r
\r
\r
/**\r
  Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If\r
  CPUID.0AH: EDX[4:0] > 2.\r
\r
  @param  ECX  MSR_IA32_FIXED_CTR2 (0x0000030B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);\r
  AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);\r
  @endcode\r
  @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.\r
**/\r
#define MSR_IA32_FIXED_CTR2                      0x0000030B\r
\r
\r
/**\r
  RO. If CPUID.01H: ECX[15] = 1.\r
\r
  @param  ECX  MSR_IA32_PERF_CAPABILITIES (0x00000345)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PERF_CAPABILITIES_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);\r
  AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.\r
**/\r
#define MSR_IA32_PERF_CAPABILITIES               0x00000345\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 5:0] LBR format.\r
    ///\r
    UINT32  LBR_FMT:6;\r
    ///\r
    /// [Bit 6] PEBS Trap.\r
    ///\r
    UINT32  PEBS_TRAP:1;\r
    ///\r
    /// [Bit 7] PEBSSaveArchRegs.\r
    ///\r
    UINT32  PEBS_ARCH_REG:1;\r
    ///\r
    /// [Bits 11:8] PEBS Record Format.\r
    ///\r
    UINT32  PEBS_REC_FMT:4;\r
    ///\r
    /// [Bit 12] 1: Freeze while SMM is supported.\r
    ///\r
    UINT32  SMM_FREEZE:1;\r
    ///\r
    /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.\r
    ///\r
    UINT32  FW_WRITE:1;\r
    UINT32  Reserved1:18;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PERF_CAPABILITIES_REGISTER;\r
\r
\r
/**\r
  Fixed-Function Performance Counter Control (R/W) Counter increments while\r
  the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with\r
  the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]\r
  > 1.\r
\r
  @param  ECX  MSR_IA32_FIXED_CTR_CTRL (0x0000038D)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_FIXED_CTR_CTRL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);\r
  AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.\r
**/\r
#define MSR_IA32_FIXED_CTR_CTRL                  0x0000038D\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.\r
    ///\r
    UINT32  EN0_OS:1;\r
    ///\r
    /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.\r
    ///\r
    UINT32  EN0_Usr:1;\r
    ///\r
    /// [Bit 2] AnyThread: When set to 1, it enables counting the associated\r
    /// event conditions occurring across all logical processors sharing a\r
    /// processor core. When set to 0, the counter only increments the\r
    /// associated event conditions occurring in the logical processor which\r
    /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r
    ///\r
    UINT32  AnyThread0:1;\r
    ///\r
    /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.\r
    ///\r
    UINT32  EN0_PMI:1;\r
    ///\r
    /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.\r
    ///\r
    UINT32  EN1_OS:1;\r
    ///\r
    /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.\r
    ///\r
    UINT32  EN1_Usr:1;\r
    ///\r
    /// [Bit 6] AnyThread: When set to 1, it enables counting the associated\r
    /// event conditions occurring across all logical processors sharing a\r
    /// processor core. When set to 0, the counter only increments the\r
    /// associated event conditions occurring in the logical processor which\r
    /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r
    ///\r
    UINT32  AnyThread1:1;\r
    ///\r
    /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.\r
    ///\r
    UINT32  EN1_PMI:1;\r
    ///\r
    /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.\r
    ///\r
    UINT32  EN2_OS:1;\r
    ///\r
    /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.\r
    ///\r
    UINT32  EN2_Usr:1;\r
    ///\r
    /// [Bit 10] AnyThread: When set to 1, it enables counting the associated\r
    /// event conditions occurring across all logical processors sharing a\r
    /// processor core. When set to 0, the counter only increments the\r
    /// associated event conditions occurring in the logical processor which\r
    /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r
    ///\r
    UINT32  AnyThread2:1;\r
    ///\r
    /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.\r
    ///\r
    UINT32  EN2_PMI:1;\r
    UINT32  Reserved1:20;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_FIXED_CTR_CTRL_REGISTER;\r
\r
\r
/**\r
  Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.\r
\r
  @param  ECX  MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PERF_GLOBAL_STATUS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);\r
  @endcode\r
  @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
**/\r
#define MSR_IA32_PERF_GLOBAL_STATUS              0x0000038E\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:\r
    /// EAX[15:8] > 0.\r
    ///\r
    UINT32  Ovf_PMC0:1;\r
    ///\r
    /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:\r
    /// EAX[15:8] > 1.\r
    ///\r
    UINT32  Ovf_PMC1:1;\r
    ///\r
    /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:\r
    /// EAX[15:8] > 2.\r
    ///\r
    UINT32  Ovf_PMC2:1;\r
    ///\r
    /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:\r
    /// EAX[15:8] > 3.\r
    ///\r
    UINT32  Ovf_PMC3:1;\r
    UINT32  Reserved1:28;\r
    ///\r
    /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If\r
    /// CPUID.0AH: EAX[7:0] > 1.\r
    ///\r
    UINT32  Ovf_FixedCtr0:1;\r
    ///\r
    /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If\r
    /// CPUID.0AH: EAX[7:0] > 1.\r
    ///\r
    UINT32  Ovf_FixedCtr1:1;\r
    ///\r
    /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If\r
    /// CPUID.0AH: EAX[7:0] > 1.\r
    ///\r
    UINT32  Ovf_FixedCtr2:1;\r
    UINT32  Reserved2:20;\r
    ///\r
    /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory\r
    /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r
    /// && IA32_RTIT_CTL.ToPA = 1.\r
    ///\r
    UINT32  Trace_ToPA_PMI:1;\r
    UINT32  Reserved3:2;\r
    ///\r
    /// [Bit 58] LBR_Frz: LBRs are frozen due to -\r
    /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, -  The LBR stack overflowed. If\r
    /// CPUID.0AH: EAX[7:0] > 3.\r
    ///\r
    UINT32  LBR_Frz:1;\r
    ///\r
    /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due\r
    /// to -  IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, -  one or more core PMU\r
    /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.\r
    ///\r
    UINT32  CTR_Frz:1;\r
    ///\r
    /// [Bit 60] ASCI: Data in the performance counters in the core PMU may\r
    /// include contributions from the direct or indirect operation intel SGX\r
    /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.\r
    ///\r
    UINT32  ASCI:1;\r
    ///\r
    /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:\r
    /// EAX[7:0] > 2.\r
    ///\r
    UINT32  Ovf_Uncore:1;\r
    ///\r
    /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:\r
    /// EAX[7:0] > 0.\r
    ///\r
    UINT32  OvfBuf:1;\r
    ///\r
    /// [Bit 63] CondChgd: status bits of this register has changed. If\r
    /// CPUID.0AH: EAX[7:0] > 0.\r
    ///\r
    UINT32  CondChgd:1;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
\r
\r
/**\r
  Global Performance Counter Control (R/W) Counter increments while the result\r
  of ANDing respective enable bit in this MSR with the corresponding OS or USR\r
  bits in the general-purpose or fixed counter control MSR is true. If\r
  CPUID.0AH: EAX[7:0] > 0.\r
\r
  @param  ECX  MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PERF_GLOBAL_CTRL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);\r
  AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.\r
**/\r
#define MSR_IA32_PERF_GLOBAL_CTRL                0x0000038F\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
///\r
  struct {\r
    ///\r
    /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.\r
    /// Enable bitmask.  Only the first n-1 bits are valid.\r
    /// Bits n..31 are reserved.\r
    ///\r
    UINT32  EN_PMCn:32;\r
    ///\r
    /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.\r
    /// Enable bitmask.  Only the first n-1 bits are valid.\r
    /// Bits 31:n are reserved.\r
    ///\r
    UINT32  EN_FIXED_CTRn:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;\r
\r
\r
/**\r
  Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >\r
  0 && CPUID.0AH: EAX[7:0] <= 3.\r
\r
  @param  ECX  MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.\r
**/\r
#define MSR_IA32_PERF_GLOBAL_OVF_CTRL            0x00000390\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r
    /// Clear bitmask.  Only the first n-1 bits are valid.\r
    /// Bits 31:n are reserved.\r
    ///\r
    UINT32  Ovf_PMCn:32;\r
    ///\r
    /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r
    /// If CPUID.0AH: EDX[4:0] > n.\r
    /// Clear bitmask.  Only the first n-1 bits are valid.\r
    /// Bits 22:n are reserved.\r
    ///\r
    UINT32  Ovf_FIXED_CTRn:23;\r
    ///\r
    /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r
    /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.\r
    ///\r
    UINT32  Trace_ToPA_PMI:1;\r
    UINT32  Reserved2:5;\r
    ///\r
    /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r
    /// Display Model 06_2EH.\r
    ///\r
    UINT32  Ovf_Uncore:1;\r
    ///\r
    /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r
    ///\r
    UINT32  OvfBuf:1;\r
    ///\r
    /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r
    ///\r
    UINT32  CondChgd:1;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
\r
\r
/**\r
  Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:\r
  EAX[7:0] > 3.\r
\r
  @param  ECX  MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);\r
  AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
**/\r
#define MSR_IA32_PERF_GLOBAL_STATUS_RESET        0x00000390\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r
    /// Clear bitmask.  Only the first n-1 bits are valid.\r
    /// Bits 31:n are reserved.\r
    ///\r
    UINT32  Ovf_PMCn:32;\r
    ///\r
    /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r
    /// If CPUID.0AH: EDX[4:0] > n.\r
    /// Clear bitmask.  Only the first n-1 bits are valid.\r
    /// Bits 22:n are reserved.\r
    ///\r
    UINT32  Ovf_FIXED_CTRn:23;\r
    ///\r
    /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r
    /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.\r
    ///\r
    UINT32  Trace_ToPA_PMI:1;\r
    UINT32  Reserved2:2;\r
    ///\r
    /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r
    ///\r
    UINT32  LBR_Frz:1;\r
    ///\r
    /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r
    ///\r
    UINT32  CTR_Frz:1;\r
    ///\r
    /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.\r
    ///\r
    UINT32  ASCI:1;\r
    ///\r
    /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r
    /// Display Model 06_2EH.\r
    ///\r
    UINT32  Ovf_Uncore:1;\r
    ///\r
    /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r
    ///\r
    UINT32  OvfBuf:1;\r
    ///\r
    /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r
    ///\r
    UINT32  CondChgd:1;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r
\r
\r
/**\r
  Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:\r
  EAX[7:0] > 3.\r
\r
  @param  ECX  MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);\r
  AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r
**/\r
#define MSR_IA32_PERF_GLOBAL_STATUS_SET          0x00000391\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.\r
    /// Set bitmask.  Only the first n-1 bits are valid.\r
    /// Bits 31:n are reserved.\r
    ///\r
    UINT32  Ovf_PMCn:32;\r
    ///\r
    /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.\r
    /// If CPUID.0AH: EAX[7:0] > n.\r
    /// Set bitmask.  Only the first n-1 bits are valid.\r
    /// Bits 22:n are reserved.\r
    ///\r
    UINT32  Ovf_FIXED_CTRn:23;\r
    ///\r
    /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.\r
    ///\r
    UINT32  Trace_ToPA_PMI:1;\r
    UINT32  Reserved2:2;\r
    ///\r
    /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r
    ///\r
    UINT32  LBR_Frz:1;\r
    ///\r
    /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r
    ///\r
    UINT32  CTR_Frz:1;\r
    ///\r
    /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.\r
    ///\r
    UINT32  ASCI:1;\r
    ///\r
    /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.\r
    ///\r
    UINT32  Ovf_Uncore:1;\r
    ///\r
    /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.\r
    ///\r
    UINT32  OvfBuf:1;\r
    UINT32  Reserved3:1;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r
\r
\r
/**\r
  Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >\r
  3.\r
\r
  @param  ECX  MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PERF_GLOBAL_INUSE_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);\r
  @endcode\r
  @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.\r
**/\r
#define MSR_IA32_PERF_GLOBAL_INUSE               0x00000392\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 31:0] IA32_PERFEVTSELn in use.  If CPUID.0AH: EAX[7:0] > n.\r
    /// Status bitmask.  Only the first n-1 bits are valid.\r
    /// Bits 31:n are reserved.\r
    ///\r
    UINT32  IA32_PERFEVTSELn:32;\r
    ///\r
    /// [Bits 62:32] IA32_FIXED_CTRn in use.\r
    /// If CPUID.0AH: EAX[7:0] > n.\r
    /// Status bitmask.  Only the first n-1 bits are valid.\r
    /// Bits 30:n are reserved.\r
    ///\r
    UINT32  IA32_FIXED_CTRn:31;\r
    ///\r
    /// [Bit 63] PMI in use.\r
    ///\r
    UINT32  PMI:1;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;\r
\r
\r
/**\r
  PEBS Control (R/W).\r
\r
  @param  ECX  MSR_IA32_PEBS_ENABLE (0x000003F1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PEBS_ENABLE_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);\r
  AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.\r
**/\r
#define MSR_IA32_PEBS_ENABLE                     0x000003F1\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /\r
    /// Display Model 06_0FH.\r
    ///\r
    UINT32  Enable:1;\r
    ///\r
    /// [Bits 3:1] Reserved or Model specific.\r
    ///\r
    UINT32  Reserved1:3;\r
    UINT32  Reserved2:28;\r
    ///\r
    /// [Bits 35:32] Reserved or Model specific.\r
    ///\r
    UINT32  Reserved3:4;\r
    UINT32  Reserved4:28;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PEBS_ENABLE_REGISTER;\r
\r
\r
/**\r
  MCn_CTL. If IA32_MCG_CAP.CNT > n.\r
\r
  @param  ECX  MSR_IA32_MCn_CTL\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);\r
  AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);\r
  @endcode\r
  @note MSR_IA32_MC0_CTL  is defined as IA32_MC0_CTL  in SDM.\r
        MSR_IA32_MC1_CTL  is defined as IA32_MC1_CTL  in SDM.\r
        MSR_IA32_MC2_CTL  is defined as IA32_MC2_CTL  in SDM.\r
        MSR_IA32_MC3_CTL  is defined as IA32_MC3_CTL  in SDM.\r
        MSR_IA32_MC4_CTL  is defined as IA32_MC4_CTL  in SDM.\r
        MSR_IA32_MC5_CTL  is defined as IA32_MC5_CTL  in SDM.\r
        MSR_IA32_MC6_CTL  is defined as IA32_MC6_CTL  in SDM.\r
        MSR_IA32_MC7_CTL  is defined as IA32_MC7_CTL  in SDM.\r
        MSR_IA32_MC8_CTL  is defined as IA32_MC8_CTL  in SDM.\r
        MSR_IA32_MC9_CTL  is defined as IA32_MC9_CTL  in SDM.\r
        MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.\r
        MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.\r
        MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.\r
        MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.\r
        MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.\r
        MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.\r
        MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.\r
        MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.\r
        MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.\r
        MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.\r
        MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.\r
        MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.\r
        MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.\r
        MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.\r
        MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.\r
        MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.\r
        MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.\r
        MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.\r
        MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.\r
  @{\r
**/\r
#define MSR_IA32_MC0_CTL                         0x00000400\r
#define MSR_IA32_MC1_CTL                         0x00000404\r
#define MSR_IA32_MC2_CTL                         0x00000408\r
#define MSR_IA32_MC3_CTL                         0x0000040C\r
#define MSR_IA32_MC4_CTL                         0x00000410\r
#define MSR_IA32_MC5_CTL                         0x00000414\r
#define MSR_IA32_MC6_CTL                         0x00000418\r
#define MSR_IA32_MC7_CTL                         0x0000041C\r
#define MSR_IA32_MC8_CTL                         0x00000420\r
#define MSR_IA32_MC9_CTL                         0x00000424\r
#define MSR_IA32_MC10_CTL                        0x00000428\r
#define MSR_IA32_MC11_CTL                        0x0000042C\r
#define MSR_IA32_MC12_CTL                        0x00000430\r
#define MSR_IA32_MC13_CTL                        0x00000434\r
#define MSR_IA32_MC14_CTL                        0x00000438\r
#define MSR_IA32_MC15_CTL                        0x0000043C\r
#define MSR_IA32_MC16_CTL                        0x00000440\r
#define MSR_IA32_MC17_CTL                        0x00000444\r
#define MSR_IA32_MC18_CTL                        0x00000448\r
#define MSR_IA32_MC19_CTL                        0x0000044C\r
#define MSR_IA32_MC20_CTL                        0x00000450\r
#define MSR_IA32_MC21_CTL                        0x00000454\r
#define MSR_IA32_MC22_CTL                        0x00000458\r
#define MSR_IA32_MC23_CTL                        0x0000045C\r
#define MSR_IA32_MC24_CTL                        0x00000460\r
#define MSR_IA32_MC25_CTL                        0x00000464\r
#define MSR_IA32_MC26_CTL                        0x00000468\r
#define MSR_IA32_MC27_CTL                        0x0000046C\r
#define MSR_IA32_MC28_CTL                        0x00000470\r
/// @}\r
\r
\r
/**\r
  MCn_STATUS. If IA32_MCG_CAP.CNT > n.\r
\r
  @param  ECX  MSR_IA32_MCn_STATUS\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);\r
  AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);\r
  @endcode\r
  @note MSR_IA32_MC0_STATUS  is defined as IA32_MC0_STATUS  in SDM.\r
        MSR_IA32_MC1_STATUS  is defined as IA32_MC1_STATUS  in SDM.\r
        MSR_IA32_MC2_STATUS  is defined as IA32_MC2_STATUS  in SDM.\r
        MSR_IA32_MC3_STATUS  is defined as IA32_MC3_STATUS  in SDM.\r
        MSR_IA32_MC4_STATUS  is defined as IA32_MC4_STATUS  in SDM.\r
        MSR_IA32_MC5_STATUS  is defined as IA32_MC5_STATUS  in SDM.\r
        MSR_IA32_MC6_STATUS  is defined as IA32_MC6_STATUS  in SDM.\r
        MSR_IA32_MC7_STATUS  is defined as IA32_MC7_STATUS  in SDM.\r
        MSR_IA32_MC8_STATUS  is defined as IA32_MC8_STATUS  in SDM.\r
        MSR_IA32_MC9_STATUS  is defined as IA32_MC9_STATUS  in SDM.\r
        MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.\r
        MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.\r
        MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.\r
        MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.\r
        MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.\r
        MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.\r
        MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.\r
        MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.\r
        MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.\r
        MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.\r
        MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.\r
        MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.\r
        MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.\r
        MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.\r
        MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.\r
        MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.\r
        MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.\r
        MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.\r
        MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.\r
  @{\r
**/\r
#define MSR_IA32_MC0_STATUS                      0x00000401\r
#define MSR_IA32_MC1_STATUS                      0x00000405\r
#define MSR_IA32_MC2_STATUS                      0x00000409\r
#define MSR_IA32_MC3_STATUS                      0x0000040D\r
#define MSR_IA32_MC4_STATUS                      0x00000411\r
#define MSR_IA32_MC5_STATUS                      0x00000415\r
#define MSR_IA32_MC6_STATUS                      0x00000419\r
#define MSR_IA32_MC7_STATUS                      0x0000041D\r
#define MSR_IA32_MC8_STATUS                      0x00000421\r
#define MSR_IA32_MC9_STATUS                      0x00000425\r
#define MSR_IA32_MC10_STATUS                     0x00000429\r
#define MSR_IA32_MC11_STATUS                     0x0000042D\r
#define MSR_IA32_MC12_STATUS                     0x00000431\r
#define MSR_IA32_MC13_STATUS                     0x00000435\r
#define MSR_IA32_MC14_STATUS                     0x00000439\r
#define MSR_IA32_MC15_STATUS                     0x0000043D\r
#define MSR_IA32_MC16_STATUS                     0x00000441\r
#define MSR_IA32_MC17_STATUS                     0x00000445\r
#define MSR_IA32_MC18_STATUS                     0x00000449\r
#define MSR_IA32_MC19_STATUS                     0x0000044D\r
#define MSR_IA32_MC20_STATUS                     0x00000451\r
#define MSR_IA32_MC21_STATUS                     0x00000455\r
#define MSR_IA32_MC22_STATUS                     0x00000459\r
#define MSR_IA32_MC23_STATUS                     0x0000045D\r
#define MSR_IA32_MC24_STATUS                     0x00000461\r
#define MSR_IA32_MC25_STATUS                     0x00000465\r
#define MSR_IA32_MC26_STATUS                     0x00000469\r
#define MSR_IA32_MC27_STATUS                     0x0000046D\r
#define MSR_IA32_MC28_STATUS                     0x00000471\r
/// @}\r
\r
\r
/**\r
  MCn_ADDR. If IA32_MCG_CAP.CNT > n.\r
\r
  @param  ECX  MSR_IA32_MCn_ADDR\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);\r
  AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);\r
  @endcode\r
  @note MSR_IA32_MC0_ADDR  is defined as IA32_MC0_ADDR  in SDM.\r
        MSR_IA32_MC1_ADDR  is defined as IA32_MC1_ADDR  in SDM.\r
        MSR_IA32_MC2_ADDR  is defined as IA32_MC2_ADDR  in SDM.\r
        MSR_IA32_MC3_ADDR  is defined as IA32_MC3_ADDR  in SDM.\r
        MSR_IA32_MC4_ADDR  is defined as IA32_MC4_ADDR  in SDM.\r
        MSR_IA32_MC5_ADDR  is defined as IA32_MC5_ADDR  in SDM.\r
        MSR_IA32_MC6_ADDR  is defined as IA32_MC6_ADDR  in SDM.\r
        MSR_IA32_MC7_ADDR  is defined as IA32_MC7_ADDR  in SDM.\r
        MSR_IA32_MC8_ADDR  is defined as IA32_MC8_ADDR  in SDM.\r
        MSR_IA32_MC9_ADDR  is defined as IA32_MC9_ADDR  in SDM.\r
        MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.\r
        MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.\r
        MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.\r
        MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.\r
        MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.\r
        MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.\r
        MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.\r
        MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.\r
        MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.\r
        MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.\r
        MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.\r
        MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.\r
        MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.\r
        MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.\r
        MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.\r
        MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.\r
        MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.\r
        MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.\r
        MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.\r
  @{\r
**/\r
#define MSR_IA32_MC0_ADDR                        0x00000402\r
#define MSR_IA32_MC1_ADDR                        0x00000406\r
#define MSR_IA32_MC2_ADDR                        0x0000040A\r
#define MSR_IA32_MC3_ADDR                        0x0000040E\r
#define MSR_IA32_MC4_ADDR                        0x00000412\r
#define MSR_IA32_MC5_ADDR                        0x00000416\r
#define MSR_IA32_MC6_ADDR                        0x0000041A\r
#define MSR_IA32_MC7_ADDR                        0x0000041E\r
#define MSR_IA32_MC8_ADDR                        0x00000422\r
#define MSR_IA32_MC9_ADDR                        0x00000426\r
#define MSR_IA32_MC10_ADDR                       0x0000042A\r
#define MSR_IA32_MC11_ADDR                       0x0000042E\r
#define MSR_IA32_MC12_ADDR                       0x00000432\r
#define MSR_IA32_MC13_ADDR                       0x00000436\r
#define MSR_IA32_MC14_ADDR                       0x0000043A\r
#define MSR_IA32_MC15_ADDR                       0x0000043E\r
#define MSR_IA32_MC16_ADDR                       0x00000442\r
#define MSR_IA32_MC17_ADDR                       0x00000446\r
#define MSR_IA32_MC18_ADDR                       0x0000044A\r
#define MSR_IA32_MC19_ADDR                       0x0000044E\r
#define MSR_IA32_MC20_ADDR                       0x00000452\r
#define MSR_IA32_MC21_ADDR                       0x00000456\r
#define MSR_IA32_MC22_ADDR                       0x0000045A\r
#define MSR_IA32_MC23_ADDR                       0x0000045E\r
#define MSR_IA32_MC24_ADDR                       0x00000462\r
#define MSR_IA32_MC25_ADDR                       0x00000466\r
#define MSR_IA32_MC26_ADDR                       0x0000046A\r
#define MSR_IA32_MC27_ADDR                       0x0000046E\r
#define MSR_IA32_MC28_ADDR                       0x00000472\r
/// @}\r
\r
\r
/**\r
  MCn_MISC. If IA32_MCG_CAP.CNT > n.\r
\r
  @param  ECX  MSR_IA32_MCn_MISC\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);\r
  AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);\r
  @endcode\r
  @note MSR_IA32_MC0_MISC  is defined as IA32_MC0_MISC  in SDM.\r
        MSR_IA32_MC1_MISC  is defined as IA32_MC1_MISC  in SDM.\r
        MSR_IA32_MC2_MISC  is defined as IA32_MC2_MISC  in SDM.\r
        MSR_IA32_MC3_MISC  is defined as IA32_MC3_MISC  in SDM.\r
        MSR_IA32_MC4_MISC  is defined as IA32_MC4_MISC  in SDM.\r
        MSR_IA32_MC5_MISC  is defined as IA32_MC5_MISC  in SDM.\r
        MSR_IA32_MC6_MISC  is defined as IA32_MC6_MISC  in SDM.\r
        MSR_IA32_MC7_MISC  is defined as IA32_MC7_MISC  in SDM.\r
        MSR_IA32_MC8_MISC  is defined as IA32_MC8_MISC  in SDM.\r
        MSR_IA32_MC9_MISC  is defined as IA32_MC9_MISC  in SDM.\r
        MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.\r
        MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.\r
        MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.\r
        MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.\r
        MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.\r
        MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.\r
        MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.\r
        MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.\r
        MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.\r
        MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.\r
        MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.\r
        MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.\r
        MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.\r
        MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.\r
        MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.\r
        MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.\r
        MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.\r
        MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.\r
        MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.\r
  @{\r
**/\r
#define MSR_IA32_MC0_MISC                        0x00000403\r
#define MSR_IA32_MC1_MISC                        0x00000407\r
#define MSR_IA32_MC2_MISC                        0x0000040B\r
#define MSR_IA32_MC3_MISC                        0x0000040F\r
#define MSR_IA32_MC4_MISC                        0x00000413\r
#define MSR_IA32_MC5_MISC                        0x00000417\r
#define MSR_IA32_MC6_MISC                        0x0000041B\r
#define MSR_IA32_MC7_MISC                        0x0000041F\r
#define MSR_IA32_MC8_MISC                        0x00000423\r
#define MSR_IA32_MC9_MISC                        0x00000427\r
#define MSR_IA32_MC10_MISC                       0x0000042B\r
#define MSR_IA32_MC11_MISC                       0x0000042F\r
#define MSR_IA32_MC12_MISC                       0x00000433\r
#define MSR_IA32_MC13_MISC                       0x00000437\r
#define MSR_IA32_MC14_MISC                       0x0000043B\r
#define MSR_IA32_MC15_MISC                       0x0000043F\r
#define MSR_IA32_MC16_MISC                       0x00000443\r
#define MSR_IA32_MC17_MISC                       0x00000447\r
#define MSR_IA32_MC18_MISC                       0x0000044B\r
#define MSR_IA32_MC19_MISC                       0x0000044F\r
#define MSR_IA32_MC20_MISC                       0x00000453\r
#define MSR_IA32_MC21_MISC                       0x00000457\r
#define MSR_IA32_MC22_MISC                       0x0000045B\r
#define MSR_IA32_MC23_MISC                       0x0000045F\r
#define MSR_IA32_MC24_MISC                       0x00000463\r
#define MSR_IA32_MC25_MISC                       0x00000467\r
#define MSR_IA32_MC26_MISC                       0x0000046B\r
#define MSR_IA32_MC27_MISC                       0x0000046F\r
#define MSR_IA32_MC28_MISC                       0x00000473\r
/// @}\r
\r
\r
/**\r
  Reporting Register of Basic VMX  Capabilities (R/O) See Appendix A.1, "Basic\r
  VMX Information.". If CPUID.01H:ECX.[5] = 1.\r
\r
  @param  ECX  MSR_IA32_VMX_BASIC (0x00000480)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_VMX_BASIC_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);\r
  @endcode\r
  @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.\r
**/\r
#define MSR_IA32_VMX_BASIC                       0x00000480\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_VMX_BASIC\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 30:0] VMCS revision identifier used by the processor.  Processors\r
    /// that use the same VMCS revision identifier use the same size for VMCS\r
    /// regions (see subsequent item on bits 44:32).\r
    ///\r
    /// @note Earlier versions of this manual specified that the VMCS revision\r
    /// identifier was a 32-bit field in bits 31:0 of this MSR. For all\r
    /// processors produced prior to this change, bit 31 of this MSR was read\r
    /// as 0.\r
    ///\r
    UINT32  VmcsRevisonId:31;\r
    UINT32  MustBeZero:1;\r
    ///\r
    /// [Bit 44:32] Reports the number of bytes that software should allocate\r
    /// for the VMXON region and any VMCS region.  It is a value greater than\r
    /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).\r
    ///\r
    UINT32  VmcsSize:13;\r
    UINT32  Reserved1:3;\r
    ///\r
    /// [Bit 48] Indicates the width of the physical addresses that may be used\r
    /// for the VMXON region, each VMCS, and data structures referenced by\r
    /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX\r
    /// transitions).  If the bit is 0, these addresses are limited to the\r
    /// processor's physical-address width.  If the bit is 1, these addresses\r
    /// are limited to 32 bits. This bit is always 0 for processors that\r
    /// support Intel 64 architecture.\r
    ///\r
    /// @note On processors that support Intel 64 architecture, the pointer\r
    /// must not set bits beyond the processor's physical address width.\r
    ///\r
    UINT32  VmcsAddressWidth:1;\r
    ///\r
    /// [Bit 49] If bit 49 is read as 1, the logical processor supports the\r
    /// dual-monitor treatment of system-management interrupts and\r
    /// system-management mode. See Section 34.15 for details of this treatment.\r
    ///\r
    UINT32  DualMonitor:1;\r
    ///\r
    /// [Bit 53:50] report the memory type that should be used for the VMCS,\r
    /// for data structures referenced by pointers in the VMCS (I/O bitmaps,\r
    /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG\r
    /// header. If software needs to access these data structures (e.g., to\r
    /// modify the contents of the MSR bitmaps), it can configure the paging\r
    /// structures to map them into the linear-address space. If it does so,\r
    /// it should establish mappings that use the memory type reported bits\r
    /// 53:50 in this MSR.\r
    ///\r
    /// As of this writing, all processors that support VMX operation indicate\r
    /// the write-back type.\r
    ///\r
    /// If software needs to access these data structures (e.g., to modify\r
    /// the contents of the MSR bitmaps), it can configure the paging\r
    /// structures to map them into the linear-address space. If it does so,\r
    /// it should establish mappings that use the memory type reported in this\r
    /// MSR.\r
    ///\r
    /// @note Alternatively, software may map any of these regions or\r
    /// structures with the UC memory type. (This may be necessary for the MSEG\r
    /// header.) Doing so is discouraged unless necessary as it will cause the\r
    /// performance of software accesses to those structures to suffer.\r
    ///\r
    ///\r
    UINT32  MemoryType:4;\r
    ///\r
    /// [Bit 54] If bit 54 is read as 1, the processor reports information in\r
    /// the VM-exit instruction-information field on VM exitsdue to execution\r
    /// of the INS and OUTS instructions (see Section 27.2.4). This reporting\r
    /// is done only if this bit is read as 1.\r
    ///\r
    UINT32  InsOutsReporting:1;\r
    ///\r
    /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may\r
    /// be cleared to 0. See Appendix A.2 for details. It also reports support\r
    /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,\r
    /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and\r
    /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,\r
    /// Appendix A.4, and Appendix A.5 for details.\r
    ///\r
    UINT32  VmxControls:1;\r
    UINT32  Reserved2:8;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_VMX_BASIC_REGISTER;\r
\r
///\r
/// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType\r
///\r
#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE  0x00\r
#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK   0x06\r
///\r
/// @}\r
///\r
\r
\r
/**\r
  Capability Reporting Register of Pinbased VM-execution Controls (R/O) See\r
  Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.\r
\r
  @param  ECX  MSR_IA32_VMX_PINBASED_CTLS (0x00000481)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);\r
  @endcode\r
  @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.\r
**/\r
#define MSR_IA32_VMX_PINBASED_CTLS               0x00000481\r
\r
\r
/**\r
  Capability Reporting Register of Primary  Processor-based VM-execution\r
  Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r
  Controls.". If CPUID.01H:ECX.[5] = 1.\r
\r
  @param  ECX  MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);\r
  @endcode\r
  @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.\r
**/\r
#define MSR_IA32_VMX_PROCBASED_CTLS              0x00000482\r
\r
\r
/**\r
  Capability Reporting Register of VM-exit  Controls (R/O) See Appendix A.4,\r
  "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.\r
\r
  @param  ECX  MSR_IA32_VMX_EXIT_CTLS (0x00000483)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);\r
  @endcode\r
  @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.\r
**/\r
#define MSR_IA32_VMX_EXIT_CTLS                   0x00000483\r
\r
\r
/**\r
  Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,\r
  "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.\r
\r
  @param  ECX  MSR_IA32_VMX_ENTRY_CTLS (0x00000484)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);\r
  @endcode\r
  @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.\r
**/\r
#define MSR_IA32_VMX_ENTRY_CTLS                  0x00000484\r
\r
\r
/**\r
  Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,\r
  "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.\r
\r
  @param  ECX  MSR_IA32_VMX_MISC (0x00000485)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  IA32_VMX_MISC_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);\r
  @endcode\r
  @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.\r
**/\r
#define MSR_IA32_VMX_MISC                        0x00000485\r
\r
/**\r
  MSR information returned for MSR index #IA32_VMX_MISC\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 4:0] Reports a value X that specifies the relationship between the\r
    /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).\r
    /// Specifically, the VMX-preemption timer (if it is active) counts down by\r
    /// 1 every time bit X in the TSC changes due to a TSC increment.\r
    ///\r
    UINT32  VmxTimerRatio:5;\r
    ///\r
    /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA\r
    /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more\r
    /// details. This bit is read as 1 on any logical processor that supports\r
    /// the 1-setting of the "unrestricted guest" VM-execution control.\r
    ///\r
    UINT32  VmExitEferLma:1;\r
    ///\r
    /// [Bit 6] reports (if set) the support for activity state 1 (HLT).\r
    ///\r
    UINT32  HltActivityStateSupported:1;\r
    ///\r
    /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).\r
    ///\r
    UINT32  ShutdownActivityStateSupported:1;\r
    ///\r
    /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).\r
    ///\r
    UINT32  WaitForSipiActivityStateSupported:1;\r
    UINT32  Reserved1:5;\r
    ///\r
    /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used\r
    /// in VMX operation. If the processor supports Intel PT but does not allow\r
    /// it to be used in VMX operation, execution of VMXON clears\r
    /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30);\r
    /// any attempt to set that bit while in VMX operation (including VMX root\r
    /// operation) using the WRMSR instruction causes a general-protection\r
    /// exception.\r
    ///\r
    UINT32  ProcessorTraceSupported:1;\r
    ///\r
    /// [Bit 15] If read as 1, the RDMSR instruction can be used in system-\r
    /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).\r
    /// See Section 34.15.6.3.\r
    ///\r
    UINT32  SmBaseMsrSupported:1;\r
    ///\r
    /// [Bits 24:16] Indicate the number of CR3-target values supported by the\r
    /// processor. This number is a value between 0 and 256, inclusive (bit 24\r
    /// is set if and only if bits 23:16 are clear).\r
    ///\r
    UINT32  NumberOfCr3TargetValues:9;\r
    ///\r
    /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum\r
    /// number of MSRs that should appear in the VM-exit MSR-store list, the\r
    /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if\r
    /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the\r
    /// recommended maximum number of MSRs to be included in each list. If the\r
    /// limit is exceeded, undefined processor behavior may result (including a\r
    /// machine check during the VMX transition).\r
    ///\r
    UINT32  MsrStoreListMaximum:3;\r
    ///\r
    /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set\r
    /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1\r
    /// (see Section 34.14.4).\r
    ///\r
    UINT32  BlockSmiSupported:1;\r
    ///\r
    /// [Bit 29] read as 1, software can use VMWRITE to write to any supported\r
    /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit\r
    /// information fields.\r
    ///\r
    UINT32  VmWriteSupported:1;\r
    ///\r
    /// [Bit 30] If read as 1, VM entry allows injection of a software\r
    /// interrupt, software exception, or privileged software exception with an\r
    /// instruction length of 0.\r
    ///\r
    UINT32  VmInjectSupported:1;\r
    UINT32  Reserved2:1;\r
    ///\r
    /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the\r
    /// processor.\r
    ///\r
    UINT32  MsegRevisionIdentifier:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} IA32_VMX_MISC_REGISTER;\r
\r
\r
/**\r
  Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,\r
  "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r
\r
  @param  ECX  MSR_IA32_VMX_CR0_FIXED0 (0x00000486)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);\r
  @endcode\r
  @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.\r
**/\r
#define MSR_IA32_VMX_CR0_FIXED0                  0x00000486\r
\r
\r
/**\r
  Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,\r
  "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r
\r
  @param  ECX  MSR_IA32_VMX_CR0_FIXED1 (0x00000487)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);\r
  @endcode\r
  @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.\r
**/\r
#define MSR_IA32_VMX_CR0_FIXED1                  0x00000487\r
\r
\r
/**\r
  Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,\r
  "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.\r
\r
  @param  ECX  MSR_IA32_VMX_CR4_FIXED0 (0x00000488)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);\r
  @endcode\r
  @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.\r
**/\r
#define MSR_IA32_VMX_CR4_FIXED0                  0x00000488\r
\r
\r
/**\r
  Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,\r
  "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.\r
\r
  @param  ECX  MSR_IA32_VMX_CR4_FIXED1 (0x00000489)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);\r
  @endcode\r
  @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.\r
**/\r
#define MSR_IA32_VMX_CR4_FIXED1                  0x00000489\r
\r
\r
/**\r
  Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix\r
  A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.\r
\r
  @param  ECX  MSR_IA32_VMX_VMCS_ENUM (0x0000048A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);\r
  @endcode\r
  @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.\r
**/\r
#define MSR_IA32_VMX_VMCS_ENUM                   0x0000048A\r
\r
\r
/**\r
  Capability Reporting Register of  Secondary Processor-based  VM-execution\r
  Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution\r
  Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).\r
\r
  @param  ECX  MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);\r
  @endcode\r
  @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.\r
**/\r
#define MSR_IA32_VMX_PROCBASED_CTLS2             0x0000048B\r
\r
\r
/**\r
  Capability Reporting Register of EPT and  VPID (R/O) See Appendix A.10,\r
  "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C\r
  TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).\r
\r
  @param  ECX  MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);\r
  @endcode\r
  @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.\r
**/\r
#define MSR_IA32_VMX_EPT_VPID_CAP                0x0000048C\r
\r
\r
/**\r
  Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)\r
  See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (\r
  CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
\r
  @param  ECX  MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);\r
  @endcode\r
  @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.\r
**/\r
#define MSR_IA32_VMX_TRUE_PINBASED_CTLS          0x0000048D\r
\r
\r
/**\r
  Capability Reporting Register of Primary  Processor-based VM-execution Flex\r
  Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r
  Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
\r
  @param  ECX  MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);\r
  @endcode\r
  @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.\r
**/\r
#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS         0x0000048E\r
\r
\r
/**\r
  Capability Reporting Register of VM-exit  Flex Controls (R/O) See Appendix\r
  A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
\r
  @param  ECX  MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);\r
  @endcode\r
  @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.\r
**/\r
#define MSR_IA32_VMX_TRUE_EXIT_CTLS              0x0000048F\r
\r
\r
/**\r
  Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix\r
  A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
\r
  @param  ECX  MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);\r
  @endcode\r
  @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.\r
**/\r
#define MSR_IA32_VMX_TRUE_ENTRY_CTLS             0x00000490\r
\r
\r
/**\r
  Capability Reporting Register of VMfunction Controls (R/O). If(\r
  CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
\r
  @param  ECX  MSR_IA32_VMX_VMFUNC (0x00000491)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);\r
  @endcode\r
  @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.\r
**/\r
#define MSR_IA32_VMX_VMFUNC                      0x00000491\r
\r
\r
/**\r
  Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&\r
  IA32_PERF_CAPABILITIES[ 13] = 1.\r
\r
  @param  ECX  MSR_IA32_A_PMCn\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);\r
  AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);\r
  @endcode\r
  @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.\r
        MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.\r
        MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.\r
        MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.\r
        MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.\r
        MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.\r
        MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.\r
        MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.\r
  @{\r
**/\r
#define MSR_IA32_A_PMC0                          0x000004C1\r
#define MSR_IA32_A_PMC1                          0x000004C2\r
#define MSR_IA32_A_PMC2                          0x000004C3\r
#define MSR_IA32_A_PMC3                          0x000004C4\r
#define MSR_IA32_A_PMC4                          0x000004C5\r
#define MSR_IA32_A_PMC5                          0x000004C6\r
#define MSR_IA32_A_PMC6                          0x000004C7\r
#define MSR_IA32_A_PMC7                          0x000004C8\r
/// @}\r
\r
\r
/**\r
  (R/W). If IA32_MCG_CAP.LMCE_P =1.\r
\r
  @param  ECX  MSR_IA32_MCG_EXT_CTL (0x000004D0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_MCG_EXT_CTL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);\r
  AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.\r
**/\r
#define MSR_IA32_MCG_EXT_CTL                     0x000004D0\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] LMCE_EN.\r
    ///\r
    UINT32  LMCE_EN:1;\r
    UINT32  Reserved1:31;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_MCG_EXT_CTL_REGISTER;\r
\r
\r
/**\r
  Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,\r
  ECX=0H): EBX[2] = 1.\r
\r
  @param  ECX  MSR_IA32_SGX_SVN_STATUS (0x00000500)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_SGX_SVN_STATUS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);\r
  @endcode\r
  @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.\r
**/\r
#define MSR_IA32_SGX_SVN_STATUS                  0x00000500\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Lock. See Section 42.11.3, "Interactions with Authenticated\r
    /// Code Modules (ACMs)".\r
    ///\r
    UINT32  Lock:1;\r
    UINT32  Reserved1:15;\r
    ///\r
    /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.11.3, "Interactions with\r
    /// Authenticated Code Modules (ACMs)".\r
    ///\r
    UINT32  SGX_SVN_SINIT:8;\r
    UINT32  Reserved2:8;\r
    UINT32  Reserved3:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_SGX_SVN_STATUS_REGISTER;\r
\r
\r
/**\r
  Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r
  && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)\r
  ) ).\r
\r
  @param  ECX  MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_RTIT_OUTPUT_BASE_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);\r
  AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.\r
**/\r
#define MSR_IA32_RTIT_OUTPUT_BASE                0x00000560\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32  Reserved:7;\r
    ///\r
    /// [Bits 31:7] Base physical address.\r
    ///\r
    UINT32  Base:25;\r
    ///\r
    /// [Bits 63:32] Base physical address.\r
    ///\r
    UINT32  BaseHi:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_RTIT_OUTPUT_BASE_REGISTER;\r
\r
\r
/**\r
  Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,\r
  ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)\r
  (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).\r
\r
  @param  ECX  MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);\r
  AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.\r
**/\r
#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS           0x00000561\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32  Reserved:7;\r
    ///\r
    /// [Bits 31:7] MaskOrTableOffset.\r
    ///\r
    UINT32  MaskOrTableOffset:25;\r
    ///\r
    /// [Bits 63:32] Output Offset.\r
    ///\r
    UINT32  OutputOffset:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;\r
\r
\r
/**\r
  Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r
\r
  @param  ECX  MSR_IA32_RTIT_CTL (0x00000570)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_RTIT_CTL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_RTIT_CTL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_RTIT_CTL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r
  AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.\r
**/\r
#define MSR_IA32_RTIT_CTL                        0x00000570\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_RTIT_CTL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] TraceEn.\r
    ///\r
    UINT32  TraceEn:1;\r
    ///\r
    /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r
    ///\r
    UINT32  CYCEn:1;\r
    ///\r
    /// [Bit 2] OS.\r
    ///\r
    UINT32  OS:1;\r
    ///\r
    /// [Bit 3] User.\r
    ///\r
    UINT32  User:1;\r
    UINT32  Reserved1:2;\r
    ///\r
    /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).\r
    ///\r
    UINT32  FabricEn:1;\r
    ///\r
    /// [Bit 7] CR3 filter.\r
    ///\r
    UINT32  CR3:1;\r
    ///\r
    /// [Bit 8] ToPA.\r
    ///\r
    UINT32  ToPA:1;\r
    ///\r
    /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r
    ///\r
    UINT32  MTCEn:1;\r
    ///\r
    /// [Bit 10] TSCEn.\r
    ///\r
    UINT32  TSCEn:1;\r
    ///\r
    /// [Bit 11] DisRETC.\r
    ///\r
    UINT32  DisRETC:1;\r
    UINT32  Reserved2:1;\r
    ///\r
    /// [Bit 13] BranchEn.\r
    ///\r
    UINT32  BranchEn:1;\r
    ///\r
    /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r
    ///\r
    UINT32  MTCFreq:4;\r
    UINT32  Reserved3:1;\r
    ///\r
    /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r
    ///\r
    UINT32  CYCThresh:4;\r
    UINT32  Reserved4:1;\r
    ///\r
    /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r
    ///\r
    UINT32  PSBFreq:4;\r
    UINT32  Reserved5:4;\r
    ///\r
    /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).\r
    ///\r
    UINT32  ADDR0_CFG:4;\r
    ///\r
    /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).\r
    ///\r
    UINT32  ADDR1_CFG:4;\r
    ///\r
    /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).\r
    ///\r
    UINT32  ADDR2_CFG:4;\r
    ///\r
    /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).\r
    ///\r
    UINT32  ADDR3_CFG:4;\r
    UINT32  Reserved6:16;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_RTIT_CTL_REGISTER;\r
\r
\r
/**\r
  Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r
\r
  @param  ECX  MSR_IA32_RTIT_STATUS (0x00000571)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_RTIT_STATUS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_RTIT_STATUS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_RTIT_STATUS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);\r
  AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.\r
**/\r
#define MSR_IA32_RTIT_STATUS                     0x00000571\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_RTIT_STATUS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] FilterEn, (writes ignored).\r
    /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).\r
    ///\r
    UINT32  FilterEn:1;\r
    ///\r
    /// [Bit 1] ContexEn, (writes ignored).\r
    ///\r
    UINT32  ContexEn:1;\r
    ///\r
    /// [Bit 2] TriggerEn, (writes ignored).\r
    ///\r
    UINT32  TriggerEn:1;\r
    UINT32  Reserved1:1;\r
    ///\r
    /// [Bit 4] Error.\r
    ///\r
    UINT32  Error:1;\r
    ///\r
    /// [Bit 5] Stopped.\r
    ///\r
    UINT32  Stopped:1;\r
    UINT32  Reserved2:26;\r
    ///\r
    /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).\r
    ///\r
    UINT32  PacketByteCnt:17;\r
    UINT32  Reserved3:15;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_RTIT_STATUS_REGISTER;\r
\r
\r
/**\r
  Trace Filter CR3 Match Register (R/W).\r
  If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r
\r
  @param  ECX  MSR_IA32_RTIT_CR3_MATCH (0x00000572)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_RTIT_CR3_MATCH_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);\r
  AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.\r
**/\r
#define MSR_IA32_RTIT_CR3_MATCH                  0x00000572\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32  Reserved:5;\r
    ///\r
    /// [Bits 31:5] CR3[63:5] value to match.\r
    ///\r
    UINT32  Cr3:27;\r
    ///\r
    /// [Bits 63:32] CR3[63:5] value to match.\r
    ///\r
    UINT32  Cr3Hi:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_RTIT_CR3_MATCH_REGISTER;\r
\r
\r
/**\r
  Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r
\r
  @param  ECX  MSR_IA32_RTIT_ADDRn_A\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_RTIT_ADDR_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);\r
  AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.\r
        MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.\r
        MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.\r
        MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.\r
  @{\r
**/\r
#define MSR_IA32_RTIT_ADDR0_A                    0x00000580\r
#define MSR_IA32_RTIT_ADDR1_A                    0x00000582\r
#define MSR_IA32_RTIT_ADDR2_A                    0x00000584\r
#define MSR_IA32_RTIT_ADDR3_A                    0x00000586\r
/// @}\r
\r
\r
/**\r
  Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r
\r
  @param  ECX  MSR_IA32_RTIT_ADDRn_B\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_RTIT_ADDR_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);\r
  AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.\r
        MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.\r
        MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.\r
        MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.\r
  @{\r
**/\r
#define MSR_IA32_RTIT_ADDR0_B                    0x00000581\r
#define MSR_IA32_RTIT_ADDR1_B                    0x00000583\r
#define MSR_IA32_RTIT_ADDR2_B                    0x00000585\r
#define MSR_IA32_RTIT_ADDR3_B                    0x00000587\r
/// @}\r
\r
\r
/**\r
  MSR information returned for MSR indexes\r
  #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and\r
  #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 31:0] Virtual Address.\r
    ///\r
    UINT32  VirtualAddress:32;\r
    ///\r
    /// [Bits 47:32] Virtual Address.\r
    ///\r
    UINT32  VirtualAddressHi:16;\r
    ///\r
    /// [Bits 63:48] SignExt_VA.\r
    ///\r
    UINT32  SignExt_VA:16;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_RTIT_ADDR_REGISTER;\r
\r
\r
/**\r
  DS Save Area (R/W)  Points to the linear address of the first byte of the DS\r
  buffer management area, which is used to manage the BTS and PEBS buffers.\r
  See Section 18.15.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]\r
  = 1.\r
\r
    [Bits 31..0] The linear address of the first byte of the DS buffer\r
    management area, if not in IA-32e mode.\r
\r
    [Bits 63..0] The linear address of the first byte of the DS buffer\r
    management area, if IA-32e mode is active.\r
\r
  @param  ECX  MSR_IA32_DS_AREA (0x00000600)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_DS_AREA_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_DS_AREA_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);\r
  AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);\r
  @endcode\r
  @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.\r
**/\r
#define MSR_IA32_DS_AREA                         0x00000600\r
\r
\r
/**\r
  TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =\r
  1.\r
\r
  @param  ECX  MSR_IA32_TSC_DEADLINE (0x000006E0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);\r
  AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);\r
  @endcode\r
  @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.\r
**/\r
#define MSR_IA32_TSC_DEADLINE                    0x000006E0\r
\r
\r
/**\r
  Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.\r
\r
  @param  ECX  MSR_IA32_PM_ENABLE (0x00000770)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PM_ENABLE_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PM_ENABLE_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PM_ENABLE_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);\r
  AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.\r
**/\r
#define MSR_IA32_PM_ENABLE                       0x00000770\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PM_ENABLE\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If\r
    /// CPUID.06H:EAX.[7] = 1.\r
    ///\r
    UINT32  HWP_ENABLE:1;\r
    UINT32  Reserved1:31;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PM_ENABLE_REGISTER;\r
\r
\r
/**\r
  HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.\r
\r
  @param  ECX  MSR_IA32_HWP_CAPABILITIES (0x00000771)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_HWP_CAPABILITIES_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);\r
  @endcode\r
  @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.\r
**/\r
#define MSR_IA32_HWP_CAPABILITIES                0x00000771\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance\r
    /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
    ///\r
    UINT32  Highest_Performance:8;\r
    ///\r
    /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP\r
    /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
    ///\r
    UINT32  Guaranteed_Performance:8;\r
    ///\r
    /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP\r
    /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
    ///\r
    UINT32  Most_Efficient_Performance:8;\r
    ///\r
    /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance\r
    /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
    ///\r
    UINT32  Lowest_Performance:8;\r
    UINT32  Reserved:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_HWP_CAPABILITIES_REGISTER;\r
\r
\r
/**\r
  Power Management Control Hints for All Logical Processors in a Package\r
  (R/W). If CPUID.06H:EAX.[11] = 1.\r
\r
  @param  ECX  MSR_IA32_HWP_REQUEST_PKG (0x00000772)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_HWP_REQUEST_PKG_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);\r
  AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.\r
**/\r
#define MSR_IA32_HWP_REQUEST_PKG                 0x00000772\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r
    /// CPUID.06H:EAX.[11] = 1.\r
    ///\r
    UINT32  Minimum_Performance:8;\r
    ///\r
    /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r
    /// CPUID.06H:EAX.[11] = 1.\r
    ///\r
    UINT32  Maximum_Performance:8;\r
    ///\r
    /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r
    /// If CPUID.06H:EAX.[11] = 1.\r
    ///\r
    UINT32  Desired_Performance:8;\r
    ///\r
    /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r
    /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.\r
    ///\r
    UINT32  Energy_Performance_Preference:8;\r
    ///\r
    /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r
    /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.\r
    ///\r
    UINT32  Activity_Window:10;\r
    UINT32  Reserved:22;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_HWP_REQUEST_PKG_REGISTER;\r
\r
\r
/**\r
  Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.\r
\r
  @param  ECX  MSR_IA32_HWP_INTERRUPT (0x00000773)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_HWP_INTERRUPT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);\r
  AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.\r
**/\r
#define MSR_IA32_HWP_INTERRUPT                   0x00000773\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP\r
    /// Notifications". If CPUID.06H:EAX.[8] = 1.\r
    ///\r
    UINT32  EN_Guaranteed_Performance_Change:1;\r
    ///\r
    /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".\r
    /// If CPUID.06H:EAX.[8] = 1.\r
    ///\r
    UINT32  EN_Excursion_Minimum:1;\r
    UINT32  Reserved1:30;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_HWP_INTERRUPT_REGISTER;\r
\r
\r
/**\r
  Power Management Control Hints to a Logical Processor (R/W). If\r
  CPUID.06H:EAX.[7] = 1.\r
\r
  @param  ECX  MSR_IA32_HWP_REQUEST (0x00000774)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_HWP_REQUEST_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_HWP_REQUEST_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_HWP_REQUEST_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);\r
  AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.\r
**/\r
#define MSR_IA32_HWP_REQUEST                     0x00000774\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_HWP_REQUEST\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r
    /// CPUID.06H:EAX.[7] = 1.\r
    ///\r
    UINT32  Minimum_Performance:8;\r
    ///\r
    /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r
    /// CPUID.06H:EAX.[7] = 1.\r
    ///\r
    UINT32  Maximum_Performance:8;\r
    ///\r
    /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r
    /// If CPUID.06H:EAX.[7] = 1.\r
    ///\r
    UINT32  Desired_Performance:8;\r
    ///\r
    /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r
    /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.\r
    ///\r
    UINT32  Energy_Performance_Preference:8;\r
    ///\r
    /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r
    /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.\r
    ///\r
    UINT32  Activity_Window:10;\r
    ///\r
    /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If\r
    /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.\r
    ///\r
    UINT32  Package_Control:1;\r
    UINT32  Reserved:21;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_HWP_REQUEST_REGISTER;\r
\r
\r
/**\r
  Log bits indicating changes to  Guaranteed & excursions to Minimum (R/W). If\r
  CPUID.06H:EAX.[7] = 1.\r
\r
  @param  ECX  MSR_IA32_HWP_STATUS (0x00000777)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_HWP_STATUS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_HWP_STATUS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_HWP_STATUS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);\r
  AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.\r
**/\r
#define MSR_IA32_HWP_STATUS                      0x00000777\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_HWP_STATUS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,\r
    /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.\r
    ///\r
    UINT32  Guaranteed_Performance_Change:1;\r
    UINT32  Reserved1:1;\r
    ///\r
    /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP\r
    /// Feedback". If CPUID.06H:EAX.[7] = 1.\r
    ///\r
    UINT32  Excursion_To_Minimum:1;\r
    UINT32  Reserved2:29;\r
    UINT32  Reserved3:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_HWP_STATUS_REGISTER;\r
\r
\r
/**\r
  x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1\r
  && IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_APICID (0x00000802)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);\r
  @endcode\r
  @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.\r
**/\r
#define MSR_IA32_X2APIC_APICID                   0x00000802\r
\r
\r
/**\r
  x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
  IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_VERSION (0x00000803)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);\r
  @endcode\r
  @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.\r
**/\r
#define MSR_IA32_X2APIC_VERSION                  0x00000803\r
\r
\r
/**\r
  x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
  IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_TPR (0x00000808)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);\r
  AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);\r
  @endcode\r
  @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.\r
**/\r
#define MSR_IA32_X2APIC_TPR                      0x00000808\r
\r
\r
/**\r
  x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
  IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_PPR (0x0000080A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);\r
  @endcode\r
  @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.\r
**/\r
#define MSR_IA32_X2APIC_PPR                      0x0000080A\r
\r
\r
/**\r
  x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]\r
  = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_EOI (0x0000080B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = 0;\r
  AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);\r
  @endcode\r
  @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.\r
**/\r
#define MSR_IA32_X2APIC_EOI                      0x0000080B\r
\r
\r
/**\r
  x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
  IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_LDR (0x0000080D)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);\r
  @endcode\r
  @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.\r
**/\r
#define MSR_IA32_X2APIC_LDR                      0x0000080D\r
\r
\r
/**\r
  x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1\r
  && IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_SIVR (0x0000080F)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);\r
  AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);\r
  @endcode\r
  @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.\r
**/\r
#define MSR_IA32_X2APIC_SIVR                     0x0000080F\r
\r
\r
/**\r
  x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).\r
  If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_ISRn\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);\r
  @endcode\r
  @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.\r
        MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.\r
        MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.\r
        MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.\r
        MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.\r
        MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.\r
        MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.\r
        MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.\r
  @{\r
**/\r
#define MSR_IA32_X2APIC_ISR0                     0x00000810\r
#define MSR_IA32_X2APIC_ISR1                     0x00000811\r
#define MSR_IA32_X2APIC_ISR2                     0x00000812\r
#define MSR_IA32_X2APIC_ISR3                     0x00000813\r
#define MSR_IA32_X2APIC_ISR4                     0x00000814\r
#define MSR_IA32_X2APIC_ISR5                     0x00000815\r
#define MSR_IA32_X2APIC_ISR6                     0x00000816\r
#define MSR_IA32_X2APIC_ISR7                     0x00000817\r
/// @}\r
\r
\r
/**\r
  x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).\r
  If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_TMRn\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);\r
  @endcode\r
  @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.\r
        MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.\r
        MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.\r
        MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.\r
        MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.\r
        MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.\r
        MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.\r
        MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.\r
  @{\r
**/\r
#define MSR_IA32_X2APIC_TMR0                     0x00000818\r
#define MSR_IA32_X2APIC_TMR1                     0x00000819\r
#define MSR_IA32_X2APIC_TMR2                     0x0000081A\r
#define MSR_IA32_X2APIC_TMR3                     0x0000081B\r
#define MSR_IA32_X2APIC_TMR4                     0x0000081C\r
#define MSR_IA32_X2APIC_TMR5                     0x0000081D\r
#define MSR_IA32_X2APIC_TMR6                     0x0000081E\r
#define MSR_IA32_X2APIC_TMR7                     0x0000081F\r
/// @}\r
\r
\r
/**\r
  x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).\r
  If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_IRRn\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);\r
  @endcode\r
  @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.\r
        MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.\r
        MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.\r
        MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.\r
        MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.\r
        MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.\r
        MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.\r
        MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.\r
  @{\r
**/\r
#define MSR_IA32_X2APIC_IRR0                     0x00000820\r
#define MSR_IA32_X2APIC_IRR1                     0x00000821\r
#define MSR_IA32_X2APIC_IRR2                     0x00000822\r
#define MSR_IA32_X2APIC_IRR3                     0x00000823\r
#define MSR_IA32_X2APIC_IRR4                     0x00000824\r
#define MSR_IA32_X2APIC_IRR5                     0x00000825\r
#define MSR_IA32_X2APIC_IRR6                     0x00000826\r
#define MSR_IA32_X2APIC_IRR7                     0x00000827\r
/// @}\r
\r
\r
/**\r
  x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
  IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_ESR (0x00000828)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);\r
  AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);\r
  @endcode\r
  @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.\r
**/\r
#define MSR_IA32_X2APIC_ESR                      0x00000828\r
\r
\r
/**\r
  x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If\r
  CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);\r
  AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);\r
  @endcode\r
  @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.\r
**/\r
#define MSR_IA32_X2APIC_LVT_CMCI                 0x0000082F\r
\r
\r
/**\r
  x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
  IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_ICR (0x00000830)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);\r
  AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);\r
  @endcode\r
  @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.\r
**/\r
#define MSR_IA32_X2APIC_ICR                      0x00000830\r
\r
\r
/**\r
  x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
  IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_LVT_TIMER (0x00000832)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);\r
  AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);\r
  @endcode\r
  @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.\r
**/\r
#define MSR_IA32_X2APIC_LVT_TIMER                0x00000832\r
\r
\r
/**\r
  x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =\r
  1 && IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);\r
  AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);\r
  @endcode\r
  @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.\r
**/\r
#define MSR_IA32_X2APIC_LVT_THERMAL              0x00000833\r
\r
\r
/**\r
  x2APIC LVT Performance Monitor Interrupt Register (R/W). If\r
  CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_LVT_PMI (0x00000834)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);\r
  AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);\r
  @endcode\r
  @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.\r
**/\r
#define MSR_IA32_X2APIC_LVT_PMI                  0x00000834\r
\r
\r
/**\r
  x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
  IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);\r
  AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);\r
  @endcode\r
  @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.\r
**/\r
#define MSR_IA32_X2APIC_LVT_LINT0                0x00000835\r
\r
\r
/**\r
  x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
  IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);\r
  AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);\r
  @endcode\r
  @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.\r
**/\r
#define MSR_IA32_X2APIC_LVT_LINT1                0x00000836\r
\r
\r
/**\r
  x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
  IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_LVT_ERROR (0x00000837)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);\r
  AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);\r
  @endcode\r
  @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.\r
**/\r
#define MSR_IA32_X2APIC_LVT_ERROR                0x00000837\r
\r
\r
/**\r
  x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
  IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_INIT_COUNT (0x00000838)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);\r
  AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);\r
  @endcode\r
  @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.\r
**/\r
#define MSR_IA32_X2APIC_INIT_COUNT               0x00000838\r
\r
\r
/**\r
  x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
  IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_CUR_COUNT (0x00000839)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);\r
  @endcode\r
  @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.\r
**/\r
#define MSR_IA32_X2APIC_CUR_COUNT                0x00000839\r
\r
\r
/**\r
  x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
  IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_DIV_CONF (0x0000083E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);\r
  AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);\r
  @endcode\r
  @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.\r
**/\r
#define MSR_IA32_X2APIC_DIV_CONF                 0x0000083E\r
\r
\r
/**\r
  x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&\r
  IA32_APIC_BASE.[10] = 1.\r
\r
  @param  ECX  MSR_IA32_X2APIC_SELF_IPI (0x0000083F)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = 0;\r
  AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);\r
  @endcode\r
  @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.\r
**/\r
#define MSR_IA32_X2APIC_SELF_IPI                 0x0000083F\r
\r
\r
/**\r
  Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.\r
\r
  @param  ECX  MSR_IA32_DEBUG_INTERFACE (0x00000C80)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_DEBUG_INTERFACE_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);\r
  AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.\r
**/\r
#define MSR_IA32_DEBUG_INTERFACE                 0x00000C80\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.\r
    /// Default is 0. If CPUID.01H:ECX.[11] = 1.\r
    ///\r
    UINT32  Enable:1;\r
    UINT32  Reserved1:29;\r
    ///\r
    /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The\r
    /// lock bit is set automatically on the first SMI assertion even if not\r
    /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.\r
    ///\r
    UINT32  Lock:1;\r
    ///\r
    /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to\r
    /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.\r
    ///\r
    UINT32  DebugOccurred:1;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_DEBUG_INTERFACE_REGISTER;\r
\r
\r
/**\r
  L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).\r
\r
  @param  ECX  MSR_IA32_L3_QOS_CFG (0x00000C81)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_L3_QOS_CFG_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);\r
  AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.\r
**/\r
#define MSR_IA32_L3_QOS_CFG                      0x00000C81\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate\r
    /// in Code and Data Prioritization (CDP) mode.\r
    ///\r
    UINT32  Enable:1;\r
    UINT32  Reserved1:31;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_L3_QOS_CFG_REGISTER;\r
\r
\r
/**\r
  Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]\r
  = 1 ).\r
\r
  @param  ECX  MSR_IA32_QM_EVTSEL (0x00000C8D)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_QM_EVTSEL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_QM_EVTSEL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_QM_EVTSEL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);\r
  AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
**/\r
#define MSR_IA32_QM_EVTSEL                       0x00000C8D\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_QM_EVTSEL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via\r
    /// IA32_QM_CTR.\r
    ///\r
    UINT32  EventID:8;\r
    UINT32  Reserved:24;\r
    ///\r
    /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to\r
    /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (\r
    /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r
    ///\r
    UINT32  ResourceMonitoringID:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_QM_EVTSEL_REGISTER;\r
\r
\r
/**\r
  Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1\r
  ).\r
\r
  @param  ECX  MSR_IA32_QM_CTR (0x00000C8E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_QM_CTR_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_QM_CTR_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_QM_CTR_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);\r
  @endcode\r
  @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.\r
**/\r
#define MSR_IA32_QM_CTR                          0x00000C8E\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_QM_CTR\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 31:0] Resource Monitored Data.\r
    ///\r
    UINT32  ResourceMonitoredData:32;\r
    ///\r
    /// [Bits 61:32] Resource Monitored Data.\r
    ///\r
    UINT32  ResourceMonitoredDataHi:30;\r
    ///\r
    /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not\r
    /// available or not monitored for this resource or RMID.\r
    ///\r
    UINT32  Unavailable:1;\r
    ///\r
    /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was\r
    /// written to IA32_PQR_QM_EVTSEL.\r
    ///\r
    UINT32  Error:1;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_QM_CTR_REGISTER;\r
\r
\r
/**\r
  Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]\r
  =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).\r
\r
  @param  ECX  MSR_IA32_PQR_ASSOC (0x00000C8F)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PQR_ASSOC_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PQR_ASSOC_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PQR_ASSOC_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);\r
  AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
**/\r
#define MSR_IA32_PQR_ASSOC                       0x00000C8F\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PQR_ASSOC\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware\r
    /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`\r
    /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r
    ///\r
    UINT32  ResourceMonitoringID:32;\r
    ///\r
    /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on\r
    /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,\r
    /// ECX=0):EBX.[15] = 1 ).\r
    ///\r
    UINT32  COS:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PQR_ASSOC_REGISTER;\r
\r
\r
/**\r
  Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,\r
  ECX=0H):EBX[14] = 1).\r
\r
  @param  ECX  MSR_IA32_BNDCFGS (0x00000D90)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_BNDCFGS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_BNDCFGS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_BNDCFGS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);\r
  AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.\r
**/\r
#define MSR_IA32_BNDCFGS                         0x00000D90\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_BNDCFGS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] EN: Enable Intel MPX in supervisor mode.\r
    ///\r
    UINT32  EN:1;\r
    ///\r
    /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch\r
    /// instructions in the absence of the BND prefix.\r
    ///\r
    UINT32  BNDPRESERVE:1;\r
    UINT32  Reserved:10;\r
    ///\r
    /// [Bits 31:12] Base Address of Bound Directory.\r
    ///\r
    UINT32  Base:20;\r
    ///\r
    /// [Bits 63:32] Base Address of Bound Directory.\r
    ///\r
    UINT32  BaseHi:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_BNDCFGS_REGISTER;\r
\r
\r
/**\r
  Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.\r
\r
  @param  ECX  MSR_IA32_XSS (0x00000DA0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_XSS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_XSS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_XSS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);\r
  AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_XSS is defined as IA32_XSS in SDM.\r
**/\r
#define MSR_IA32_XSS                             0x00000DA0\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_XSS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32  Reserved1:8;\r
    ///\r
    /// [Bit 8] Trace Packet Configuration State (R/W).\r
    ///\r
    UINT32  TracePacketConfigurationState:1;\r
    UINT32  Reserved2:23;\r
    UINT32  Reserved3:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_XSS_REGISTER;\r
\r
\r
/**\r
  Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.\r
\r
  @param  ECX  MSR_IA32_PKG_HDC_CTL (0x00000DB0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PKG_HDC_CTL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);\r
  AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.\r
**/\r
#define MSR_IA32_PKG_HDC_CTL                     0x00000DB0\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled\r
    /// logical processors in the package. See Section 14.5.2, "Package level\r
    /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.\r
    ///\r
    UINT32  HDC_Pkg_Enable:1;\r
    UINT32  Reserved1:31;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PKG_HDC_CTL_REGISTER;\r
\r
\r
/**\r
  Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.\r
\r
  @param  ECX  MSR_IA32_PM_CTL1 (0x00000DB1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_PM_CTL1_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_PM_CTL1_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_PM_CTL1_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);\r
  AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.\r
**/\r
#define MSR_IA32_PM_CTL1                         0x00000DB1\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_PM_CTL1\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for\r
    /// package level HDC control. See Section 14.5.3.\r
    /// If CPUID.06H:EAX.[13] = 1.\r
    ///\r
    UINT32  HDC_Allow_Block:1;\r
    UINT32  Reserved1:31;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_PM_CTL1_REGISTER;\r
\r
\r
/**\r
  Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.\r
  Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical\r
  processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.\r
\r
  @param  ECX  MSR_IA32_THREAD_STALL (0x00000DB2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);\r
  @endcode\r
  @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.\r
**/\r
#define MSR_IA32_THREAD_STALL                    0x00000DB2\r
\r
\r
/**\r
  Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]\r
  CPUID.80000001H:EDX.[2 9]).\r
\r
  @param  ECX  MSR_IA32_EFER (0xC0000080)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_EFER_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_EFER_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_EFER_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);\r
  AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_EFER is defined as IA32_EFER in SDM.\r
**/\r
#define MSR_IA32_EFER                            0xC0000080\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_EFER\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET\r
    /// instructions in 64-bit mode.\r
    ///\r
    UINT32  SCE:1;\r
    UINT32  Reserved1:7;\r
    ///\r
    /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode\r
    /// operation.\r
    ///\r
    UINT32  LME:1;\r
    UINT32  Reserved2:1;\r
    ///\r
    /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode\r
    /// is active when set.\r
    ///\r
    UINT32  LMA:1;\r
    ///\r
    /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).\r
    ///\r
    UINT32  NXE:1;\r
    UINT32  Reserved3:20;\r
    UINT32  Reserved4:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_EFER_REGISTER;\r
\r
\r
/**\r
  System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r
\r
  @param  ECX  MSR_IA32_STAR (0xC0000081)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_STAR);\r
  AsmWriteMsr64 (MSR_IA32_STAR, Msr);\r
  @endcode\r
  @note MSR_IA32_STAR is defined as IA32_STAR in SDM.\r
**/\r
#define MSR_IA32_STAR                            0xC0000081\r
\r
\r
/**\r
  IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r
\r
  @param  ECX  MSR_IA32_LSTAR (0xC0000082)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_LSTAR);\r
  AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);\r
  @endcode\r
  @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.\r
**/\r
#define MSR_IA32_LSTAR                           0xC0000082\r
\r
\r
/**\r
  System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.\r
\r
  @param  ECX  MSR_IA32_FMASK (0xC0000084)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_FMASK);\r
  AsmWriteMsr64 (MSR_IA32_FMASK, Msr);\r
  @endcode\r
  @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.\r
**/\r
#define MSR_IA32_FMASK                           0xC0000084\r
\r
\r
/**\r
  Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.\r
\r
  @param  ECX  MSR_IA32_FS_BASE (0xC0000100)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);\r
  AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);\r
  @endcode\r
  @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.\r
**/\r
#define MSR_IA32_FS_BASE                         0xC0000100\r
\r
\r
/**\r
  Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r
\r
  @param  ECX  MSR_IA32_GS_BASE (0xC0000101)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);\r
  AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);\r
  @endcode\r
  @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.\r
**/\r
#define MSR_IA32_GS_BASE                         0xC0000101\r
\r
\r
/**\r
  Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r
\r
  @param  ECX  MSR_IA32_KERNEL_GS_BASE (0xC0000102)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);\r
  AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);\r
  @endcode\r
  @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.\r
**/\r
#define MSR_IA32_KERNEL_GS_BASE                  0xC0000102\r
\r
\r
/**\r
  Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.\r
\r
  @param  ECX  MSR_IA32_TSC_AUX (0xC0000103)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_IA32_TSC_AUX_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_IA32_TSC_AUX_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_IA32_TSC_AUX_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);\r
  AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);\r
  @endcode\r
  @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.\r
**/\r
#define MSR_IA32_TSC_AUX                         0xC0000103\r
\r
/**\r
  MSR information returned for MSR index #MSR_IA32_TSC_AUX\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 31:0] AUX: Auxiliary signature of TSC.\r
    ///\r
    UINT32  AUX:32;\r
    UINT32  Reserved:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_IA32_TSC_AUX_REGISTER;\r
\r
#endif\r