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| 04c980a6 MK |
1 | /** @file\r |
| 2 | Architectural MSR Definitions.\r | |
| 3 | \r | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| 9 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
| 10 | This program and the accompanying materials\r | |
| 11 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 12 | which accompanies this distribution. The full text of the license may be found at\r | |
| 13 | http://opensource.org/licenses/bsd-license.php\r | |
| 14 | \r | |
| 15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 17 | \r | |
| 18 | @par Specification Reference:\r | |
| 19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
| 20 | December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1.\r | |
| 21 | \r | |
| 22 | **/\r | |
| 23 | \r | |
| 24 | #ifndef __ARCHITECTURAL_MSR_H__\r | |
| 25 | #define __ARCHITECTURAL_MSR_H__\r | |
| 26 | \r | |
| 27 | /**\r | |
| 28 | See Section 35.20, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r | |
| 29 | \r | |
| 30 | @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)\r | |
| 31 | @param EAX Lower 32-bits of MSR value.\r | |
| 32 | @param EDX Upper 32-bits of MSR value.\r | |
| 33 | \r | |
| 34 | <b>Example usage</b>\r | |
| 35 | @code\r | |
| 36 | UINT64 Msr;\r | |
| 37 | \r | |
| 38 | Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);\r | |
| 39 | AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);\r | |
| 40 | @endcode\r | |
| 7de98828 | 41 | @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.\r |
| 04c980a6 MK |
42 | **/\r |
| 43 | #define MSR_IA32_P5_MC_ADDR 0x00000000\r | |
| 44 | \r | |
| 45 | \r | |
| 46 | /**\r | |
| 47 | See Section 35.20, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r | |
| 48 | \r | |
| 49 | @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)\r | |
| 50 | @param EAX Lower 32-bits of MSR value.\r | |
| 51 | @param EDX Upper 32-bits of MSR value.\r | |
| 52 | \r | |
| 53 | <b>Example usage</b>\r | |
| 54 | @code\r | |
| 55 | UINT64 Msr;\r | |
| 56 | \r | |
| 57 | Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);\r | |
| 58 | AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);\r | |
| 59 | @endcode\r | |
| 7de98828 | 60 | @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.\r |
| 04c980a6 MK |
61 | **/\r |
| 62 | #define MSR_IA32_P5_MC_TYPE 0x00000001\r | |
| 63 | \r | |
| 64 | \r | |
| 65 | /**\r | |
| 66 | See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced\r | |
| 67 | at Display Family / Display Model 0F_03H.\r | |
| 68 | \r | |
| 69 | @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)\r | |
| 70 | @param EAX Lower 32-bits of MSR value.\r | |
| 71 | @param EDX Upper 32-bits of MSR value.\r | |
| 72 | \r | |
| 73 | <b>Example usage</b>\r | |
| 74 | @code\r | |
| 75 | UINT64 Msr;\r | |
| 76 | \r | |
| 77 | Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);\r | |
| 78 | AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);\r | |
| 79 | @endcode\r | |
| 7de98828 | 80 | @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.\r |
| 04c980a6 MK |
81 | **/\r |
| 82 | #define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006\r | |
| 83 | \r | |
| 84 | \r | |
| 85 | /**\r | |
| 86 | See Section 17.14, "Time-Stamp Counter.". Introduced at Display Family /\r | |
| 87 | Display Model 05_01H.\r | |
| 88 | \r | |
| 89 | @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)\r | |
| 90 | @param EAX Lower 32-bits of MSR value.\r | |
| 91 | @param EDX Upper 32-bits of MSR value.\r | |
| 92 | \r | |
| 93 | <b>Example usage</b>\r | |
| 94 | @code\r | |
| 95 | UINT64 Msr;\r | |
| 96 | \r | |
| 97 | Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);\r | |
| 98 | AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);\r | |
| 99 | @endcode\r | |
| 7de98828 | 100 | @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.\r |
| 04c980a6 MK |
101 | **/\r |
| 102 | #define MSR_IA32_TIME_STAMP_COUNTER 0x00000010\r | |
| 103 | \r | |
| 104 | \r | |
| 105 | /**\r | |
| 106 | Platform ID (RO) The operating system can use this MSR to determine "slot"\r | |
| 107 | information for the processor and the proper microcode update to load.\r | |
| 108 | Introduced at Display Family / Display Model 06_01H.\r | |
| 109 | \r | |
| 110 | @param ECX MSR_IA32_PLATFORM_ID (0x00000017)\r | |
| 111 | @param EAX Lower 32-bits of MSR value.\r | |
| 112 | Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r | |
| 113 | @param EDX Upper 32-bits of MSR value.\r | |
| 114 | Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r | |
| 115 | \r | |
| 116 | <b>Example usage</b>\r | |
| 117 | @code\r | |
| 118 | MSR_IA32_PLATFORM_ID_REGISTER Msr;\r | |
| 119 | \r | |
| 120 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);\r | |
| 121 | @endcode\r | |
| 7de98828 | 122 | @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.\r |
| 04c980a6 MK |
123 | **/\r |
| 124 | #define MSR_IA32_PLATFORM_ID 0x00000017\r | |
| 125 | \r | |
| 126 | /**\r | |
| 127 | MSR information returned for MSR index #MSR_IA32_PLATFORM_ID\r | |
| 128 | **/\r | |
| 129 | typedef union {\r | |
| 130 | ///\r | |
| 131 | /// Individual bit fields\r | |
| 132 | ///\r | |
| 133 | struct {\r | |
| 134 | UINT32 Reserved1:32;\r | |
| 135 | UINT32 Reserved2:18;\r | |
| 136 | ///\r | |
| 137 | /// [Bits 52:50] Platform Id (RO) Contains information concerning the\r | |
| 138 | /// intended platform for the processor.\r | |
| 139 | /// 52 51 50\r | |
| 140 | /// -- -- --\r | |
| 141 | /// 0 0 0 Processor Flag 0.\r | |
| 142 | /// 0 0 1 Processor Flag 1\r | |
| 143 | /// 0 1 0 Processor Flag 2\r | |
| 144 | /// 0 1 1 Processor Flag 3\r | |
| 145 | /// 1 0 0 Processor Flag 4\r | |
| 146 | /// 1 0 1 Processor Flag 5\r | |
| 147 | /// 1 1 0 Processor Flag 6\r | |
| 148 | /// 1 1 1 Processor Flag 7\r | |
| 149 | ///\r | |
| 150 | UINT32 PlatformId:3;\r | |
| 151 | UINT32 Reserved3:11;\r | |
| 152 | } Bits;\r | |
| 153 | ///\r | |
| 154 | /// All bit fields as a 64-bit value\r | |
| 155 | ///\r | |
| 156 | UINT64 Uint64;\r | |
| 157 | } MSR_IA32_PLATFORM_ID_REGISTER;\r | |
| 158 | \r | |
| 159 | \r | |
| 160 | /**\r | |
| 161 | 06_01H.\r | |
| 162 | \r | |
| 163 | @param ECX MSR_IA32_APIC_BASE (0x0000001B)\r | |
| 164 | @param EAX Lower 32-bits of MSR value.\r | |
| 165 | Described by the type MSR_IA32_APIC_BASE_REGISTER.\r | |
| 166 | @param EDX Upper 32-bits of MSR value.\r | |
| 167 | Described by the type MSR_IA32_APIC_BASE_REGISTER.\r | |
| 168 | \r | |
| 169 | <b>Example usage</b>\r | |
| 170 | @code\r | |
| 171 | MSR_IA32_APIC_BASE_REGISTER Msr;\r | |
| 172 | \r | |
| 173 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r | |
| 174 | AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);\r | |
| 175 | @endcode\r | |
| 7de98828 | 176 | @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.\r |
| 04c980a6 MK |
177 | **/\r |
| 178 | #define MSR_IA32_APIC_BASE 0x0000001B\r | |
| 179 | \r | |
| 180 | /**\r | |
| 181 | MSR information returned for MSR index #MSR_IA32_APIC_BASE\r | |
| 182 | **/\r | |
| 183 | typedef union {\r | |
| 184 | ///\r | |
| 185 | /// Individual bit fields\r | |
| 186 | ///\r | |
| 187 | struct {\r | |
| 188 | UINT32 Reserved1:8;\r | |
| 189 | ///\r | |
| 190 | /// [Bit 8] BSP flag (R/W).\r | |
| 191 | ///\r | |
| 192 | UINT32 BSP:1;\r | |
| 193 | UINT32 Reserved2:1;\r | |
| 194 | ///\r | |
| 195 | /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display\r | |
| 196 | /// Model 06_1AH.\r | |
| 197 | ///\r | |
| 198 | UINT32 EXTD:1;\r | |
| 199 | ///\r | |
| 200 | /// [Bit 11] APIC Global Enable (R/W).\r | |
| 201 | ///\r | |
| 202 | UINT32 EN:1;\r | |
| 203 | ///\r | |
| 204 | /// [Bits 31:12] APIC Base (R/W).\r | |
| 205 | ///\r | |
| 206 | UINT32 ApicBase:20;\r | |
| 207 | ///\r | |
| 208 | /// [Bits 63:32] APIC Base (R/W).\r | |
| 209 | ///\r | |
| 210 | UINT32 ApicBaseHi:32;\r | |
| 211 | } Bits;\r | |
| 212 | ///\r | |
| 213 | /// All bit fields as a 64-bit value\r | |
| 214 | ///\r | |
| 215 | UINT64 Uint64;\r | |
| 216 | } MSR_IA32_APIC_BASE_REGISTER;\r | |
| 217 | \r | |
| 218 | \r | |
| 219 | /**\r | |
| 220 | Control Features in Intel 64 Processor (R/W). If any one enumeration\r | |
| 221 | condition for defined bit field holds.\r | |
| 222 | \r | |
| 223 | @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)\r | |
| 224 | @param EAX Lower 32-bits of MSR value.\r | |
| 225 | Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r | |
| 226 | @param EDX Upper 32-bits of MSR value.\r | |
| 227 | Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r | |
| 228 | \r | |
| 229 | <b>Example usage</b>\r | |
| 230 | @code\r | |
| 231 | MSR_IA32_FEATURE_CONTROL_REGISTER Msr;\r | |
| 232 | \r | |
| 233 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);\r | |
| 234 | AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);\r | |
| 235 | @endcode\r | |
| 7de98828 | 236 | @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r |
| 04c980a6 MK |
237 | **/\r |
| 238 | #define MSR_IA32_FEATURE_CONTROL 0x0000003A\r | |
| 239 | \r | |
| 240 | /**\r | |
| 241 | MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL\r | |
| 242 | **/\r | |
| 243 | typedef union {\r | |
| 244 | ///\r | |
| 245 | /// Individual bit fields\r | |
| 246 | ///\r | |
| 247 | struct {\r | |
| 248 | ///\r | |
| 249 | /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from\r | |
| 250 | /// being written, writes to this bit will result in GP(0). Note: Once the\r | |
| 251 | /// Lock bit is set, the contents of this register cannot be modified.\r | |
| 252 | /// Therefore the lock bit must be set after configuring support for Intel\r | |
| 253 | /// Virtualization Technology and prior to transferring control to an\r | |
| 254 | /// option ROM or the OS. Hence, once the Lock bit is set, the entire\r | |
| 255 | /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD\r | |
| 256 | /// is not deasserted. If any one enumeration condition for defined bit\r | |
| 257 | /// field position greater than bit 0 holds.\r | |
| 258 | ///\r | |
| 259 | UINT32 Lock:1;\r | |
| 260 | ///\r | |
| 261 | /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a\r | |
| 262 | /// system executive to use VMX in conjunction with SMX to support\r | |
| 263 | /// Intel(R) Trusted Execution Technology. BIOS must set this bit only\r | |
| 264 | /// when the CPUID function 1 returns VMX feature flag and SMX feature\r | |
| 265 | /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&\r | |
| 266 | /// CPUID.01H:ECX[6] = 1.\r | |
| 267 | ///\r | |
| 268 | UINT32 EnableVmxInsideSmx:1;\r | |
| 269 | ///\r | |
| 270 | /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX\r | |
| 271 | /// for system executive that do not require SMX. BIOS must set this bit\r | |
| 272 | /// only when the CPUID function 1 returns VMX feature flag set (ECX bit\r | |
| 273 | /// 5). If CPUID.01H:ECX[5] = 1.\r | |
| 274 | ///\r | |
| 275 | UINT32 EnableVmxOutsideSmx:1;\r | |
| 276 | UINT32 Reserved1:5;\r | |
| 277 | ///\r | |
| 278 | /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit\r | |
| 279 | /// in the field represents an enable control for a corresponding SENTER\r | |
| 280 | /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If\r | |
| 281 | /// CPUID.01H:ECX[6] = 1.\r | |
| 282 | ///\r | |
| 283 | UINT32 SenterLocalFunctionEnables:7;\r | |
| 284 | ///\r | |
| 285 | /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable\r | |
| 286 | /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit\r | |
| 287 | /// 6] is set. If CPUID.01H:ECX[6] = 1.\r | |
| 288 | ///\r | |
| 289 | UINT32 SenterGlobalEnable:1;\r | |
| 290 | UINT32 Reserved2:2;\r | |
| 291 | ///\r | |
| 292 | /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX\r | |
| 293 | /// leaf functions. This bit is supported only if CPUID.1:ECX.[bit 6] is\r | |
| 294 | /// set. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r | |
| 295 | ///\r | |
| 296 | UINT32 SgxEnable:1;\r | |
| 297 | UINT32 Reserved3:1;\r | |
| 298 | ///\r | |
| 299 | /// [Bit 20] LMCE On (R/WL): When set, system software can program the\r | |
| 300 | /// MSRs associated with LMCE to configure delivery of some machine check\r | |
| 301 | /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.\r | |
| 302 | ///\r | |
| 303 | UINT32 LmceOn:1;\r | |
| 304 | UINT32 Reserved4:11;\r | |
| 305 | UINT32 Reserved5:32;\r | |
| 306 | } Bits;\r | |
| 307 | ///\r | |
| 308 | /// All bit fields as a 32-bit value\r | |
| 309 | ///\r | |
| 310 | UINT32 Uint32;\r | |
| 311 | ///\r | |
| 312 | /// All bit fields as a 64-bit value\r | |
| 313 | ///\r | |
| 314 | UINT64 Uint64;\r | |
| 315 | } MSR_IA32_FEATURE_CONTROL_REGISTER;\r | |
| 316 | \r | |
| 317 | \r | |
| 318 | /**\r | |
| 319 | Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,\r | |
| 320 | ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for\r | |
| 321 | a logical processor. Reset value is Zero. A write to IA32_TSC will modify\r | |
| 322 | the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does\r | |
| 323 | not affect the internal invariant TSC hardware.\r | |
| 324 | \r | |
| 325 | @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)\r | |
| 326 | @param EAX Lower 32-bits of MSR value.\r | |
| 327 | @param EDX Upper 32-bits of MSR value.\r | |
| 328 | \r | |
| 329 | <b>Example usage</b>\r | |
| 330 | @code\r | |
| 331 | UINT64 Msr;\r | |
| 332 | \r | |
| 333 | Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);\r | |
| 334 | AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);\r | |
| 335 | @endcode\r | |
| 7de98828 | 336 | @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.\r |
| 04c980a6 MK |
337 | **/\r |
| 338 | #define MSR_IA32_TSC_ADJUST 0x0000003B\r | |
| 339 | \r | |
| 340 | \r | |
| 341 | /**\r | |
| 342 | BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a\r | |
| 343 | microcode update to be loaded into the processor. See Section 9.11.6,\r | |
| 344 | "Microcode Update Loader." A processor may prevent writing to this MSR when\r | |
| 345 | loading guest states on VM entries or saving guest states on VM exits.\r | |
| 346 | Introduced at Display Family / Display Model 06_01H.\r | |
| 347 | \r | |
| 348 | @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)\r | |
| 349 | @param EAX Lower 32-bits of MSR value.\r | |
| 350 | @param EDX Upper 32-bits of MSR value.\r | |
| 351 | \r | |
| 352 | <b>Example usage</b>\r | |
| 353 | @code\r | |
| 354 | UINT64 Msr;\r | |
| 355 | \r | |
| 356 | Msr = 0;\r | |
| 357 | AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);\r | |
| 358 | @endcode\r | |
| 7de98828 | 359 | @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.\r |
| 04c980a6 MK |
360 | **/\r |
| 361 | #define MSR_IA32_BIOS_UPDT_TRIG 0x00000079\r | |
| 362 | \r | |
| 363 | \r | |
| 364 | /**\r | |
| 365 | BIOS Update Signature (RO) Returns the microcode update signature following\r | |
| 366 | the execution of CPUID.01H. A processor may prevent writing to this MSR when\r | |
| 367 | loading guest states on VM entries or saving guest states on VM exits.\r | |
| 368 | Introduced at Display Family / Display Model 06_01H.\r | |
| 369 | \r | |
| 370 | @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)\r | |
| 371 | @param EAX Lower 32-bits of MSR value.\r | |
| 372 | Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r | |
| 373 | @param EDX Upper 32-bits of MSR value.\r | |
| 374 | Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r | |
| 375 | \r | |
| 376 | <b>Example usage</b>\r | |
| 377 | @code\r | |
| 378 | MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;\r | |
| 379 | \r | |
| 380 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);\r | |
| 381 | @endcode\r | |
| 7de98828 | 382 | @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.\r |
| 04c980a6 MK |
383 | **/\r |
| 384 | #define MSR_IA32_BIOS_SIGN_ID 0x0000008B\r | |
| 385 | \r | |
| 386 | /**\r | |
| 387 | MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID\r | |
| 388 | **/\r | |
| 389 | typedef union {\r | |
| 390 | ///\r | |
| 391 | /// Individual bit fields\r | |
| 392 | ///\r | |
| 393 | struct {\r | |
| 394 | UINT32 Reserved:32;\r | |
| 395 | ///\r | |
| 396 | /// [Bits 63:32] Microcode update signature. This field contains the\r | |
| 397 | /// signature of the currently loaded microcode update when read following\r | |
| 398 | /// the execution of the CPUID instruction, function 1. It is required\r | |
| 399 | /// that this register field be pre-loaded with zero prior to executing\r | |
| 400 | /// the CPUID, function 1. If the field remains equal to zero, then there\r | |
| 401 | /// is no microcode update loaded. Another nonzero value will be the\r | |
| 402 | /// signature.\r | |
| 403 | ///\r | |
| 404 | UINT32 MicrocodeUpdateSignature:32;\r | |
| 405 | } Bits;\r | |
| 406 | ///\r | |
| 407 | /// All bit fields as a 64-bit value\r | |
| 408 | ///\r | |
| 409 | UINT64 Uint64;\r | |
| 410 | } MSR_IA32_BIOS_SIGN_ID_REGISTER;\r | |
| 411 | \r | |
| 412 | \r | |
| 413 | /**\r | |
| 414 | SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1. CPUID.01H: ECX[6] =\r | |
| 415 | 1.\r | |
| 416 | \r | |
| 417 | @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)\r | |
| 418 | @param EAX Lower 32-bits of MSR value.\r | |
| 419 | Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r | |
| 420 | @param EDX Upper 32-bits of MSR value.\r | |
| 421 | Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r | |
| 422 | \r | |
| 423 | <b>Example usage</b>\r | |
| 424 | @code\r | |
| 425 | MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;\r | |
| 426 | \r | |
| 427 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);\r | |
| 428 | AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);\r | |
| 429 | @endcode\r | |
| 7de98828 | 430 | @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.\r |
| 04c980a6 MK |
431 | **/\r |
| 432 | #define MSR_IA32_SMM_MONITOR_CTL 0x0000009B\r | |
| 433 | \r | |
| 434 | /**\r | |
| 435 | MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL\r | |
| 436 | **/\r | |
| 437 | typedef union {\r | |
| 438 | ///\r | |
| 439 | /// Individual bit fields\r | |
| 440 | ///\r | |
| 441 | struct {\r | |
| 442 | ///\r | |
| 443 | /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this\r | |
| 444 | /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment\r | |
| 445 | /// (see Section 34.15.6), the dual-monitor treatment cannot be activated\r | |
| 446 | /// if the bit is 0. This bit is cleared when the logical processor is\r | |
| 447 | /// reset.\r | |
| 448 | ///\r | |
| 449 | UINT32 Valid:1;\r | |
| 450 | UINT32 Reserved1:1;\r | |
| 451 | ///\r | |
| 452 | /// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the\r | |
| 453 | /// default treatment of SMIs and SMM. Executions of VMXOFF unblock SMIs\r | |
| 454 | /// unless bit 2 is 1 (the value of bit 0 is irrelevant).\r | |
| 455 | ///\r | |
| 456 | UINT32 BlockSmi:1;\r | |
| 457 | UINT32 Reserved2:9;\r | |
| 458 | ///\r | |
| 459 | /// [Bits 31:12] MSEG Base (R/W).\r | |
| 460 | ///\r | |
| 461 | UINT32 MsegBase:20;\r | |
| 462 | UINT32 Reserved3:32;\r | |
| 463 | } Bits;\r | |
| 464 | ///\r | |
| 465 | /// All bit fields as a 32-bit value\r | |
| 466 | ///\r | |
| 467 | UINT32 Uint32;\r | |
| 468 | ///\r | |
| 469 | /// All bit fields as a 64-bit value\r | |
| 470 | ///\r | |
| 471 | UINT64 Uint64;\r | |
| 472 | } MSR_IA32_SMM_MONITOR_CTL_REGISTER;\r | |
| 473 | \r | |
| 474 | \r | |
| 475 | /**\r | |
| 476 | Base address of the logical processor's SMRAM image (RO, SMM only). If\r | |
| 477 | IA32_VMX_MISC[15].\r | |
| 478 | \r | |
| 479 | @param ECX MSR_IA32_SMBASE (0x0000009E)\r | |
| 480 | @param EAX Lower 32-bits of MSR value.\r | |
| 481 | @param EDX Upper 32-bits of MSR value.\r | |
| 482 | \r | |
| 483 | <b>Example usage</b>\r | |
| 484 | @code\r | |
| 485 | UINT64 Msr;\r | |
| 486 | \r | |
| 487 | Msr = AsmReadMsr64 (MSR_IA32_SMBASE);\r | |
| 488 | @endcode\r | |
| 7de98828 | 489 | @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.\r |
| 04c980a6 MK |
490 | **/\r |
| 491 | #define MSR_IA32_SMBASE 0x0000009E\r | |
| 492 | \r | |
| 493 | \r | |
| 494 | /**\r | |
| 495 | General Performance Counters (R/W).\r | |
| 496 | MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.\r | |
| 497 | \r | |
| 498 | @param ECX MSR_IA32_PMCn\r | |
| 499 | @param EAX Lower 32-bits of MSR value.\r | |
| 500 | @param EDX Upper 32-bits of MSR value.\r | |
| 501 | \r | |
| 502 | <b>Example usage</b>\r | |
| 503 | @code\r | |
| 504 | UINT64 Msr;\r | |
| 505 | \r | |
| 506 | Msr = AsmReadMsr64 (MSR_IA32_PMC0);\r | |
| 507 | AsmWriteMsr64 (MSR_IA32_PMC0, Msr);\r | |
| 508 | @endcode\r | |
| 7de98828 JF |
509 | @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.\r |
| 510 | MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.\r | |
| 511 | MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.\r | |
| 512 | MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.\r | |
| 513 | MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.\r | |
| 514 | MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.\r | |
| 515 | MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.\r | |
| 516 | MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.\r | |
| 04c980a6 MK |
517 | @{\r |
| 518 | **/\r | |
| 519 | #define MSR_IA32_PMC0 0x000000C1\r | |
| 520 | #define MSR_IA32_PMC1 0x000000C2\r | |
| 521 | #define MSR_IA32_PMC2 0x000000C3\r | |
| 522 | #define MSR_IA32_PMC3 0x000000C4\r | |
| 523 | #define MSR_IA32_PMC4 0x000000C5\r | |
| 524 | #define MSR_IA32_PMC5 0x000000C6\r | |
| 525 | #define MSR_IA32_PMC6 0x000000C7\r | |
| 526 | #define MSR_IA32_PMC7 0x000000C8\r | |
| 527 | /// @}\r | |
| 528 | \r | |
| 529 | \r | |
| 530 | /**\r | |
| 531 | TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.\r | |
| 532 | C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative\r | |
| 533 | to TSC freq.) when the logical processor is in C0. Cleared upon overflow /\r | |
| 534 | wrap-around of IA32_APERF.\r | |
| 535 | \r | |
| 536 | @param ECX MSR_IA32_MPERF (0x000000E7)\r | |
| 537 | @param EAX Lower 32-bits of MSR value.\r | |
| 538 | @param EDX Upper 32-bits of MSR value.\r | |
| 539 | \r | |
| 540 | <b>Example usage</b>\r | |
| 541 | @code\r | |
| 542 | UINT64 Msr;\r | |
| 543 | \r | |
| 544 | Msr = AsmReadMsr64 (MSR_IA32_MPERF);\r | |
| 545 | AsmWriteMsr64 (MSR_IA32_MPERF, Msr);\r | |
| 546 | @endcode\r | |
| 7de98828 | 547 | @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.\r |
| 04c980a6 MK |
548 | **/\r |
| 549 | #define MSR_IA32_MPERF 0x000000E7\r | |
| 550 | \r | |
| 551 | \r | |
| 552 | /**\r | |
| 553 | Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =\r | |
| 554 | 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at\r | |
| 555 | the coordinated clock frequency, when the logical processor is in C0.\r | |
| 556 | Cleared upon overflow / wrap-around of IA32_MPERF.\r | |
| 557 | \r | |
| 558 | @param ECX MSR_IA32_APERF (0x000000E8)\r | |
| 559 | @param EAX Lower 32-bits of MSR value.\r | |
| 560 | @param EDX Upper 32-bits of MSR value.\r | |
| 561 | \r | |
| 562 | <b>Example usage</b>\r | |
| 563 | @code\r | |
| 564 | UINT64 Msr;\r | |
| 565 | \r | |
| 566 | Msr = AsmReadMsr64 (MSR_IA32_APERF);\r | |
| 567 | AsmWriteMsr64 (MSR_IA32_APERF, Msr);\r | |
| 568 | @endcode\r | |
| 7de98828 | 569 | @note MSR_IA32_APERF is defined as IA32_APERF in SDM.\r |
| 04c980a6 MK |
570 | **/\r |
| 571 | #define MSR_IA32_APERF 0x000000E8\r | |
| 572 | \r | |
| 573 | \r | |
| 574 | /**\r | |
| 575 | MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".\r | |
| 576 | Introduced at Display Family / Display Model 06_01H.\r | |
| 577 | \r | |
| 578 | @param ECX MSR_IA32_MTRRCAP (0x000000FE)\r | |
| 579 | @param EAX Lower 32-bits of MSR value.\r | |
| 580 | Described by the type MSR_IA32_MTRRCAP_REGISTER.\r | |
| 581 | @param EDX Upper 32-bits of MSR value.\r | |
| 582 | Described by the type MSR_IA32_MTRRCAP_REGISTER.\r | |
| 583 | \r | |
| 584 | <b>Example usage</b>\r | |
| 585 | @code\r | |
| 586 | MSR_IA32_MTRRCAP_REGISTER Msr;\r | |
| 587 | \r | |
| 588 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r | |
| 589 | @endcode\r | |
| 7de98828 | 590 | @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.\r |
| 04c980a6 MK |
591 | **/\r |
| 592 | #define MSR_IA32_MTRRCAP 0x000000FE\r | |
| 593 | \r | |
| 594 | /**\r | |
| 595 | MSR information returned for MSR index #MSR_IA32_MTRRCAP\r | |
| 596 | **/\r | |
| 597 | typedef union {\r | |
| 598 | ///\r | |
| 599 | /// Individual bit fields\r | |
| 600 | ///\r | |
| 601 | struct {\r | |
| 602 | ///\r | |
| 603 | /// [Bits 7:0] VCNT: The number of variable memory type ranges in the\r | |
| 604 | /// processor.\r | |
| 605 | ///\r | |
| 606 | UINT32 VCNT:8;\r | |
| 607 | ///\r | |
| 608 | /// [Bit 8] Fixed range MTRRs are supported when set.\r | |
| 609 | ///\r | |
| 610 | UINT32 FIX:1;\r | |
| 611 | UINT32 Reserved1:1;\r | |
| 612 | ///\r | |
| 613 | /// [Bit 10] WC Supported when set.\r | |
| 614 | ///\r | |
| 615 | UINT32 WC:1;\r | |
| 616 | ///\r | |
| 617 | /// [Bit 11] SMRR Supported when set.\r | |
| 618 | ///\r | |
| 619 | UINT32 SMRR:1;\r | |
| 620 | UINT32 Reserved2:20;\r | |
| 621 | UINT32 Reserved3:32;\r | |
| 622 | } Bits;\r | |
| 623 | ///\r | |
| 624 | /// All bit fields as a 32-bit value\r | |
| 625 | ///\r | |
| 626 | UINT32 Uint32;\r | |
| 627 | ///\r | |
| 628 | /// All bit fields as a 64-bit value\r | |
| 629 | ///\r | |
| 630 | UINT64 Uint64;\r | |
| 631 | } MSR_IA32_MTRRCAP_REGISTER;\r | |
| 632 | \r | |
| 633 | \r | |
| 634 | /**\r | |
| 635 | SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r | |
| 636 | \r | |
| 637 | @param ECX MSR_IA32_SYSENTER_CS (0x00000174)\r | |
| 638 | @param EAX Lower 32-bits of MSR value.\r | |
| 639 | Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r | |
| 640 | @param EDX Upper 32-bits of MSR value.\r | |
| 641 | Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r | |
| 642 | \r | |
| 643 | <b>Example usage</b>\r | |
| 644 | @code\r | |
| 645 | MSR_IA32_SYSENTER_CS_REGISTER Msr;\r | |
| 646 | \r | |
| 647 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);\r | |
| 648 | AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);\r | |
| 649 | @endcode\r | |
| 7de98828 | 650 | @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.\r |
| 04c980a6 MK |
651 | **/\r |
| 652 | #define MSR_IA32_SYSENTER_CS 0x00000174\r | |
| 653 | \r | |
| 654 | /**\r | |
| 655 | MSR information returned for MSR index #MSR_IA32_SYSENTER_CS\r | |
| 656 | **/\r | |
| 657 | typedef union {\r | |
| 658 | ///\r | |
| 659 | /// Individual bit fields\r | |
| 660 | ///\r | |
| 661 | struct {\r | |
| 662 | ///\r | |
| 663 | /// [Bits 15:0] CS Selector.\r | |
| 664 | ///\r | |
| 665 | UINT32 CS:16;\r | |
| 666 | UINT32 Reserved1:16;\r | |
| 667 | UINT32 Reserved2:32;\r | |
| 668 | } Bits;\r | |
| 669 | ///\r | |
| 670 | /// All bit fields as a 32-bit value\r | |
| 671 | ///\r | |
| 672 | UINT32 Uint32;\r | |
| 673 | ///\r | |
| 674 | /// All bit fields as a 64-bit value\r | |
| 675 | ///\r | |
| 676 | UINT64 Uint64;\r | |
| 677 | } MSR_IA32_SYSENTER_CS_REGISTER;\r | |
| 678 | \r | |
| 679 | \r | |
| 680 | /**\r | |
| 681 | SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r | |
| 682 | \r | |
| 683 | @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)\r | |
| 684 | @param EAX Lower 32-bits of MSR value.\r | |
| 685 | @param EDX Upper 32-bits of MSR value.\r | |
| 686 | \r | |
| 687 | <b>Example usage</b>\r | |
| 688 | @code\r | |
| 689 | UINT64 Msr;\r | |
| 690 | \r | |
| 691 | Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);\r | |
| 692 | AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);\r | |
| 693 | @endcode\r | |
| 7de98828 | 694 | @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.\r |
| 04c980a6 MK |
695 | **/\r |
| 696 | #define MSR_IA32_SYSENTER_ESP 0x00000175\r | |
| 697 | \r | |
| 698 | \r | |
| 699 | /**\r | |
| 700 | SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r | |
| 701 | \r | |
| 702 | @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)\r | |
| 703 | @param EAX Lower 32-bits of MSR value.\r | |
| 704 | @param EDX Upper 32-bits of MSR value.\r | |
| 705 | \r | |
| 706 | <b>Example usage</b>\r | |
| 707 | @code\r | |
| 708 | UINT64 Msr;\r | |
| 709 | \r | |
| 710 | Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);\r | |
| 711 | AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);\r | |
| 712 | @endcode\r | |
| 7de98828 | 713 | @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.\r |
| 04c980a6 MK |
714 | **/\r |
| 715 | #define MSR_IA32_SYSENTER_EIP 0x00000176\r | |
| 716 | \r | |
| 717 | \r | |
| 718 | /**\r | |
| 719 | Global Machine Check Capability (RO). Introduced at Display Family / Display\r | |
| 720 | Model 06_01H.\r | |
| 721 | \r | |
| 722 | @param ECX MSR_IA32_MCG_CAP (0x00000179)\r | |
| 723 | @param EAX Lower 32-bits of MSR value.\r | |
| 724 | Described by the type MSR_IA32_MCG_CAP_REGISTER.\r | |
| 725 | @param EDX Upper 32-bits of MSR value.\r | |
| 726 | Described by the type MSR_IA32_MCG_CAP_REGISTER.\r | |
| 727 | \r | |
| 728 | <b>Example usage</b>\r | |
| 729 | @code\r | |
| 730 | MSR_IA32_MCG_CAP_REGISTER Msr;\r | |
| 731 | \r | |
| 732 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r | |
| 733 | @endcode\r | |
| 7de98828 | 734 | @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r |
| 04c980a6 MK |
735 | **/\r |
| 736 | #define MSR_IA32_MCG_CAP 0x00000179\r | |
| 737 | \r | |
| 738 | /**\r | |
| 739 | MSR information returned for MSR index #MSR_IA32_MCG_CAP\r | |
| 740 | **/\r | |
| 741 | typedef union {\r | |
| 742 | ///\r | |
| 743 | /// Individual bit fields\r | |
| 744 | ///\r | |
| 745 | struct {\r | |
| 746 | ///\r | |
| 747 | /// [Bits 7:0] Count: Number of reporting banks.\r | |
| 748 | ///\r | |
| 749 | UINT32 Count:8;\r | |
| 750 | ///\r | |
| 751 | /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.\r | |
| 752 | ///\r | |
| 753 | UINT32 MCG_CTL_P:1;\r | |
| 754 | ///\r | |
| 755 | /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present\r | |
| 756 | /// if this bit is set.\r | |
| 757 | ///\r | |
| 758 | UINT32 MCG_EXT_P:1;\r | |
| 759 | ///\r | |
| 760 | /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.\r | |
| 761 | /// Introduced at Display Family / Display Model 06_01H.\r | |
| 762 | ///\r | |
| 763 | UINT32 MCP_CMCI_P:1;\r | |
| 764 | ///\r | |
| 765 | /// [Bit 11] MCG_TES_P: Threshold-based error status register are present\r | |
| 766 | /// if this bit is set.\r | |
| 767 | ///\r | |
| 768 | UINT32 MCG_TES_P:1;\r | |
| 769 | UINT32 Reserved1:4;\r | |
| 770 | ///\r | |
| 771 | /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state\r | |
| 772 | /// registers present.\r | |
| 773 | ///\r | |
| 774 | UINT32 MCG_EXT_CNT:8;\r | |
| 775 | ///\r | |
| 776 | /// [Bit 24] MCG_SER_P: The processor supports software error recovery if\r | |
| 777 | /// this bit is set.\r | |
| 778 | ///\r | |
| 779 | UINT32 MCG_SER_P:1;\r | |
| 780 | UINT32 Reserved2:1;\r | |
| 781 | ///\r | |
| 782 | /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform\r | |
| 783 | /// firmware to be invoked when an error is detected so that it may\r | |
| 784 | /// provide additional platform specific information in an ACPI format\r | |
| 785 | /// "Generic Error Data Entry" that augments the data included in machine\r | |
| 786 | /// check bank registers. Introduced at Display Family / Display Model\r | |
| 787 | /// 06_3EH.\r | |
| 788 | ///\r | |
| 789 | UINT32 MCG_ELOG_P:1;\r | |
| 790 | ///\r | |
| 791 | /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended\r | |
| 792 | /// state in IA32_MCG_STATUS and associated MSR necessary to configure\r | |
| 793 | /// Local Machine Check Exception (LMCE). Introduced at Display Family /\r | |
| 794 | /// Display Model 06_3EH.\r | |
| 795 | ///\r | |
| 796 | UINT32 MCG_LMCE_P:1;\r | |
| 797 | UINT32 Reserved3:4;\r | |
| 798 | UINT32 Reserved4:32;\r | |
| 799 | } Bits;\r | |
| 800 | ///\r | |
| 801 | /// All bit fields as a 32-bit value\r | |
| 802 | ///\r | |
| 803 | UINT32 Uint32;\r | |
| 804 | ///\r | |
| 805 | /// All bit fields as a 64-bit value\r | |
| 806 | ///\r | |
| 807 | UINT64 Uint64;\r | |
| 808 | } MSR_IA32_MCG_CAP_REGISTER;\r | |
| 809 | \r | |
| 810 | \r | |
| 811 | /**\r | |
| 812 | Global Machine Check Status (R/W0). Introduced at Display Family / Display\r | |
| 813 | Model 06_01H.\r | |
| 814 | \r | |
| 815 | @param ECX MSR_IA32_MCG_STATUS (0x0000017A)\r | |
| 816 | @param EAX Lower 32-bits of MSR value.\r | |
| 817 | Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r | |
| 818 | @param EDX Upper 32-bits of MSR value.\r | |
| 819 | Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r | |
| 820 | \r | |
| 821 | <b>Example usage</b>\r | |
| 822 | @code\r | |
| 823 | MSR_IA32_MCG_STATUS_REGISTER Msr;\r | |
| 824 | \r | |
| 825 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);\r | |
| 826 | AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);\r | |
| 827 | @endcode\r | |
| 7de98828 | 828 | @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.\r |
| 04c980a6 MK |
829 | **/\r |
| 830 | #define MSR_IA32_MCG_STATUS 0x0000017A\r | |
| 831 | \r | |
| 832 | /**\r | |
| 833 | MSR information returned for MSR index #MSR_IA32_MCG_STATUS\r | |
| 834 | **/\r | |
| 835 | typedef union {\r | |
| 836 | ///\r | |
| 837 | /// Individual bit fields\r | |
| 838 | ///\r | |
| 839 | struct {\r | |
| 840 | ///\r | |
| 841 | /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display\r | |
| 842 | /// Model 06_01H.\r | |
| 843 | ///\r | |
| 844 | UINT32 RIPV:1;\r | |
| 845 | ///\r | |
| 846 | /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display\r | |
| 847 | /// Model 06_01H.\r | |
| 848 | ///\r | |
| 849 | UINT32 EIPV:1;\r | |
| 850 | ///\r | |
| 851 | /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family\r | |
| 852 | /// / Display Model 06_01H.\r | |
| 853 | ///\r | |
| 854 | UINT32 MCIP:1;\r | |
| 855 | ///\r | |
| 856 | /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.\r | |
| 857 | ///\r | |
| 858 | UINT32 LMCE_S:1;\r | |
| 859 | UINT32 Reserved1:28;\r | |
| 860 | UINT32 Reserved2:32;\r | |
| 861 | } Bits;\r | |
| 862 | ///\r | |
| 863 | /// All bit fields as a 32-bit value\r | |
| 864 | ///\r | |
| 865 | UINT32 Uint32;\r | |
| 866 | ///\r | |
| 867 | /// All bit fields as a 64-bit value\r | |
| 868 | ///\r | |
| 869 | UINT64 Uint64;\r | |
| 870 | } MSR_IA32_MCG_STATUS_REGISTER;\r | |
| 871 | \r | |
| 872 | \r | |
| 873 | /**\r | |
| 874 | Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.\r | |
| 875 | \r | |
| 876 | @param ECX MSR_IA32_MCG_CTL (0x0000017B)\r | |
| 877 | @param EAX Lower 32-bits of MSR value.\r | |
| 878 | @param EDX Upper 32-bits of MSR value.\r | |
| 879 | \r | |
| 880 | <b>Example usage</b>\r | |
| 881 | @code\r | |
| 882 | UINT64 Msr;\r | |
| 883 | \r | |
| 884 | Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);\r | |
| 885 | AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);\r | |
| 886 | @endcode\r | |
| 7de98828 | 887 | @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.\r |
| 04c980a6 MK |
888 | **/\r |
| 889 | #define MSR_IA32_MCG_CTL 0x0000017B\r | |
| 890 | \r | |
| 891 | \r | |
| 892 | /**\r | |
| 893 | Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.\r | |
| 894 | \r | |
| 895 | @param ECX MSR_IA32_PERFEVTSELn\r | |
| 896 | @param EAX Lower 32-bits of MSR value.\r | |
| 897 | Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r | |
| 898 | @param EDX Upper 32-bits of MSR value.\r | |
| 899 | Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r | |
| 900 | \r | |
| 901 | <b>Example usage</b>\r | |
| 902 | @code\r | |
| 903 | MSR_IA32_PERFEVTSEL_REGISTER Msr;\r | |
| 904 | \r | |
| 905 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);\r | |
| 906 | AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);\r | |
| 907 | @endcode\r | |
| 7de98828 JF |
908 | @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.\r |
| 909 | MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.\r | |
| 910 | MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.\r | |
| 911 | MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r | |
| 04c980a6 MK |
912 | @{\r |
| 913 | **/\r | |
| 914 | #define MSR_IA32_PERFEVTSEL0 0x00000186\r | |
| 915 | #define MSR_IA32_PERFEVTSEL1 0x00000187\r | |
| 916 | #define MSR_IA32_PERFEVTSEL2 0x00000188\r | |
| 917 | #define MSR_IA32_PERFEVTSEL3 0x00000189\r | |
| 918 | /// @}\r | |
| 919 | \r | |
| 920 | /**\r | |
| 921 | MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to\r | |
| 922 | #MSR_IA32_PERFEVTSEL3\r | |
| 923 | **/\r | |
| 924 | typedef union {\r | |
| 925 | ///\r | |
| 926 | /// Individual bit fields\r | |
| 927 | ///\r | |
| 928 | struct {\r | |
| 929 | ///\r | |
| 930 | /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r | |
| 931 | ///\r | |
| 932 | UINT32 EventSelect:8;\r | |
| 933 | ///\r | |
| 934 | /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r | |
| 935 | /// detect on the selected event logic.\r | |
| 936 | ///\r | |
| 937 | UINT32 UMASK:8;\r | |
| 938 | ///\r | |
| 939 | /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r | |
| 940 | ///\r | |
| 941 | UINT32 USR:1;\r | |
| 942 | ///\r | |
| 943 | /// [Bit 17] OS: Counts while in privilege level is ring 0.\r | |
| 944 | ///\r | |
| 945 | UINT32 OS:1;\r | |
| 946 | ///\r | |
| 947 | /// [Bit 18] Edge: Enables edge detection if set.\r | |
| 948 | ///\r | |
| 949 | UINT32 E:1;\r | |
| 950 | ///\r | |
| 951 | /// [Bit 19] PC: enables pin control.\r | |
| 952 | ///\r | |
| 953 | UINT32 PC:1;\r | |
| 954 | ///\r | |
| 955 | /// [Bit 20] INT: enables interrupt on counter overflow.\r | |
| 956 | ///\r | |
| 957 | UINT32 INT:1;\r | |
| 958 | ///\r | |
| 959 | /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r | |
| 960 | /// event conditions occurring across all logical processors sharing a\r | |
| 961 | /// processor core. When set to 0, the counter only increments the\r | |
| 962 | /// associated event conditions occurring in the logical processor which\r | |
| 963 | /// programmed the MSR.\r | |
| 964 | ///\r | |
| 965 | UINT32 ANY:1;\r | |
| 966 | ///\r | |
| 967 | /// [Bit 22] EN: enables the corresponding performance counter to commence\r | |
| 968 | /// counting when this bit is set.\r | |
| 969 | ///\r | |
| 970 | UINT32 EN:1;\r | |
| 971 | ///\r | |
| 972 | /// [Bit 23] INV: invert the CMASK.\r | |
| 973 | ///\r | |
| 974 | UINT32 INV:1;\r | |
| 975 | ///\r | |
| 976 | /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r | |
| 977 | /// performance counter increments each cycle if the event count is\r | |
| 978 | /// greater than or equal to the CMASK.\r | |
| 979 | ///\r | |
| 980 | UINT32 CMASK:8;\r | |
| 981 | UINT32 Reserved:32;\r | |
| 982 | } Bits;\r | |
| 983 | ///\r | |
| 984 | /// All bit fields as a 32-bit value\r | |
| 985 | ///\r | |
| 986 | UINT32 Uint32;\r | |
| 987 | ///\r | |
| 988 | /// All bit fields as a 64-bit value\r | |
| 989 | ///\r | |
| 990 | UINT64 Uint64;\r | |
| 991 | } MSR_IA32_PERFEVTSEL_REGISTER;\r | |
| 992 | \r | |
| 993 | \r | |
| 994 | /**\r | |
| 995 | Current performance state(P-State) operating point (RO). Introduced at\r | |
| 996 | Display Family / Display Model 0F_03H.\r | |
| 997 | \r | |
| 998 | @param ECX MSR_IA32_PERF_STATUS (0x00000198)\r | |
| 999 | @param EAX Lower 32-bits of MSR value.\r | |
| 1000 | Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r | |
| 1001 | @param EDX Upper 32-bits of MSR value.\r | |
| 1002 | Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r | |
| 1003 | \r | |
| 1004 | <b>Example usage</b>\r | |
| 1005 | @code\r | |
| 1006 | MSR_IA32_PERF_STATUS_REGISTER Msr;\r | |
| 1007 | \r | |
| 1008 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);\r | |
| 1009 | @endcode\r | |
| 7de98828 | 1010 | @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.\r |
| 04c980a6 MK |
1011 | **/\r |
| 1012 | #define MSR_IA32_PERF_STATUS 0x00000198\r | |
| 1013 | \r | |
| 1014 | /**\r | |
| 1015 | MSR information returned for MSR index #MSR_IA32_PERF_STATUS\r | |
| 1016 | **/\r | |
| 1017 | typedef union {\r | |
| 1018 | ///\r | |
| 1019 | /// Individual bit fields\r | |
| 1020 | ///\r | |
| 1021 | struct {\r | |
| 1022 | ///\r | |
| 1023 | /// [Bits 15:0] Current performance State Value.\r | |
| 1024 | ///\r | |
| 1025 | UINT32 State:16;\r | |
| 1026 | UINT32 Reserved1:16;\r | |
| 1027 | UINT32 Reserved2:32;\r | |
| 1028 | } Bits;\r | |
| 1029 | ///\r | |
| 1030 | /// All bit fields as a 32-bit value\r | |
| 1031 | ///\r | |
| 1032 | UINT32 Uint32;\r | |
| 1033 | ///\r | |
| 1034 | /// All bit fields as a 64-bit value\r | |
| 1035 | ///\r | |
| 1036 | UINT64 Uint64;\r | |
| 1037 | } MSR_IA32_PERF_STATUS_REGISTER;\r | |
| 1038 | \r | |
| 1039 | \r | |
| 1040 | /**\r | |
| 1041 | (R/W). Introduced at Display Family / Display Model 0F_03H.\r | |
| 1042 | \r | |
| 1043 | @param ECX MSR_IA32_PERF_CTL (0x00000199)\r | |
| 1044 | @param EAX Lower 32-bits of MSR value.\r | |
| 1045 | Described by the type MSR_IA32_PERF_CTL_REGISTER.\r | |
| 1046 | @param EDX Upper 32-bits of MSR value.\r | |
| 1047 | Described by the type MSR_IA32_PERF_CTL_REGISTER.\r | |
| 1048 | \r | |
| 1049 | <b>Example usage</b>\r | |
| 1050 | @code\r | |
| 1051 | MSR_IA32_PERF_CTL_REGISTER Msr;\r | |
| 1052 | \r | |
| 1053 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);\r | |
| 1054 | AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);\r | |
| 1055 | @endcode\r | |
| 7de98828 | 1056 | @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.\r |
| 04c980a6 MK |
1057 | **/\r |
| 1058 | #define MSR_IA32_PERF_CTL 0x00000199\r | |
| 1059 | \r | |
| 1060 | /**\r | |
| 1061 | MSR information returned for MSR index #MSR_IA32_PERF_CTL\r | |
| 1062 | **/\r | |
| 1063 | typedef union {\r | |
| 1064 | ///\r | |
| 1065 | /// Individual bit fields\r | |
| 1066 | ///\r | |
| 1067 | struct {\r | |
| 1068 | ///\r | |
| 1069 | /// [Bits 15:0] Target performance State Value.\r | |
| 1070 | ///\r | |
| 1071 | UINT32 TargetState:16;\r | |
| 1072 | UINT32 Reserved1:16;\r | |
| 1073 | ///\r | |
| 1074 | /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH\r | |
| 1075 | /// (Mobile only).\r | |
| 1076 | ///\r | |
| 1077 | UINT32 IDA:1;\r | |
| 1078 | UINT32 Reserved2:31;\r | |
| 1079 | } Bits;\r | |
| 1080 | ///\r | |
| 1081 | /// All bit fields as a 64-bit value\r | |
| 1082 | ///\r | |
| 1083 | UINT64 Uint64;\r | |
| 1084 | } MSR_IA32_PERF_CTL_REGISTER;\r | |
| 1085 | \r | |
| 1086 | \r | |
| 1087 | /**\r | |
| 1088 | Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled\r | |
| 1089 | Clock Modulation.". Introduced at Display Family / Display Model 0F_0H.\r | |
| 1090 | \r | |
| 1091 | @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)\r | |
| 1092 | @param EAX Lower 32-bits of MSR value.\r | |
| 1093 | Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r | |
| 1094 | @param EDX Upper 32-bits of MSR value.\r | |
| 1095 | Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r | |
| 1096 | \r | |
| 1097 | <b>Example usage</b>\r | |
| 1098 | @code\r | |
| 1099 | MSR_IA32_CLOCK_MODULATION_REGISTER Msr;\r | |
| 1100 | \r | |
| 1101 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);\r | |
| 1102 | AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);\r | |
| 1103 | @endcode\r | |
| 7de98828 | 1104 | @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.\r |
| 04c980a6 MK |
1105 | **/\r |
| 1106 | #define MSR_IA32_CLOCK_MODULATION 0x0000019A\r | |
| 1107 | \r | |
| 1108 | /**\r | |
| 1109 | MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION\r | |
| 1110 | **/\r | |
| 1111 | typedef union {\r | |
| 1112 | ///\r | |
| 1113 | /// Individual bit fields\r | |
| 1114 | ///\r | |
| 1115 | struct {\r | |
| 1116 | ///\r | |
| 1117 | /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If\r | |
| 1118 | /// CPUID.06H:EAX[5] = 1.\r | |
| 1119 | ///\r | |
| 1120 | UINT32 ExtendedOnDemandClockModulationDutyCycle:1;\r | |
| 1121 | ///\r | |
| 1122 | /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded\r | |
| 1123 | /// values for target duty cycle modulation.\r | |
| 1124 | ///\r | |
| 1125 | UINT32 OnDemandClockModulationDutyCycle:3;\r | |
| 1126 | ///\r | |
| 1127 | /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.\r | |
| 1128 | ///\r | |
| 1129 | UINT32 OnDemandClockModulationEnable:1;\r | |
| 1130 | UINT32 Reserved1:27;\r | |
| 1131 | UINT32 Reserved2:32;\r | |
| 1132 | } Bits;\r | |
| 1133 | ///\r | |
| 1134 | /// All bit fields as a 32-bit value\r | |
| 1135 | ///\r | |
| 1136 | UINT32 Uint32;\r | |
| 1137 | ///\r | |
| 1138 | /// All bit fields as a 64-bit value\r | |
| 1139 | ///\r | |
| 1140 | UINT64 Uint64;\r | |
| 1141 | } MSR_IA32_CLOCK_MODULATION_REGISTER;\r | |
| 1142 | \r | |
| 1143 | \r | |
| 1144 | /**\r | |
| 1145 | Thermal Interrupt Control (R/W) Enables and disables the generation of an\r | |
| 1146 | interrupt on temperature transitions detected with the processor's thermal\r | |
| 1147 | sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".\r | |
| 1148 | Introduced at Display Family / Display Model 0F_0H.\r | |
| 1149 | \r | |
| 1150 | @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)\r | |
| 1151 | @param EAX Lower 32-bits of MSR value.\r | |
| 1152 | Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r | |
| 1153 | @param EDX Upper 32-bits of MSR value.\r | |
| 1154 | Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r | |
| 1155 | \r | |
| 1156 | <b>Example usage</b>\r | |
| 1157 | @code\r | |
| 1158 | MSR_IA32_THERM_INTERRUPT_REGISTER Msr;\r | |
| 1159 | \r | |
| 1160 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);\r | |
| 1161 | AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);\r | |
| 1162 | @endcode\r | |
| 7de98828 | 1163 | @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.\r |
| 04c980a6 MK |
1164 | **/\r |
| 1165 | #define MSR_IA32_THERM_INTERRUPT 0x0000019B\r | |
| 1166 | \r | |
| 1167 | /**\r | |
| 1168 | MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT\r | |
| 1169 | **/\r | |
| 1170 | typedef union {\r | |
| 1171 | ///\r | |
| 1172 | /// Individual bit fields\r | |
| 1173 | ///\r | |
| 1174 | struct {\r | |
| 1175 | ///\r | |
| 1176 | /// [Bit 0] High-Temperature Interrupt Enable.\r | |
| 1177 | ///\r | |
| 1178 | UINT32 HighTempEnable:1;\r | |
| 1179 | ///\r | |
| 1180 | /// [Bit 1] Low-Temperature Interrupt Enable.\r | |
| 1181 | ///\r | |
| 1182 | UINT32 LowTempEnable:1;\r | |
| 1183 | ///\r | |
| 1184 | /// [Bit 2] PROCHOT# Interrupt Enable.\r | |
| 1185 | ///\r | |
| 1186 | UINT32 PROCHOT_Enable:1;\r | |
| 1187 | ///\r | |
| 1188 | /// [Bit 3] FORCEPR# Interrupt Enable.\r | |
| 1189 | ///\r | |
| 1190 | UINT32 FORCEPR_Enable:1;\r | |
| 1191 | ///\r | |
| 1192 | /// [Bit 4] Critical Temperature Interrupt Enable.\r | |
| 1193 | ///\r | |
| 1194 | UINT32 CriticalTempEnable:1;\r | |
| 1195 | UINT32 Reserved1:3;\r | |
| 1196 | ///\r | |
| 1197 | /// [Bits 14:8] Threshold #1 Value.\r | |
| 1198 | ///\r | |
| 1199 | UINT32 Threshold1:7;\r | |
| 1200 | ///\r | |
| 1201 | /// [Bit 15] Threshold #1 Interrupt Enable.\r | |
| 1202 | ///\r | |
| 1203 | UINT32 Threshold1Enable:1;\r | |
| 1204 | ///\r | |
| 1205 | /// [Bits 22:16] Threshold #2 Value.\r | |
| 1206 | ///\r | |
| 1207 | UINT32 Threshold2:7;\r | |
| 1208 | ///\r | |
| 1209 | /// [Bit 23] Threshold #2 Interrupt Enable.\r | |
| 1210 | ///\r | |
| 1211 | UINT32 Threshold2Enable:1;\r | |
| 1212 | ///\r | |
| 1213 | /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.\r | |
| 1214 | ///\r | |
| 1215 | UINT32 PowerLimitNotificationEnable:1;\r | |
| 1216 | UINT32 Reserved2:7;\r | |
| 1217 | UINT32 Reserved3:32;\r | |
| 1218 | } Bits;\r | |
| 1219 | ///\r | |
| 1220 | /// All bit fields as a 32-bit value\r | |
| 1221 | ///\r | |
| 1222 | UINT32 Uint32;\r | |
| 1223 | ///\r | |
| 1224 | /// All bit fields as a 64-bit value\r | |
| 1225 | ///\r | |
| 1226 | UINT64 Uint64;\r | |
| 1227 | } MSR_IA32_THERM_INTERRUPT_REGISTER;\r | |
| 1228 | \r | |
| 1229 | \r | |
| 1230 | /**\r | |
| 1231 | Thermal Status Information (RO) Contains status information about the\r | |
| 1232 | processor's thermal sensor and automatic thermal monitoring facilities. See\r | |
| 1233 | Section 14.7.2, "Thermal Monitor". Introduced at Display Family / Display\r | |
| 1234 | Model 0F_0H.\r | |
| 1235 | \r | |
| 1236 | @param ECX MSR_IA32_THERM_STATUS (0x0000019C)\r | |
| 1237 | @param EAX Lower 32-bits of MSR value.\r | |
| 1238 | Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r | |
| 1239 | @param EDX Upper 32-bits of MSR value.\r | |
| 1240 | Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r | |
| 1241 | \r | |
| 1242 | <b>Example usage</b>\r | |
| 1243 | @code\r | |
| 1244 | MSR_IA32_THERM_STATUS_REGISTER Msr;\r | |
| 1245 | \r | |
| 1246 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);\r | |
| 1247 | @endcode\r | |
| 7de98828 | 1248 | @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.\r |
| 04c980a6 MK |
1249 | **/\r |
| 1250 | #define MSR_IA32_THERM_STATUS 0x0000019C\r | |
| 1251 | \r | |
| 1252 | /**\r | |
| 1253 | MSR information returned for MSR index #MSR_IA32_THERM_STATUS\r | |
| 1254 | **/\r | |
| 1255 | typedef union {\r | |
| 1256 | ///\r | |
| 1257 | /// Individual bit fields\r | |
| 1258 | ///\r | |
| 1259 | struct {\r | |
| 1260 | ///\r | |
| 1261 | /// [Bit 0] Thermal Status (RO):.\r | |
| 1262 | ///\r | |
| 1263 | UINT32 ThermalStatus:1;\r | |
| 1264 | ///\r | |
| 1265 | /// [Bit 1] Thermal Status Log (R/W):.\r | |
| 1266 | ///\r | |
| 1267 | UINT32 ThermalStatusLog:1;\r | |
| 1268 | ///\r | |
| 1269 | /// [Bit 2] PROCHOT # or FORCEPR# event (RO).\r | |
| 1270 | ///\r | |
| 1271 | UINT32 PROCHOT_FORCEPR_Event:1;\r | |
| 1272 | ///\r | |
| 1273 | /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0).\r | |
| 1274 | ///\r | |
| 1275 | UINT32 PROCHOT_FORCEPR_Log:1;\r | |
| 1276 | ///\r | |
| 1277 | /// [Bit 4] Critical Temperature Status (RO).\r | |
| 1278 | ///\r | |
| 1279 | UINT32 CriticalTempStatus:1;\r | |
| 1280 | ///\r | |
| 1281 | /// [Bit 5] Critical Temperature Status log (R/WC0).\r | |
| 1282 | ///\r | |
| 1283 | UINT32 CriticalTempStatusLog:1;\r | |
| 1284 | ///\r | |
| 1285 | /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.\r | |
| 1286 | ///\r | |
| 1287 | UINT32 ThermalThreshold1Status:1;\r | |
| 1288 | ///\r | |
| 1289 | /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r | |
| 1290 | ///\r | |
| 1291 | UINT32 ThermalThreshold1Log:1;\r | |
| 1292 | ///\r | |
| 1293 | /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.\r | |
| 1294 | ///\r | |
| 1295 | UINT32 ThermalThreshold2Status:1;\r | |
| 1296 | ///\r | |
| 1297 | /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r | |
| 1298 | ///\r | |
| 1299 | UINT32 ThermalThreshold2Log:1;\r | |
| 1300 | ///\r | |
| 1301 | /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.\r | |
| 1302 | ///\r | |
| 1303 | UINT32 PowerLimitStatus:1;\r | |
| 1304 | ///\r | |
| 1305 | /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.\r | |
| 1306 | ///\r | |
| 1307 | UINT32 PowerLimitLog:1;\r | |
| 1308 | ///\r | |
| 1309 | /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r | |
| 1310 | ///\r | |
| 1311 | UINT32 CurrentLimitStatus:1;\r | |
| 1312 | ///\r | |
| 1313 | /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r | |
| 1314 | ///\r | |
| 1315 | UINT32 CurrentLimitLog:1;\r | |
| 1316 | ///\r | |
| 1317 | /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r | |
| 1318 | ///\r | |
| 1319 | UINT32 CrossDomainLimitStatus:1;\r | |
| 1320 | ///\r | |
| 1321 | /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r | |
| 1322 | ///\r | |
| 1323 | UINT32 CrossDomainLimitLog:1;\r | |
| 1324 | ///\r | |
| 1325 | /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.\r | |
| 1326 | ///\r | |
| 1327 | UINT32 DigitalReadout:7;\r | |
| 1328 | UINT32 Reserved1:4;\r | |
| 1329 | ///\r | |
| 1330 | /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =\r | |
| 1331 | /// 1.\r | |
| 1332 | ///\r | |
| 1333 | UINT32 ResolutionInDegreesCelsius:4;\r | |
| 1334 | ///\r | |
| 1335 | /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.\r | |
| 1336 | ///\r | |
| 1337 | UINT32 ReadingValid:1;\r | |
| 1338 | UINT32 Reserved2:32;\r | |
| 1339 | } Bits;\r | |
| 1340 | ///\r | |
| 1341 | /// All bit fields as a 32-bit value\r | |
| 1342 | ///\r | |
| 1343 | UINT32 Uint32;\r | |
| 1344 | ///\r | |
| 1345 | /// All bit fields as a 64-bit value\r | |
| 1346 | ///\r | |
| 1347 | UINT64 Uint64;\r | |
| 1348 | } MSR_IA32_THERM_STATUS_REGISTER;\r | |
| 1349 | \r | |
| 1350 | \r | |
| 1351 | /**\r | |
| 1352 | Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
| 1353 | functions to be enabled and disabled.\r | |
| 1354 | \r | |
| 1355 | @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)\r | |
| 1356 | @param EAX Lower 32-bits of MSR value.\r | |
| 1357 | Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r | |
| 1358 | @param EDX Upper 32-bits of MSR value.\r | |
| 1359 | Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r | |
| 1360 | \r | |
| 1361 | <b>Example usage</b>\r | |
| 1362 | @code\r | |
| 1363 | MSR_IA32_MISC_ENABLE_REGISTER Msr;\r | |
| 1364 | \r | |
| 1365 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);\r | |
| 1366 | AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);\r | |
| 1367 | @endcode\r | |
| 7de98828 | 1368 | @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r |
| 04c980a6 MK |
1369 | **/\r |
| 1370 | #define MSR_IA32_MISC_ENABLE 0x000001A0\r | |
| 1371 | \r | |
| 1372 | /**\r | |
| 1373 | MSR information returned for MSR index #MSR_IA32_MISC_ENABLE\r | |
| 1374 | **/\r | |
| 1375 | typedef union {\r | |
| 1376 | ///\r | |
| 1377 | /// Individual bit fields\r | |
| 1378 | ///\r | |
| 1379 | struct {\r | |
| 1380 | ///\r | |
| 1381 | /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for\r | |
| 1382 | /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings\r | |
| 1383 | /// are disabled. Introduced at Display Family / Display Model 0F_0H.\r | |
| 1384 | ///\r | |
| 1385 | UINT32 FastStrings:1;\r | |
| 1386 | UINT32 Reserved1:2;\r | |
| 1387 | ///\r | |
| 1388 | /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting\r | |
| 1389 | /// this bit enables the thermal control circuit (TCC) portion of the\r | |
| 1390 | /// Intel Thermal Monitor feature. This allows the processor to\r | |
| 1391 | /// automatically reduce power consumption in response to TCC activation.\r | |
| 1392 | /// 0 = Disabled. Note: In some products clearing this bit might be\r | |
| 1393 | /// ignored in critical thermal conditions, and TM1, TM2 and adaptive\r | |
| 1394 | /// thermal throttling will still be activated. Introduced at Display\r | |
| 1395 | /// Family / Display Model 0F_0H.\r | |
| 1396 | ///\r | |
| 1397 | UINT32 AutomaticThermalControlCircuit:1;\r | |
| 1398 | UINT32 Reserved2:3;\r | |
| 1399 | ///\r | |
| 1400 | /// [Bit 7] Performance Monitoring Available (R) 1 = Performance\r | |
| 1401 | /// monitoring enabled 0 = Performance monitoring disabled. Introduced at\r | |
| 1402 | /// Display Family / Display Model 0F_0H.\r | |
| 1403 | ///\r | |
| 1404 | UINT32 PerformanceMonitoring:1;\r | |
| 1405 | UINT32 Reserved3:3;\r | |
| 1406 | ///\r | |
| 1407 | /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't\r | |
| 1408 | /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at\r | |
| 1409 | /// Display Family / Display Model 0F_0H.\r | |
| 1410 | ///\r | |
| 1411 | UINT32 BTS:1;\r | |
| 1412 | ///\r | |
| 1413 | /// [Bit 12] Precise Event Based Sampling (PEBS) Unavailable (RO) 1 =\r | |
| 1414 | /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display\r | |
| 1415 | /// Family / Display Model 06_0FH.\r | |
| 1416 | ///\r | |
| 1417 | UINT32 PEBS:1;\r | |
| 1418 | UINT32 Reserved4:3;\r | |
| 1419 | ///\r | |
| 1420 | /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced\r | |
| 1421 | /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep\r | |
| 1422 | /// Technology enabled. If CPUID.01H: ECX[7] =1.\r | |
| 1423 | ///\r | |
| 1424 | UINT32 EIST:1;\r | |
| 1425 | UINT32 Reserved5:1;\r | |
| 1426 | ///\r | |
| 1427 | /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the\r | |
| 1428 | /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This\r | |
| 1429 | /// indicates that MONITOR/MWAIT are not supported. Software attempts to\r | |
| 1430 | /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit\r | |
| 1431 | /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit\r | |
| 1432 | /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit\r | |
| 1433 | /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it\r | |
| 1434 | /// in the default state. Writing this bit when the SSE3 feature flag is\r | |
| 1435 | /// set to 0 may generate a #GP exception. Introduced at Display Family /\r | |
| 1436 | /// Display Model 0F_03H.\r | |
| 1437 | ///\r | |
| 1438 | UINT32 MONITOR:1;\r | |
| 1439 | UINT32 Reserved6:3;\r | |
| 1440 | ///\r | |
| 1441 | /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H\r | |
| 1442 | /// returns a maximum value in EAX[7:0] of 3. BIOS should contain a setup\r | |
| 1443 | /// question that allows users to specify when the installed OS does not\r | |
| 1444 | /// support CPUID functions greater than 3. Before setting this bit, BIOS\r | |
| 1445 | /// must execute the CPUID.0H and examine the maximum value returned in\r | |
| 1446 | /// EAX[7:0]. If the maximum value is greater than 3, the bit is\r | |
| 1447 | /// supported. Otherwise, the bit is not supported. Writing to this bit\r | |
| 1448 | /// when the maximum value is greater than 3 may generate a #GP exception.\r | |
| 1449 | /// Setting this bit may cause unexpected behavior in software that\r | |
| 1450 | /// depends on the availability of CPUID leaves greater than 3. Introduced\r | |
| 1451 | /// at Display Family / Display Model 0F_03H.\r | |
| 1452 | ///\r | |
| 1453 | UINT32 LimitCpuidMaxval:1;\r | |
| 1454 | ///\r | |
| 1455 | /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r | |
| 1456 | /// disabled. xTPR messages are optional messages that allow the processor\r | |
| 1457 | /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.\r | |
| 1458 | ///\r | |
| 1459 | UINT32 xTPR_Message_Disable:1;\r | |
| 1460 | UINT32 Reserved7:8;\r | |
| 1461 | UINT32 Reserved8:2;\r | |
| 1462 | ///\r | |
| 1463 | /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit\r | |
| 1464 | /// feature (XD Bit) is disabled and the XD Bit extended feature flag will\r | |
| 1465 | /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the\r | |
| 1466 | /// Execute Disable Bit feature (if available) allows the OS to enable PAE\r | |
| 1467 | /// paging and take advantage of data only pages. BIOS must not alter the\r | |
| 1468 | /// contents of this bit location, if XD bit is not supported. Writing\r | |
| 1469 | /// this bit to 1 when the XD Bit extended feature flag is set to 0 may\r | |
| 1470 | /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.\r | |
| 1471 | ///\r | |
| 1472 | UINT32 XD:1;\r | |
| 1473 | UINT32 Reserved9:29;\r | |
| 1474 | } Bits;\r | |
| 1475 | ///\r | |
| 1476 | /// All bit fields as a 64-bit value\r | |
| 1477 | ///\r | |
| 1478 | UINT64 Uint64;\r | |
| 1479 | } MSR_IA32_MISC_ENABLE_REGISTER;\r | |
| 1480 | \r | |
| 1481 | \r | |
| 1482 | /**\r | |
| 1483 | Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.\r | |
| 1484 | \r | |
| 1485 | @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)\r | |
| 1486 | @param EAX Lower 32-bits of MSR value.\r | |
| 1487 | Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r | |
| 1488 | @param EDX Upper 32-bits of MSR value.\r | |
| 1489 | Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r | |
| 1490 | \r | |
| 1491 | <b>Example usage</b>\r | |
| 1492 | @code\r | |
| 1493 | MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;\r | |
| 1494 | \r | |
| 1495 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);\r | |
| 1496 | AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);\r | |
| 1497 | @endcode\r | |
| 7de98828 | 1498 | @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r |
| 04c980a6 MK |
1499 | **/\r |
| 1500 | #define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0\r | |
| 1501 | \r | |
| 1502 | /**\r | |
| 1503 | MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS\r | |
| 1504 | **/\r | |
| 1505 | typedef union {\r | |
| 1506 | ///\r | |
| 1507 | /// Individual bit fields\r | |
| 1508 | ///\r | |
| 1509 | struct {\r | |
| 1510 | ///\r | |
| 1511 | /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest\r | |
| 1512 | /// performance. 15 indicates preference to maximize energy saving.\r | |
| 1513 | ///\r | |
| 1514 | UINT32 PowerPolicyPreference:4;\r | |
| 1515 | UINT32 Reserved1:28;\r | |
| 1516 | UINT32 Reserved2:32;\r | |
| 1517 | } Bits;\r | |
| 1518 | ///\r | |
| 1519 | /// All bit fields as a 32-bit value\r | |
| 1520 | ///\r | |
| 1521 | UINT32 Uint32;\r | |
| 1522 | ///\r | |
| 1523 | /// All bit fields as a 64-bit value\r | |
| 1524 | ///\r | |
| 1525 | UINT64 Uint64;\r | |
| 1526 | } MSR_IA32_ENERGY_PERF_BIAS_REGISTER;\r | |
| 1527 | \r | |
| 1528 | \r | |
| 1529 | /**\r | |
| 1530 | Package Thermal Status Information (RO) Contains status information about\r | |
| 1531 | the package's thermal sensor. See Section 14.8, "Package Level Thermal\r | |
| 1532 | Management.". If CPUID.06H: EAX[6] = 1.\r | |
| 1533 | \r | |
| 1534 | @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)\r | |
| 1535 | @param EAX Lower 32-bits of MSR value.\r | |
| 1536 | Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r | |
| 1537 | @param EDX Upper 32-bits of MSR value.\r | |
| 1538 | Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r | |
| 1539 | \r | |
| 1540 | <b>Example usage</b>\r | |
| 1541 | @code\r | |
| 1542 | MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;\r | |
| 1543 | \r | |
| 1544 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);\r | |
| 1545 | @endcode\r | |
| 7de98828 | 1546 | @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.\r |
| 04c980a6 MK |
1547 | **/\r |
| 1548 | #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1\r | |
| 1549 | \r | |
| 1550 | /**\r | |
| 1551 | MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS\r | |
| 1552 | **/\r | |
| 1553 | typedef union {\r | |
| 1554 | ///\r | |
| 1555 | /// Individual bit fields\r | |
| 1556 | ///\r | |
| 1557 | struct {\r | |
| 1558 | ///\r | |
| 1559 | /// [Bit 0] Pkg Thermal Status (RO):.\r | |
| 1560 | ///\r | |
| 1561 | UINT32 ThermalStatus:1;\r | |
| 1562 | ///\r | |
| 1563 | /// [Bit 1] Pkg Thermal Status Log (R/W):.\r | |
| 1564 | ///\r | |
| 1565 | UINT32 ThermalStatusLog:1;\r | |
| 1566 | ///\r | |
| 1567 | /// [Bit 2] Pkg PROCHOT # event (RO).\r | |
| 1568 | ///\r | |
| 1569 | UINT32 PROCHOT_Event:1;\r | |
| 1570 | ///\r | |
| 1571 | /// [Bit 3] Pkg PROCHOT # log (R/WC0).\r | |
| 1572 | ///\r | |
| 1573 | UINT32 PROCHOT_Log:1;\r | |
| 1574 | ///\r | |
| 1575 | /// [Bit 4] Pkg Critical Temperature Status (RO).\r | |
| 1576 | ///\r | |
| 1577 | UINT32 CriticalTempStatus:1;\r | |
| 1578 | ///\r | |
| 1579 | /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).\r | |
| 1580 | ///\r | |
| 1581 | UINT32 CriticalTempStatusLog:1;\r | |
| 1582 | ///\r | |
| 1583 | /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).\r | |
| 1584 | ///\r | |
| 1585 | UINT32 ThermalThreshold1Status:1;\r | |
| 1586 | ///\r | |
| 1587 | /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).\r | |
| 1588 | ///\r | |
| 1589 | UINT32 ThermalThreshold1Log:1;\r | |
| 1590 | ///\r | |
| 1591 | /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).\r | |
| 1592 | ///\r | |
| 1593 | UINT32 ThermalThreshold2Status:1;\r | |
| 1594 | ///\r | |
| 1595 | /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).\r | |
| 1596 | ///\r | |
| 1597 | UINT32 ThermalThreshold2Log:1;\r | |
| 1598 | ///\r | |
| 1599 | /// [Bit 10] Pkg Power Limitation Status (RO).\r | |
| 1600 | ///\r | |
| 1601 | UINT32 PowerLimitStatus:1;\r | |
| 1602 | ///\r | |
| 1603 | /// [Bit 11] Pkg Power Limitation log (R/WC0).\r | |
| 1604 | ///\r | |
| 1605 | UINT32 PowerLimitLog:1;\r | |
| 1606 | UINT32 Reserved1:4;\r | |
| 1607 | ///\r | |
| 1608 | /// [Bits 22:16] Pkg Digital Readout (RO).\r | |
| 1609 | ///\r | |
| 1610 | UINT32 DigitalReadout:7;\r | |
| 1611 | UINT32 Reserved2:9;\r | |
| 1612 | UINT32 Reserved3:32;\r | |
| 1613 | } Bits;\r | |
| 1614 | ///\r | |
| 1615 | /// All bit fields as a 32-bit value\r | |
| 1616 | ///\r | |
| 1617 | UINT32 Uint32;\r | |
| 1618 | ///\r | |
| 1619 | /// All bit fields as a 64-bit value\r | |
| 1620 | ///\r | |
| 1621 | UINT64 Uint64;\r | |
| 1622 | } MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;\r | |
| 1623 | \r | |
| 1624 | \r | |
| 1625 | /**\r | |
| 1626 | Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of\r | |
| 1627 | an interrupt on temperature transitions detected with the package's thermal\r | |
| 1628 | sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:\r | |
| 1629 | EAX[6] = 1.\r | |
| 1630 | \r | |
| 1631 | @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)\r | |
| 1632 | @param EAX Lower 32-bits of MSR value.\r | |
| 1633 | Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r | |
| 1634 | @param EDX Upper 32-bits of MSR value.\r | |
| 1635 | Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r | |
| 1636 | \r | |
| 1637 | <b>Example usage</b>\r | |
| 1638 | @code\r | |
| 1639 | MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;\r | |
| 1640 | \r | |
| 1641 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);\r | |
| 1642 | AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);\r | |
| 1643 | @endcode\r | |
| 7de98828 | 1644 | @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.\r |
| 04c980a6 MK |
1645 | **/\r |
| 1646 | #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2\r | |
| 1647 | \r | |
| 1648 | /**\r | |
| 1649 | MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT\r | |
| 1650 | **/\r | |
| 1651 | typedef union {\r | |
| 1652 | ///\r | |
| 1653 | /// Individual bit fields\r | |
| 1654 | ///\r | |
| 1655 | struct {\r | |
| 1656 | ///\r | |
| 1657 | /// [Bit 0] Pkg High-Temperature Interrupt Enable.\r | |
| 1658 | ///\r | |
| 1659 | UINT32 HighTempEnable:1;\r | |
| 1660 | ///\r | |
| 1661 | /// [Bit 1] Pkg Low-Temperature Interrupt Enable.\r | |
| 1662 | ///\r | |
| 1663 | UINT32 LowTempEnable:1;\r | |
| 1664 | ///\r | |
| 1665 | /// [Bit 2] Pkg PROCHOT# Interrupt Enable.\r | |
| 1666 | ///\r | |
| 1667 | UINT32 PROCHOT_Enable:1;\r | |
| 1668 | UINT32 Reserved1:1;\r | |
| 1669 | ///\r | |
| 1670 | /// [Bit 4] Pkg Overheat Interrupt Enable.\r | |
| 1671 | ///\r | |
| 1672 | UINT32 OverheatEnable:1;\r | |
| 1673 | UINT32 Reserved2:3;\r | |
| 1674 | ///\r | |
| 1675 | /// [Bits 14:8] Pkg Threshold #1 Value.\r | |
| 1676 | ///\r | |
| 1677 | UINT32 Threshold1:7;\r | |
| 1678 | ///\r | |
| 1679 | /// [Bit 15] Pkg Threshold #1 Interrupt Enable.\r | |
| 1680 | ///\r | |
| 1681 | UINT32 Threshold1Enable:1;\r | |
| 1682 | ///\r | |
| 1683 | /// [Bits 22:16] Pkg Threshold #2 Value.\r | |
| 1684 | ///\r | |
| 1685 | UINT32 Threshold2:7;\r | |
| 1686 | ///\r | |
| 1687 | /// [Bit 23] Pkg Threshold #2 Interrupt Enable.\r | |
| 1688 | ///\r | |
| 1689 | UINT32 Threshold2Enable:1;\r | |
| 1690 | ///\r | |
| 1691 | /// [Bit 24] Pkg Power Limit Notification Enable.\r | |
| 1692 | ///\r | |
| 1693 | UINT32 PowerLimitNotificationEnable:1;\r | |
| 1694 | UINT32 Reserved3:7;\r | |
| 1695 | UINT32 Reserved4:32;\r | |
| 1696 | } Bits;\r | |
| 1697 | ///\r | |
| 1698 | /// All bit fields as a 32-bit value\r | |
| 1699 | ///\r | |
| 1700 | UINT32 Uint32;\r | |
| 1701 | ///\r | |
| 1702 | /// All bit fields as a 64-bit value\r | |
| 1703 | ///\r | |
| 1704 | UINT64 Uint64;\r | |
| 1705 | } MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;\r | |
| 1706 | \r | |
| 1707 | \r | |
| 1708 | /**\r | |
| 1709 | Trace/Profile Resource Control (R/W). Introduced at Display Family / Display\r | |
| 1710 | Model 06_0EH.\r | |
| 1711 | \r | |
| 1712 | @param ECX MSR_IA32_DEBUGCTL (0x000001D9)\r | |
| 1713 | @param EAX Lower 32-bits of MSR value.\r | |
| 1714 | Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r | |
| 1715 | @param EDX Upper 32-bits of MSR value.\r | |
| 1716 | Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r | |
| 1717 | \r | |
| 1718 | <b>Example usage</b>\r | |
| 1719 | @code\r | |
| 1720 | MSR_IA32_DEBUGCTL_REGISTER Msr;\r | |
| 1721 | \r | |
| 1722 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);\r | |
| 1723 | AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);\r | |
| 1724 | @endcode\r | |
| 7de98828 | 1725 | @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.\r |
| 04c980a6 MK |
1726 | **/\r |
| 1727 | #define MSR_IA32_DEBUGCTL 0x000001D9\r | |
| 1728 | \r | |
| 1729 | /**\r | |
| 1730 | MSR information returned for MSR index #MSR_IA32_DEBUGCTL\r | |
| 1731 | **/\r | |
| 1732 | typedef union {\r | |
| 1733 | ///\r | |
| 1734 | /// Individual bit fields\r | |
| 1735 | ///\r | |
| 1736 | struct {\r | |
| 1737 | ///\r | |
| 1738 | /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a\r | |
| 1739 | /// running trace of the most recent branches taken by the processor in\r | |
| 1740 | /// the LBR stack. Introduced at Display Family / Display Model 06_01H.\r | |
| 1741 | ///\r | |
| 1742 | UINT32 LBR:1;\r | |
| 1743 | ///\r | |
| 1744 | /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat\r | |
| 1745 | /// EFLAGS.TF as single-step on branches instead of single-step on\r | |
| 1746 | /// instructions. Introduced at Display Family / Display Model 06_01H.\r | |
| 1747 | ///\r | |
| 1748 | UINT32 BTF:1;\r | |
| 1749 | UINT32 Reserved1:4;\r | |
| 1750 | ///\r | |
| 1751 | /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be\r | |
| 1752 | /// sent. Introduced at Display Family / Display Model 06_0EH.\r | |
| 1753 | ///\r | |
| 1754 | UINT32 TR:1;\r | |
| 1755 | ///\r | |
| 1756 | /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to\r | |
| 1757 | /// be logged in a BTS buffer. Introduced at Display Family / Display\r | |
| 1758 | /// Model 06_0EH.\r | |
| 1759 | ///\r | |
| 1760 | UINT32 BTS:1;\r | |
| 1761 | ///\r | |
| 1762 | /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular\r | |
| 1763 | /// fashion. When this bit is set, an interrupt is generated by the BTS\r | |
| 1764 | /// facility when the BTS buffer is full. Introduced at Display Family /\r | |
| 1765 | /// Display Model 06_0EH.\r | |
| 1766 | ///\r | |
| 1767 | UINT32 BTINT:1;\r | |
| 1768 | ///\r | |
| 1769 | /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.\r | |
| 1770 | /// Introduced at Display Family / Display Model 06_0FH.\r | |
| 1771 | ///\r | |
| 1772 | UINT32 BTS_OFF_OS:1;\r | |
| 1773 | ///\r | |
| 1774 | /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.\r | |
| 1775 | /// Introduced at Display Family / Display Model 06_0FH.\r | |
| 1776 | ///\r | |
| 1777 | UINT32 BTS_OFF_USR:1;\r | |
| 1778 | ///\r | |
| 1779 | /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a\r | |
| 1780 | /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r | |
| 1781 | ///\r | |
| 1782 | UINT32 FREEZE_LBRS_ON_PMI:1;\r | |
| 1783 | ///\r | |
| 1784 | /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the\r | |
| 1785 | /// global counter control MSR are frozen (address 38FH) on a PMI request.\r | |
| 1786 | /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r | |
| 1787 | ///\r | |
| 1788 | UINT32 FREEZE_PERFMON_ON_PMI:1;\r | |
| 1789 | ///\r | |
| 1790 | /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to\r | |
| 1791 | /// receive and generate PMI on behalf of the uncore. Introduced at\r | |
| 1792 | /// Display Family / Display Model 06_1AH.\r | |
| 1793 | ///\r | |
| 1794 | UINT32 ENABLE_UNCORE_PMI:1;\r | |
| 1795 | ///\r | |
| 1796 | /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace\r | |
| 1797 | /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.\r | |
| 1798 | ///\r | |
| 1799 | UINT32 FREEZE_WHILE_SMM:1;\r | |
| 1800 | ///\r | |
| 1801 | /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If\r | |
| 1802 | /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).\r | |
| 1803 | ///\r | |
| 1804 | UINT32 RTM_DEBUG:1;\r | |
| 1805 | UINT32 Reserved2:16;\r | |
| 1806 | UINT32 Reserved3:32;\r | |
| 1807 | } Bits;\r | |
| 1808 | ///\r | |
| 1809 | /// All bit fields as a 32-bit value\r | |
| 1810 | ///\r | |
| 1811 | UINT32 Uint32;\r | |
| 1812 | ///\r | |
| 1813 | /// All bit fields as a 64-bit value\r | |
| 1814 | ///\r | |
| 1815 | UINT64 Uint64;\r | |
| 1816 | } MSR_IA32_DEBUGCTL_REGISTER;\r | |
| 1817 | \r | |
| 1818 | \r | |
| 1819 | /**\r | |
| 1820 | SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.\r | |
| 1821 | If IA32_MTRRCAP.SMRR[11] = 1.\r | |
| 1822 | \r | |
| 1823 | @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)\r | |
| 1824 | @param EAX Lower 32-bits of MSR value.\r | |
| 1825 | Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r | |
| 1826 | @param EDX Upper 32-bits of MSR value.\r | |
| 1827 | Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r | |
| 1828 | \r | |
| 1829 | <b>Example usage</b>\r | |
| 1830 | @code\r | |
| 1831 | MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;\r | |
| 1832 | \r | |
| 1833 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);\r | |
| 1834 | AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);\r | |
| 1835 | @endcode\r | |
| 7de98828 | 1836 | @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.\r |
| 04c980a6 MK |
1837 | **/\r |
| 1838 | #define MSR_IA32_SMRR_PHYSBASE 0x000001F2\r | |
| 1839 | \r | |
| 1840 | /**\r | |
| 1841 | MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE\r | |
| 1842 | **/\r | |
| 1843 | typedef union {\r | |
| 1844 | ///\r | |
| 1845 | /// Individual bit fields\r | |
| 1846 | ///\r | |
| 1847 | struct {\r | |
| 1848 | ///\r | |
| 1849 | /// [Bits 7:0] Type. Specifies memory type of the range.\r | |
| 1850 | ///\r | |
| 1851 | UINT32 Type:8;\r | |
| 1852 | UINT32 Reserved1:4;\r | |
| 1853 | ///\r | |
| 1854 | /// [Bits 31:12] PhysBase. SMRR physical Base Address.\r | |
| 1855 | ///\r | |
| 1856 | UINT32 PhysBase:20;\r | |
| 1857 | UINT32 Reserved2:32;\r | |
| 1858 | } Bits;\r | |
| 1859 | ///\r | |
| 1860 | /// All bit fields as a 32-bit value\r | |
| 1861 | ///\r | |
| 1862 | UINT32 Uint32;\r | |
| 1863 | ///\r | |
| 1864 | /// All bit fields as a 64-bit value\r | |
| 1865 | ///\r | |
| 1866 | UINT64 Uint64;\r | |
| 1867 | } MSR_IA32_SMRR_PHYSBASE_REGISTER;\r | |
| 1868 | \r | |
| 1869 | \r | |
| 1870 | /**\r | |
| 1871 | SMRR Range Mask. (Writeable only in SMM) Range Mask of SMM memory range. If\r | |
| 1872 | IA32_MTRRCAP[SMRR] = 1.\r | |
| 1873 | \r | |
| 1874 | @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)\r | |
| 1875 | @param EAX Lower 32-bits of MSR value.\r | |
| 1876 | Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r | |
| 1877 | @param EDX Upper 32-bits of MSR value.\r | |
| 1878 | Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r | |
| 1879 | \r | |
| 1880 | <b>Example usage</b>\r | |
| 1881 | @code\r | |
| 1882 | MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;\r | |
| 1883 | \r | |
| 1884 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);\r | |
| 1885 | AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);\r | |
| 1886 | @endcode\r | |
| 7de98828 | 1887 | @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.\r |
| 04c980a6 MK |
1888 | **/\r |
| 1889 | #define MSR_IA32_SMRR_PHYSMASK 0x000001F3\r | |
| 1890 | \r | |
| 1891 | /**\r | |
| 1892 | MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK\r | |
| 1893 | **/\r | |
| 1894 | typedef union {\r | |
| 1895 | ///\r | |
| 1896 | /// Individual bit fields\r | |
| 1897 | ///\r | |
| 1898 | struct {\r | |
| 1899 | UINT32 Reserved1:11;\r | |
| 1900 | ///\r | |
| 1901 | /// [Bit 11] Valid Enable range mask.\r | |
| 1902 | ///\r | |
| 1903 | UINT32 Valid:1;\r | |
| 1904 | ///\r | |
| 1905 | /// [Bits 31:12] PhysMask SMRR address range mask.\r | |
| 1906 | ///\r | |
| 1907 | UINT32 PhysMask:20;\r | |
| 1908 | UINT32 Reserved2:32;\r | |
| 1909 | } Bits;\r | |
| 1910 | ///\r | |
| 1911 | /// All bit fields as a 32-bit value\r | |
| 1912 | ///\r | |
| 1913 | UINT32 Uint32;\r | |
| 1914 | ///\r | |
| 1915 | /// All bit fields as a 64-bit value\r | |
| 1916 | ///\r | |
| 1917 | UINT64 Uint64;\r | |
| 1918 | } MSR_IA32_SMRR_PHYSMASK_REGISTER;\r | |
| 1919 | \r | |
| 1920 | \r | |
| 1921 | /**\r | |
| 1922 | DCA Capability (R). If CPUID.01H: ECX[18] = 1.\r | |
| 1923 | \r | |
| 1924 | @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)\r | |
| 1925 | @param EAX Lower 32-bits of MSR value.\r | |
| 1926 | @param EDX Upper 32-bits of MSR value.\r | |
| 1927 | \r | |
| 1928 | <b>Example usage</b>\r | |
| 1929 | @code\r | |
| 1930 | UINT64 Msr;\r | |
| 1931 | \r | |
| 1932 | Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);\r | |
| 1933 | @endcode\r | |
| 7de98828 | 1934 | @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.\r |
| 04c980a6 MK |
1935 | **/\r |
| 1936 | #define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8\r | |
| 1937 | \r | |
| 1938 | \r | |
| 1939 | /**\r | |
| 1940 | If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.\r | |
| 1941 | \r | |
| 1942 | @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)\r | |
| 1943 | @param EAX Lower 32-bits of MSR value.\r | |
| 1944 | @param EDX Upper 32-bits of MSR value.\r | |
| 1945 | \r | |
| 1946 | <b>Example usage</b>\r | |
| 1947 | @code\r | |
| 1948 | UINT64 Msr;\r | |
| 1949 | \r | |
| 1950 | Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);\r | |
| 1951 | AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);\r | |
| 1952 | @endcode\r | |
| 7de98828 | 1953 | @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.\r |
| 04c980a6 MK |
1954 | **/\r |
| 1955 | #define MSR_IA32_CPU_DCA_CAP 0x000001F9\r | |
| 1956 | \r | |
| 1957 | \r | |
| 1958 | /**\r | |
| 1959 | DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.\r | |
| 1960 | \r | |
| 1961 | @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)\r | |
| 1962 | @param EAX Lower 32-bits of MSR value.\r | |
| 1963 | Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r | |
| 1964 | @param EDX Upper 32-bits of MSR value.\r | |
| 1965 | Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r | |
| 1966 | \r | |
| 1967 | <b>Example usage</b>\r | |
| 1968 | @code\r | |
| 1969 | MSR_IA32_DCA_0_CAP_REGISTER Msr;\r | |
| 1970 | \r | |
| 1971 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);\r | |
| 1972 | AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);\r | |
| 1973 | @endcode\r | |
| 7de98828 | 1974 | @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.\r |
| 04c980a6 MK |
1975 | **/\r |
| 1976 | #define MSR_IA32_DCA_0_CAP 0x000001FA\r | |
| 1977 | \r | |
| 1978 | /**\r | |
| 1979 | MSR information returned for MSR index #MSR_IA32_DCA_0_CAP\r | |
| 1980 | **/\r | |
| 1981 | typedef union {\r | |
| 1982 | ///\r | |
| 1983 | /// Individual bit fields\r | |
| 1984 | ///\r | |
| 1985 | struct {\r | |
| 1986 | ///\r | |
| 1987 | /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no\r | |
| 1988 | /// defeatures are set.\r | |
| 1989 | ///\r | |
| 1990 | UINT32 DCA_ACTIVE:1;\r | |
| 1991 | ///\r | |
| 1992 | /// [Bits 2:1] TRANSACTION.\r | |
| 1993 | ///\r | |
| 1994 | UINT32 TRANSACTION:2;\r | |
| 1995 | ///\r | |
| 1996 | /// [Bits 6:3] DCA_TYPE.\r | |
| 1997 | ///\r | |
| 1998 | UINT32 DCA_TYPE:4;\r | |
| 1999 | ///\r | |
| 2000 | /// [Bits 10:7] DCA_QUEUE_SIZE.\r | |
| 2001 | ///\r | |
| 2002 | UINT32 DCA_QUEUE_SIZE:4;\r | |
| 2003 | UINT32 Reserved1:2;\r | |
| 2004 | ///\r | |
| 2005 | /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW\r | |
| 2006 | /// side-effect.\r | |
| 2007 | ///\r | |
| 2008 | UINT32 DCA_DELAY:4;\r | |
| 2009 | UINT32 Reserved2:7;\r | |
| 2010 | ///\r | |
| 2011 | /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.\r | |
| 2012 | ///\r | |
| 2013 | UINT32 SW_BLOCK:1;\r | |
| 2014 | UINT32 Reserved3:1;\r | |
| 2015 | ///\r | |
| 2016 | /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).\r | |
| 2017 | ///\r | |
| 2018 | UINT32 HW_BLOCK:1;\r | |
| 2019 | UINT32 Reserved4:5;\r | |
| 2020 | UINT32 Reserved5:32;\r | |
| 2021 | } Bits;\r | |
| 2022 | ///\r | |
| 2023 | /// All bit fields as a 32-bit value\r | |
| 2024 | ///\r | |
| 2025 | UINT32 Uint32;\r | |
| 2026 | ///\r | |
| 2027 | /// All bit fields as a 64-bit value\r | |
| 2028 | ///\r | |
| 2029 | UINT64 Uint64;\r | |
| 2030 | } MSR_IA32_DCA_0_CAP_REGISTER;\r | |
| 2031 | \r | |
| 2032 | \r | |
| 2033 | /**\r | |
| 2034 | MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".\r | |
| 2035 | If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r | |
| 2036 | \r | |
| 2037 | @param ECX MSR_IA32_MTRR_PHYSBASEn\r | |
| 2038 | @param EAX Lower 32-bits of MSR value.\r | |
| 2039 | Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r | |
| 2040 | @param EDX Upper 32-bits of MSR value.\r | |
| 2041 | Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r | |
| 2042 | \r | |
| 2043 | <b>Example usage</b>\r | |
| 2044 | @code\r | |
| 2045 | MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;\r | |
| 2046 | \r | |
| 2047 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);\r | |
| 2048 | AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);\r | |
| 2049 | @endcode\r | |
| 7de98828 JF |
2050 | @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.\r |
| 2051 | MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.\r | |
| 2052 | MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.\r | |
| 2053 | MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.\r | |
| 2054 | MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.\r | |
| 2055 | MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.\r | |
| 2056 | MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.\r | |
| 2057 | MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.\r | |
| 2058 | MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.\r | |
| 2059 | MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.\r | |
| 04c980a6 MK |
2060 | @{\r |
| 2061 | **/\r | |
| 2062 | #define MSR_IA32_MTRR_PHYSBASE0 0x00000200\r | |
| 2063 | #define MSR_IA32_MTRR_PHYSBASE1 0x00000202\r | |
| 2064 | #define MSR_IA32_MTRR_PHYSBASE2 0x00000204\r | |
| 2065 | #define MSR_IA32_MTRR_PHYSBASE3 0x00000206\r | |
| 2066 | #define MSR_IA32_MTRR_PHYSBASE4 0x00000208\r | |
| 2067 | #define MSR_IA32_MTRR_PHYSBASE5 0x0000020A\r | |
| 2068 | #define MSR_IA32_MTRR_PHYSBASE6 0x0000020C\r | |
| 2069 | #define MSR_IA32_MTRR_PHYSBASE7 0x0000020E\r | |
| 2070 | #define MSR_IA32_MTRR_PHYSBASE8 0x00000210\r | |
| 2071 | #define MSR_IA32_MTRR_PHYSBASE9 0x00000212\r | |
| 2072 | /// @}\r | |
| 2073 | \r | |
| 2074 | /**\r | |
| 2075 | MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to\r | |
| 2076 | #MSR_IA32_MTRR_PHYSBASE9\r | |
| 2077 | **/\r | |
| 2078 | typedef union {\r | |
| 2079 | ///\r | |
| 2080 | /// Individual bit fields\r | |
| 2081 | ///\r | |
| 2082 | struct {\r | |
| 2083 | ///\r | |
| 2084 | /// [Bits 7:0] Type. Specifies memory type of the range.\r | |
| 2085 | ///\r | |
| 2086 | UINT32 Type:8;\r | |
| 2087 | UINT32 Reserved1:4;\r | |
| 2088 | ///\r | |
| 2089 | /// [Bits 31:12] PhysBase. MTRR physical Base Address.\r | |
| 2090 | ///\r | |
| 2091 | UINT32 PhysBase:20;\r | |
| 2092 | ///\r | |
| 2093 | /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.\r | |
| 2094 | /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r | |
| 2095 | /// maximum physical address range supported by the processor. It is\r | |
| 2096 | /// reported by CPUID leaf function 80000008H. If CPUID does not support\r | |
| 2097 | /// leaf 80000008H, the processor supports 36-bit physical address size,\r | |
| 2098 | /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r | |
| 2099 | ///\r | |
| 2100 | UINT32 PhysBaseHi:32;\r | |
| 2101 | } Bits;\r | |
| 2102 | ///\r | |
| 2103 | /// All bit fields as a 64-bit value\r | |
| 2104 | ///\r | |
| 2105 | UINT64 Uint64;\r | |
| 2106 | } MSR_IA32_MTRR_PHYSBASE_REGISTER;\r | |
| 2107 | \r | |
| 2108 | \r | |
| 2109 | /**\r | |
| 2110 | MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".\r | |
| 2111 | If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r | |
| 2112 | \r | |
| 2113 | @param ECX MSR_IA32_MTRR_PHYSMASKn\r | |
| 2114 | @param EAX Lower 32-bits of MSR value.\r | |
| 2115 | Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r | |
| 2116 | @param EDX Upper 32-bits of MSR value.\r | |
| 2117 | Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r | |
| 2118 | \r | |
| 2119 | <b>Example usage</b>\r | |
| 2120 | @code\r | |
| 2121 | MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;\r | |
| 2122 | \r | |
| 2123 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);\r | |
| 2124 | AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);\r | |
| 2125 | @endcode\r | |
| 7de98828 JF |
2126 | @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.\r |
| 2127 | MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.\r | |
| 2128 | MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.\r | |
| 2129 | MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.\r | |
| 2130 | MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.\r | |
| 2131 | MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.\r | |
| 2132 | MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.\r | |
| 2133 | MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.\r | |
| 2134 | MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.\r | |
| 2135 | MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.\r | |
| 04c980a6 MK |
2136 | @{\r |
| 2137 | **/\r | |
| 2138 | #define MSR_IA32_MTRR_PHYSMASK0 0x00000201\r | |
| 2139 | #define MSR_IA32_MTRR_PHYSMASK1 0x00000203\r | |
| 2140 | #define MSR_IA32_MTRR_PHYSMASK2 0x00000205\r | |
| 2141 | #define MSR_IA32_MTRR_PHYSMASK3 0x00000207\r | |
| 2142 | #define MSR_IA32_MTRR_PHYSMASK4 0x00000209\r | |
| 2143 | #define MSR_IA32_MTRR_PHYSMASK5 0x0000020B\r | |
| 2144 | #define MSR_IA32_MTRR_PHYSMASK6 0x0000020D\r | |
| 2145 | #define MSR_IA32_MTRR_PHYSMASK7 0x0000020F\r | |
| 2146 | #define MSR_IA32_MTRR_PHYSMASK8 0x00000211\r | |
| 2147 | #define MSR_IA32_MTRR_PHYSMASK9 0x00000213\r | |
| 2148 | /// @}\r | |
| 2149 | \r | |
| 2150 | /**\r | |
| 2151 | MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to\r | |
| 2152 | #MSR_IA32_MTRR_PHYSMASK9\r | |
| 2153 | **/\r | |
| 2154 | typedef union {\r | |
| 2155 | ///\r | |
| 2156 | /// Individual bit fields\r | |
| 2157 | ///\r | |
| 2158 | struct {\r | |
| 2159 | UINT32 Reserved1:11;\r | |
| 2160 | ///\r | |
| 2161 | /// [Bit 11] Valid Enable range mask.\r | |
| 2162 | ///\r | |
| 490b048b | 2163 | UINT32 V:1;\r |
| 04c980a6 MK |
2164 | ///\r |
| 2165 | /// [Bits 31:12] PhysMask. MTRR address range mask.\r | |
| 2166 | ///\r | |
| 2167 | UINT32 PhysMask:20;\r | |
| 2168 | ///\r | |
| 2169 | /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.\r | |
| 2170 | /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r | |
| 2171 | /// maximum physical address range supported by the processor. It is\r | |
| 2172 | /// reported by CPUID leaf function 80000008H. If CPUID does not support\r | |
| 2173 | /// leaf 80000008H, the processor supports 36-bit physical address size,\r | |
| 2174 | /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r | |
| 2175 | ///\r | |
| 2176 | UINT32 PhysMaskHi:32;\r | |
| 2177 | } Bits;\r | |
| 2178 | ///\r | |
| 2179 | /// All bit fields as a 64-bit value\r | |
| 2180 | ///\r | |
| 2181 | UINT64 Uint64;\r | |
| 2182 | } MSR_IA32_MTRR_PHYSMASK_REGISTER;\r | |
| 2183 | \r | |
| 2184 | \r | |
| 2185 | /**\r | |
| 2186 | MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2187 | \r | |
| 2188 | @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)\r | |
| 2189 | @param EAX Lower 32-bits of MSR value.\r | |
| 2190 | @param EDX Upper 32-bits of MSR value.\r | |
| 2191 | \r | |
| 2192 | <b>Example usage</b>\r | |
| 2193 | @code\r | |
| 2194 | UINT64 Msr;\r | |
| 2195 | \r | |
| 2196 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);\r | |
| 2197 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);\r | |
| 2198 | @endcode\r | |
| 7de98828 | 2199 | @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.\r |
| 04c980a6 MK |
2200 | **/\r |
| 2201 | #define MSR_IA32_MTRR_FIX64K_00000 0x00000250\r | |
| 2202 | \r | |
| 2203 | \r | |
| 2204 | /**\r | |
| 2205 | MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2206 | \r | |
| 2207 | @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)\r | |
| 2208 | @param EAX Lower 32-bits of MSR value.\r | |
| 2209 | @param EDX Upper 32-bits of MSR value.\r | |
| 2210 | \r | |
| 2211 | <b>Example usage</b>\r | |
| 2212 | @code\r | |
| 2213 | UINT64 Msr;\r | |
| 2214 | \r | |
| 2215 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);\r | |
| 2216 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);\r | |
| 2217 | @endcode\r | |
| 7de98828 | 2218 | @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.\r |
| 04c980a6 MK |
2219 | **/\r |
| 2220 | #define MSR_IA32_MTRR_FIX16K_80000 0x00000258\r | |
| 2221 | \r | |
| 2222 | \r | |
| 2223 | /**\r | |
| 2224 | MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2225 | \r | |
| 2226 | @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)\r | |
| 2227 | @param EAX Lower 32-bits of MSR value.\r | |
| 2228 | @param EDX Upper 32-bits of MSR value.\r | |
| 2229 | \r | |
| 2230 | <b>Example usage</b>\r | |
| 2231 | @code\r | |
| 2232 | UINT64 Msr;\r | |
| 2233 | \r | |
| 2234 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);\r | |
| 2235 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);\r | |
| 2236 | @endcode\r | |
| 7de98828 | 2237 | @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.\r |
| 04c980a6 MK |
2238 | **/\r |
| 2239 | #define MSR_IA32_MTRR_FIX16K_A0000 0x00000259\r | |
| 2240 | \r | |
| 2241 | \r | |
| 2242 | /**\r | |
| 2243 | See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2244 | \r | |
| 2245 | @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)\r | |
| 2246 | @param EAX Lower 32-bits of MSR value.\r | |
| 2247 | @param EDX Upper 32-bits of MSR value.\r | |
| 2248 | \r | |
| 2249 | <b>Example usage</b>\r | |
| 2250 | @code\r | |
| 2251 | UINT64 Msr;\r | |
| 2252 | \r | |
| 2253 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);\r | |
| 2254 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);\r | |
| 2255 | @endcode\r | |
| 7de98828 | 2256 | @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.\r |
| 04c980a6 MK |
2257 | **/\r |
| 2258 | #define MSR_IA32_MTRR_FIX4K_C0000 0x00000268\r | |
| 2259 | \r | |
| 2260 | \r | |
| 2261 | /**\r | |
| 2262 | MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2263 | \r | |
| 2264 | @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)\r | |
| 2265 | @param EAX Lower 32-bits of MSR value.\r | |
| 2266 | @param EDX Upper 32-bits of MSR value.\r | |
| 2267 | \r | |
| 2268 | <b>Example usage</b>\r | |
| 2269 | @code\r | |
| 2270 | UINT64 Msr;\r | |
| 2271 | \r | |
| 2272 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);\r | |
| 2273 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);\r | |
| 2274 | @endcode\r | |
| 7de98828 | 2275 | @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.\r |
| 04c980a6 MK |
2276 | **/\r |
| 2277 | #define MSR_IA32_MTRR_FIX4K_C8000 0x00000269\r | |
| 2278 | \r | |
| 2279 | \r | |
| 2280 | /**\r | |
| 2281 | MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2282 | \r | |
| 2283 | @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)\r | |
| 2284 | @param EAX Lower 32-bits of MSR value.\r | |
| 2285 | @param EDX Upper 32-bits of MSR value.\r | |
| 2286 | \r | |
| 2287 | <b>Example usage</b>\r | |
| 2288 | @code\r | |
| 2289 | UINT64 Msr;\r | |
| 2290 | \r | |
| 2291 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);\r | |
| 2292 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);\r | |
| 2293 | @endcode\r | |
| 7de98828 | 2294 | @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.\r |
| 04c980a6 MK |
2295 | **/\r |
| 2296 | #define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A\r | |
| 2297 | \r | |
| 2298 | \r | |
| 2299 | /**\r | |
| 2300 | MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2301 | \r | |
| 2302 | @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)\r | |
| 2303 | @param EAX Lower 32-bits of MSR value.\r | |
| 2304 | @param EDX Upper 32-bits of MSR value.\r | |
| 2305 | \r | |
| 2306 | <b>Example usage</b>\r | |
| 2307 | @code\r | |
| 2308 | UINT64 Msr;\r | |
| 2309 | \r | |
| 2310 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);\r | |
| 2311 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);\r | |
| 2312 | @endcode\r | |
| 7de98828 | 2313 | @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.\r |
| 04c980a6 MK |
2314 | **/\r |
| 2315 | #define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B\r | |
| 2316 | \r | |
| 2317 | \r | |
| 2318 | /**\r | |
| 2319 | MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2320 | \r | |
| 2321 | @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)\r | |
| 2322 | @param EAX Lower 32-bits of MSR value.\r | |
| 2323 | @param EDX Upper 32-bits of MSR value.\r | |
| 2324 | \r | |
| 2325 | <b>Example usage</b>\r | |
| 2326 | @code\r | |
| 2327 | UINT64 Msr;\r | |
| 2328 | \r | |
| 2329 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);\r | |
| 2330 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);\r | |
| 2331 | @endcode\r | |
| 7de98828 | 2332 | @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.\r |
| 04c980a6 MK |
2333 | **/\r |
| 2334 | #define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C\r | |
| 2335 | \r | |
| 2336 | \r | |
| 2337 | /**\r | |
| 2338 | MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2339 | \r | |
| 2340 | @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)\r | |
| 2341 | @param EAX Lower 32-bits of MSR value.\r | |
| 2342 | @param EDX Upper 32-bits of MSR value.\r | |
| 2343 | \r | |
| 2344 | <b>Example usage</b>\r | |
| 2345 | @code\r | |
| 2346 | UINT64 Msr;\r | |
| 2347 | \r | |
| 2348 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);\r | |
| 2349 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);\r | |
| 2350 | @endcode\r | |
| 7de98828 | 2351 | @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.\r |
| 04c980a6 MK |
2352 | **/\r |
| 2353 | #define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D\r | |
| 2354 | \r | |
| 2355 | \r | |
| 2356 | /**\r | |
| 2357 | MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2358 | \r | |
| 2359 | @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)\r | |
| 2360 | @param EAX Lower 32-bits of MSR value.\r | |
| 2361 | @param EDX Upper 32-bits of MSR value.\r | |
| 2362 | \r | |
| 2363 | <b>Example usage</b>\r | |
| 2364 | @code\r | |
| 2365 | UINT64 Msr;\r | |
| 2366 | \r | |
| 2367 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);\r | |
| 2368 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);\r | |
| 2369 | @endcode\r | |
| 7de98828 | 2370 | @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.\r |
| 04c980a6 MK |
2371 | **/\r |
| 2372 | #define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E\r | |
| 2373 | \r | |
| 2374 | \r | |
| 2375 | /**\r | |
| 2376 | MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2377 | \r | |
| 2378 | @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)\r | |
| 2379 | @param EAX Lower 32-bits of MSR value.\r | |
| 2380 | @param EDX Upper 32-bits of MSR value.\r | |
| 2381 | \r | |
| 2382 | <b>Example usage</b>\r | |
| 2383 | @code\r | |
| 2384 | UINT64 Msr;\r | |
| 2385 | \r | |
| 2386 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);\r | |
| 2387 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);\r | |
| 2388 | @endcode\r | |
| 7de98828 | 2389 | @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.\r |
| 04c980a6 MK |
2390 | **/\r |
| 2391 | #define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F\r | |
| 2392 | \r | |
| 2393 | \r | |
| 2394 | /**\r | |
| 2395 | IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.\r | |
| 2396 | \r | |
| 2397 | @param ECX MSR_IA32_PAT (0x00000277)\r | |
| 2398 | @param EAX Lower 32-bits of MSR value.\r | |
| 2399 | Described by the type MSR_IA32_PAT_REGISTER.\r | |
| 2400 | @param EDX Upper 32-bits of MSR value.\r | |
| 2401 | Described by the type MSR_IA32_PAT_REGISTER.\r | |
| 2402 | \r | |
| 2403 | <b>Example usage</b>\r | |
| 2404 | @code\r | |
| 2405 | MSR_IA32_PAT_REGISTER Msr;\r | |
| 2406 | \r | |
| 2407 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);\r | |
| 2408 | AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);\r | |
| 2409 | @endcode\r | |
| 7de98828 | 2410 | @note MSR_IA32_PAT is defined as IA32_PAT in SDM.\r |
| 04c980a6 MK |
2411 | **/\r |
| 2412 | #define MSR_IA32_PAT 0x00000277\r | |
| 2413 | \r | |
| 2414 | /**\r | |
| 2415 | MSR information returned for MSR index #MSR_IA32_PAT\r | |
| 2416 | **/\r | |
| 2417 | typedef union {\r | |
| 2418 | ///\r | |
| 2419 | /// Individual bit fields\r | |
| 2420 | ///\r | |
| 2421 | struct {\r | |
| 2422 | ///\r | |
| 2423 | /// [Bits 2:0] PA0.\r | |
| 2424 | ///\r | |
| 2425 | UINT32 PA0:3;\r | |
| 2426 | UINT32 Reserved1:5;\r | |
| 2427 | ///\r | |
| 2428 | /// [Bits 10:8] PA1.\r | |
| 2429 | ///\r | |
| 2430 | UINT32 PA1:3;\r | |
| 2431 | UINT32 Reserved2:5;\r | |
| 2432 | ///\r | |
| 2433 | /// [Bits 18:16] PA2.\r | |
| 2434 | ///\r | |
| 2435 | UINT32 PA2:3;\r | |
| 2436 | UINT32 Reserved3:5;\r | |
| 2437 | ///\r | |
| 2438 | /// [Bits 26:24] PA3.\r | |
| 2439 | ///\r | |
| 2440 | UINT32 PA3:3;\r | |
| 2441 | UINT32 Reserved4:5;\r | |
| 2442 | ///\r | |
| 2443 | /// [Bits 34:32] PA4.\r | |
| 2444 | ///\r | |
| 2445 | UINT32 PA4:3;\r | |
| 2446 | UINT32 Reserved5:5;\r | |
| 2447 | ///\r | |
| 2448 | /// [Bits 42:40] PA5.\r | |
| 2449 | ///\r | |
| 2450 | UINT32 PA5:3;\r | |
| 2451 | UINT32 Reserved6:5;\r | |
| 2452 | ///\r | |
| 2453 | /// [Bits 50:48] PA6.\r | |
| 2454 | ///\r | |
| 2455 | UINT32 PA6:3;\r | |
| 2456 | UINT32 Reserved7:5;\r | |
| 2457 | ///\r | |
| 2458 | /// [Bits 58:56] PA7.\r | |
| 2459 | ///\r | |
| 2460 | UINT32 PA7:3;\r | |
| 2461 | UINT32 Reserved8:5;\r | |
| 2462 | } Bits;\r | |
| 2463 | ///\r | |
| 2464 | /// All bit fields as a 64-bit value\r | |
| 2465 | ///\r | |
| 2466 | UINT64 Uint64;\r | |
| 2467 | } MSR_IA32_PAT_REGISTER;\r | |
| 2468 | \r | |
| 2469 | \r | |
| 2470 | /**\r | |
| 2471 | Provides the programming interface to use corrected MC error signaling\r | |
| 2472 | capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.\r | |
| 2473 | \r | |
| 2474 | @param ECX MSR_IA32_MCn_CTL2\r | |
| 2475 | @param EAX Lower 32-bits of MSR value.\r | |
| 2476 | Described by the type MSR_IA32_MC_CTL2_REGISTER.\r | |
| 2477 | @param EDX Upper 32-bits of MSR value.\r | |
| 2478 | Described by the type MSR_IA32_MC_CTL2_REGISTER.\r | |
| 2479 | \r | |
| 2480 | <b>Example usage</b>\r | |
| 2481 | @code\r | |
| 2482 | MSR_IA32_MC_CTL2_REGISTER Msr;\r | |
| 2483 | \r | |
| 2484 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);\r | |
| 2485 | AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);\r | |
| 2486 | @endcode\r | |
| 7de98828 JF |
2487 | @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM.\r |
| 2488 | MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM.\r | |
| 2489 | MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM.\r | |
| 2490 | MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM.\r | |
| 2491 | MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.\r | |
| 2492 | MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM.\r | |
| 2493 | MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM.\r | |
| 2494 | MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM.\r | |
| 2495 | MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM.\r | |
| 2496 | MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM.\r | |
| 2497 | MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.\r | |
| 2498 | MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.\r | |
| 2499 | MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.\r | |
| 2500 | MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.\r | |
| 2501 | MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.\r | |
| 2502 | MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.\r | |
| 2503 | MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.\r | |
| 2504 | MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.\r | |
| 2505 | MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.\r | |
| 2506 | MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.\r | |
| 2507 | MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.\r | |
| 2508 | MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.\r | |
| 2509 | MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.\r | |
| 2510 | MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.\r | |
| 2511 | MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.\r | |
| 2512 | MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.\r | |
| 2513 | MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.\r | |
| 2514 | MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.\r | |
| 2515 | MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.\r | |
| 2516 | MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.\r | |
| 2517 | MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.\r | |
| 2518 | MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.\r | |
| 04c980a6 MK |
2519 | @{\r |
| 2520 | **/\r | |
| 2521 | #define MSR_IA32_MC0_CTL2 0x00000280\r | |
| 2522 | #define MSR_IA32_MC1_CTL2 0x00000281\r | |
| 2523 | #define MSR_IA32_MC2_CTL2 0x00000282\r | |
| 2524 | #define MSR_IA32_MC3_CTL2 0x00000283\r | |
| 2525 | #define MSR_IA32_MC4_CTL2 0x00000284\r | |
| 2526 | #define MSR_IA32_MC5_CTL2 0x00000285\r | |
| 2527 | #define MSR_IA32_MC6_CTL2 0x00000286\r | |
| 2528 | #define MSR_IA32_MC7_CTL2 0x00000287\r | |
| 2529 | #define MSR_IA32_MC8_CTL2 0x00000288\r | |
| 2530 | #define MSR_IA32_MC9_CTL2 0x00000289\r | |
| 2531 | #define MSR_IA32_MC10_CTL2 0x0000028A\r | |
| 2532 | #define MSR_IA32_MC11_CTL2 0x0000028B\r | |
| 2533 | #define MSR_IA32_MC12_CTL2 0x0000028C\r | |
| 2534 | #define MSR_IA32_MC13_CTL2 0x0000028D\r | |
| 2535 | #define MSR_IA32_MC14_CTL2 0x0000028E\r | |
| 2536 | #define MSR_IA32_MC15_CTL2 0x0000028F\r | |
| 2537 | #define MSR_IA32_MC16_CTL2 0x00000290\r | |
| 2538 | #define MSR_IA32_MC17_CTL2 0x00000291\r | |
| 2539 | #define MSR_IA32_MC18_CTL2 0x00000292\r | |
| 2540 | #define MSR_IA32_MC19_CTL2 0x00000293\r | |
| 2541 | #define MSR_IA32_MC20_CTL2 0x00000294\r | |
| 2542 | #define MSR_IA32_MC21_CTL2 0x00000295\r | |
| 2543 | #define MSR_IA32_MC22_CTL2 0x00000296\r | |
| 2544 | #define MSR_IA32_MC23_CTL2 0x00000297\r | |
| 2545 | #define MSR_IA32_MC24_CTL2 0x00000298\r | |
| 2546 | #define MSR_IA32_MC25_CTL2 0x00000299\r | |
| 2547 | #define MSR_IA32_MC26_CTL2 0x0000029A\r | |
| 2548 | #define MSR_IA32_MC27_CTL2 0x0000029B\r | |
| 2549 | #define MSR_IA32_MC28_CTL2 0x0000029C\r | |
| 2550 | #define MSR_IA32_MC29_CTL2 0x0000029D\r | |
| 2551 | #define MSR_IA32_MC30_CTL2 0x0000029E\r | |
| 2552 | #define MSR_IA32_MC31_CTL2 0x0000029F\r | |
| 2553 | /// @}\r | |
| 2554 | \r | |
| 2555 | /**\r | |
| 2556 | MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2\r | |
| 2557 | to #MSR_IA32_MC31_CTL2\r | |
| 2558 | **/\r | |
| 2559 | typedef union {\r | |
| 2560 | ///\r | |
| 2561 | /// Individual bit fields\r | |
| 2562 | ///\r | |
| 2563 | struct {\r | |
| 2564 | ///\r | |
| 2565 | /// [Bits 14:0] Corrected error count threshold.\r | |
| 2566 | ///\r | |
| 2567 | UINT32 CorrectedErrorCountThreshold:15;\r | |
| 2568 | UINT32 Reserved1:15;\r | |
| 2569 | ///\r | |
| 2570 | /// [Bit 30] CMCI_EN.\r | |
| 2571 | ///\r | |
| 2572 | UINT32 CMCI_EN:1;\r | |
| 2573 | UINT32 Reserved2:1;\r | |
| 2574 | UINT32 Reserved3:32;\r | |
| 2575 | } Bits;\r | |
| 2576 | ///\r | |
| 2577 | /// All bit fields as a 32-bit value\r | |
| 2578 | ///\r | |
| 2579 | UINT32 Uint32;\r | |
| 2580 | ///\r | |
| 2581 | /// All bit fields as a 64-bit value\r | |
| 2582 | ///\r | |
| 2583 | UINT64 Uint64;\r | |
| 2584 | } MSR_IA32_MC_CTL2_REGISTER;\r | |
| 2585 | \r | |
| 2586 | \r | |
| 2587 | /**\r | |
| 2588 | MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2589 | \r | |
| 2590 | @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)\r | |
| 2591 | @param EAX Lower 32-bits of MSR value.\r | |
| 2592 | Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r | |
| 2593 | @param EDX Upper 32-bits of MSR value.\r | |
| 2594 | Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r | |
| 2595 | \r | |
| 2596 | <b>Example usage</b>\r | |
| 2597 | @code\r | |
| 2598 | MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;\r | |
| 2599 | \r | |
| 2600 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r | |
| 2601 | AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);\r | |
| 2602 | @endcode\r | |
| 7de98828 | 2603 | @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.\r |
| 04c980a6 MK |
2604 | **/\r |
| 2605 | #define MSR_IA32_MTRR_DEF_TYPE 0x000002FF\r | |
| 2606 | \r | |
| 2607 | /**\r | |
| 2608 | MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE\r | |
| 2609 | **/\r | |
| 2610 | typedef union {\r | |
| 2611 | ///\r | |
| 2612 | /// Individual bit fields\r | |
| 2613 | ///\r | |
| 2614 | struct {\r | |
| 2615 | ///\r | |
| 2616 | /// [Bits 2:0] Default Memory Type.\r | |
| 2617 | ///\r | |
| 2618 | UINT32 Type:3;\r | |
| 2619 | UINT32 Reserved1:7;\r | |
| 2620 | ///\r | |
| 2621 | /// [Bit 10] Fixed Range MTRR Enable.\r | |
| 2622 | ///\r | |
| 2623 | UINT32 FE:1;\r | |
| 2624 | ///\r | |
| 2625 | /// [Bit 11] MTRR Enable.\r | |
| 2626 | ///\r | |
| 2627 | UINT32 E:1;\r | |
| 2628 | UINT32 Reserved2:20;\r | |
| 2629 | UINT32 Reserved3:32;\r | |
| 2630 | } Bits;\r | |
| 2631 | ///\r | |
| 2632 | /// All bit fields as a 32-bit value\r | |
| 2633 | ///\r | |
| 2634 | UINT32 Uint32;\r | |
| 2635 | ///\r | |
| 2636 | /// All bit fields as a 64-bit value\r | |
| 2637 | ///\r | |
| 2638 | UINT64 Uint64;\r | |
| 2639 | } MSR_IA32_MTRR_DEF_TYPE_REGISTER;\r | |
| 2640 | \r | |
| 2641 | \r | |
| 2642 | /**\r | |
| 2643 | Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If\r | |
| 2644 | CPUID.0AH: EDX[4:0] > 0.\r | |
| 2645 | \r | |
| 2646 | @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)\r | |
| 2647 | @param EAX Lower 32-bits of MSR value.\r | |
| 2648 | @param EDX Upper 32-bits of MSR value.\r | |
| 2649 | \r | |
| 2650 | <b>Example usage</b>\r | |
| 2651 | @code\r | |
| 2652 | UINT64 Msr;\r | |
| 2653 | \r | |
| 2654 | Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);\r | |
| 2655 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);\r | |
| 2656 | @endcode\r | |
| 7de98828 | 2657 | @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.\r |
| 04c980a6 MK |
2658 | **/\r |
| 2659 | #define MSR_IA32_FIXED_CTR0 0x00000309\r | |
| 2660 | \r | |
| 2661 | \r | |
| 2662 | /**\r | |
| 2663 | Fixed-Function Performance Counter 1 0 (R/W): Counts CPU_CLK_Unhalted.Core.\r | |
| 2664 | If CPUID.0AH: EDX[4:0] > 1.\r | |
| 2665 | \r | |
| 2666 | @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)\r | |
| 2667 | @param EAX Lower 32-bits of MSR value.\r | |
| 2668 | @param EDX Upper 32-bits of MSR value.\r | |
| 2669 | \r | |
| 2670 | <b>Example usage</b>\r | |
| 2671 | @code\r | |
| 2672 | UINT64 Msr;\r | |
| 2673 | \r | |
| 2674 | Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);\r | |
| 2675 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);\r | |
| 2676 | @endcode\r | |
| 7de98828 | 2677 | @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.\r |
| 04c980a6 MK |
2678 | **/\r |
| 2679 | #define MSR_IA32_FIXED_CTR1 0x0000030A\r | |
| 2680 | \r | |
| 2681 | \r | |
| 2682 | /**\r | |
| 2683 | Fixed-Function Performance Counter 0 0 (R/W): Counts CPU_CLK_Unhalted.Ref.\r | |
| 2684 | If CPUID.0AH: EDX[4:0] > 2.\r | |
| 2685 | \r | |
| 2686 | @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)\r | |
| 2687 | @param EAX Lower 32-bits of MSR value.\r | |
| 2688 | @param EDX Upper 32-bits of MSR value.\r | |
| 2689 | \r | |
| 2690 | <b>Example usage</b>\r | |
| 2691 | @code\r | |
| 2692 | UINT64 Msr;\r | |
| 2693 | \r | |
| 2694 | Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);\r | |
| 2695 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);\r | |
| 2696 | @endcode\r | |
| 7de98828 | 2697 | @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.\r |
| 04c980a6 MK |
2698 | **/\r |
| 2699 | #define MSR_IA32_FIXED_CTR2 0x0000030B\r | |
| 2700 | \r | |
| 2701 | \r | |
| 2702 | /**\r | |
| 2703 | RO. If CPUID.01H: ECX[15] = 1.\r | |
| 2704 | \r | |
| 2705 | @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)\r | |
| 2706 | @param EAX Lower 32-bits of MSR value.\r | |
| 2707 | Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r | |
| 2708 | @param EDX Upper 32-bits of MSR value.\r | |
| 2709 | Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r | |
| 2710 | \r | |
| 2711 | <b>Example usage</b>\r | |
| 2712 | @code\r | |
| 2713 | MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;\r | |
| 2714 | \r | |
| 2715 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);\r | |
| 2716 | AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);\r | |
| 2717 | @endcode\r | |
| 7de98828 | 2718 | @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.\r |
| 04c980a6 MK |
2719 | **/\r |
| 2720 | #define MSR_IA32_PERF_CAPABILITIES 0x00000345\r | |
| 2721 | \r | |
| 2722 | /**\r | |
| 2723 | MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES\r | |
| 2724 | **/\r | |
| 2725 | typedef union {\r | |
| 2726 | ///\r | |
| 2727 | /// Individual bit fields\r | |
| 2728 | ///\r | |
| 2729 | struct {\r | |
| 2730 | ///\r | |
| 2731 | /// [Bits 5:0] LBR format.\r | |
| 2732 | ///\r | |
| 2733 | UINT32 LBR_FMT:6;\r | |
| 2734 | ///\r | |
| 2735 | /// [Bit 6] PEBS Trap.\r | |
| 2736 | ///\r | |
| 2737 | UINT32 PEBS_TRAP:1;\r | |
| 2738 | ///\r | |
| 2739 | /// [Bit 7] PEBSSaveArchRegs.\r | |
| 2740 | ///\r | |
| 2741 | UINT32 PEBS_ARCH_REG:1;\r | |
| 2742 | ///\r | |
| 2743 | /// [Bits 11:8] PEBS Record Format.\r | |
| 2744 | ///\r | |
| 2745 | UINT32 PEBS_REC_FMT:4;\r | |
| 2746 | ///\r | |
| 2747 | /// [Bit 12] 1: Freeze while SMM is supported.\r | |
| 2748 | ///\r | |
| 2749 | UINT32 SMM_FREEZE:1;\r | |
| 2750 | ///\r | |
| 2751 | /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.\r | |
| 2752 | ///\r | |
| 2753 | UINT32 FW_WRITE:1;\r | |
| 2754 | UINT32 Reserved1:18;\r | |
| 2755 | UINT32 Reserved2:32;\r | |
| 2756 | } Bits;\r | |
| 2757 | ///\r | |
| 2758 | /// All bit fields as a 32-bit value\r | |
| 2759 | ///\r | |
| 2760 | UINT32 Uint32;\r | |
| 2761 | ///\r | |
| 2762 | /// All bit fields as a 64-bit value\r | |
| 2763 | ///\r | |
| 2764 | UINT64 Uint64;\r | |
| 2765 | } MSR_IA32_PERF_CAPABILITIES_REGISTER;\r | |
| 2766 | \r | |
| 2767 | \r | |
| 2768 | /**\r | |
| 2769 | Fixed-Function Performance Counter Control (R/W) Counter increments while\r | |
| 2770 | the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with\r | |
| 2771 | the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]\r | |
| 2772 | > 1.\r | |
| 2773 | \r | |
| 2774 | @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)\r | |
| 2775 | @param EAX Lower 32-bits of MSR value.\r | |
| 2776 | Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r | |
| 2777 | @param EDX Upper 32-bits of MSR value.\r | |
| 2778 | Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r | |
| 2779 | \r | |
| 2780 | <b>Example usage</b>\r | |
| 2781 | @code\r | |
| 2782 | MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;\r | |
| 2783 | \r | |
| 2784 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);\r | |
| 2785 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);\r | |
| 2786 | @endcode\r | |
| 7de98828 | 2787 | @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.\r |
| 04c980a6 MK |
2788 | **/\r |
| 2789 | #define MSR_IA32_FIXED_CTR_CTRL 0x0000038D\r | |
| 2790 | \r | |
| 2791 | /**\r | |
| 2792 | MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL\r | |
| 2793 | **/\r | |
| 2794 | typedef union {\r | |
| 2795 | ///\r | |
| 2796 | /// Individual bit fields\r | |
| 2797 | ///\r | |
| 2798 | struct {\r | |
| 2799 | ///\r | |
| 2800 | /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.\r | |
| 2801 | ///\r | |
| 2802 | UINT32 EN0_OS:1;\r | |
| 2803 | ///\r | |
| 2804 | /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.\r | |
| 2805 | ///\r | |
| 2806 | UINT32 EN0_Usr:1;\r | |
| 2807 | ///\r | |
| 2808 | /// [Bit 2] AnyThread: When set to 1, it enables counting the associated\r | |
| 2809 | /// event conditions occurring across all logical processors sharing a\r | |
| 2810 | /// processor core. When set to 0, the counter only increments the\r | |
| 2811 | /// associated event conditions occurring in the logical processor which\r | |
| 2812 | /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r | |
| 2813 | ///\r | |
| 2814 | UINT32 AnyThread0:1;\r | |
| 2815 | ///\r | |
| 2816 | /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.\r | |
| 2817 | ///\r | |
| 2818 | UINT32 EN0_PMI:1;\r | |
| 2819 | ///\r | |
| 2820 | /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.\r | |
| 2821 | ///\r | |
| 2822 | UINT32 EN1_OS:1;\r | |
| 2823 | ///\r | |
| 2824 | /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.\r | |
| 2825 | ///\r | |
| 2826 | UINT32 EN1_Usr:1;\r | |
| 2827 | ///\r | |
| 2828 | /// [Bit 6] AnyThread: When set to 1, it enables counting the associated\r | |
| 2829 | /// event conditions occurring across all logical processors sharing a\r | |
| 2830 | /// processor core. When set to 0, the counter only increments the\r | |
| 2831 | /// associated event conditions occurring in the logical processor which\r | |
| 2832 | /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r | |
| 2833 | ///\r | |
| 2834 | UINT32 AnyThread1:1;\r | |
| 2835 | ///\r | |
| 2836 | /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.\r | |
| 2837 | ///\r | |
| 2838 | UINT32 EN1_PMI:1;\r | |
| 2839 | ///\r | |
| 2840 | /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.\r | |
| 2841 | ///\r | |
| 2842 | UINT32 EN2_OS:1;\r | |
| 2843 | ///\r | |
| 2844 | /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.\r | |
| 2845 | ///\r | |
| 2846 | UINT32 EN2_Usr:1;\r | |
| 2847 | ///\r | |
| 2848 | /// [Bit 10] AnyThread: When set to 1, it enables counting the associated\r | |
| 2849 | /// event conditions occurring across all logical processors sharing a\r | |
| 2850 | /// processor core. When set to 0, the counter only increments the\r | |
| 2851 | /// associated event conditions occurring in the logical processor which\r | |
| 2852 | /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r | |
| 2853 | ///\r | |
| 2854 | UINT32 AnyThread2:1;\r | |
| 2855 | ///\r | |
| 2856 | /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.\r | |
| 2857 | ///\r | |
| 2858 | UINT32 EN2_PMI:1;\r | |
| 2859 | UINT32 Reserved1:20;\r | |
| 2860 | UINT32 Reserved2:32;\r | |
| 2861 | } Bits;\r | |
| 2862 | ///\r | |
| 2863 | /// All bit fields as a 32-bit value\r | |
| 2864 | ///\r | |
| 2865 | UINT32 Uint32;\r | |
| 2866 | ///\r | |
| 2867 | /// All bit fields as a 64-bit value\r | |
| 2868 | ///\r | |
| 2869 | UINT64 Uint64;\r | |
| 2870 | } MSR_IA32_FIXED_CTR_CTRL_REGISTER;\r | |
| 2871 | \r | |
| 2872 | \r | |
| 2873 | /**\r | |
| 2874 | Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.\r | |
| 2875 | \r | |
| 2876 | @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r | |
| 2877 | @param EAX Lower 32-bits of MSR value.\r | |
| 2878 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r | |
| 2879 | @param EDX Upper 32-bits of MSR value.\r | |
| 2880 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r | |
| 2881 | \r | |
| 2882 | <b>Example usage</b>\r | |
| 2883 | @code\r | |
| 2884 | MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r | |
| 2885 | \r | |
| 2886 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);\r | |
| 2887 | @endcode\r | |
| 7de98828 | 2888 | @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r |
| 04c980a6 MK |
2889 | **/\r |
| 2890 | #define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E\r | |
| 2891 | \r | |
| 2892 | /**\r | |
| 2893 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS\r | |
| 2894 | **/\r | |
| 2895 | typedef union {\r | |
| 2896 | ///\r | |
| 2897 | /// Individual bit fields\r | |
| 2898 | ///\r | |
| 2899 | struct {\r | |
| 2900 | ///\r | |
| 2901 | /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:\r | |
| 2902 | /// EAX[15:8] > 0.\r | |
| 2903 | ///\r | |
| 2904 | UINT32 Ovf_PMC0:1;\r | |
| 2905 | ///\r | |
| 2906 | /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:\r | |
| 2907 | /// EAX[15:8] > 1.\r | |
| 2908 | ///\r | |
| 2909 | UINT32 Ovf_PMC1:1;\r | |
| 2910 | ///\r | |
| 2911 | /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:\r | |
| 2912 | /// EAX[15:8] > 2.\r | |
| 2913 | ///\r | |
| 2914 | UINT32 Ovf_PMC2:1;\r | |
| 2915 | ///\r | |
| 2916 | /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:\r | |
| 2917 | /// EAX[15:8] > 3.\r | |
| 2918 | ///\r | |
| 2919 | UINT32 Ovf_PMC3:1;\r | |
| 2920 | UINT32 Reserved1:28;\r | |
| 2921 | ///\r | |
| 2922 | /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If\r | |
| 2923 | /// CPUID.0AH: EAX[7:0] > 1.\r | |
| 2924 | ///\r | |
| 2925 | UINT32 Ovf_FixedCtr0:1;\r | |
| 2926 | ///\r | |
| 2927 | /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If\r | |
| 2928 | /// CPUID.0AH: EAX[7:0] > 1.\r | |
| 2929 | ///\r | |
| 2930 | UINT32 Ovf_FixedCtr1:1;\r | |
| 2931 | ///\r | |
| 2932 | /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If\r | |
| 2933 | /// CPUID.0AH: EAX[7:0] > 1.\r | |
| 2934 | ///\r | |
| 2935 | UINT32 Ovf_FixedCtr2:1;\r | |
| 2936 | UINT32 Reserved2:20;\r | |
| 2937 | ///\r | |
| 2938 | /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory\r | |
| 2939 | /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r | |
| 2940 | /// && IA32_RTIT_CTL.ToPA = 1.\r | |
| 2941 | ///\r | |
| 2942 | UINT32 Trace_ToPA_PMI:1;\r | |
| 2943 | UINT32 Reserved3:2;\r | |
| 2944 | ///\r | |
| 2945 | /// [Bit 58] LBR_Frz: LBRs are frozen due to -\r | |
| 2946 | /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If\r | |
| 2947 | /// CPUID.0AH: EAX[7:0] > 3.\r | |
| 2948 | ///\r | |
| 2949 | UINT32 LBR_Frz:1;\r | |
| 2950 | ///\r | |
| 2951 | /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due\r | |
| 2952 | /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU\r | |
| 2953 | /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 2954 | ///\r | |
| 2955 | UINT32 CTR_Frz:1;\r | |
| 2956 | ///\r | |
| 2957 | /// [Bit 60] ASCI: Data in the performance counters in the core PMU may\r | |
| 2958 | /// include contributions from the direct or indirect operation intel SGX\r | |
| 2959 | /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.\r | |
| 2960 | ///\r | |
| 2961 | UINT32 ASCI:1;\r | |
| 2962 | ///\r | |
| 2963 | /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:\r | |
| 2964 | /// EAX[7:0] > 2.\r | |
| 2965 | ///\r | |
| 2966 | UINT32 Ovf_Uncore:1;\r | |
| 2967 | ///\r | |
| 2968 | /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:\r | |
| 2969 | /// EAX[7:0] > 0.\r | |
| 2970 | ///\r | |
| 2971 | UINT32 OvfBuf:1;\r | |
| 2972 | ///\r | |
| 2973 | /// [Bit 63] CondChgd: status bits of this register has changed. If\r | |
| 2974 | /// CPUID.0AH: EAX[7:0] > 0.\r | |
| 2975 | ///\r | |
| 2976 | UINT32 CondChgd:1;\r | |
| 2977 | } Bits;\r | |
| 2978 | ///\r | |
| 2979 | /// All bit fields as a 64-bit value\r | |
| 2980 | ///\r | |
| 2981 | UINT64 Uint64;\r | |
| 2982 | } MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;\r | |
| 2983 | \r | |
| 2984 | \r | |
| 2985 | /**\r | |
| 2986 | Global Performance Counter Control (R/W) Counter increments while the result\r | |
| 2987 | of ANDing respective enable bit in this MSR with the corresponding OS or USR\r | |
| 2988 | bits in the general-purpose or fixed counter control MSR is true. If\r | |
| 2989 | CPUID.0AH: EAX[7:0] > 0.\r | |
| 2990 | \r | |
| 2991 | @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)\r | |
| 2992 | @param EAX Lower 32-bits of MSR value.\r | |
| 2993 | Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r | |
| 2994 | @param EDX Upper 32-bits of MSR value.\r | |
| 2995 | Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r | |
| 2996 | \r | |
| 2997 | <b>Example usage</b>\r | |
| 2998 | @code\r | |
| 2999 | MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;\r | |
| 3000 | \r | |
| 3001 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);\r | |
| 3002 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);\r | |
| 3003 | @endcode\r | |
| 7de98828 | 3004 | @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.\r |
| 04c980a6 MK |
3005 | **/\r |
| 3006 | #define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F\r | |
| 3007 | \r | |
| 3008 | /**\r | |
| 3009 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL\r | |
| 3010 | **/\r | |
| 3011 | typedef union {\r | |
| 3012 | ///\r | |
| 3013 | /// Individual bit fields\r | |
| 3014 | ///\r | |
| 3015 | struct {\r | |
| 3016 | ///\r | |
| 3017 | /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.\r | |
| 3018 | /// Enable bitmask. Only the first n-1 bits are valid.\r | |
| 3019 | /// Bits n..31 are reserved.\r | |
| 3020 | ///\r | |
| 3021 | UINT32 EN_PMCn:32;\r | |
| 3022 | ///\r | |
| 3023 | /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.\r | |
| 3024 | /// Enable bitmask. Only the first n-1 bits are valid.\r | |
| 3025 | /// Bits 31:n are reserved.\r | |
| 3026 | ///\r | |
| 3027 | UINT32 EN_FIXED_CTRn:32;\r | |
| 3028 | } Bits;\r | |
| 3029 | ///\r | |
| 3030 | /// All bit fields as a 64-bit value\r | |
| 3031 | ///\r | |
| 3032 | UINT64 Uint64;\r | |
| 3033 | } MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;\r | |
| 3034 | \r | |
| 3035 | \r | |
| 3036 | /**\r | |
| 3037 | Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >\r | |
| 3038 | 0 && CPUID.0AH: EAX[7:0] <= 3.\r | |
| 3039 | \r | |
| 3040 | @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)\r | |
| 3041 | @param EAX Lower 32-bits of MSR value.\r | |
| 3042 | Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r | |
| 3043 | @param EDX Upper 32-bits of MSR value.\r | |
| 3044 | Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r | |
| 3045 | \r | |
| 3046 | <b>Example usage</b>\r | |
| 3047 | @code\r | |
| 3048 | MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r | |
| 3049 | \r | |
| 3050 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);\r | |
| 3051 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r | |
| 3052 | @endcode\r | |
| 7de98828 | 3053 | @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.\r |
| 04c980a6 MK |
3054 | **/\r |
| 3055 | #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r | |
| 3056 | \r | |
| 3057 | /**\r | |
| 3058 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL\r | |
| 3059 | **/\r | |
| 3060 | typedef union {\r | |
| 3061 | ///\r | |
| 3062 | /// Individual bit fields\r | |
| 3063 | ///\r | |
| 3064 | struct {\r | |
| 3065 | ///\r | |
| 3066 | /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r | |
| 3067 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
| 3068 | /// Bits 31:n are reserved.\r | |
| 3069 | ///\r | |
| 3070 | UINT32 Ovf_PMCn:32;\r | |
| 3071 | ///\r | |
| 3072 | /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r | |
| 3073 | /// If CPUID.0AH: EDX[4:0] > n.\r | |
| 3074 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
| 3075 | /// Bits 22:n are reserved.\r | |
| 3076 | ///\r | |
| 3077 | UINT32 Ovf_FIXED_CTRn:23;\r | |
| 3078 | ///\r | |
| 3079 | /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r | |
| 3080 | /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.\r | |
| 3081 | ///\r | |
| 3082 | UINT32 Trace_ToPA_PMI:1;\r | |
| 3083 | UINT32 Reserved2:5;\r | |
| 3084 | ///\r | |
| 3085 | /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r | |
| 3086 | /// Display Model 06_2EH.\r | |
| 3087 | ///\r | |
| 3088 | UINT32 Ovf_Uncore:1;\r | |
| 3089 | ///\r | |
| 3090 | /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
| 3091 | ///\r | |
| 3092 | UINT32 OvfBuf:1;\r | |
| 3093 | ///\r | |
| 3094 | /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
| 3095 | ///\r | |
| 3096 | UINT32 CondChgd:1;\r | |
| 3097 | } Bits;\r | |
| 3098 | ///\r | |
| 3099 | /// All bit fields as a 64-bit value\r | |
| 3100 | ///\r | |
| 3101 | UINT64 Uint64;\r | |
| 3102 | } MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r | |
| 3103 | \r | |
| 3104 | \r | |
| 3105 | /**\r | |
| 3106 | Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:\r | |
| 3107 | EAX[7:0] > 3.\r | |
| 3108 | \r | |
| 3109 | @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r | |
| 3110 | @param EAX Lower 32-bits of MSR value.\r | |
| 3111 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r | |
| 3112 | @param EDX Upper 32-bits of MSR value.\r | |
| 3113 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r | |
| 3114 | \r | |
| 3115 | <b>Example usage</b>\r | |
| 3116 | @code\r | |
| 3117 | MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r | |
| 3118 | \r | |
| 3119 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);\r | |
| 3120 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r | |
| 3121 | @endcode\r | |
| 7de98828 | 3122 | @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r |
| 04c980a6 MK |
3123 | **/\r |
| 3124 | #define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r | |
| 3125 | \r | |
| 3126 | /**\r | |
| 3127 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET\r | |
| 3128 | **/\r | |
| 3129 | typedef union {\r | |
| 3130 | ///\r | |
| 3131 | /// Individual bit fields\r | |
| 3132 | ///\r | |
| 3133 | struct {\r | |
| 3134 | ///\r | |
| 3135 | /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r | |
| 3136 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
| 3137 | /// Bits 31:n are reserved.\r | |
| 3138 | ///\r | |
| 3139 | UINT32 Ovf_PMCn:32;\r | |
| 3140 | ///\r | |
| 3141 | /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r | |
| 3142 | /// If CPUID.0AH: EDX[4:0] > n.\r | |
| 3143 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
| 3144 | /// Bits 22:n are reserved.\r | |
| 3145 | ///\r | |
| 3146 | UINT32 Ovf_FIXED_CTRn:23;\r | |
| 3147 | ///\r | |
| 3148 | /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r | |
| 3149 | /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.\r | |
| 3150 | ///\r | |
| 3151 | UINT32 Trace_ToPA_PMI:1;\r | |
| 3152 | UINT32 Reserved2:2;\r | |
| 3153 | ///\r | |
| 3154 | /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3155 | ///\r | |
| 3156 | UINT32 LBR_Frz:1;\r | |
| 3157 | ///\r | |
| 3158 | /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3159 | ///\r | |
| 3160 | UINT32 CTR_Frz:1;\r | |
| 3161 | ///\r | |
| 3162 | /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3163 | ///\r | |
| 3164 | UINT32 ASCI:1;\r | |
| 3165 | ///\r | |
| 3166 | /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r | |
| 3167 | /// Display Model 06_2EH.\r | |
| 3168 | ///\r | |
| 3169 | UINT32 Ovf_Uncore:1;\r | |
| 3170 | ///\r | |
| 3171 | /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
| 3172 | ///\r | |
| 3173 | UINT32 OvfBuf:1;\r | |
| 3174 | ///\r | |
| 3175 | /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
| 3176 | ///\r | |
| 3177 | UINT32 CondChgd:1;\r | |
| 3178 | } Bits;\r | |
| 3179 | ///\r | |
| 3180 | /// All bit fields as a 64-bit value\r | |
| 3181 | ///\r | |
| 3182 | UINT64 Uint64;\r | |
| 3183 | } MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r | |
| 3184 | \r | |
| 3185 | \r | |
| 3186 | /**\r | |
| 3187 | Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:\r | |
| 3188 | EAX[7:0] > 3.\r | |
| 3189 | \r | |
| 3190 | @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r | |
| 3191 | @param EAX Lower 32-bits of MSR value.\r | |
| 3192 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r | |
| 3193 | @param EDX Upper 32-bits of MSR value.\r | |
| 3194 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r | |
| 3195 | \r | |
| 3196 | <b>Example usage</b>\r | |
| 3197 | @code\r | |
| 3198 | MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r | |
| 3199 | \r | |
| 3200 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);\r | |
| 3201 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r | |
| 3202 | @endcode\r | |
| 7de98828 | 3203 | @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r |
| 04c980a6 MK |
3204 | **/\r |
| 3205 | #define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r | |
| 3206 | \r | |
| 3207 | /**\r | |
| 3208 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET\r | |
| 3209 | **/\r | |
| 3210 | typedef union {\r | |
| 3211 | ///\r | |
| 3212 | /// Individual bit fields\r | |
| 3213 | ///\r | |
| 3214 | struct {\r | |
| 3215 | ///\r | |
| 3216 | /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.\r | |
| 3217 | /// Set bitmask. Only the first n-1 bits are valid.\r | |
| 3218 | /// Bits 31:n are reserved.\r | |
| 3219 | ///\r | |
| 3220 | UINT32 Ovf_PMCn:32;\r | |
| 3221 | ///\r | |
| 3222 | /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.\r | |
| 3223 | /// If CPUID.0AH: EAX[7:0] > n.\r | |
| 3224 | /// Set bitmask. Only the first n-1 bits are valid.\r | |
| 3225 | /// Bits 22:n are reserved.\r | |
| 3226 | ///\r | |
| 3227 | UINT32 Ovf_FIXED_CTRn:23;\r | |
| 3228 | ///\r | |
| 3229 | /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3230 | ///\r | |
| 3231 | UINT32 Trace_ToPA_PMI:1;\r | |
| 3232 | UINT32 Reserved2:2;\r | |
| 3233 | ///\r | |
| 3234 | /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3235 | ///\r | |
| 3236 | UINT32 LBR_Frz:1;\r | |
| 3237 | ///\r | |
| 3238 | /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3239 | ///\r | |
| 3240 | UINT32 CTR_Frz:1;\r | |
| 3241 | ///\r | |
| 3242 | /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3243 | ///\r | |
| 3244 | UINT32 ASCI:1;\r | |
| 3245 | ///\r | |
| 3246 | /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3247 | ///\r | |
| 3248 | UINT32 Ovf_Uncore:1;\r | |
| 3249 | ///\r | |
| 3250 | /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3251 | ///\r | |
| 3252 | UINT32 OvfBuf:1;\r | |
| 3253 | UINT32 Reserved3:1;\r | |
| 3254 | } Bits;\r | |
| 3255 | ///\r | |
| 3256 | /// All bit fields as a 64-bit value\r | |
| 3257 | ///\r | |
| 3258 | UINT64 Uint64;\r | |
| 3259 | } MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r | |
| 3260 | \r | |
| 3261 | \r | |
| 3262 | /**\r | |
| 3263 | Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >\r | |
| 3264 | 3.\r | |
| 3265 | \r | |
| 3266 | @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)\r | |
| 3267 | @param EAX Lower 32-bits of MSR value.\r | |
| 3268 | Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r | |
| 3269 | @param EDX Upper 32-bits of MSR value.\r | |
| 3270 | Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r | |
| 3271 | \r | |
| 3272 | <b>Example usage</b>\r | |
| 3273 | @code\r | |
| 3274 | MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;\r | |
| 3275 | \r | |
| 3276 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);\r | |
| 3277 | @endcode\r | |
| 7de98828 | 3278 | @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.\r |
| 04c980a6 MK |
3279 | **/\r |
| 3280 | #define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392\r | |
| 3281 | \r | |
| 3282 | /**\r | |
| 3283 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE\r | |
| 3284 | **/\r | |
| 3285 | typedef union {\r | |
| 3286 | ///\r | |
| 3287 | /// Individual bit fields\r | |
| 3288 | ///\r | |
| 3289 | struct {\r | |
| 3290 | ///\r | |
| 3291 | /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.\r | |
| 3292 | /// Status bitmask. Only the first n-1 bits are valid.\r | |
| 3293 | /// Bits 31:n are reserved.\r | |
| 3294 | ///\r | |
| 3295 | UINT32 IA32_PERFEVTSELn:32;\r | |
| 3296 | ///\r | |
| 3297 | /// [Bits 62:32] IA32_FIXED_CTRn in use.\r | |
| 3298 | /// If CPUID.0AH: EAX[7:0] > n.\r | |
| 3299 | /// Status bitmask. Only the first n-1 bits are valid.\r | |
| 3300 | /// Bits 30:n are reserved.\r | |
| 3301 | ///\r | |
| 3302 | UINT32 IA32_FIXED_CTRn:31;\r | |
| 3303 | ///\r | |
| 3304 | /// [Bit 63] PMI in use.\r | |
| 3305 | ///\r | |
| 3306 | UINT32 PMI:1;\r | |
| 3307 | } Bits;\r | |
| 3308 | ///\r | |
| 3309 | /// All bit fields as a 64-bit value\r | |
| 3310 | ///\r | |
| 3311 | UINT64 Uint64;\r | |
| 3312 | } MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;\r | |
| 3313 | \r | |
| 3314 | \r | |
| 3315 | /**\r | |
| 3316 | PEBS Control (R/W).\r | |
| 3317 | \r | |
| 3318 | @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)\r | |
| 3319 | @param EAX Lower 32-bits of MSR value.\r | |
| 3320 | Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r | |
| 3321 | @param EDX Upper 32-bits of MSR value.\r | |
| 3322 | Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r | |
| 3323 | \r | |
| 3324 | <b>Example usage</b>\r | |
| 3325 | @code\r | |
| 3326 | MSR_IA32_PEBS_ENABLE_REGISTER Msr;\r | |
| 3327 | \r | |
| 3328 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);\r | |
| 3329 | AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);\r | |
| 3330 | @endcode\r | |
| 7de98828 | 3331 | @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.\r |
| 04c980a6 MK |
3332 | **/\r |
| 3333 | #define MSR_IA32_PEBS_ENABLE 0x000003F1\r | |
| 3334 | \r | |
| 3335 | /**\r | |
| 3336 | MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE\r | |
| 3337 | **/\r | |
| 3338 | typedef union {\r | |
| 3339 | ///\r | |
| 3340 | /// Individual bit fields\r | |
| 3341 | ///\r | |
| 3342 | struct {\r | |
| 3343 | ///\r | |
| 3344 | /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /\r | |
| 3345 | /// Display Model 06_0FH.\r | |
| 3346 | ///\r | |
| 3347 | UINT32 Enable:1;\r | |
| 3348 | ///\r | |
| 3349 | /// [Bits 3:1] Reserved or Model specific.\r | |
| 3350 | ///\r | |
| 3351 | UINT32 Reserved1:3;\r | |
| 3352 | UINT32 Reserved2:28;\r | |
| 3353 | ///\r | |
| 3354 | /// [Bits 35:32] Reserved or Model specific.\r | |
| 3355 | ///\r | |
| 3356 | UINT32 Reserved3:4;\r | |
| 3357 | UINT32 Reserved4:28;\r | |
| 3358 | } Bits;\r | |
| 3359 | ///\r | |
| 3360 | /// All bit fields as a 64-bit value\r | |
| 3361 | ///\r | |
| 3362 | UINT64 Uint64;\r | |
| 3363 | } MSR_IA32_PEBS_ENABLE_REGISTER;\r | |
| 3364 | \r | |
| 3365 | \r | |
| 3366 | /**\r | |
| 3367 | MCn_CTL. If IA32_MCG_CAP.CNT > n.\r | |
| 3368 | \r | |
| 3369 | @param ECX MSR_IA32_MCn_CTL\r | |
| 3370 | @param EAX Lower 32-bits of MSR value.\r | |
| 3371 | @param EDX Upper 32-bits of MSR value.\r | |
| 3372 | \r | |
| 3373 | <b>Example usage</b>\r | |
| 3374 | @code\r | |
| 3375 | UINT64 Msr;\r | |
| 3376 | \r | |
| 3377 | Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);\r | |
| 3378 | AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);\r | |
| 3379 | @endcode\r | |
| 7de98828 JF |
3380 | @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM.\r |
| 3381 | MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM.\r | |
| 3382 | MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM.\r | |
| 3383 | MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM.\r | |
| 3384 | MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.\r | |
| 3385 | MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM.\r | |
| 3386 | MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM.\r | |
| 3387 | MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM.\r | |
| 3388 | MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM.\r | |
| 3389 | MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM.\r | |
| 3390 | MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.\r | |
| 3391 | MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.\r | |
| 3392 | MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.\r | |
| 3393 | MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.\r | |
| 3394 | MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.\r | |
| 3395 | MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.\r | |
| 3396 | MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.\r | |
| 3397 | MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.\r | |
| 3398 | MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.\r | |
| 3399 | MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.\r | |
| 3400 | MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.\r | |
| 3401 | MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.\r | |
| 3402 | MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.\r | |
| 3403 | MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.\r | |
| 3404 | MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.\r | |
| 3405 | MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.\r | |
| 3406 | MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.\r | |
| 3407 | MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.\r | |
| 3408 | MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.\r | |
| 04c980a6 MK |
3409 | @{\r |
| 3410 | **/\r | |
| 3411 | #define MSR_IA32_MC0_CTL 0x00000400\r | |
| 3412 | #define MSR_IA32_MC1_CTL 0x00000404\r | |
| 3413 | #define MSR_IA32_MC2_CTL 0x00000408\r | |
| 3414 | #define MSR_IA32_MC3_CTL 0x0000040C\r | |
| 3415 | #define MSR_IA32_MC4_CTL 0x00000410\r | |
| 3416 | #define MSR_IA32_MC5_CTL 0x00000414\r | |
| 3417 | #define MSR_IA32_MC6_CTL 0x00000418\r | |
| 3418 | #define MSR_IA32_MC7_CTL 0x0000041C\r | |
| 3419 | #define MSR_IA32_MC8_CTL 0x00000420\r | |
| 3420 | #define MSR_IA32_MC9_CTL 0x00000424\r | |
| 3421 | #define MSR_IA32_MC10_CTL 0x00000428\r | |
| 3422 | #define MSR_IA32_MC11_CTL 0x0000042C\r | |
| 3423 | #define MSR_IA32_MC12_CTL 0x00000430\r | |
| 3424 | #define MSR_IA32_MC13_CTL 0x00000434\r | |
| 3425 | #define MSR_IA32_MC14_CTL 0x00000438\r | |
| 3426 | #define MSR_IA32_MC15_CTL 0x0000043C\r | |
| 3427 | #define MSR_IA32_MC16_CTL 0x00000440\r | |
| 3428 | #define MSR_IA32_MC17_CTL 0x00000444\r | |
| 3429 | #define MSR_IA32_MC18_CTL 0x00000448\r | |
| 3430 | #define MSR_IA32_MC19_CTL 0x0000044C\r | |
| 3431 | #define MSR_IA32_MC20_CTL 0x00000450\r | |
| 3432 | #define MSR_IA32_MC21_CTL 0x00000454\r | |
| 3433 | #define MSR_IA32_MC22_CTL 0x00000458\r | |
| 3434 | #define MSR_IA32_MC23_CTL 0x0000045C\r | |
| 3435 | #define MSR_IA32_MC24_CTL 0x00000460\r | |
| 3436 | #define MSR_IA32_MC25_CTL 0x00000464\r | |
| 3437 | #define MSR_IA32_MC26_CTL 0x00000468\r | |
| 3438 | #define MSR_IA32_MC27_CTL 0x0000046C\r | |
| 3439 | #define MSR_IA32_MC28_CTL 0x00000470\r | |
| 3440 | /// @}\r | |
| 3441 | \r | |
| 3442 | \r | |
| 3443 | /**\r | |
| 3444 | MCn_STATUS. If IA32_MCG_CAP.CNT > n.\r | |
| 3445 | \r | |
| 3446 | @param ECX MSR_IA32_MCn_STATUS\r | |
| 3447 | @param EAX Lower 32-bits of MSR value.\r | |
| 3448 | @param EDX Upper 32-bits of MSR value.\r | |
| 3449 | \r | |
| 3450 | <b>Example usage</b>\r | |
| 3451 | @code\r | |
| 3452 | UINT64 Msr;\r | |
| 3453 | \r | |
| 3454 | Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);\r | |
| 3455 | AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);\r | |
| 3456 | @endcode\r | |
| 7de98828 JF |
3457 | @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM.\r |
| 3458 | MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM.\r | |
| 3459 | MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM.\r | |
| 3460 | MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM.\r | |
| 3461 | MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM.\r | |
| 3462 | MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM.\r | |
| 3463 | MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM.\r | |
| 3464 | MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM.\r | |
| 3465 | MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM.\r | |
| 3466 | MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM.\r | |
| 3467 | MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.\r | |
| 3468 | MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.\r | |
| 3469 | MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.\r | |
| 3470 | MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.\r | |
| 3471 | MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.\r | |
| 3472 | MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.\r | |
| 3473 | MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.\r | |
| 3474 | MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.\r | |
| 3475 | MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.\r | |
| 3476 | MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.\r | |
| 3477 | MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.\r | |
| 3478 | MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.\r | |
| 3479 | MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.\r | |
| 3480 | MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.\r | |
| 3481 | MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.\r | |
| 3482 | MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.\r | |
| 3483 | MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.\r | |
| 3484 | MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.\r | |
| 3485 | MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.\r | |
| 04c980a6 MK |
3486 | @{\r |
| 3487 | **/\r | |
| 3488 | #define MSR_IA32_MC0_STATUS 0x00000401\r | |
| 3489 | #define MSR_IA32_MC1_STATUS 0x00000405\r | |
| 3490 | #define MSR_IA32_MC2_STATUS 0x00000409\r | |
| 3491 | #define MSR_IA32_MC3_STATUS 0x0000040D\r | |
| 3492 | #define MSR_IA32_MC4_STATUS 0x00000411\r | |
| 3493 | #define MSR_IA32_MC5_STATUS 0x00000415\r | |
| 3494 | #define MSR_IA32_MC6_STATUS 0x00000419\r | |
| 3495 | #define MSR_IA32_MC7_STATUS 0x0000041D\r | |
| 3496 | #define MSR_IA32_MC8_STATUS 0x00000421\r | |
| 3497 | #define MSR_IA32_MC9_STATUS 0x00000425\r | |
| 3498 | #define MSR_IA32_MC10_STATUS 0x00000429\r | |
| 3499 | #define MSR_IA32_MC11_STATUS 0x0000042D\r | |
| 3500 | #define MSR_IA32_MC12_STATUS 0x00000431\r | |
| 3501 | #define MSR_IA32_MC13_STATUS 0x00000435\r | |
| 3502 | #define MSR_IA32_MC14_STATUS 0x00000439\r | |
| 3503 | #define MSR_IA32_MC15_STATUS 0x0000043D\r | |
| 3504 | #define MSR_IA32_MC16_STATUS 0x00000441\r | |
| 3505 | #define MSR_IA32_MC17_STATUS 0x00000445\r | |
| 3506 | #define MSR_IA32_MC18_STATUS 0x00000449\r | |
| 3507 | #define MSR_IA32_MC19_STATUS 0x0000044D\r | |
| 3508 | #define MSR_IA32_MC20_STATUS 0x00000451\r | |
| 3509 | #define MSR_IA32_MC21_STATUS 0x00000455\r | |
| 3510 | #define MSR_IA32_MC22_STATUS 0x00000459\r | |
| 3511 | #define MSR_IA32_MC23_STATUS 0x0000045D\r | |
| 3512 | #define MSR_IA32_MC24_STATUS 0x00000461\r | |
| 3513 | #define MSR_IA32_MC25_STATUS 0x00000465\r | |
| 3514 | #define MSR_IA32_MC26_STATUS 0x00000469\r | |
| 3515 | #define MSR_IA32_MC27_STATUS 0x0000046D\r | |
| 3516 | #define MSR_IA32_MC28_STATUS 0x00000471\r | |
| 3517 | /// @}\r | |
| 3518 | \r | |
| 3519 | \r | |
| 3520 | /**\r | |
| 3521 | MCn_ADDR. If IA32_MCG_CAP.CNT > n.\r | |
| 3522 | \r | |
| 3523 | @param ECX MSR_IA32_MCn_ADDR\r | |
| 3524 | @param EAX Lower 32-bits of MSR value.\r | |
| 3525 | @param EDX Upper 32-bits of MSR value.\r | |
| 3526 | \r | |
| 3527 | <b>Example usage</b>\r | |
| 3528 | @code\r | |
| 3529 | UINT64 Msr;\r | |
| 3530 | \r | |
| 3531 | Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);\r | |
| 3532 | AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);\r | |
| 3533 | @endcode\r | |
| 7de98828 JF |
3534 | @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM.\r |
| 3535 | MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM.\r | |
| 3536 | MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM.\r | |
| 3537 | MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM.\r | |
| 3538 | MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM.\r | |
| 3539 | MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM.\r | |
| 3540 | MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM.\r | |
| 3541 | MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM.\r | |
| 3542 | MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM.\r | |
| 3543 | MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM.\r | |
| 3544 | MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.\r | |
| 3545 | MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.\r | |
| 3546 | MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.\r | |
| 3547 | MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.\r | |
| 3548 | MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.\r | |
| 3549 | MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.\r | |
| 3550 | MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.\r | |
| 3551 | MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.\r | |
| 3552 | MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.\r | |
| 3553 | MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.\r | |
| 3554 | MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.\r | |
| 3555 | MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.\r | |
| 3556 | MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.\r | |
| 3557 | MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.\r | |
| 3558 | MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.\r | |
| 3559 | MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.\r | |
| 3560 | MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.\r | |
| 3561 | MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.\r | |
| 3562 | MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.\r | |
| 04c980a6 MK |
3563 | @{\r |
| 3564 | **/\r | |
| 3565 | #define MSR_IA32_MC0_ADDR 0x00000402\r | |
| 3566 | #define MSR_IA32_MC1_ADDR 0x00000406\r | |
| 3567 | #define MSR_IA32_MC2_ADDR 0x0000040A\r | |
| 3568 | #define MSR_IA32_MC3_ADDR 0x0000040E\r | |
| 3569 | #define MSR_IA32_MC4_ADDR 0x00000412\r | |
| 3570 | #define MSR_IA32_MC5_ADDR 0x00000416\r | |
| 3571 | #define MSR_IA32_MC6_ADDR 0x0000041A\r | |
| 3572 | #define MSR_IA32_MC7_ADDR 0x0000041E\r | |
| 3573 | #define MSR_IA32_MC8_ADDR 0x00000422\r | |
| 3574 | #define MSR_IA32_MC9_ADDR 0x00000426\r | |
| 3575 | #define MSR_IA32_MC10_ADDR 0x0000042A\r | |
| 3576 | #define MSR_IA32_MC11_ADDR 0x0000042E\r | |
| 3577 | #define MSR_IA32_MC12_ADDR 0x00000432\r | |
| 3578 | #define MSR_IA32_MC13_ADDR 0x00000436\r | |
| 3579 | #define MSR_IA32_MC14_ADDR 0x0000043A\r | |
| 3580 | #define MSR_IA32_MC15_ADDR 0x0000043E\r | |
| 3581 | #define MSR_IA32_MC16_ADDR 0x00000442\r | |
| 3582 | #define MSR_IA32_MC17_ADDR 0x00000446\r | |
| 3583 | #define MSR_IA32_MC18_ADDR 0x0000044A\r | |
| 3584 | #define MSR_IA32_MC19_ADDR 0x0000044E\r | |
| 3585 | #define MSR_IA32_MC20_ADDR 0x00000452\r | |
| 3586 | #define MSR_IA32_MC21_ADDR 0x00000456\r | |
| 3587 | #define MSR_IA32_MC22_ADDR 0x0000045A\r | |
| 3588 | #define MSR_IA32_MC23_ADDR 0x0000045E\r | |
| 3589 | #define MSR_IA32_MC24_ADDR 0x00000462\r | |
| 3590 | #define MSR_IA32_MC25_ADDR 0x00000466\r | |
| 3591 | #define MSR_IA32_MC26_ADDR 0x0000046A\r | |
| 3592 | #define MSR_IA32_MC27_ADDR 0x0000046E\r | |
| 3593 | #define MSR_IA32_MC28_ADDR 0x00000472\r | |
| 3594 | /// @}\r | |
| 3595 | \r | |
| 3596 | \r | |
| 3597 | /**\r | |
| 3598 | MCn_MISC. If IA32_MCG_CAP.CNT > n.\r | |
| 3599 | \r | |
| 3600 | @param ECX MSR_IA32_MCn_MISC\r | |
| 3601 | @param EAX Lower 32-bits of MSR value.\r | |
| 3602 | @param EDX Upper 32-bits of MSR value.\r | |
| 3603 | \r | |
| 3604 | <b>Example usage</b>\r | |
| 3605 | @code\r | |
| 3606 | UINT64 Msr;\r | |
| 3607 | \r | |
| 3608 | Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);\r | |
| 3609 | AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);\r | |
| 3610 | @endcode\r | |
| 7de98828 JF |
3611 | @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM.\r |
| 3612 | MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM.\r | |
| 3613 | MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM.\r | |
| 3614 | MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM.\r | |
| 3615 | MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM.\r | |
| 3616 | MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM.\r | |
| 3617 | MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r | |
| 3618 | MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM.\r | |
| 3619 | MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM.\r | |
| 3620 | MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM.\r | |
| 3621 | MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.\r | |
| 3622 | MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.\r | |
| 3623 | MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.\r | |
| 3624 | MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.\r | |
| 3625 | MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.\r | |
| 3626 | MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.\r | |
| 3627 | MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.\r | |
| 3628 | MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.\r | |
| 3629 | MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.\r | |
| 3630 | MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.\r | |
| 3631 | MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.\r | |
| 3632 | MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.\r | |
| 3633 | MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.\r | |
| 3634 | MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.\r | |
| 3635 | MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.\r | |
| 3636 | MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.\r | |
| 3637 | MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.\r | |
| 3638 | MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.\r | |
| 3639 | MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.\r | |
| 04c980a6 MK |
3640 | @{\r |
| 3641 | **/\r | |
| 3642 | #define MSR_IA32_MC0_MISC 0x00000403\r | |
| 3643 | #define MSR_IA32_MC1_MISC 0x00000407\r | |
| 3644 | #define MSR_IA32_MC2_MISC 0x0000040B\r | |
| 3645 | #define MSR_IA32_MC3_MISC 0x0000040F\r | |
| 3646 | #define MSR_IA32_MC4_MISC 0x00000413\r | |
| 3647 | #define MSR_IA32_MC5_MISC 0x00000417\r | |
| 3648 | #define MSR_IA32_MC6_MISC 0x0000041B\r | |
| 3649 | #define MSR_IA32_MC7_MISC 0x0000041F\r | |
| 3650 | #define MSR_IA32_MC8_MISC 0x00000423\r | |
| 3651 | #define MSR_IA32_MC9_MISC 0x00000427\r | |
| 3652 | #define MSR_IA32_MC10_MISC 0x0000042B\r | |
| 3653 | #define MSR_IA32_MC11_MISC 0x0000042F\r | |
| 3654 | #define MSR_IA32_MC12_MISC 0x00000433\r | |
| 3655 | #define MSR_IA32_MC13_MISC 0x00000437\r | |
| 3656 | #define MSR_IA32_MC14_MISC 0x0000043B\r | |
| 3657 | #define MSR_IA32_MC15_MISC 0x0000043F\r | |
| 3658 | #define MSR_IA32_MC16_MISC 0x00000443\r | |
| 3659 | #define MSR_IA32_MC17_MISC 0x00000447\r | |
| 3660 | #define MSR_IA32_MC18_MISC 0x0000044B\r | |
| 3661 | #define MSR_IA32_MC19_MISC 0x0000044F\r | |
| 3662 | #define MSR_IA32_MC20_MISC 0x00000453\r | |
| 3663 | #define MSR_IA32_MC21_MISC 0x00000457\r | |
| 3664 | #define MSR_IA32_MC22_MISC 0x0000045B\r | |
| 3665 | #define MSR_IA32_MC23_MISC 0x0000045F\r | |
| 3666 | #define MSR_IA32_MC24_MISC 0x00000463\r | |
| 3667 | #define MSR_IA32_MC25_MISC 0x00000467\r | |
| 3668 | #define MSR_IA32_MC26_MISC 0x0000046B\r | |
| 3669 | #define MSR_IA32_MC27_MISC 0x0000046F\r | |
| 3670 | #define MSR_IA32_MC28_MISC 0x00000473\r | |
| 3671 | /// @}\r | |
| 3672 | \r | |
| 3673 | \r | |
| 3674 | /**\r | |
| 3675 | Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic\r | |
| 3676 | VMX Information.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3677 | \r | |
| 3678 | @param ECX MSR_IA32_VMX_BASIC (0x00000480)\r | |
| 3679 | @param EAX Lower 32-bits of MSR value.\r | |
| 3680 | @param EDX Upper 32-bits of MSR value.\r | |
| 3681 | \r | |
| 3682 | <b>Example usage</b>\r | |
| 3683 | @code\r | |
| 3684 | UINT64 Msr;\r | |
| 3685 | \r | |
| 3686 | Msr = AsmReadMsr64 (MSR_IA32_VMX_BASIC);\r | |
| 3687 | @endcode\r | |
| 7de98828 | 3688 | @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.\r |
| 04c980a6 MK |
3689 | **/\r |
| 3690 | #define MSR_IA32_VMX_BASIC 0x00000480\r | |
| 3691 | \r | |
| 3692 | \r | |
| 3693 | /**\r | |
| 3694 | Capability Reporting Register of Pinbased VM-execution Controls (R/O) See\r | |
| 3695 | Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3696 | \r | |
| 3697 | @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)\r | |
| 3698 | @param EAX Lower 32-bits of MSR value.\r | |
| 3699 | @param EDX Upper 32-bits of MSR value.\r | |
| 3700 | \r | |
| 3701 | <b>Example usage</b>\r | |
| 3702 | @code\r | |
| 3703 | UINT64 Msr;\r | |
| 3704 | \r | |
| 3705 | Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);\r | |
| 3706 | @endcode\r | |
| 7de98828 | 3707 | @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.\r |
| 04c980a6 MK |
3708 | **/\r |
| 3709 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481\r | |
| 3710 | \r | |
| 3711 | \r | |
| 3712 | /**\r | |
| 3713 | Capability Reporting Register of Primary Processor-based VM-execution\r | |
| 3714 | Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r | |
| 3715 | Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3716 | \r | |
| 3717 | @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)\r | |
| 3718 | @param EAX Lower 32-bits of MSR value.\r | |
| 3719 | @param EDX Upper 32-bits of MSR value.\r | |
| 3720 | \r | |
| 3721 | <b>Example usage</b>\r | |
| 3722 | @code\r | |
| 3723 | UINT64 Msr;\r | |
| 3724 | \r | |
| 3725 | Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);\r | |
| 3726 | @endcode\r | |
| 7de98828 | 3727 | @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.\r |
| 04c980a6 MK |
3728 | **/\r |
| 3729 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482\r | |
| 3730 | \r | |
| 3731 | \r | |
| 3732 | /**\r | |
| 3733 | Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,\r | |
| 3734 | "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3735 | \r | |
| 3736 | @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)\r | |
| 3737 | @param EAX Lower 32-bits of MSR value.\r | |
| 3738 | @param EDX Upper 32-bits of MSR value.\r | |
| 3739 | \r | |
| 3740 | <b>Example usage</b>\r | |
| 3741 | @code\r | |
| 3742 | UINT64 Msr;\r | |
| 3743 | \r | |
| 3744 | Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);\r | |
| 3745 | @endcode\r | |
| 7de98828 | 3746 | @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.\r |
| 04c980a6 MK |
3747 | **/\r |
| 3748 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483\r | |
| 3749 | \r | |
| 3750 | \r | |
| 3751 | /**\r | |
| 3752 | Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,\r | |
| 3753 | "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3754 | \r | |
| 3755 | @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)\r | |
| 3756 | @param EAX Lower 32-bits of MSR value.\r | |
| 3757 | @param EDX Upper 32-bits of MSR value.\r | |
| 3758 | \r | |
| 3759 | <b>Example usage</b>\r | |
| 3760 | @code\r | |
| 3761 | UINT64 Msr;\r | |
| 3762 | \r | |
| 3763 | Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);\r | |
| 3764 | @endcode\r | |
| 7de98828 | 3765 | @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.\r |
| 04c980a6 MK |
3766 | **/\r |
| 3767 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484\r | |
| 3768 | \r | |
| 3769 | \r | |
| 3770 | /**\r | |
| 3771 | Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,\r | |
| 3772 | "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3773 | \r | |
| 3774 | @param ECX MSR_IA32_VMX_MISC (0x00000485)\r | |
| 3775 | @param EAX Lower 32-bits of MSR value.\r | |
| 3776 | @param EDX Upper 32-bits of MSR value.\r | |
| 3777 | \r | |
| 3778 | <b>Example usage</b>\r | |
| 3779 | @code\r | |
| 3780 | UINT64 Msr;\r | |
| 3781 | \r | |
| 3782 | Msr = AsmReadMsr64 (MSR_IA32_VMX_MISC);\r | |
| 3783 | @endcode\r | |
| 7de98828 | 3784 | @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.\r |
| 04c980a6 MK |
3785 | **/\r |
| 3786 | #define MSR_IA32_VMX_MISC 0x00000485\r | |
| 3787 | \r | |
| 3788 | \r | |
| 3789 | /**\r | |
| 3790 | Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,\r | |
| 3791 | "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3792 | \r | |
| 3793 | @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486)\r | |
| 3794 | @param EAX Lower 32-bits of MSR value.\r | |
| 3795 | @param EDX Upper 32-bits of MSR value.\r | |
| 3796 | \r | |
| 3797 | <b>Example usage</b>\r | |
| 3798 | @code\r | |
| 3799 | UINT64 Msr;\r | |
| 3800 | \r | |
| 3801 | Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);\r | |
| 3802 | @endcode\r | |
| 7de98828 | 3803 | @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.\r |
| 04c980a6 MK |
3804 | **/\r |
| 3805 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486\r | |
| 3806 | \r | |
| 3807 | \r | |
| 3808 | /**\r | |
| 3809 | Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,\r | |
| 3810 | "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3811 | \r | |
| 3812 | @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487)\r | |
| 3813 | @param EAX Lower 32-bits of MSR value.\r | |
| 3814 | @param EDX Upper 32-bits of MSR value.\r | |
| 3815 | \r | |
| 3816 | <b>Example usage</b>\r | |
| 3817 | @code\r | |
| 3818 | UINT64 Msr;\r | |
| 3819 | \r | |
| 3820 | Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);\r | |
| 3821 | @endcode\r | |
| 7de98828 | 3822 | @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.\r |
| 04c980a6 MK |
3823 | **/\r |
| 3824 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487\r | |
| 3825 | \r | |
| 3826 | \r | |
| 3827 | /**\r | |
| 3828 | Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,\r | |
| 3829 | "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3830 | \r | |
| 3831 | @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488)\r | |
| 3832 | @param EAX Lower 32-bits of MSR value.\r | |
| 3833 | @param EDX Upper 32-bits of MSR value.\r | |
| 3834 | \r | |
| 3835 | <b>Example usage</b>\r | |
| 3836 | @code\r | |
| 3837 | UINT64 Msr;\r | |
| 3838 | \r | |
| 3839 | Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);\r | |
| 3840 | @endcode\r | |
| 7de98828 | 3841 | @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.\r |
| 04c980a6 MK |
3842 | **/\r |
| 3843 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488\r | |
| 3844 | \r | |
| 3845 | \r | |
| 3846 | /**\r | |
| 3847 | Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,\r | |
| 3848 | "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3849 | \r | |
| 3850 | @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489)\r | |
| 3851 | @param EAX Lower 32-bits of MSR value.\r | |
| 3852 | @param EDX Upper 32-bits of MSR value.\r | |
| 3853 | \r | |
| 3854 | <b>Example usage</b>\r | |
| 3855 | @code\r | |
| 3856 | UINT64 Msr;\r | |
| 3857 | \r | |
| 3858 | Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);\r | |
| 3859 | @endcode\r | |
| 7de98828 | 3860 | @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.\r |
| 04c980a6 MK |
3861 | **/\r |
| 3862 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489\r | |
| 3863 | \r | |
| 3864 | \r | |
| 3865 | /**\r | |
| 3866 | Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix\r | |
| 3867 | A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3868 | \r | |
| 3869 | @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A)\r | |
| 3870 | @param EAX Lower 32-bits of MSR value.\r | |
| 3871 | @param EDX Upper 32-bits of MSR value.\r | |
| 3872 | \r | |
| 3873 | <b>Example usage</b>\r | |
| 3874 | @code\r | |
| 3875 | UINT64 Msr;\r | |
| 3876 | \r | |
| 3877 | Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);\r | |
| 3878 | @endcode\r | |
| 7de98828 | 3879 | @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.\r |
| 04c980a6 MK |
3880 | **/\r |
| 3881 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048A\r | |
| 3882 | \r | |
| 3883 | \r | |
| 3884 | /**\r | |
| 3885 | Capability Reporting Register of Secondary Processor-based VM-execution\r | |
| 3886 | Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution\r | |
| 3887 | Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).\r | |
| 3888 | \r | |
| 3889 | @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)\r | |
| 3890 | @param EAX Lower 32-bits of MSR value.\r | |
| 3891 | @param EDX Upper 32-bits of MSR value.\r | |
| 3892 | \r | |
| 3893 | <b>Example usage</b>\r | |
| 3894 | @code\r | |
| 3895 | UINT64 Msr;\r | |
| 3896 | \r | |
| 3897 | Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);\r | |
| 3898 | @endcode\r | |
| 7de98828 | 3899 | @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.\r |
| 04c980a6 MK |
3900 | **/\r |
| 3901 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B\r | |
| 3902 | \r | |
| 3903 | \r | |
| 3904 | /**\r | |
| 3905 | Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,\r | |
| 3906 | "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C\r | |
| 3907 | TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).\r | |
| 3908 | \r | |
| 3909 | @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)\r | |
| 3910 | @param EAX Lower 32-bits of MSR value.\r | |
| 3911 | @param EDX Upper 32-bits of MSR value.\r | |
| 3912 | \r | |
| 3913 | <b>Example usage</b>\r | |
| 3914 | @code\r | |
| 3915 | UINT64 Msr;\r | |
| 3916 | \r | |
| 3917 | Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);\r | |
| 3918 | @endcode\r | |
| 7de98828 | 3919 | @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.\r |
| 04c980a6 MK |
3920 | **/\r |
| 3921 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C\r | |
| 3922 | \r | |
| 3923 | \r | |
| 3924 | /**\r | |
| 3925 | Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)\r | |
| 3926 | See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (\r | |
| 3927 | CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
| 3928 | \r | |
| 3929 | @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)\r | |
| 3930 | @param EAX Lower 32-bits of MSR value.\r | |
| 3931 | @param EDX Upper 32-bits of MSR value.\r | |
| 3932 | \r | |
| 3933 | <b>Example usage</b>\r | |
| 3934 | @code\r | |
| 3935 | UINT64 Msr;\r | |
| 3936 | \r | |
| 3937 | Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);\r | |
| 3938 | @endcode\r | |
| 7de98828 | 3939 | @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.\r |
| 04c980a6 MK |
3940 | **/\r |
| 3941 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D\r | |
| 3942 | \r | |
| 3943 | \r | |
| 3944 | /**\r | |
| 3945 | Capability Reporting Register of Primary Processor-based VM-execution Flex\r | |
| 3946 | Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r | |
| 3947 | Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
| 3948 | \r | |
| 3949 | @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)\r | |
| 3950 | @param EAX Lower 32-bits of MSR value.\r | |
| 3951 | @param EDX Upper 32-bits of MSR value.\r | |
| 3952 | \r | |
| 3953 | <b>Example usage</b>\r | |
| 3954 | @code\r | |
| 3955 | UINT64 Msr;\r | |
| 3956 | \r | |
| 3957 | Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);\r | |
| 3958 | @endcode\r | |
| 7de98828 | 3959 | @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.\r |
| 04c980a6 MK |
3960 | **/\r |
| 3961 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E\r | |
| 3962 | \r | |
| 3963 | \r | |
| 3964 | /**\r | |
| 3965 | Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix\r | |
| 3966 | A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
| 3967 | \r | |
| 3968 | @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)\r | |
| 3969 | @param EAX Lower 32-bits of MSR value.\r | |
| 3970 | @param EDX Upper 32-bits of MSR value.\r | |
| 3971 | \r | |
| 3972 | <b>Example usage</b>\r | |
| 3973 | @code\r | |
| 3974 | UINT64 Msr;\r | |
| 3975 | \r | |
| 3976 | Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);\r | |
| 3977 | @endcode\r | |
| 7de98828 | 3978 | @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.\r |
| 04c980a6 MK |
3979 | **/\r |
| 3980 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F\r | |
| 3981 | \r | |
| 3982 | \r | |
| 3983 | /**\r | |
| 3984 | Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix\r | |
| 3985 | A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
| 3986 | \r | |
| 3987 | @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)\r | |
| 3988 | @param EAX Lower 32-bits of MSR value.\r | |
| 3989 | @param EDX Upper 32-bits of MSR value.\r | |
| 3990 | \r | |
| 3991 | <b>Example usage</b>\r | |
| 3992 | @code\r | |
| 3993 | UINT64 Msr;\r | |
| 3994 | \r | |
| 3995 | Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);\r | |
| 3996 | @endcode\r | |
| 7de98828 | 3997 | @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.\r |
| 04c980a6 MK |
3998 | **/\r |
| 3999 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490\r | |
| 4000 | \r | |
| 4001 | \r | |
| 4002 | /**\r | |
| 4003 | Capability Reporting Register of VMfunction Controls (R/O). If(\r | |
| 4004 | CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r | |
| 4005 | \r | |
| 4006 | @param ECX MSR_IA32_VMX_VMFUNC (0x00000491)\r | |
| 4007 | @param EAX Lower 32-bits of MSR value.\r | |
| 4008 | @param EDX Upper 32-bits of MSR value.\r | |
| 4009 | \r | |
| 4010 | <b>Example usage</b>\r | |
| 4011 | @code\r | |
| 4012 | UINT64 Msr;\r | |
| 4013 | \r | |
| 4014 | Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);\r | |
| 4015 | @endcode\r | |
| 7de98828 | 4016 | @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.\r |
| 04c980a6 MK |
4017 | **/\r |
| 4018 | #define MSR_IA32_VMX_VMFUNC 0x00000491\r | |
| 4019 | \r | |
| 4020 | \r | |
| 4021 | /**\r | |
| 4022 | Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&\r | |
| 4023 | IA32_PERF_CAPABILITIES[ 13] = 1.\r | |
| 4024 | \r | |
| 4025 | @param ECX MSR_IA32_A_PMCn\r | |
| 4026 | @param EAX Lower 32-bits of MSR value.\r | |
| 4027 | @param EDX Upper 32-bits of MSR value.\r | |
| 4028 | \r | |
| 4029 | <b>Example usage</b>\r | |
| 4030 | @code\r | |
| 4031 | UINT64 Msr;\r | |
| 4032 | \r | |
| 4033 | Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);\r | |
| 4034 | AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);\r | |
| 4035 | @endcode\r | |
| 7de98828 JF |
4036 | @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.\r |
| 4037 | MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.\r | |
| 4038 | MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.\r | |
| 4039 | MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.\r | |
| 4040 | MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.\r | |
| 4041 | MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.\r | |
| 4042 | MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.\r | |
| 4043 | MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.\r | |
| 04c980a6 MK |
4044 | @{\r |
| 4045 | **/\r | |
| 4046 | #define MSR_IA32_A_PMC0 0x000004C1\r | |
| 4047 | #define MSR_IA32_A_PMC1 0x000004C2\r | |
| 4048 | #define MSR_IA32_A_PMC2 0x000004C3\r | |
| 4049 | #define MSR_IA32_A_PMC3 0x000004C4\r | |
| 4050 | #define MSR_IA32_A_PMC4 0x000004C5\r | |
| 4051 | #define MSR_IA32_A_PMC5 0x000004C6\r | |
| 4052 | #define MSR_IA32_A_PMC6 0x000004C7\r | |
| 4053 | #define MSR_IA32_A_PMC7 0x000004C8\r | |
| 4054 | /// @}\r | |
| 4055 | \r | |
| 4056 | \r | |
| 4057 | /**\r | |
| 4058 | (R/W). If IA32_MCG_CAP.LMCE_P =1.\r | |
| 4059 | \r | |
| 4060 | @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0)\r | |
| 4061 | @param EAX Lower 32-bits of MSR value.\r | |
| 4062 | Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.\r | |
| 4063 | @param EDX Upper 32-bits of MSR value.\r | |
| 4064 | Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.\r | |
| 4065 | \r | |
| 4066 | <b>Example usage</b>\r | |
| 4067 | @code\r | |
| 4068 | MSR_IA32_MCG_EXT_CTL_REGISTER Msr;\r | |
| 4069 | \r | |
| 4070 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);\r | |
| 4071 | AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);\r | |
| 4072 | @endcode\r | |
| 7de98828 | 4073 | @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.\r |
| 04c980a6 MK |
4074 | **/\r |
| 4075 | #define MSR_IA32_MCG_EXT_CTL 0x000004D0\r | |
| 4076 | \r | |
| 4077 | /**\r | |
| 4078 | MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL\r | |
| 4079 | **/\r | |
| 4080 | typedef union {\r | |
| 4081 | ///\r | |
| 4082 | /// Individual bit fields\r | |
| 4083 | ///\r | |
| 4084 | struct {\r | |
| 4085 | ///\r | |
| 4086 | /// [Bit 0] LMCE_EN.\r | |
| 4087 | ///\r | |
| 4088 | UINT32 LMCE_EN:1;\r | |
| 4089 | UINT32 Reserved1:31;\r | |
| 4090 | UINT32 Reserved2:32;\r | |
| 4091 | } Bits;\r | |
| 4092 | ///\r | |
| 4093 | /// All bit fields as a 32-bit value\r | |
| 4094 | ///\r | |
| 4095 | UINT32 Uint32;\r | |
| 4096 | ///\r | |
| 4097 | /// All bit fields as a 64-bit value\r | |
| 4098 | ///\r | |
| 4099 | UINT64 Uint64;\r | |
| 4100 | } MSR_IA32_MCG_EXT_CTL_REGISTER;\r | |
| 4101 | \r | |
| 4102 | \r | |
| 4103 | /**\r | |
| 4104 | Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,\r | |
| 4105 | ECX=0H): EBX[2] = 1.\r | |
| 4106 | \r | |
| 4107 | @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500)\r | |
| 4108 | @param EAX Lower 32-bits of MSR value.\r | |
| 4109 | Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.\r | |
| 4110 | @param EDX Upper 32-bits of MSR value.\r | |
| 4111 | Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.\r | |
| 4112 | \r | |
| 4113 | <b>Example usage</b>\r | |
| 4114 | @code\r | |
| 4115 | MSR_IA32_SGX_SVN_STATUS_REGISTER Msr;\r | |
| 4116 | \r | |
| 4117 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);\r | |
| 4118 | @endcode\r | |
| 7de98828 | 4119 | @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.\r |
| 04c980a6 MK |
4120 | **/\r |
| 4121 | #define MSR_IA32_SGX_SVN_STATUS 0x00000500\r | |
| 4122 | \r | |
| 4123 | /**\r | |
| 4124 | MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS\r | |
| 4125 | **/\r | |
| 4126 | typedef union {\r | |
| 4127 | ///\r | |
| 4128 | /// Individual bit fields\r | |
| 4129 | ///\r | |
| 4130 | struct {\r | |
| 4131 | ///\r | |
| 4132 | /// [Bit 0] Lock. See Section 42.12.3, "Interactions with Authenticated\r | |
| 4133 | /// Code Modules (ACMs)".\r | |
| 4134 | ///\r | |
| 4135 | UINT32 Lock:1;\r | |
| 4136 | UINT32 Reserved1:15;\r | |
| 4137 | ///\r | |
| 4138 | /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.12.3, "Interactions with\r | |
| 4139 | /// Authenticated Code Modules (ACMs)".\r | |
| 4140 | ///\r | |
| 4141 | UINT32 SGX_SVN_SINIT:8;\r | |
| 4142 | UINT32 Reserved2:8;\r | |
| 4143 | UINT32 Reserved3:32;\r | |
| 4144 | } Bits;\r | |
| 4145 | ///\r | |
| 4146 | /// All bit fields as a 32-bit value\r | |
| 4147 | ///\r | |
| 4148 | UINT32 Uint32;\r | |
| 4149 | ///\r | |
| 4150 | /// All bit fields as a 64-bit value\r | |
| 4151 | ///\r | |
| 4152 | UINT64 Uint64;\r | |
| 4153 | } MSR_IA32_SGX_SVN_STATUS_REGISTER;\r | |
| 4154 | \r | |
| 4155 | \r | |
| 4156 | /**\r | |
| 4157 | Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r | |
| 4158 | && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)\r | |
| 4159 | ) ).\r | |
| 4160 | \r | |
| 4161 | @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)\r | |
| 4162 | @param EAX Lower 32-bits of MSR value.\r | |
| 4163 | Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.\r | |
| 4164 | @param EDX Upper 32-bits of MSR value.\r | |
| 4165 | Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.\r | |
| 4166 | \r | |
| 4167 | <b>Example usage</b>\r | |
| 4168 | @code\r | |
| 4169 | MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr;\r | |
| 4170 | \r | |
| 4171 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);\r | |
| 4172 | AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);\r | |
| 4173 | @endcode\r | |
| 7de98828 | 4174 | @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.\r |
| 04c980a6 MK |
4175 | **/\r |
| 4176 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560\r | |
| 4177 | \r | |
| 4178 | /**\r | |
| 4179 | MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE\r | |
| 4180 | **/\r | |
| 4181 | typedef union {\r | |
| 4182 | ///\r | |
| 4183 | /// Individual bit fields\r | |
| 4184 | ///\r | |
| 4185 | struct {\r | |
| 4186 | UINT32 Reserved:7;\r | |
| 4187 | ///\r | |
| 4188 | /// [Bits 31:7] Base physical address.\r | |
| 4189 | ///\r | |
| 4190 | UINT32 Base:25;\r | |
| 4191 | ///\r | |
| 4192 | /// [Bits 63:32] Base physical address.\r | |
| 4193 | ///\r | |
| 4194 | UINT32 BaseHi:32;\r | |
| 4195 | } Bits;\r | |
| 4196 | ///\r | |
| 4197 | /// All bit fields as a 64-bit value\r | |
| 4198 | ///\r | |
| 4199 | UINT64 Uint64;\r | |
| 4200 | } MSR_IA32_RTIT_OUTPUT_BASE_REGISTER;\r | |
| 4201 | \r | |
| 4202 | \r | |
| 4203 | /**\r | |
| 4204 | Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,\r | |
| 4205 | ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)\r | |
| 4206 | (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).\r | |
| 4207 | \r | |
| 4208 | @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)\r | |
| 4209 | @param EAX Lower 32-bits of MSR value.\r | |
| 4210 | Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.\r | |
| 4211 | @param EDX Upper 32-bits of MSR value.\r | |
| 4212 | Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.\r | |
| 4213 | \r | |
| 4214 | <b>Example usage</b>\r | |
| 4215 | @code\r | |
| 4216 | MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr;\r | |
| 4217 | \r | |
| 4218 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);\r | |
| 4219 | AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);\r | |
| 4220 | @endcode\r | |
| 7de98828 | 4221 | @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.\r |
| 04c980a6 MK |
4222 | **/\r |
| 4223 | #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561\r | |
| 4224 | \r | |
| 4225 | /**\r | |
| 4226 | MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS\r | |
| 4227 | **/\r | |
| 4228 | typedef union {\r | |
| 4229 | ///\r | |
| 4230 | /// Individual bit fields\r | |
| 4231 | ///\r | |
| 4232 | struct {\r | |
| 4233 | UINT32 Reserved:7;\r | |
| 4234 | ///\r | |
| 4235 | /// [Bits 31:7] MaskOrTableOffset.\r | |
| 4236 | ///\r | |
| 4237 | UINT32 MaskOrTableOffset:25;\r | |
| 4238 | ///\r | |
| 4239 | /// [Bits 63:32] Output Offset.\r | |
| 4240 | ///\r | |
| 4241 | UINT32 OutputOffset:32;\r | |
| 4242 | } Bits;\r | |
| 4243 | ///\r | |
| 4244 | /// All bit fields as a 64-bit value\r | |
| 4245 | ///\r | |
| 4246 | UINT64 Uint64;\r | |
| 4247 | } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;\r | |
| 4248 | \r | |
| 4249 | \r | |
| 4250 | /**\r | |
| 4251 | Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r | |
| 4252 | \r | |
| 4253 | @param ECX MSR_IA32_RTIT_CTL (0x00000570)\r | |
| 4254 | @param EAX Lower 32-bits of MSR value.\r | |
| 4255 | Described by the type MSR_IA32_RTIT_CTL_REGISTER.\r | |
| 4256 | @param EDX Upper 32-bits of MSR value.\r | |
| 4257 | Described by the type MSR_IA32_RTIT_CTL_REGISTER.\r | |
| 4258 | \r | |
| 4259 | <b>Example usage</b>\r | |
| 4260 | @code\r | |
| 4261 | MSR_IA32_RTIT_CTL_REGISTER Msr;\r | |
| 4262 | \r | |
| 4263 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r | |
| 4264 | AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);\r | |
| 4265 | @endcode\r | |
| 7de98828 | 4266 | @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.\r |
| 04c980a6 MK |
4267 | **/\r |
| 4268 | #define MSR_IA32_RTIT_CTL 0x00000570\r | |
| 4269 | \r | |
| 4270 | /**\r | |
| 4271 | MSR information returned for MSR index #MSR_IA32_RTIT_CTL\r | |
| 4272 | **/\r | |
| 4273 | typedef union {\r | |
| 4274 | ///\r | |
| 4275 | /// Individual bit fields\r | |
| 4276 | ///\r | |
| 4277 | struct {\r | |
| 4278 | ///\r | |
| 4279 | /// [Bit 0] TraceEn.\r | |
| 4280 | ///\r | |
| 4281 | UINT32 TraceEn:1;\r | |
| 4282 | ///\r | |
| 4283 | /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r | |
| 4284 | ///\r | |
| 4285 | UINT32 CYCEn:1;\r | |
| 4286 | ///\r | |
| 4287 | /// [Bit 2] OS.\r | |
| 4288 | ///\r | |
| 4289 | UINT32 OS:1;\r | |
| 4290 | ///\r | |
| 4291 | /// [Bit 3] User.\r | |
| 4292 | ///\r | |
| 4293 | UINT32 User:1;\r | |
| 4294 | UINT32 Reserved1:2;\r | |
| 4295 | ///\r | |
| 4296 | /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).\r | |
| 4297 | ///\r | |
| 4298 | UINT32 FabricEn:1;\r | |
| 4299 | ///\r | |
| 4300 | /// [Bit 7] CR3 filter.\r | |
| 4301 | ///\r | |
| 4302 | UINT32 CR3:1;\r | |
| 4303 | ///\r | |
| 4304 | /// [Bit 8] ToPA.\r | |
| 4305 | ///\r | |
| 4306 | UINT32 ToPA:1;\r | |
| 4307 | ///\r | |
| 4308 | /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r | |
| 4309 | ///\r | |
| 4310 | UINT32 MTCEn:1;\r | |
| 4311 | ///\r | |
| 4312 | /// [Bit 10] TSCEn.\r | |
| 4313 | ///\r | |
| 4314 | UINT32 TSCEn:1;\r | |
| 4315 | ///\r | |
| 4316 | /// [Bit 11] DisRETC.\r | |
| 4317 | ///\r | |
| 4318 | UINT32 DisRETC:1;\r | |
| 4319 | UINT32 Reserved2:1;\r | |
| 4320 | ///\r | |
| 4321 | /// [Bit 13] BranchEn.\r | |
| 4322 | ///\r | |
| 4323 | UINT32 BranchEn:1;\r | |
| 4324 | ///\r | |
| 4325 | /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r | |
| 4326 | ///\r | |
| 4327 | UINT32 MTCFreq:4;\r | |
| 4328 | UINT32 Reserved3:1;\r | |
| 4329 | ///\r | |
| 4330 | /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r | |
| 4331 | ///\r | |
| 4332 | UINT32 CYCThresh:4;\r | |
| 4333 | UINT32 Reserved4:1;\r | |
| 4334 | ///\r | |
| 4335 | /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r | |
| 4336 | ///\r | |
| 4337 | UINT32 PSBFreq:4;\r | |
| 4338 | UINT32 Reserved5:4;\r | |
| 4339 | ///\r | |
| 4340 | /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).\r | |
| 4341 | ///\r | |
| 4342 | UINT32 ADDR0_CFG:4;\r | |
| 4343 | ///\r | |
| 4344 | /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).\r | |
| 4345 | ///\r | |
| 4346 | UINT32 ADDR1_CFG:4;\r | |
| 4347 | ///\r | |
| 4348 | /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).\r | |
| 4349 | ///\r | |
| 4350 | UINT32 ADDR2_CFG:4;\r | |
| 4351 | ///\r | |
| 4352 | /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).\r | |
| 4353 | ///\r | |
| 4354 | UINT32 ADDR3_CFG:4;\r | |
| 4355 | UINT32 Reserved6:16;\r | |
| 4356 | } Bits;\r | |
| 4357 | ///\r | |
| 4358 | /// All bit fields as a 64-bit value\r | |
| 4359 | ///\r | |
| 4360 | UINT64 Uint64;\r | |
| 4361 | } MSR_IA32_RTIT_CTL_REGISTER;\r | |
| 4362 | \r | |
| 4363 | \r | |
| 4364 | /**\r | |
| 4365 | Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r | |
| 4366 | \r | |
| 4367 | @param ECX MSR_IA32_RTIT_STATUS (0x00000571)\r | |
| 4368 | @param EAX Lower 32-bits of MSR value.\r | |
| 4369 | Described by the type MSR_IA32_RTIT_STATUS_REGISTER.\r | |
| 4370 | @param EDX Upper 32-bits of MSR value.\r | |
| 4371 | Described by the type MSR_IA32_RTIT_STATUS_REGISTER.\r | |
| 4372 | \r | |
| 4373 | <b>Example usage</b>\r | |
| 4374 | @code\r | |
| 4375 | MSR_IA32_RTIT_STATUS_REGISTER Msr;\r | |
| 4376 | \r | |
| 4377 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);\r | |
| 4378 | AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);\r | |
| 4379 | @endcode\r | |
| 7de98828 | 4380 | @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.\r |
| 04c980a6 MK |
4381 | **/\r |
| 4382 | #define MSR_IA32_RTIT_STATUS 0x00000571\r | |
| 4383 | \r | |
| 4384 | /**\r | |
| 4385 | MSR information returned for MSR index #MSR_IA32_RTIT_STATUS\r | |
| 4386 | **/\r | |
| 4387 | typedef union {\r | |
| 4388 | ///\r | |
| 4389 | /// Individual bit fields\r | |
| 4390 | ///\r | |
| 4391 | struct {\r | |
| 4392 | ///\r | |
| 4393 | /// [Bit 0] FilterEn, (writes ignored).\r | |
| 4394 | /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).\r | |
| 4395 | ///\r | |
| 4396 | UINT32 FilterEn:1;\r | |
| 4397 | ///\r | |
| 4398 | /// [Bit 1] ContexEn, (writes ignored).\r | |
| 4399 | ///\r | |
| 4400 | UINT32 ContexEn:1;\r | |
| 4401 | ///\r | |
| 4402 | /// [Bit 2] TriggerEn, (writes ignored).\r | |
| 4403 | ///\r | |
| 4404 | UINT32 TriggerEn:1;\r | |
| 4405 | UINT32 Reserved1:1;\r | |
| 4406 | ///\r | |
| 4407 | /// [Bit 4] Error.\r | |
| 4408 | ///\r | |
| 4409 | UINT32 Error:1;\r | |
| 4410 | ///\r | |
| 4411 | /// [Bit 5] Stopped.\r | |
| 4412 | ///\r | |
| 4413 | UINT32 Stopped:1;\r | |
| 4414 | UINT32 Reserved2:26;\r | |
| 4415 | ///\r | |
| 4416 | /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).\r | |
| 4417 | ///\r | |
| 4418 | UINT32 PacketByteCnt:17;\r | |
| 4419 | UINT32 Reserved3:15;\r | |
| 4420 | } Bits;\r | |
| 4421 | ///\r | |
| 4422 | /// All bit fields as a 64-bit value\r | |
| 4423 | ///\r | |
| 4424 | UINT64 Uint64;\r | |
| 4425 | } MSR_IA32_RTIT_STATUS_REGISTER;\r | |
| 4426 | \r | |
| 4427 | \r | |
| 4428 | /**\r | |
| 4429 | Trace Filter CR3 Match Register (R/W).\r | |
| 4430 | If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r | |
| 4431 | \r | |
| 4432 | @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572)\r | |
| 4433 | @param EAX Lower 32-bits of MSR value.\r | |
| 4434 | Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.\r | |
| 4435 | @param EDX Upper 32-bits of MSR value.\r | |
| 4436 | Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.\r | |
| 4437 | \r | |
| 4438 | <b>Example usage</b>\r | |
| 4439 | @code\r | |
| 4440 | MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr;\r | |
| 4441 | \r | |
| 4442 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);\r | |
| 4443 | AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);\r | |
| 4444 | @endcode\r | |
| 7de98828 | 4445 | @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.\r |
| 04c980a6 MK |
4446 | **/\r |
| 4447 | #define MSR_IA32_RTIT_CR3_MATCH 0x00000572\r | |
| 4448 | \r | |
| 4449 | /**\r | |
| 4450 | MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH\r | |
| 4451 | **/\r | |
| 4452 | typedef union {\r | |
| 4453 | ///\r | |
| 4454 | /// Individual bit fields\r | |
| 4455 | ///\r | |
| 4456 | struct {\r | |
| 4457 | UINT32 Reserved:5;\r | |
| 4458 | ///\r | |
| 4459 | /// [Bits 31:5] CR3[63:5] value to match.\r | |
| 4460 | ///\r | |
| 4461 | UINT32 Cr3:27;\r | |
| 4462 | ///\r | |
| 4463 | /// [Bits 63:32] CR3[63:5] value to match.\r | |
| 4464 | ///\r | |
| 4465 | UINT32 Cr3Hi:32;\r | |
| 4466 | } Bits;\r | |
| 4467 | ///\r | |
| 4468 | /// All bit fields as a 64-bit value\r | |
| 4469 | ///\r | |
| 4470 | UINT64 Uint64;\r | |
| 4471 | } MSR_IA32_RTIT_CR3_MATCH_REGISTER;\r | |
| 4472 | \r | |
| 4473 | \r | |
| 4474 | /**\r | |
| 4475 | Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r | |
| 4476 | \r | |
| 4477 | @param ECX MSR_IA32_RTIT_ADDRn_A\r | |
| 4478 | @param EAX Lower 32-bits of MSR value.\r | |
| 4479 | Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r | |
| 4480 | @param EDX Upper 32-bits of MSR value.\r | |
| 4481 | Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r | |
| 4482 | \r | |
| 4483 | <b>Example usage</b>\r | |
| 4484 | @code\r | |
| 4485 | MSR_IA32_RTIT_ADDR_REGISTER Msr;\r | |
| 4486 | \r | |
| 4487 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);\r | |
| 4488 | AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);\r | |
| 4489 | @endcode\r | |
| 7de98828 JF |
4490 | @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.\r |
| 4491 | MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.\r | |
| 4492 | MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.\r | |
| 4493 | MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.\r | |
| 04c980a6 MK |
4494 | @{\r |
| 4495 | **/\r | |
| 4496 | #define MSR_IA32_RTIT_ADDR0_A 0x00000580\r | |
| 4497 | #define MSR_IA32_RTIT_ADDR1_A 0x00000582\r | |
| 4498 | #define MSR_IA32_RTIT_ADDR2_A 0x00000584\r | |
| 4499 | #define MSR_IA32_RTIT_ADDR3_A 0x00000586\r | |
| 4500 | /// @}\r | |
| 4501 | \r | |
| 4502 | \r | |
| 4503 | /**\r | |
| 4504 | Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r | |
| 4505 | \r | |
| 4506 | @param ECX MSR_IA32_RTIT_ADDRn_B\r | |
| 4507 | @param EAX Lower 32-bits of MSR value.\r | |
| 4508 | Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r | |
| 4509 | @param EDX Upper 32-bits of MSR value.\r | |
| 4510 | Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r | |
| 4511 | \r | |
| 4512 | <b>Example usage</b>\r | |
| 4513 | @code\r | |
| 4514 | MSR_IA32_RTIT_ADDR_REGISTER Msr;\r | |
| 4515 | \r | |
| 4516 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);\r | |
| 4517 | AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);\r | |
| 4518 | @endcode\r | |
| 7de98828 JF |
4519 | @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.\r |
| 4520 | MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.\r | |
| 4521 | MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.\r | |
| 4522 | MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.\r | |
| 04c980a6 MK |
4523 | @{\r |
| 4524 | **/\r | |
| 4525 | #define MSR_IA32_RTIT_ADDR0_B 0x00000581\r | |
| 4526 | #define MSR_IA32_RTIT_ADDR1_B 0x00000583\r | |
| 4527 | #define MSR_IA32_RTIT_ADDR2_B 0x00000585\r | |
| 4528 | #define MSR_IA32_RTIT_ADDR3_B 0x00000587\r | |
| 4529 | /// @}\r | |
| 4530 | \r | |
| 4531 | \r | |
| 4532 | /**\r | |
| 4533 | MSR information returned for MSR indexes\r | |
| 4534 | #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and\r | |
| 4535 | #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B\r | |
| 4536 | **/\r | |
| 4537 | typedef union {\r | |
| 4538 | ///\r | |
| 4539 | /// Individual bit fields\r | |
| 4540 | ///\r | |
| 4541 | struct {\r | |
| 4542 | ///\r | |
| 4543 | /// [Bits 31:0] Virtual Address.\r | |
| 4544 | ///\r | |
| 4545 | UINT32 VirtualAddress:32;\r | |
| 4546 | ///\r | |
| 4547 | /// [Bits 47:32] Virtual Address.\r | |
| 4548 | ///\r | |
| 4549 | UINT32 VirtualAddressHi:16;\r | |
| 4550 | ///\r | |
| 4551 | /// [Bits 63:48] SignExt_VA.\r | |
| 4552 | ///\r | |
| 4553 | UINT32 SignExt_VA:16;\r | |
| 4554 | } Bits;\r | |
| 4555 | ///\r | |
| 4556 | /// All bit fields as a 64-bit value\r | |
| 4557 | ///\r | |
| 4558 | UINT64 Uint64;\r | |
| 4559 | } MSR_IA32_RTIT_ADDR_REGISTER;\r | |
| 4560 | \r | |
| 4561 | \r | |
| 4562 | /**\r | |
| 4563 | DS Save Area (R/W) Points to the linear address of the first byte of the DS\r | |
| 4564 | buffer management area, which is used to manage the BTS and PEBS buffers.\r | |
| 4565 | See Section 18.12.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]\r | |
| 4566 | = 1.\r | |
| 4567 | \r | |
| 4568 | [Bits 31..0] The linear address of the first byte of the DS buffer\r | |
| 4569 | management area, if not in IA-32e mode.\r | |
| 4570 | \r | |
| 4571 | [Bits 63..0] The linear address of the first byte of the DS buffer\r | |
| 4572 | management area, if IA-32e mode is active.\r | |
| 4573 | \r | |
| 4574 | @param ECX MSR_IA32_DS_AREA (0x00000600)\r | |
| 4575 | @param EAX Lower 32-bits of MSR value.\r | |
| 4576 | Described by the type MSR_IA32_DS_AREA_REGISTER.\r | |
| 4577 | @param EDX Upper 32-bits of MSR value.\r | |
| 4578 | Described by the type MSR_IA32_DS_AREA_REGISTER.\r | |
| 4579 | \r | |
| 4580 | <b>Example usage</b>\r | |
| 4581 | @code\r | |
| 4582 | UINT64 Msr;\r | |
| 4583 | \r | |
| 4584 | Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);\r | |
| 4585 | AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);\r | |
| 4586 | @endcode\r | |
| 7de98828 | 4587 | @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.\r |
| 04c980a6 MK |
4588 | **/\r |
| 4589 | #define MSR_IA32_DS_AREA 0x00000600\r | |
| 4590 | \r | |
| 4591 | \r | |
| 4592 | /**\r | |
| 4593 | TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =\r | |
| 4594 | 1.\r | |
| 4595 | \r | |
| 4596 | @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0)\r | |
| 4597 | @param EAX Lower 32-bits of MSR value.\r | |
| 4598 | @param EDX Upper 32-bits of MSR value.\r | |
| 4599 | \r | |
| 4600 | <b>Example usage</b>\r | |
| 4601 | @code\r | |
| 4602 | UINT64 Msr;\r | |
| 4603 | \r | |
| 4604 | Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);\r | |
| 4605 | AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);\r | |
| 4606 | @endcode\r | |
| 7de98828 | 4607 | @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.\r |
| 04c980a6 MK |
4608 | **/\r |
| 4609 | #define MSR_IA32_TSC_DEADLINE 0x000006E0\r | |
| 4610 | \r | |
| 4611 | \r | |
| 4612 | /**\r | |
| 4613 | Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.\r | |
| 4614 | \r | |
| 4615 | @param ECX MSR_IA32_PM_ENABLE (0x00000770)\r | |
| 4616 | @param EAX Lower 32-bits of MSR value.\r | |
| 4617 | Described by the type MSR_IA32_PM_ENABLE_REGISTER.\r | |
| 4618 | @param EDX Upper 32-bits of MSR value.\r | |
| 4619 | Described by the type MSR_IA32_PM_ENABLE_REGISTER.\r | |
| 4620 | \r | |
| 4621 | <b>Example usage</b>\r | |
| 4622 | @code\r | |
| 4623 | MSR_IA32_PM_ENABLE_REGISTER Msr;\r | |
| 4624 | \r | |
| 4625 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);\r | |
| 4626 | AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);\r | |
| 4627 | @endcode\r | |
| 7de98828 | 4628 | @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.\r |
| 04c980a6 MK |
4629 | **/\r |
| 4630 | #define MSR_IA32_PM_ENABLE 0x00000770\r | |
| 4631 | \r | |
| 4632 | /**\r | |
| 4633 | MSR information returned for MSR index #MSR_IA32_PM_ENABLE\r | |
| 4634 | **/\r | |
| 4635 | typedef union {\r | |
| 4636 | ///\r | |
| 4637 | /// Individual bit fields\r | |
| 4638 | ///\r | |
| 4639 | struct {\r | |
| 4640 | ///\r | |
| 4641 | /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If\r | |
| 4642 | /// CPUID.06H:EAX.[7] = 1.\r | |
| 4643 | ///\r | |
| 4644 | UINT32 HWP_ENABLE:1;\r | |
| 4645 | UINT32 Reserved1:31;\r | |
| 4646 | UINT32 Reserved2:32;\r | |
| 4647 | } Bits;\r | |
| 4648 | ///\r | |
| 4649 | /// All bit fields as a 32-bit value\r | |
| 4650 | ///\r | |
| 4651 | UINT32 Uint32;\r | |
| 4652 | ///\r | |
| 4653 | /// All bit fields as a 64-bit value\r | |
| 4654 | ///\r | |
| 4655 | UINT64 Uint64;\r | |
| 4656 | } MSR_IA32_PM_ENABLE_REGISTER;\r | |
| 4657 | \r | |
| 4658 | \r | |
| 4659 | /**\r | |
| 4660 | HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.\r | |
| 4661 | \r | |
| 4662 | @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771)\r | |
| 4663 | @param EAX Lower 32-bits of MSR value.\r | |
| 4664 | Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.\r | |
| 4665 | @param EDX Upper 32-bits of MSR value.\r | |
| 4666 | Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.\r | |
| 4667 | \r | |
| 4668 | <b>Example usage</b>\r | |
| 4669 | @code\r | |
| 4670 | MSR_IA32_HWP_CAPABILITIES_REGISTER Msr;\r | |
| 4671 | \r | |
| 4672 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);\r | |
| 4673 | @endcode\r | |
| 7de98828 | 4674 | @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.\r |
| 04c980a6 MK |
4675 | **/\r |
| 4676 | #define MSR_IA32_HWP_CAPABILITIES 0x00000771\r | |
| 4677 | \r | |
| 4678 | /**\r | |
| 4679 | MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES\r | |
| 4680 | **/\r | |
| 4681 | typedef union {\r | |
| 4682 | ///\r | |
| 4683 | /// Individual bit fields\r | |
| 4684 | ///\r | |
| 4685 | struct {\r | |
| 4686 | ///\r | |
| 4687 | /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance\r | |
| 4688 | /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r | |
| 4689 | ///\r | |
| 4690 | UINT32 Highest_Performance:8;\r | |
| 4691 | ///\r | |
| 4692 | /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP\r | |
| 4693 | /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r | |
| 4694 | ///\r | |
| 4695 | UINT32 Guaranteed_Performance:8;\r | |
| 4696 | ///\r | |
| 4697 | /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP\r | |
| 4698 | /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r | |
| 4699 | ///\r | |
| 4700 | UINT32 Most_Efficient_Performance:8;\r | |
| 4701 | ///\r | |
| 4702 | /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance\r | |
| 4703 | /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r | |
| 4704 | ///\r | |
| 4705 | UINT32 Lowest_Performance:8;\r | |
| 4706 | UINT32 Reserved:32;\r | |
| 4707 | } Bits;\r | |
| 4708 | ///\r | |
| 4709 | /// All bit fields as a 32-bit value\r | |
| 4710 | ///\r | |
| 4711 | UINT32 Uint32;\r | |
| 4712 | ///\r | |
| 4713 | /// All bit fields as a 64-bit value\r | |
| 4714 | ///\r | |
| 4715 | UINT64 Uint64;\r | |
| 4716 | } MSR_IA32_HWP_CAPABILITIES_REGISTER;\r | |
| 4717 | \r | |
| 4718 | \r | |
| 4719 | /**\r | |
| 4720 | Power Management Control Hints for All Logical Processors in a Package\r | |
| 4721 | (R/W). If CPUID.06H:EAX.[11] = 1.\r | |
| 4722 | \r | |
| 4723 | @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772)\r | |
| 4724 | @param EAX Lower 32-bits of MSR value.\r | |
| 4725 | Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.\r | |
| 4726 | @param EDX Upper 32-bits of MSR value.\r | |
| 4727 | Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.\r | |
| 4728 | \r | |
| 4729 | <b>Example usage</b>\r | |
| 4730 | @code\r | |
| 4731 | MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr;\r | |
| 4732 | \r | |
| 4733 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);\r | |
| 4734 | AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);\r | |
| 4735 | @endcode\r | |
| 7de98828 | 4736 | @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.\r |
| 04c980a6 MK |
4737 | **/\r |
| 4738 | #define MSR_IA32_HWP_REQUEST_PKG 0x00000772\r | |
| 4739 | \r | |
| 4740 | /**\r | |
| 4741 | MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG\r | |
| 4742 | **/\r | |
| 4743 | typedef union {\r | |
| 4744 | ///\r | |
| 4745 | /// Individual bit fields\r | |
| 4746 | ///\r | |
| 4747 | struct {\r | |
| 4748 | ///\r | |
| 4749 | /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r | |
| 4750 | /// CPUID.06H:EAX.[11] = 1.\r | |
| 4751 | ///\r | |
| 4752 | UINT32 Minimum_Performance:8;\r | |
| 4753 | ///\r | |
| 4754 | /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r | |
| 4755 | /// CPUID.06H:EAX.[11] = 1.\r | |
| 4756 | ///\r | |
| 4757 | UINT32 Maximum_Performance:8;\r | |
| 4758 | ///\r | |
| 4759 | /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r | |
| 4760 | /// If CPUID.06H:EAX.[11] = 1.\r | |
| 4761 | ///\r | |
| 4762 | UINT32 Desired_Performance:8;\r | |
| 4763 | ///\r | |
| 4764 | /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r | |
| 4765 | /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.\r | |
| 4766 | ///\r | |
| 4767 | UINT32 Energy_Performance_Preference:8;\r | |
| 4768 | ///\r | |
| 4769 | /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r | |
| 4770 | /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.\r | |
| 4771 | ///\r | |
| 4772 | UINT32 Activity_Window:10;\r | |
| 4773 | UINT32 Reserved:22;\r | |
| 4774 | } Bits;\r | |
| 4775 | ///\r | |
| 4776 | /// All bit fields as a 64-bit value\r | |
| 4777 | ///\r | |
| 4778 | UINT64 Uint64;\r | |
| 4779 | } MSR_IA32_HWP_REQUEST_PKG_REGISTER;\r | |
| 4780 | \r | |
| 4781 | \r | |
| 4782 | /**\r | |
| 4783 | Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.\r | |
| 4784 | \r | |
| 4785 | @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773)\r | |
| 4786 | @param EAX Lower 32-bits of MSR value.\r | |
| 4787 | Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.\r | |
| 4788 | @param EDX Upper 32-bits of MSR value.\r | |
| 4789 | Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.\r | |
| 4790 | \r | |
| 4791 | <b>Example usage</b>\r | |
| 4792 | @code\r | |
| 4793 | MSR_IA32_HWP_INTERRUPT_REGISTER Msr;\r | |
| 4794 | \r | |
| 4795 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);\r | |
| 4796 | AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);\r | |
| 4797 | @endcode\r | |
| 7de98828 | 4798 | @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.\r |
| 04c980a6 MK |
4799 | **/\r |
| 4800 | #define MSR_IA32_HWP_INTERRUPT 0x00000773\r | |
| 4801 | \r | |
| 4802 | /**\r | |
| 4803 | MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT\r | |
| 4804 | **/\r | |
| 4805 | typedef union {\r | |
| 4806 | ///\r | |
| 4807 | /// Individual bit fields\r | |
| 4808 | ///\r | |
| 4809 | struct {\r | |
| 4810 | ///\r | |
| 4811 | /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP\r | |
| 4812 | /// Notifications". If CPUID.06H:EAX.[8] = 1.\r | |
| 4813 | ///\r | |
| 4814 | UINT32 EN_Guaranteed_Performance_Change:1;\r | |
| 4815 | ///\r | |
| 4816 | /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".\r | |
| 4817 | /// If CPUID.06H:EAX.[8] = 1.\r | |
| 4818 | ///\r | |
| 4819 | UINT32 EN_Excursion_Minimum:1;\r | |
| 4820 | UINT32 Reserved1:30;\r | |
| 4821 | UINT32 Reserved2:32;\r | |
| 4822 | } Bits;\r | |
| 4823 | ///\r | |
| 4824 | /// All bit fields as a 32-bit value\r | |
| 4825 | ///\r | |
| 4826 | UINT32 Uint32;\r | |
| 4827 | ///\r | |
| 4828 | /// All bit fields as a 64-bit value\r | |
| 4829 | ///\r | |
| 4830 | UINT64 Uint64;\r | |
| 4831 | } MSR_IA32_HWP_INTERRUPT_REGISTER;\r | |
| 4832 | \r | |
| 4833 | \r | |
| 4834 | /**\r | |
| 4835 | Power Management Control Hints to a Logical Processor (R/W). If\r | |
| 4836 | CPUID.06H:EAX.[7] = 1.\r | |
| 4837 | \r | |
| 4838 | @param ECX MSR_IA32_HWP_REQUEST (0x00000774)\r | |
| 4839 | @param EAX Lower 32-bits of MSR value.\r | |
| 4840 | Described by the type MSR_IA32_HWP_REQUEST_REGISTER.\r | |
| 4841 | @param EDX Upper 32-bits of MSR value.\r | |
| 4842 | Described by the type MSR_IA32_HWP_REQUEST_REGISTER.\r | |
| 4843 | \r | |
| 4844 | <b>Example usage</b>\r | |
| 4845 | @code\r | |
| 4846 | MSR_IA32_HWP_REQUEST_REGISTER Msr;\r | |
| 4847 | \r | |
| 4848 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);\r | |
| 4849 | AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);\r | |
| 4850 | @endcode\r | |
| 7de98828 | 4851 | @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.\r |
| 04c980a6 MK |
4852 | **/\r |
| 4853 | #define MSR_IA32_HWP_REQUEST 0x00000774\r | |
| 4854 | \r | |
| 4855 | /**\r | |
| 4856 | MSR information returned for MSR index #MSR_IA32_HWP_REQUEST\r | |
| 4857 | **/\r | |
| 4858 | typedef union {\r | |
| 4859 | ///\r | |
| 4860 | /// Individual bit fields\r | |
| 4861 | ///\r | |
| 4862 | struct {\r | |
| 4863 | ///\r | |
| 4864 | /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r | |
| 4865 | /// CPUID.06H:EAX.[7] = 1.\r | |
| 4866 | ///\r | |
| 4867 | UINT32 Minimum_Performance:8;\r | |
| 4868 | ///\r | |
| 4869 | /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r | |
| 4870 | /// CPUID.06H:EAX.[7] = 1.\r | |
| 4871 | ///\r | |
| 4872 | UINT32 Maximum_Performance:8;\r | |
| 4873 | ///\r | |
| 4874 | /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r | |
| 4875 | /// If CPUID.06H:EAX.[7] = 1.\r | |
| 4876 | ///\r | |
| 4877 | UINT32 Desired_Performance:8;\r | |
| 4878 | ///\r | |
| 4879 | /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r | |
| 4880 | /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.\r | |
| 4881 | ///\r | |
| 4882 | UINT32 Energy_Performance_Preference:8;\r | |
| 4883 | ///\r | |
| 4884 | /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r | |
| 4885 | /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.\r | |
| 4886 | ///\r | |
| 4887 | UINT32 Activity_Window:10;\r | |
| 4888 | ///\r | |
| 4889 | /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If\r | |
| 4890 | /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.\r | |
| 4891 | ///\r | |
| 4892 | UINT32 Package_Control:1;\r | |
| 4893 | UINT32 Reserved:21;\r | |
| 4894 | } Bits;\r | |
| 4895 | ///\r | |
| 4896 | /// All bit fields as a 64-bit value\r | |
| 4897 | ///\r | |
| 4898 | UINT64 Uint64;\r | |
| 4899 | } MSR_IA32_HWP_REQUEST_REGISTER;\r | |
| 4900 | \r | |
| 4901 | \r | |
| 4902 | /**\r | |
| 4903 | Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If\r | |
| 4904 | CPUID.06H:EAX.[7] = 1.\r | |
| 4905 | \r | |
| 4906 | @param ECX MSR_IA32_HWP_STATUS (0x00000777)\r | |
| 4907 | @param EAX Lower 32-bits of MSR value.\r | |
| 4908 | Described by the type MSR_IA32_HWP_STATUS_REGISTER.\r | |
| 4909 | @param EDX Upper 32-bits of MSR value.\r | |
| 4910 | Described by the type MSR_IA32_HWP_STATUS_REGISTER.\r | |
| 4911 | \r | |
| 4912 | <b>Example usage</b>\r | |
| 4913 | @code\r | |
| 4914 | MSR_IA32_HWP_STATUS_REGISTER Msr;\r | |
| 4915 | \r | |
| 4916 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);\r | |
| 4917 | AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);\r | |
| 4918 | @endcode\r | |
| 7de98828 | 4919 | @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.\r |
| 04c980a6 MK |
4920 | **/\r |
| 4921 | #define MSR_IA32_HWP_STATUS 0x00000777\r | |
| 4922 | \r | |
| 4923 | /**\r | |
| 4924 | MSR information returned for MSR index #MSR_IA32_HWP_STATUS\r | |
| 4925 | **/\r | |
| 4926 | typedef union {\r | |
| 4927 | ///\r | |
| 4928 | /// Individual bit fields\r | |
| 4929 | ///\r | |
| 4930 | struct {\r | |
| 4931 | ///\r | |
| 4932 | /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,\r | |
| 4933 | /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.\r | |
| 4934 | ///\r | |
| 4935 | UINT32 Guaranteed_Performance_Change:1;\r | |
| 4936 | UINT32 Reserved1:1;\r | |
| 4937 | ///\r | |
| 4938 | /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP\r | |
| 4939 | /// Feedback". If CPUID.06H:EAX.[7] = 1.\r | |
| 4940 | ///\r | |
| 4941 | UINT32 Excursion_To_Minimum:1;\r | |
| 4942 | UINT32 Reserved2:29;\r | |
| 4943 | UINT32 Reserved3:32;\r | |
| 4944 | } Bits;\r | |
| 4945 | ///\r | |
| 4946 | /// All bit fields as a 32-bit value\r | |
| 4947 | ///\r | |
| 4948 | UINT32 Uint32;\r | |
| 4949 | ///\r | |
| 4950 | /// All bit fields as a 64-bit value\r | |
| 4951 | ///\r | |
| 4952 | UINT64 Uint64;\r | |
| 4953 | } MSR_IA32_HWP_STATUS_REGISTER;\r | |
| 4954 | \r | |
| 4955 | \r | |
| 4956 | /**\r | |
| 4957 | x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1\r | |
| 4958 | && IA32_APIC_BASE.[10] = 1.\r | |
| 4959 | \r | |
| 4960 | @param ECX MSR_IA32_X2APIC_APICID (0x00000802)\r | |
| 4961 | @param EAX Lower 32-bits of MSR value.\r | |
| 4962 | @param EDX Upper 32-bits of MSR value.\r | |
| 4963 | \r | |
| 4964 | <b>Example usage</b>\r | |
| 4965 | @code\r | |
| 4966 | UINT64 Msr;\r | |
| 4967 | \r | |
| 4968 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);\r | |
| 4969 | @endcode\r | |
| 7de98828 | 4970 | @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.\r |
| 04c980a6 MK |
4971 | **/\r |
| 4972 | #define MSR_IA32_X2APIC_APICID 0x00000802\r | |
| 4973 | \r | |
| 4974 | \r | |
| 4975 | /**\r | |
| 4976 | x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 4977 | IA32_APIC_BASE.[10] = 1.\r | |
| 4978 | \r | |
| 4979 | @param ECX MSR_IA32_X2APIC_VERSION (0x00000803)\r | |
| 4980 | @param EAX Lower 32-bits of MSR value.\r | |
| 4981 | @param EDX Upper 32-bits of MSR value.\r | |
| 4982 | \r | |
| 4983 | <b>Example usage</b>\r | |
| 4984 | @code\r | |
| 4985 | UINT64 Msr;\r | |
| 4986 | \r | |
| 4987 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);\r | |
| 4988 | @endcode\r | |
| 7de98828 | 4989 | @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.\r |
| 04c980a6 MK |
4990 | **/\r |
| 4991 | #define MSR_IA32_X2APIC_VERSION 0x00000803\r | |
| 4992 | \r | |
| 4993 | \r | |
| 4994 | /**\r | |
| 4995 | x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 4996 | IA32_APIC_BASE.[10] = 1.\r | |
| 4997 | \r | |
| 4998 | @param ECX MSR_IA32_X2APIC_TPR (0x00000808)\r | |
| 4999 | @param EAX Lower 32-bits of MSR value.\r | |
| 5000 | @param EDX Upper 32-bits of MSR value.\r | |
| 5001 | \r | |
| 5002 | <b>Example usage</b>\r | |
| 5003 | @code\r | |
| 5004 | UINT64 Msr;\r | |
| 5005 | \r | |
| 5006 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);\r | |
| 5007 | AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);\r | |
| 5008 | @endcode\r | |
| 7de98828 | 5009 | @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.\r |
| 04c980a6 MK |
5010 | **/\r |
| 5011 | #define MSR_IA32_X2APIC_TPR 0x00000808\r | |
| 5012 | \r | |
| 5013 | \r | |
| 5014 | /**\r | |
| 5015 | x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5016 | IA32_APIC_BASE.[10] = 1.\r | |
| 5017 | \r | |
| 5018 | @param ECX MSR_IA32_X2APIC_PPR (0x0000080A)\r | |
| 5019 | @param EAX Lower 32-bits of MSR value.\r | |
| 5020 | @param EDX Upper 32-bits of MSR value.\r | |
| 5021 | \r | |
| 5022 | <b>Example usage</b>\r | |
| 5023 | @code\r | |
| 5024 | UINT64 Msr;\r | |
| 5025 | \r | |
| 5026 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);\r | |
| 5027 | @endcode\r | |
| 7de98828 | 5028 | @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.\r |
| 04c980a6 MK |
5029 | **/\r |
| 5030 | #define MSR_IA32_X2APIC_PPR 0x0000080A\r | |
| 5031 | \r | |
| 5032 | \r | |
| 5033 | /**\r | |
| 5034 | x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]\r | |
| 5035 | = 1.\r | |
| 5036 | \r | |
| 5037 | @param ECX MSR_IA32_X2APIC_EOI (0x0000080B)\r | |
| 5038 | @param EAX Lower 32-bits of MSR value.\r | |
| 5039 | @param EDX Upper 32-bits of MSR value.\r | |
| 5040 | \r | |
| 5041 | <b>Example usage</b>\r | |
| 5042 | @code\r | |
| 5043 | UINT64 Msr;\r | |
| 5044 | \r | |
| 5045 | Msr = 0;\r | |
| 5046 | AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);\r | |
| 5047 | @endcode\r | |
| 7de98828 | 5048 | @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.\r |
| 04c980a6 MK |
5049 | **/\r |
| 5050 | #define MSR_IA32_X2APIC_EOI 0x0000080B\r | |
| 5051 | \r | |
| 5052 | \r | |
| 5053 | /**\r | |
| 5054 | x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5055 | IA32_APIC_BASE.[10] = 1.\r | |
| 5056 | \r | |
| 5057 | @param ECX MSR_IA32_X2APIC_LDR (0x0000080D)\r | |
| 5058 | @param EAX Lower 32-bits of MSR value.\r | |
| 5059 | @param EDX Upper 32-bits of MSR value.\r | |
| 5060 | \r | |
| 5061 | <b>Example usage</b>\r | |
| 5062 | @code\r | |
| 5063 | UINT64 Msr;\r | |
| 5064 | \r | |
| 5065 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);\r | |
| 5066 | @endcode\r | |
| 7de98828 | 5067 | @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.\r |
| 04c980a6 MK |
5068 | **/\r |
| 5069 | #define MSR_IA32_X2APIC_LDR 0x0000080D\r | |
| 5070 | \r | |
| 5071 | \r | |
| 5072 | /**\r | |
| 5073 | x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1\r | |
| 5074 | && IA32_APIC_BASE.[10] = 1.\r | |
| 5075 | \r | |
| 5076 | @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F)\r | |
| 5077 | @param EAX Lower 32-bits of MSR value.\r | |
| 5078 | @param EDX Upper 32-bits of MSR value.\r | |
| 5079 | \r | |
| 5080 | <b>Example usage</b>\r | |
| 5081 | @code\r | |
| 5082 | UINT64 Msr;\r | |
| 5083 | \r | |
| 5084 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);\r | |
| 5085 | AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);\r | |
| 5086 | @endcode\r | |
| 7de98828 | 5087 | @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.\r |
| 04c980a6 MK |
5088 | **/\r |
| 5089 | #define MSR_IA32_X2APIC_SIVR 0x0000080F\r | |
| 5090 | \r | |
| 5091 | \r | |
| 5092 | /**\r | |
| 5093 | x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).\r | |
| 5094 | If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5095 | \r | |
| 5096 | @param ECX MSR_IA32_X2APIC_ISRn\r | |
| 5097 | @param EAX Lower 32-bits of MSR value.\r | |
| 5098 | @param EDX Upper 32-bits of MSR value.\r | |
| 5099 | \r | |
| 5100 | <b>Example usage</b>\r | |
| 5101 | @code\r | |
| 5102 | UINT64 Msr;\r | |
| 5103 | \r | |
| 5104 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);\r | |
| 5105 | @endcode\r | |
| 7de98828 JF |
5106 | @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.\r |
| 5107 | MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.\r | |
| 5108 | MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.\r | |
| 5109 | MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.\r | |
| 5110 | MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.\r | |
| 5111 | MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.\r | |
| 5112 | MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.\r | |
| 5113 | MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.\r | |
| 04c980a6 MK |
5114 | @{\r |
| 5115 | **/\r | |
| 5116 | #define MSR_IA32_X2APIC_ISR0 0x00000810\r | |
| 5117 | #define MSR_IA32_X2APIC_ISR1 0x00000811\r | |
| 5118 | #define MSR_IA32_X2APIC_ISR2 0x00000812\r | |
| 5119 | #define MSR_IA32_X2APIC_ISR3 0x00000813\r | |
| 5120 | #define MSR_IA32_X2APIC_ISR4 0x00000814\r | |
| 5121 | #define MSR_IA32_X2APIC_ISR5 0x00000815\r | |
| 5122 | #define MSR_IA32_X2APIC_ISR6 0x00000816\r | |
| 5123 | #define MSR_IA32_X2APIC_ISR7 0x00000817\r | |
| 5124 | /// @}\r | |
| 5125 | \r | |
| 5126 | \r | |
| 5127 | /**\r | |
| 5128 | x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).\r | |
| 5129 | If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5130 | \r | |
| 5131 | @param ECX MSR_IA32_X2APIC_TMRn\r | |
| 5132 | @param EAX Lower 32-bits of MSR value.\r | |
| 5133 | @param EDX Upper 32-bits of MSR value.\r | |
| 5134 | \r | |
| 5135 | <b>Example usage</b>\r | |
| 5136 | @code\r | |
| 5137 | UINT64 Msr;\r | |
| 5138 | \r | |
| 5139 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);\r | |
| 5140 | @endcode\r | |
| 7de98828 JF |
5141 | @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.\r |
| 5142 | MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.\r | |
| 5143 | MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.\r | |
| 5144 | MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.\r | |
| 5145 | MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.\r | |
| 5146 | MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.\r | |
| 5147 | MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.\r | |
| 5148 | MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.\r | |
| 04c980a6 MK |
5149 | @{\r |
| 5150 | **/\r | |
| 5151 | #define MSR_IA32_X2APIC_TMR0 0x00000818\r | |
| 5152 | #define MSR_IA32_X2APIC_TMR1 0x00000819\r | |
| 5153 | #define MSR_IA32_X2APIC_TMR2 0x0000081A\r | |
| 5154 | #define MSR_IA32_X2APIC_TMR3 0x0000081B\r | |
| 5155 | #define MSR_IA32_X2APIC_TMR4 0x0000081C\r | |
| 5156 | #define MSR_IA32_X2APIC_TMR5 0x0000081D\r | |
| 5157 | #define MSR_IA32_X2APIC_TMR6 0x0000081E\r | |
| 5158 | #define MSR_IA32_X2APIC_TMR7 0x0000081F\r | |
| 5159 | /// @}\r | |
| 5160 | \r | |
| 5161 | \r | |
| 5162 | /**\r | |
| 5163 | x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).\r | |
| 5164 | If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5165 | \r | |
| 5166 | @param ECX MSR_IA32_X2APIC_IRRn\r | |
| 5167 | @param EAX Lower 32-bits of MSR value.\r | |
| 5168 | @param EDX Upper 32-bits of MSR value.\r | |
| 5169 | \r | |
| 5170 | <b>Example usage</b>\r | |
| 5171 | @code\r | |
| 5172 | UINT64 Msr;\r | |
| 5173 | \r | |
| 5174 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);\r | |
| 5175 | @endcode\r | |
| 7de98828 JF |
5176 | @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.\r |
| 5177 | MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.\r | |
| 5178 | MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.\r | |
| 5179 | MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.\r | |
| 5180 | MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.\r | |
| 5181 | MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.\r | |
| 5182 | MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.\r | |
| 5183 | MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.\r | |
| 04c980a6 MK |
5184 | @{\r |
| 5185 | **/\r | |
| 5186 | #define MSR_IA32_X2APIC_IRR0 0x00000820\r | |
| 5187 | #define MSR_IA32_X2APIC_IRR1 0x00000821\r | |
| 5188 | #define MSR_IA32_X2APIC_IRR2 0x00000822\r | |
| 5189 | #define MSR_IA32_X2APIC_IRR3 0x00000823\r | |
| 5190 | #define MSR_IA32_X2APIC_IRR4 0x00000824\r | |
| 5191 | #define MSR_IA32_X2APIC_IRR5 0x00000825\r | |
| 5192 | #define MSR_IA32_X2APIC_IRR6 0x00000826\r | |
| 5193 | #define MSR_IA32_X2APIC_IRR7 0x00000827\r | |
| 5194 | /// @}\r | |
| 5195 | \r | |
| 5196 | \r | |
| 5197 | /**\r | |
| 5198 | x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5199 | IA32_APIC_BASE.[10] = 1.\r | |
| 5200 | \r | |
| 5201 | @param ECX MSR_IA32_X2APIC_ESR (0x00000828)\r | |
| 5202 | @param EAX Lower 32-bits of MSR value.\r | |
| 5203 | @param EDX Upper 32-bits of MSR value.\r | |
| 5204 | \r | |
| 5205 | <b>Example usage</b>\r | |
| 5206 | @code\r | |
| 5207 | UINT64 Msr;\r | |
| 5208 | \r | |
| 5209 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);\r | |
| 5210 | AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);\r | |
| 5211 | @endcode\r | |
| 7de98828 | 5212 | @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.\r |
| 04c980a6 MK |
5213 | **/\r |
| 5214 | #define MSR_IA32_X2APIC_ESR 0x00000828\r | |
| 5215 | \r | |
| 5216 | \r | |
| 5217 | /**\r | |
| 5218 | x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If\r | |
| 5219 | CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5220 | \r | |
| 5221 | @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)\r | |
| 5222 | @param EAX Lower 32-bits of MSR value.\r | |
| 5223 | @param EDX Upper 32-bits of MSR value.\r | |
| 5224 | \r | |
| 5225 | <b>Example usage</b>\r | |
| 5226 | @code\r | |
| 5227 | UINT64 Msr;\r | |
| 5228 | \r | |
| 5229 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);\r | |
| 5230 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);\r | |
| 5231 | @endcode\r | |
| 7de98828 | 5232 | @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.\r |
| 04c980a6 MK |
5233 | **/\r |
| 5234 | #define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F\r | |
| 5235 | \r | |
| 5236 | \r | |
| 5237 | /**\r | |
| 5238 | x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5239 | IA32_APIC_BASE.[10] = 1.\r | |
| 5240 | \r | |
| 5241 | @param ECX MSR_IA32_X2APIC_ICR (0x00000830)\r | |
| 5242 | @param EAX Lower 32-bits of MSR value.\r | |
| 5243 | @param EDX Upper 32-bits of MSR value.\r | |
| 5244 | \r | |
| 5245 | <b>Example usage</b>\r | |
| 5246 | @code\r | |
| 5247 | UINT64 Msr;\r | |
| 5248 | \r | |
| 5249 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);\r | |
| 5250 | AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);\r | |
| 5251 | @endcode\r | |
| 7de98828 | 5252 | @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.\r |
| 04c980a6 MK |
5253 | **/\r |
| 5254 | #define MSR_IA32_X2APIC_ICR 0x00000830\r | |
| 5255 | \r | |
| 5256 | \r | |
| 5257 | /**\r | |
| 5258 | x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5259 | IA32_APIC_BASE.[10] = 1.\r | |
| 5260 | \r | |
| 5261 | @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832)\r | |
| 5262 | @param EAX Lower 32-bits of MSR value.\r | |
| 5263 | @param EDX Upper 32-bits of MSR value.\r | |
| 5264 | \r | |
| 5265 | <b>Example usage</b>\r | |
| 5266 | @code\r | |
| 5267 | UINT64 Msr;\r | |
| 5268 | \r | |
| 5269 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);\r | |
| 5270 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);\r | |
| 5271 | @endcode\r | |
| 7de98828 | 5272 | @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.\r |
| 04c980a6 MK |
5273 | **/\r |
| 5274 | #define MSR_IA32_X2APIC_LVT_TIMER 0x00000832\r | |
| 5275 | \r | |
| 5276 | \r | |
| 5277 | /**\r | |
| 5278 | x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =\r | |
| 5279 | 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5280 | \r | |
| 5281 | @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)\r | |
| 5282 | @param EAX Lower 32-bits of MSR value.\r | |
| 5283 | @param EDX Upper 32-bits of MSR value.\r | |
| 5284 | \r | |
| 5285 | <b>Example usage</b>\r | |
| 5286 | @code\r | |
| 5287 | UINT64 Msr;\r | |
| 5288 | \r | |
| 5289 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);\r | |
| 5290 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);\r | |
| 5291 | @endcode\r | |
| 7de98828 | 5292 | @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.\r |
| 04c980a6 MK |
5293 | **/\r |
| 5294 | #define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833\r | |
| 5295 | \r | |
| 5296 | \r | |
| 5297 | /**\r | |
| 5298 | x2APIC LVT Performance Monitor Interrupt Register (R/W). If\r | |
| 5299 | CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r | |
| 5300 | \r | |
| 5301 | @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834)\r | |
| 5302 | @param EAX Lower 32-bits of MSR value.\r | |
| 5303 | @param EDX Upper 32-bits of MSR value.\r | |
| 5304 | \r | |
| 5305 | <b>Example usage</b>\r | |
| 5306 | @code\r | |
| 5307 | UINT64 Msr;\r | |
| 5308 | \r | |
| 5309 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);\r | |
| 5310 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);\r | |
| 5311 | @endcode\r | |
| 7de98828 | 5312 | @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.\r |
| 04c980a6 MK |
5313 | **/\r |
| 5314 | #define MSR_IA32_X2APIC_LVT_PMI 0x00000834\r | |
| 5315 | \r | |
| 5316 | \r | |
| 5317 | /**\r | |
| 5318 | x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5319 | IA32_APIC_BASE.[10] = 1.\r | |
| 5320 | \r | |
| 5321 | @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)\r | |
| 5322 | @param EAX Lower 32-bits of MSR value.\r | |
| 5323 | @param EDX Upper 32-bits of MSR value.\r | |
| 5324 | \r | |
| 5325 | <b>Example usage</b>\r | |
| 5326 | @code\r | |
| 5327 | UINT64 Msr;\r | |
| 5328 | \r | |
| 5329 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);\r | |
| 5330 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);\r | |
| 5331 | @endcode\r | |
| 7de98828 | 5332 | @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.\r |
| 04c980a6 MK |
5333 | **/\r |
| 5334 | #define MSR_IA32_X2APIC_LVT_LINT0 0x00000835\r | |
| 5335 | \r | |
| 5336 | \r | |
| 5337 | /**\r | |
| 5338 | x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5339 | IA32_APIC_BASE.[10] = 1.\r | |
| 5340 | \r | |
| 5341 | @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)\r | |
| 5342 | @param EAX Lower 32-bits of MSR value.\r | |
| 5343 | @param EDX Upper 32-bits of MSR value.\r | |
| 5344 | \r | |
| 5345 | <b>Example usage</b>\r | |
| 5346 | @code\r | |
| 5347 | UINT64 Msr;\r | |
| 5348 | \r | |
| 5349 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);\r | |
| 5350 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);\r | |
| 5351 | @endcode\r | |
| 7de98828 | 5352 | @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.\r |
| 04c980a6 MK |
5353 | **/\r |
| 5354 | #define MSR_IA32_X2APIC_LVT_LINT1 0x00000836\r | |
| 5355 | \r | |
| 5356 | \r | |
| 5357 | /**\r | |
| 5358 | x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5359 | IA32_APIC_BASE.[10] = 1.\r | |
| 5360 | \r | |
| 5361 | @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837)\r | |
| 5362 | @param EAX Lower 32-bits of MSR value.\r | |
| 5363 | @param EDX Upper 32-bits of MSR value.\r | |
| 5364 | \r | |
| 5365 | <b>Example usage</b>\r | |
| 5366 | @code\r | |
| 5367 | UINT64 Msr;\r | |
| 5368 | \r | |
| 5369 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);\r | |
| 5370 | AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);\r | |
| 5371 | @endcode\r | |
| 7de98828 | 5372 | @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.\r |
| 04c980a6 MK |
5373 | **/\r |
| 5374 | #define MSR_IA32_X2APIC_LVT_ERROR 0x00000837\r | |
| 5375 | \r | |
| 5376 | \r | |
| 5377 | /**\r | |
| 5378 | x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5379 | IA32_APIC_BASE.[10] = 1.\r | |
| 5380 | \r | |
| 5381 | @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838)\r | |
| 5382 | @param EAX Lower 32-bits of MSR value.\r | |
| 5383 | @param EDX Upper 32-bits of MSR value.\r | |
| 5384 | \r | |
| 5385 | <b>Example usage</b>\r | |
| 5386 | @code\r | |
| 5387 | UINT64 Msr;\r | |
| 5388 | \r | |
| 5389 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);\r | |
| 5390 | AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);\r | |
| 5391 | @endcode\r | |
| 7de98828 | 5392 | @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.\r |
| 04c980a6 MK |
5393 | **/\r |
| 5394 | #define MSR_IA32_X2APIC_INIT_COUNT 0x00000838\r | |
| 5395 | \r | |
| 5396 | \r | |
| 5397 | /**\r | |
| 5398 | x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5399 | IA32_APIC_BASE.[10] = 1.\r | |
| 5400 | \r | |
| 5401 | @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839)\r | |
| 5402 | @param EAX Lower 32-bits of MSR value.\r | |
| 5403 | @param EDX Upper 32-bits of MSR value.\r | |
| 5404 | \r | |
| 5405 | <b>Example usage</b>\r | |
| 5406 | @code\r | |
| 5407 | UINT64 Msr;\r | |
| 5408 | \r | |
| 5409 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);\r | |
| 5410 | @endcode\r | |
| 7de98828 | 5411 | @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.\r |
| 04c980a6 MK |
5412 | **/\r |
| 5413 | #define MSR_IA32_X2APIC_CUR_COUNT 0x00000839\r | |
| 5414 | \r | |
| 5415 | \r | |
| 5416 | /**\r | |
| 5417 | x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5418 | IA32_APIC_BASE.[10] = 1.\r | |
| 5419 | \r | |
| 5420 | @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E)\r | |
| 5421 | @param EAX Lower 32-bits of MSR value.\r | |
| 5422 | @param EDX Upper 32-bits of MSR value.\r | |
| 5423 | \r | |
| 5424 | <b>Example usage</b>\r | |
| 5425 | @code\r | |
| 5426 | UINT64 Msr;\r | |
| 5427 | \r | |
| 5428 | Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);\r | |
| 5429 | AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);\r | |
| 5430 | @endcode\r | |
| 7de98828 | 5431 | @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.\r |
| 04c980a6 MK |
5432 | **/\r |
| 5433 | #define MSR_IA32_X2APIC_DIV_CONF 0x0000083E\r | |
| 5434 | \r | |
| 5435 | \r | |
| 5436 | /**\r | |
| 5437 | x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&\r | |
| 5438 | IA32_APIC_BASE.[10] = 1.\r | |
| 5439 | \r | |
| 5440 | @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F)\r | |
| 5441 | @param EAX Lower 32-bits of MSR value.\r | |
| 5442 | @param EDX Upper 32-bits of MSR value.\r | |
| 5443 | \r | |
| 5444 | <b>Example usage</b>\r | |
| 5445 | @code\r | |
| 5446 | UINT64 Msr;\r | |
| 5447 | \r | |
| 5448 | Msr = 0;\r | |
| 5449 | AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);\r | |
| 5450 | @endcode\r | |
| 7de98828 | 5451 | @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.\r |
| 04c980a6 MK |
5452 | **/\r |
| 5453 | #define MSR_IA32_X2APIC_SELF_IPI 0x0000083F\r | |
| 5454 | \r | |
| 5455 | \r | |
| 5456 | /**\r | |
| 5457 | Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.\r | |
| 5458 | \r | |
| 5459 | @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80)\r | |
| 5460 | @param EAX Lower 32-bits of MSR value.\r | |
| 5461 | Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.\r | |
| 5462 | @param EDX Upper 32-bits of MSR value.\r | |
| 5463 | Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.\r | |
| 5464 | \r | |
| 5465 | <b>Example usage</b>\r | |
| 5466 | @code\r | |
| 5467 | MSR_IA32_DEBUG_INTERFACE_REGISTER Msr;\r | |
| 5468 | \r | |
| 5469 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);\r | |
| 5470 | AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);\r | |
| 5471 | @endcode\r | |
| 7de98828 | 5472 | @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.\r |
| 04c980a6 MK |
5473 | **/\r |
| 5474 | #define MSR_IA32_DEBUG_INTERFACE 0x00000C80\r | |
| 5475 | \r | |
| 5476 | /**\r | |
| 5477 | MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE\r | |
| 5478 | **/\r | |
| 5479 | typedef union {\r | |
| 5480 | ///\r | |
| 5481 | /// Individual bit fields\r | |
| 5482 | ///\r | |
| 5483 | struct {\r | |
| 5484 | ///\r | |
| 5485 | /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.\r | |
| 5486 | /// Default is 0. If CPUID.01H:ECX.[11] = 1.\r | |
| 5487 | ///\r | |
| 5488 | UINT32 Enable:1;\r | |
| 5489 | UINT32 Reserved1:29;\r | |
| 5490 | ///\r | |
| 5491 | /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The\r | |
| 5492 | /// lock bit is set automatically on the first SMI assertion even if not\r | |
| 5493 | /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.\r | |
| 5494 | ///\r | |
| 5495 | UINT32 Lock:1;\r | |
| 5496 | ///\r | |
| 5497 | /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to\r | |
| 5498 | /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.\r | |
| 5499 | ///\r | |
| 5500 | UINT32 DebugOccurred:1;\r | |
| 5501 | UINT32 Reserved2:32;\r | |
| 5502 | } Bits;\r | |
| 5503 | ///\r | |
| 5504 | /// All bit fields as a 32-bit value\r | |
| 5505 | ///\r | |
| 5506 | UINT32 Uint32;\r | |
| 5507 | ///\r | |
| 5508 | /// All bit fields as a 64-bit value\r | |
| 5509 | ///\r | |
| 5510 | UINT64 Uint64;\r | |
| 5511 | } MSR_IA32_DEBUG_INTERFACE_REGISTER;\r | |
| 5512 | \r | |
| 5513 | \r | |
| 5514 | /**\r | |
| 5515 | L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).\r | |
| 5516 | \r | |
| 5517 | @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81)\r | |
| 5518 | @param EAX Lower 32-bits of MSR value.\r | |
| 5519 | Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.\r | |
| 5520 | @param EDX Upper 32-bits of MSR value.\r | |
| 5521 | Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.\r | |
| 5522 | \r | |
| 5523 | <b>Example usage</b>\r | |
| 5524 | @code\r | |
| 5525 | MSR_IA32_L3_QOS_CFG_REGISTER Msr;\r | |
| 5526 | \r | |
| 5527 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);\r | |
| 5528 | AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);\r | |
| 5529 | @endcode\r | |
| 7de98828 | 5530 | @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.\r |
| 04c980a6 MK |
5531 | **/\r |
| 5532 | #define MSR_IA32_L3_QOS_CFG 0x00000C81\r | |
| 5533 | \r | |
| 5534 | /**\r | |
| 5535 | MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG\r | |
| 5536 | **/\r | |
| 5537 | typedef union {\r | |
| 5538 | ///\r | |
| 5539 | /// Individual bit fields\r | |
| 5540 | ///\r | |
| 5541 | struct {\r | |
| 5542 | ///\r | |
| 5543 | /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate\r | |
| 5544 | /// in Code and Data Prioritization (CDP) mode.\r | |
| 5545 | ///\r | |
| 5546 | UINT32 Enable:1;\r | |
| 5547 | UINT32 Reserved1:31;\r | |
| 5548 | UINT32 Reserved2:32;\r | |
| 5549 | } Bits;\r | |
| 5550 | ///\r | |
| 5551 | /// All bit fields as a 32-bit value\r | |
| 5552 | ///\r | |
| 5553 | UINT32 Uint32;\r | |
| 5554 | ///\r | |
| 5555 | /// All bit fields as a 64-bit value\r | |
| 5556 | ///\r | |
| 5557 | UINT64 Uint64;\r | |
| 5558 | } MSR_IA32_L3_QOS_CFG_REGISTER;\r | |
| 5559 | \r | |
| 5560 | \r | |
| 5561 | /**\r | |
| 5562 | Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]\r | |
| 5563 | = 1 ).\r | |
| 5564 | \r | |
| 5565 | @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D)\r | |
| 5566 | @param EAX Lower 32-bits of MSR value.\r | |
| 5567 | Described by the type MSR_IA32_QM_EVTSEL_REGISTER.\r | |
| 5568 | @param EDX Upper 32-bits of MSR value.\r | |
| 5569 | Described by the type MSR_IA32_QM_EVTSEL_REGISTER.\r | |
| 5570 | \r | |
| 5571 | <b>Example usage</b>\r | |
| 5572 | @code\r | |
| 5573 | MSR_IA32_QM_EVTSEL_REGISTER Msr;\r | |
| 5574 | \r | |
| 5575 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);\r | |
| 5576 | AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);\r | |
| 5577 | @endcode\r | |
| 7de98828 | 5578 | @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r |
| 04c980a6 MK |
5579 | **/\r |
| 5580 | #define MSR_IA32_QM_EVTSEL 0x00000C8D\r | |
| 5581 | \r | |
| 5582 | /**\r | |
| 5583 | MSR information returned for MSR index #MSR_IA32_QM_EVTSEL\r | |
| 5584 | **/\r | |
| 5585 | typedef union {\r | |
| 5586 | ///\r | |
| 5587 | /// Individual bit fields\r | |
| 5588 | ///\r | |
| 5589 | struct {\r | |
| 5590 | ///\r | |
| 5591 | /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via\r | |
| 5592 | /// IA32_QM_CTR.\r | |
| 5593 | ///\r | |
| 5594 | UINT32 EventID:8;\r | |
| 5595 | UINT32 Reserved:24;\r | |
| 5596 | ///\r | |
| 5597 | /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to\r | |
| 5598 | /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (\r | |
| 5599 | /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r | |
| 5600 | ///\r | |
| 5601 | UINT32 ResourceMonitoringID:32;\r | |
| 5602 | } Bits;\r | |
| 5603 | ///\r | |
| 5604 | /// All bit fields as a 64-bit value\r | |
| 5605 | ///\r | |
| 5606 | UINT64 Uint64;\r | |
| 5607 | } MSR_IA32_QM_EVTSEL_REGISTER;\r | |
| 5608 | \r | |
| 5609 | \r | |
| 5610 | /**\r | |
| 5611 | Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1\r | |
| 5612 | ).\r | |
| 5613 | \r | |
| 5614 | @param ECX MSR_IA32_QM_CTR (0x00000C8E)\r | |
| 5615 | @param EAX Lower 32-bits of MSR value.\r | |
| 5616 | Described by the type MSR_IA32_QM_CTR_REGISTER.\r | |
| 5617 | @param EDX Upper 32-bits of MSR value.\r | |
| 5618 | Described by the type MSR_IA32_QM_CTR_REGISTER.\r | |
| 5619 | \r | |
| 5620 | <b>Example usage</b>\r | |
| 5621 | @code\r | |
| 5622 | MSR_IA32_QM_CTR_REGISTER Msr;\r | |
| 5623 | \r | |
| 5624 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);\r | |
| 5625 | @endcode\r | |
| 7de98828 | 5626 | @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.\r |
| 04c980a6 MK |
5627 | **/\r |
| 5628 | #define MSR_IA32_QM_CTR 0x00000C8E\r | |
| 5629 | \r | |
| 5630 | /**\r | |
| 5631 | MSR information returned for MSR index #MSR_IA32_QM_CTR\r | |
| 5632 | **/\r | |
| 5633 | typedef union {\r | |
| 5634 | ///\r | |
| 5635 | /// Individual bit fields\r | |
| 5636 | ///\r | |
| 5637 | struct {\r | |
| 5638 | ///\r | |
| 5639 | /// [Bits 31:0] Resource Monitored Data.\r | |
| 5640 | ///\r | |
| 5641 | UINT32 ResourceMonitoredData:32;\r | |
| 5642 | ///\r | |
| 5643 | /// [Bits 61:32] Resource Monitored Data.\r | |
| 5644 | ///\r | |
| 5645 | UINT32 ResourceMonitoredDataHi:30;\r | |
| 5646 | ///\r | |
| 5647 | /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not\r | |
| 5648 | /// available or not monitored for this resource or RMID.\r | |
| 5649 | ///\r | |
| 5650 | UINT32 Unavailable:1;\r | |
| 5651 | ///\r | |
| 5652 | /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was\r | |
| 5653 | /// written to IA32_PQR_QM_EVTSEL.\r | |
| 5654 | ///\r | |
| 5655 | UINT32 Error:1;\r | |
| 5656 | } Bits;\r | |
| 5657 | ///\r | |
| 5658 | /// All bit fields as a 64-bit value\r | |
| 5659 | ///\r | |
| 5660 | UINT64 Uint64;\r | |
| 5661 | } MSR_IA32_QM_CTR_REGISTER;\r | |
| 5662 | \r | |
| 5663 | \r | |
| 5664 | /**\r | |
| 5665 | Resource Association Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] =\r | |
| 5666 | 1 ).\r | |
| 5667 | \r | |
| 5668 | @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)\r | |
| 5669 | @param EAX Lower 32-bits of MSR value.\r | |
| 5670 | Described by the type MSR_IA32_PQR_ASSOC_REGISTER.\r | |
| 5671 | @param EDX Upper 32-bits of MSR value.\r | |
| 5672 | Described by the type MSR_IA32_PQR_ASSOC_REGISTER.\r | |
| 5673 | \r | |
| 5674 | <b>Example usage</b>\r | |
| 5675 | @code\r | |
| 5676 | MSR_IA32_PQR_ASSOC_REGISTER Msr;\r | |
| 5677 | \r | |
| 5678 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);\r | |
| 5679 | AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);\r | |
| 5680 | @endcode\r | |
| 7de98828 | 5681 | @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r |
| 04c980a6 MK |
5682 | **/\r |
| 5683 | #define MSR_IA32_PQR_ASSOC 0x00000C8F\r | |
| 5684 | \r | |
| 5685 | /**\r | |
| 5686 | MSR information returned for MSR index #MSR_IA32_PQR_ASSOC\r | |
| 5687 | **/\r | |
| 5688 | typedef union {\r | |
| 5689 | ///\r | |
| 5690 | /// Individual bit fields\r | |
| 5691 | ///\r | |
| 5692 | struct {\r | |
| 5693 | ///\r | |
| 5694 | /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware\r | |
| 5695 | /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`\r | |
| 5696 | /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r | |
| 5697 | ///\r | |
| 5698 | UINT32 ResourceMonitoringID:32;\r | |
| 5699 | ///\r | |
| 5700 | /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on\r | |
| 5701 | /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,\r | |
| 5702 | /// ECX=0):EBX.[15] = 1 ).\r | |
| 5703 | ///\r | |
| 5704 | UINT32 COS:32;\r | |
| 5705 | } Bits;\r | |
| 5706 | ///\r | |
| 5707 | /// All bit fields as a 64-bit value\r | |
| 5708 | ///\r | |
| 5709 | UINT64 Uint64;\r | |
| 5710 | } MSR_IA32_PQR_ASSOC_REGISTER;\r | |
| 5711 | \r | |
| 5712 | \r | |
| 5713 | /**\r | |
| 5714 | Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,\r | |
| 5715 | ECX=0H):EBX[14] = 1).\r | |
| 5716 | \r | |
| 5717 | @param ECX MSR_IA32_BNDCFGS (0x00000D90)\r | |
| 5718 | @param EAX Lower 32-bits of MSR value.\r | |
| 5719 | Described by the type MSR_IA32_BNDCFGS_REGISTER.\r | |
| 5720 | @param EDX Upper 32-bits of MSR value.\r | |
| 5721 | Described by the type MSR_IA32_BNDCFGS_REGISTER.\r | |
| 5722 | \r | |
| 5723 | <b>Example usage</b>\r | |
| 5724 | @code\r | |
| 5725 | MSR_IA32_BNDCFGS_REGISTER Msr;\r | |
| 5726 | \r | |
| 5727 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);\r | |
| 5728 | AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);\r | |
| 5729 | @endcode\r | |
| 7de98828 | 5730 | @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.\r |
| 04c980a6 MK |
5731 | **/\r |
| 5732 | #define MSR_IA32_BNDCFGS 0x00000D90\r | |
| 5733 | \r | |
| 5734 | /**\r | |
| 5735 | MSR information returned for MSR index #MSR_IA32_BNDCFGS\r | |
| 5736 | **/\r | |
| 5737 | typedef union {\r | |
| 5738 | ///\r | |
| 5739 | /// Individual bit fields\r | |
| 5740 | ///\r | |
| 5741 | struct {\r | |
| 5742 | ///\r | |
| 5743 | /// [Bit 0] EN: Enable Intel MPX in supervisor mode.\r | |
| 5744 | ///\r | |
| 5745 | UINT32 EN:1;\r | |
| 5746 | ///\r | |
| 5747 | /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch\r | |
| 5748 | /// instructions in the absence of the BND prefix.\r | |
| 5749 | ///\r | |
| 5750 | UINT32 BNDPRESERVE:1;\r | |
| 5751 | UINT32 Reserved:10;\r | |
| 5752 | ///\r | |
| 5753 | /// [Bits 31:12] Base Address of Bound Directory.\r | |
| 5754 | ///\r | |
| 5755 | UINT32 Base:20;\r | |
| 5756 | ///\r | |
| 5757 | /// [Bits 63:32] Base Address of Bound Directory.\r | |
| 5758 | ///\r | |
| 5759 | UINT32 BaseHi:32;\r | |
| 5760 | } Bits;\r | |
| 5761 | ///\r | |
| 5762 | /// All bit fields as a 64-bit value\r | |
| 5763 | ///\r | |
| 5764 | UINT64 Uint64;\r | |
| 5765 | } MSR_IA32_BNDCFGS_REGISTER;\r | |
| 5766 | \r | |
| 5767 | \r | |
| 5768 | /**\r | |
| 5769 | Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.\r | |
| 5770 | \r | |
| 5771 | @param ECX MSR_IA32_XSS (0x00000DA0)\r | |
| 5772 | @param EAX Lower 32-bits of MSR value.\r | |
| 5773 | Described by the type MSR_IA32_XSS_REGISTER.\r | |
| 5774 | @param EDX Upper 32-bits of MSR value.\r | |
| 5775 | Described by the type MSR_IA32_XSS_REGISTER.\r | |
| 5776 | \r | |
| 5777 | <b>Example usage</b>\r | |
| 5778 | @code\r | |
| 5779 | MSR_IA32_XSS_REGISTER Msr;\r | |
| 5780 | \r | |
| 5781 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);\r | |
| 5782 | AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);\r | |
| 5783 | @endcode\r | |
| 7de98828 | 5784 | @note MSR_IA32_XSS is defined as IA32_XSS in SDM.\r |
| 04c980a6 MK |
5785 | **/\r |
| 5786 | #define MSR_IA32_XSS 0x00000DA0\r | |
| 5787 | \r | |
| 5788 | /**\r | |
| 5789 | MSR information returned for MSR index #MSR_IA32_XSS\r | |
| 5790 | **/\r | |
| 5791 | typedef union {\r | |
| 5792 | ///\r | |
| 5793 | /// Individual bit fields\r | |
| 5794 | ///\r | |
| 5795 | struct {\r | |
| 5796 | UINT32 Reserved1:8;\r | |
| 5797 | ///\r | |
| 5798 | /// [Bit 8] Trace Packet Configuration State (R/W).\r | |
| 5799 | ///\r | |
| 5800 | UINT32 TracePacketConfigurationState:1;\r | |
| 5801 | UINT32 Reserved2:23;\r | |
| 5802 | UINT32 Reserved3:32;\r | |
| 5803 | } Bits;\r | |
| 5804 | ///\r | |
| 5805 | /// All bit fields as a 32-bit value\r | |
| 5806 | ///\r | |
| 5807 | UINT32 Uint32;\r | |
| 5808 | ///\r | |
| 5809 | /// All bit fields as a 64-bit value\r | |
| 5810 | ///\r | |
| 5811 | UINT64 Uint64;\r | |
| 5812 | } MSR_IA32_XSS_REGISTER;\r | |
| 5813 | \r | |
| 5814 | \r | |
| 5815 | /**\r | |
| 5816 | Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.\r | |
| 5817 | \r | |
| 5818 | @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0)\r | |
| 5819 | @param EAX Lower 32-bits of MSR value.\r | |
| 5820 | Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.\r | |
| 5821 | @param EDX Upper 32-bits of MSR value.\r | |
| 5822 | Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.\r | |
| 5823 | \r | |
| 5824 | <b>Example usage</b>\r | |
| 5825 | @code\r | |
| 5826 | MSR_IA32_PKG_HDC_CTL_REGISTER Msr;\r | |
| 5827 | \r | |
| 5828 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);\r | |
| 5829 | AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);\r | |
| 5830 | @endcode\r | |
| 7de98828 | 5831 | @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.\r |
| 04c980a6 MK |
5832 | **/\r |
| 5833 | #define MSR_IA32_PKG_HDC_CTL 0x00000DB0\r | |
| 5834 | \r | |
| 5835 | /**\r | |
| 5836 | MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL\r | |
| 5837 | **/\r | |
| 5838 | typedef union {\r | |
| 5839 | ///\r | |
| 5840 | /// Individual bit fields\r | |
| 5841 | ///\r | |
| 5842 | struct {\r | |
| 5843 | ///\r | |
| 5844 | /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled\r | |
| 5845 | /// logical processors in the package. See Section 14.5.2, "Package level\r | |
| 5846 | /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.\r | |
| 5847 | ///\r | |
| 5848 | UINT32 HDC_Pkg_Enable:1;\r | |
| 5849 | UINT32 Reserved1:31;\r | |
| 5850 | UINT32 Reserved2:32;\r | |
| 5851 | } Bits;\r | |
| 5852 | ///\r | |
| 5853 | /// All bit fields as a 32-bit value\r | |
| 5854 | ///\r | |
| 5855 | UINT32 Uint32;\r | |
| 5856 | ///\r | |
| 5857 | /// All bit fields as a 64-bit value\r | |
| 5858 | ///\r | |
| 5859 | UINT64 Uint64;\r | |
| 5860 | } MSR_IA32_PKG_HDC_CTL_REGISTER;\r | |
| 5861 | \r | |
| 5862 | \r | |
| 5863 | /**\r | |
| 5864 | Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.\r | |
| 5865 | \r | |
| 5866 | @param ECX MSR_IA32_PM_CTL1 (0x00000DB1)\r | |
| 5867 | @param EAX Lower 32-bits of MSR value.\r | |
| 5868 | Described by the type MSR_IA32_PM_CTL1_REGISTER.\r | |
| 5869 | @param EDX Upper 32-bits of MSR value.\r | |
| 5870 | Described by the type MSR_IA32_PM_CTL1_REGISTER.\r | |
| 5871 | \r | |
| 5872 | <b>Example usage</b>\r | |
| 5873 | @code\r | |
| 5874 | MSR_IA32_PM_CTL1_REGISTER Msr;\r | |
| 5875 | \r | |
| 5876 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);\r | |
| 5877 | AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);\r | |
| 5878 | @endcode\r | |
| 7de98828 | 5879 | @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.\r |
| 04c980a6 MK |
5880 | **/\r |
| 5881 | #define MSR_IA32_PM_CTL1 0x00000DB1\r | |
| 5882 | \r | |
| 5883 | /**\r | |
| 5884 | MSR information returned for MSR index #MSR_IA32_PM_CTL1\r | |
| 5885 | **/\r | |
| 5886 | typedef union {\r | |
| 5887 | ///\r | |
| 5888 | /// Individual bit fields\r | |
| 5889 | ///\r | |
| 5890 | struct {\r | |
| 5891 | ///\r | |
| 5892 | /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for\r | |
| 5893 | /// package level HDC control. See Section 14.5.3.\r | |
| 5894 | /// If CPUID.06H:EAX.[13] = 1.\r | |
| 5895 | ///\r | |
| 5896 | UINT32 HDC_Allow_Block:1;\r | |
| 5897 | UINT32 Reserved1:31;\r | |
| 5898 | UINT32 Reserved2:32;\r | |
| 5899 | } Bits;\r | |
| 5900 | ///\r | |
| 5901 | /// All bit fields as a 32-bit value\r | |
| 5902 | ///\r | |
| 5903 | UINT32 Uint32;\r | |
| 5904 | ///\r | |
| 5905 | /// All bit fields as a 64-bit value\r | |
| 5906 | ///\r | |
| 5907 | UINT64 Uint64;\r | |
| 5908 | } MSR_IA32_PM_CTL1_REGISTER;\r | |
| 5909 | \r | |
| 5910 | \r | |
| 5911 | /**\r | |
| 5912 | Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.\r | |
| 5913 | Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical\r | |
| 5914 | processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.\r | |
| 5915 | \r | |
| 5916 | @param ECX MSR_IA32_THREAD_STALL (0x00000DB2)\r | |
| 5917 | @param EAX Lower 32-bits of MSR value.\r | |
| 5918 | @param EDX Upper 32-bits of MSR value.\r | |
| 5919 | \r | |
| 5920 | <b>Example usage</b>\r | |
| 5921 | @code\r | |
| 5922 | UINT64 Msr;\r | |
| 5923 | \r | |
| 5924 | Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);\r | |
| 5925 | @endcode\r | |
| 7de98828 | 5926 | @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.\r |
| 04c980a6 MK |
5927 | **/\r |
| 5928 | #define MSR_IA32_THREAD_STALL 0x00000DB2\r | |
| 5929 | \r | |
| 5930 | \r | |
| 5931 | /**\r | |
| 5932 | Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]\r | |
| 5933 | CPUID.80000001H:EDX.[2 9]).\r | |
| 5934 | \r | |
| 5935 | @param ECX MSR_IA32_EFER (0xC0000080)\r | |
| 5936 | @param EAX Lower 32-bits of MSR value.\r | |
| 5937 | Described by the type MSR_IA32_EFER_REGISTER.\r | |
| 5938 | @param EDX Upper 32-bits of MSR value.\r | |
| 5939 | Described by the type MSR_IA32_EFER_REGISTER.\r | |
| 5940 | \r | |
| 5941 | <b>Example usage</b>\r | |
| 5942 | @code\r | |
| 5943 | MSR_IA32_EFER_REGISTER Msr;\r | |
| 5944 | \r | |
| 5945 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);\r | |
| 5946 | AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);\r | |
| 5947 | @endcode\r | |
| 7de98828 | 5948 | @note MSR_IA32_EFER is defined as IA32_EFER in SDM.\r |
| 04c980a6 MK |
5949 | **/\r |
| 5950 | #define MSR_IA32_EFER 0xC0000080\r | |
| 5951 | \r | |
| 5952 | /**\r | |
| 5953 | MSR information returned for MSR index #MSR_IA32_EFER\r | |
| 5954 | **/\r | |
| 5955 | typedef union {\r | |
| 5956 | ///\r | |
| 5957 | /// Individual bit fields\r | |
| 5958 | ///\r | |
| 5959 | struct {\r | |
| 5960 | ///\r | |
| 5961 | /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET\r | |
| 5962 | /// instructions in 64-bit mode.\r | |
| 5963 | ///\r | |
| 5964 | UINT32 SCE:1;\r | |
| 5965 | UINT32 Reserved1:7;\r | |
| 5966 | ///\r | |
| 5967 | /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode\r | |
| 5968 | /// operation.\r | |
| 5969 | ///\r | |
| 5970 | UINT32 LME:1;\r | |
| 5971 | UINT32 Reserved2:1;\r | |
| 5972 | ///\r | |
| 5973 | /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode\r | |
| 5974 | /// is active when set.\r | |
| 5975 | ///\r | |
| 5976 | UINT32 LMA:1;\r | |
| 5977 | ///\r | |
| 5978 | /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).\r | |
| 5979 | ///\r | |
| 5980 | UINT32 NXE:1;\r | |
| 5981 | UINT32 Reserved3:20;\r | |
| 5982 | UINT32 Reserved4:32;\r | |
| 5983 | } Bits;\r | |
| 5984 | ///\r | |
| 5985 | /// All bit fields as a 32-bit value\r | |
| 5986 | ///\r | |
| 5987 | UINT32 Uint32;\r | |
| 5988 | ///\r | |
| 5989 | /// All bit fields as a 64-bit value\r | |
| 5990 | ///\r | |
| 5991 | UINT64 Uint64;\r | |
| 5992 | } MSR_IA32_EFER_REGISTER;\r | |
| 5993 | \r | |
| 5994 | \r | |
| 5995 | /**\r | |
| 5996 | System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 5997 | \r | |
| 5998 | @param ECX MSR_IA32_STAR (0xC0000081)\r | |
| 5999 | @param EAX Lower 32-bits of MSR value.\r | |
| 6000 | @param EDX Upper 32-bits of MSR value.\r | |
| 6001 | \r | |
| 6002 | <b>Example usage</b>\r | |
| 6003 | @code\r | |
| 6004 | UINT64 Msr;\r | |
| 6005 | \r | |
| 6006 | Msr = AsmReadMsr64 (MSR_IA32_STAR);\r | |
| 6007 | AsmWriteMsr64 (MSR_IA32_STAR, Msr);\r | |
| 6008 | @endcode\r | |
| 7de98828 | 6009 | @note MSR_IA32_STAR is defined as IA32_STAR in SDM.\r |
| 04c980a6 MK |
6010 | **/\r |
| 6011 | #define MSR_IA32_STAR 0xC0000081\r | |
| 6012 | \r | |
| 6013 | \r | |
| 6014 | /**\r | |
| 6015 | IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6016 | \r | |
| 6017 | @param ECX MSR_IA32_LSTAR (0xC0000082)\r | |
| 6018 | @param EAX Lower 32-bits of MSR value.\r | |
| 6019 | @param EDX Upper 32-bits of MSR value.\r | |
| 6020 | \r | |
| 6021 | <b>Example usage</b>\r | |
| 6022 | @code\r | |
| 6023 | UINT64 Msr;\r | |
| 6024 | \r | |
| 6025 | Msr = AsmReadMsr64 (MSR_IA32_LSTAR);\r | |
| 6026 | AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);\r | |
| 6027 | @endcode\r | |
| 7de98828 | 6028 | @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.\r |
| 04c980a6 MK |
6029 | **/\r |
| 6030 | #define MSR_IA32_LSTAR 0xC0000082\r | |
| 6031 | \r | |
| 6032 | \r | |
| 6033 | /**\r | |
| 6034 | System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6035 | \r | |
| 6036 | @param ECX MSR_IA32_FMASK (0xC0000084)\r | |
| 6037 | @param EAX Lower 32-bits of MSR value.\r | |
| 6038 | @param EDX Upper 32-bits of MSR value.\r | |
| 6039 | \r | |
| 6040 | <b>Example usage</b>\r | |
| 6041 | @code\r | |
| 6042 | UINT64 Msr;\r | |
| 6043 | \r | |
| 6044 | Msr = AsmReadMsr64 (MSR_IA32_FMASK);\r | |
| 6045 | AsmWriteMsr64 (MSR_IA32_FMASK, Msr);\r | |
| 6046 | @endcode\r | |
| 7de98828 | 6047 | @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.\r |
| 04c980a6 MK |
6048 | **/\r |
| 6049 | #define MSR_IA32_FMASK 0xC0000084\r | |
| 6050 | \r | |
| 6051 | \r | |
| 6052 | /**\r | |
| 6053 | Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6054 | \r | |
| 6055 | @param ECX MSR_IA32_FS_BASE (0xC0000100)\r | |
| 6056 | @param EAX Lower 32-bits of MSR value.\r | |
| 6057 | @param EDX Upper 32-bits of MSR value.\r | |
| 6058 | \r | |
| 6059 | <b>Example usage</b>\r | |
| 6060 | @code\r | |
| 6061 | UINT64 Msr;\r | |
| 6062 | \r | |
| 6063 | Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);\r | |
| 6064 | AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);\r | |
| 6065 | @endcode\r | |
| 7de98828 | 6066 | @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.\r |
| 04c980a6 MK |
6067 | **/\r |
| 6068 | #define MSR_IA32_FS_BASE 0xC0000100\r | |
| 6069 | \r | |
| 6070 | \r | |
| 6071 | /**\r | |
| 6072 | Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6073 | \r | |
| 6074 | @param ECX MSR_IA32_GS_BASE (0xC0000101)\r | |
| 6075 | @param EAX Lower 32-bits of MSR value.\r | |
| 6076 | @param EDX Upper 32-bits of MSR value.\r | |
| 6077 | \r | |
| 6078 | <b>Example usage</b>\r | |
| 6079 | @code\r | |
| 6080 | UINT64 Msr;\r | |
| 6081 | \r | |
| 6082 | Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);\r | |
| 6083 | AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);\r | |
| 6084 | @endcode\r | |
| 7de98828 | 6085 | @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.\r |
| 04c980a6 MK |
6086 | **/\r |
| 6087 | #define MSR_IA32_GS_BASE 0xC0000101\r | |
| 6088 | \r | |
| 6089 | \r | |
| 6090 | /**\r | |
| 6091 | Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r | |
| 6092 | \r | |
| 6093 | @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102)\r | |
| 6094 | @param EAX Lower 32-bits of MSR value.\r | |
| 6095 | @param EDX Upper 32-bits of MSR value.\r | |
| 6096 | \r | |
| 6097 | <b>Example usage</b>\r | |
| 6098 | @code\r | |
| 6099 | UINT64 Msr;\r | |
| 6100 | \r | |
| 6101 | Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);\r | |
| 6102 | AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);\r | |
| 6103 | @endcode\r | |
| 7de98828 | 6104 | @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.\r |
| 04c980a6 MK |
6105 | **/\r |
| 6106 | #define MSR_IA32_KERNEL_GS_BASE 0xC0000102\r | |
| 6107 | \r | |
| 6108 | \r | |
| 6109 | /**\r | |
| 6110 | Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.\r | |
| 6111 | \r | |
| 6112 | @param ECX MSR_IA32_TSC_AUX (0xC0000103)\r | |
| 6113 | @param EAX Lower 32-bits of MSR value.\r | |
| 6114 | Described by the type MSR_IA32_TSC_AUX_REGISTER.\r | |
| 6115 | @param EDX Upper 32-bits of MSR value.\r | |
| 6116 | Described by the type MSR_IA32_TSC_AUX_REGISTER.\r | |
| 6117 | \r | |
| 6118 | <b>Example usage</b>\r | |
| 6119 | @code\r | |
| 6120 | MSR_IA32_TSC_AUX_REGISTER Msr;\r | |
| 6121 | \r | |
| 6122 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);\r | |
| 6123 | AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);\r | |
| 6124 | @endcode\r | |
| 7de98828 | 6125 | @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.\r |
| 04c980a6 MK |
6126 | **/\r |
| 6127 | #define MSR_IA32_TSC_AUX 0xC0000103\r | |
| 6128 | \r | |
| 6129 | /**\r | |
| 6130 | MSR information returned for MSR index #MSR_IA32_TSC_AUX\r | |
| 6131 | **/\r | |
| 6132 | typedef union {\r | |
| 6133 | ///\r | |
| 6134 | /// Individual bit fields\r | |
| 6135 | ///\r | |
| 6136 | struct {\r | |
| 6137 | ///\r | |
| 6138 | /// [Bits 31:0] AUX: Auxiliary signature of TSC.\r | |
| 6139 | ///\r | |
| 6140 | UINT32 AUX:32;\r | |
| 6141 | UINT32 Reserved:32;\r | |
| 6142 | } Bits;\r | |
| 6143 | ///\r | |
| 6144 | /// All bit fields as a 32-bit value\r | |
| 6145 | ///\r | |
| 6146 | UINT32 Uint32;\r | |
| 6147 | ///\r | |
| 6148 | /// All bit fields as a 64-bit value\r | |
| 6149 | ///\r | |
| 6150 | UINT64 Uint64;\r | |
| 6151 | } MSR_IA32_TSC_AUX_REGISTER;\r | |
| 6152 | \r | |
| 6153 | #endif\r |