[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / AtomMsr.h

/** @file\r
  MSR Definitions for the Intel(R) Atom(TM) Processor Family.\r
\r
  Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
  are provided for MSRs that contain one or more bit fields.  If the MSR value\r
  returned is a single 32-bit or 64-bit value, then a data structure is not\r
  provided for that MSR.\r
\r
  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
  @par Specification Reference:\r
  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
  September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.3.\r
\r
**/\r
\r
#ifndef __ATOM_MSR_H__\r
#define __ATOM_MSR_H__\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
/**\r
  Is Intel(R) Atom(TM) Processor Family?\r
\r
  @param   DisplayFamily  Display Family ID\r
  @param   DisplayModel   Display Model ID\r
\r
  @retval  TRUE   Yes, it is.\r
  @retval  FALSE  No, it isn't.\r
**/\r
#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \\r
  (DisplayFamily == 0x06 && \\r
   (                        \\r
    DisplayModel == 0x1C || \\r
    DisplayModel == 0x26 || \\r
    DisplayModel == 0x27 || \\r
    DisplayModel == 0x35 || \\r
    DisplayModel == 0x36    \\r
    )                       \\r
   )\r
\r
/**\r
  Shared. Model Specific Platform ID (R).\r
\r
  @param  ECX  MSR_ATOM_PLATFORM_ID (0x00000017)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_ATOM_PLATFORM_ID_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);\r
  @endcode\r
  @note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
**/\r
#define MSR_ATOM_PLATFORM_ID                     0x00000017\r
\r
/**\r
  MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32  Reserved1:8;\r
    ///\r
    /// [Bits 12:8] Maximum Qualified Ratio (R)  The maximum allowed bus ratio.\r
    ///\r
    UINT32  MaximumQualifiedRatio:5;\r
    UINT32  Reserved2:19;\r
    UINT32  Reserved3:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_ATOM_PLATFORM_ID_REGISTER;\r
\r
\r
/**\r
  Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r
  processor features; (R) indicates current processor configuration.\r
\r
  @param  ECX  MSR_ATOM_EBL_CR_POWERON (0x0000002A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_ATOM_EBL_CR_POWERON_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);\r
  AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);\r
  @endcode\r
  @note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
**/\r
#define MSR_ATOM_EBL_CR_POWERON                  0x0000002A\r
\r
/**\r
  MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32  Reserved1:1;\r
    ///\r
    /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
    /// Always 0.\r
    ///\r
    UINT32  DataErrorCheckingEnable:1;\r
    ///\r
    /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
    /// Always 0.\r
    ///\r
    UINT32  ResponseErrorCheckingEnable:1;\r
    ///\r
    /// [Bit 3] AERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Always 0.\r
    ///\r
    UINT32  AERR_DriveEnable:1;\r
    ///\r
    /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =\r
    /// Disabled Always 0.\r
    ///\r
    UINT32  BERR_Enable:1;\r
    UINT32  Reserved2:1;\r
    UINT32  Reserved3:1;\r
    ///\r
    /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r
    ///\r
    UINT32  BINIT_DriverEnable:1;\r
    UINT32  Reserved4:1;\r
    ///\r
    /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
    ///\r
    UINT32  ExecuteBIST:1;\r
    ///\r
    /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
    /// Always 0.\r
    ///\r
    UINT32  AERR_ObservationEnabled:1;\r
    UINT32  Reserved5:1;\r
    ///\r
    /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
    /// Always 0.\r
    ///\r
    UINT32  BINIT_ObservationEnabled:1;\r
    UINT32  Reserved6:1;\r
    ///\r
    /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r
    ///\r
    UINT32  ResetVector:1;\r
    UINT32  Reserved7:1;\r
    ///\r
    /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.\r
    ///\r
    UINT32  APICClusterID:2;\r
    UINT32  Reserved8:2;\r
    ///\r
    /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.\r
    ///\r
    UINT32  SymmetricArbitrationID:2;\r
    ///\r
    /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).\r
    ///\r
    UINT32  IntegerBusFrequencyRatio:5;\r
    UINT32  Reserved9:5;\r
    UINT32  Reserved10:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_ATOM_EBL_CR_POWERON_REGISTER;\r
\r
\r
/**\r
  Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch\r
  record registers on the last branch record stack. The From_IP part of the\r
  stack contains pointers to the source instruction . See also: -  Last Branch\r
  Record Stack TOS at 1C9H -  Section 17.5.\r
\r
  @param  ECX  MSR_ATOM_LASTBRANCH_n_FROM_IP\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);\r
  AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);\r
  @endcode\r
  @note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
        MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
        MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
        MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
        MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
        MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
        MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
        MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
  @{\r
**/\r
#define MSR_ATOM_LASTBRANCH_0_FROM_IP            0x00000040\r
#define MSR_ATOM_LASTBRANCH_1_FROM_IP            0x00000041\r
#define MSR_ATOM_LASTBRANCH_2_FROM_IP            0x00000042\r
#define MSR_ATOM_LASTBRANCH_3_FROM_IP            0x00000043\r
#define MSR_ATOM_LASTBRANCH_4_FROM_IP            0x00000044\r
#define MSR_ATOM_LASTBRANCH_5_FROM_IP            0x00000045\r
#define MSR_ATOM_LASTBRANCH_6_FROM_IP            0x00000046\r
#define MSR_ATOM_LASTBRANCH_7_FROM_IP            0x00000047\r
/// @}\r
\r
\r
/**\r
  Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch\r
  record registers on the last branch record stack. The To_IP part of the\r
  stack contains pointers to the destination instruction.\r
\r
  @param  ECX  MSR_ATOM_LASTBRANCH_n_TO_IP\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);\r
  AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);\r
  @endcode\r
  @note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
        MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
        MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
        MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
        MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
        MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
        MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
        MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
  @{\r
**/\r
#define MSR_ATOM_LASTBRANCH_0_TO_IP              0x00000060\r
#define MSR_ATOM_LASTBRANCH_1_TO_IP              0x00000061\r
#define MSR_ATOM_LASTBRANCH_2_TO_IP              0x00000062\r
#define MSR_ATOM_LASTBRANCH_3_TO_IP              0x00000063\r
#define MSR_ATOM_LASTBRANCH_4_TO_IP              0x00000064\r
#define MSR_ATOM_LASTBRANCH_5_TO_IP              0x00000065\r
#define MSR_ATOM_LASTBRANCH_6_TO_IP              0x00000066\r
#define MSR_ATOM_LASTBRANCH_7_TO_IP              0x00000067\r
/// @}\r
\r
\r
/**\r
  Shared. Scalable Bus Speed(RO) This field indicates the intended scalable\r
  bus clock speed for processors based on Intel Atom microarchitecture:.\r
\r
  @param  ECX  MSR_ATOM_FSB_FREQ (0x000000CD)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_ATOM_FSB_FREQ_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_ATOM_FSB_FREQ_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_ATOM_FSB_FREQ_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);\r
  @endcode\r
  @note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
**/\r
#define MSR_ATOM_FSB_FREQ                        0x000000CD\r
\r
/**\r
  MSR information returned for MSR index #MSR_ATOM_FSB_FREQ\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 2:0] - Scalable Bus Speed\r
    ///\r
    /// Atom Processor Family\r
    /// ---------------------\r
    ///   111B: 083 MHz (FSB 333)\r
    ///   101B: 100 MHz (FSB 400)\r
    ///   001B: 133 MHz (FSB 533)\r
    ///   011B: 167 MHz (FSB 667)\r
    ///\r
    /// 133.33 MHz should be utilized if performing calculation with\r
    /// System Bus Speed when encoding is 001B.\r
    /// 166.67 MHz should be utilized if performing calculation with\r
    /// System Bus Speed when\r
    /// encoding is 011B.\r
    ///\r
    UINT32  ScalableBusSpeed:3;\r
    UINT32  Reserved1:29;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_ATOM_FSB_FREQ_REGISTER;\r
\r
\r
/**\r
  Shared.\r
\r
  @param  ECX  MSR_ATOM_BBL_CR_CTL3 (0x0000011E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_ATOM_BBL_CR_CTL3_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);\r
  AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);\r
  @endcode\r
  @note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
**/\r
#define MSR_ATOM_BBL_CR_CTL3                     0x0000011E\r
\r
/**\r
  MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
    /// Indicates if the L2 is hardware-disabled.\r
    ///\r
    UINT32  L2HardwareEnabled:1;\r
    UINT32  Reserved1:7;\r
    ///\r
    /// [Bit 8] L2 Enabled. (R/W)  1 = L2 cache has been initialized 0 =\r
    /// Disabled (default) Until this bit is set the processor will not\r
    /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
    ///\r
    UINT32  L2Enabled:1;\r
    UINT32  Reserved2:14;\r
    ///\r
    /// [Bit 23] L2 Not Present (RO)  1. = L2 Present 2. = L2 Not Present.\r
    ///\r
    UINT32  L2NotPresent:1;\r
    UINT32  Reserved3:8;\r
    UINT32  Reserved4:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_ATOM_BBL_CR_CTL3_REGISTER;\r
\r
\r
/**\r
  Shared.\r
\r
  @param  ECX  MSR_ATOM_PERF_STATUS (0x00000198)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_ATOM_PERF_STATUS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_ATOM_PERF_STATUS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_ATOM_PERF_STATUS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);\r
  AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);\r
  @endcode\r
  @note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r
**/\r
#define MSR_ATOM_PERF_STATUS                     0x00000198\r
\r
/**\r
  MSR information returned for MSR index #MSR_ATOM_PERF_STATUS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 15:0] Current Performance State Value.\r
    ///\r
    UINT32  CurrentPerformanceStateValue:16;\r
    UINT32  Reserved1:16;\r
    UINT32  Reserved2:8;\r
    ///\r
    /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio\r
    /// configured for the processor.\r
    ///\r
    UINT32  MaximumBusRatio:5;\r
    UINT32  Reserved3:19;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_ATOM_PERF_STATUS_REGISTER;\r
\r
\r
/**\r
  Shared.\r
\r
  @param  ECX  MSR_ATOM_THERM2_CTL (0x0000019D)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_ATOM_THERM2_CTL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_ATOM_THERM2_CTL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_ATOM_THERM2_CTL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);\r
  AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);\r
  @endcode\r
  @note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
**/\r
#define MSR_ATOM_THERM2_CTL                      0x0000019D\r
\r
/**\r
  MSR information returned for MSR index #MSR_ATOM_THERM2_CTL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32  Reserved1:16;\r
    ///\r
    /// [Bit 16] TM_SELECT (R/W)  Mode of automatic thermal monitor: 1. =\r
    /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
    /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r
    /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
    /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.\r
    ///\r
    UINT32  TM_SELECT:1;\r
    UINT32  Reserved2:15;\r
    UINT32  Reserved3:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_ATOM_THERM2_CTL_REGISTER;\r
\r
\r
/**\r
  Unique. Enable Misc. Processor Features (R/W)  Allows a variety of processor\r
  functions to be enabled and disabled.\r
\r
  @param  ECX  MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_ATOM_IA32_MISC_ENABLE_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);\r
  AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);\r
  @endcode\r
  @note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
#define MSR_ATOM_IA32_MISC_ENABLE                0x000001A0\r
\r
/**\r
  MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Fast-Strings Enable See Table 35-2.\r
    ///\r
    UINT32  FastStrings:1;\r
    UINT32  Reserved1:2;\r
    ///\r
    /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
    /// Table 35-2. Default value is 0.\r
    ///\r
    UINT32  AutomaticThermalControlCircuit:1;\r
    UINT32  Reserved2:3;\r
    ///\r
    /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.\r
    ///\r
    UINT32  PerformanceMonitoring:1;\r
    UINT32  Reserved3:1;\r
    UINT32  Reserved4:1;\r
    ///\r
    /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r
    /// the processor to indicate a pending break event within the processor 0\r
    /// = Indicates compatible FERR# signaling behavior This bit must be set\r
    /// to 1 to support XAPIC interrupt model usage.\r
    ///\r
    UINT32  FERR:1;\r
    ///\r
    /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.\r
    ///\r
    UINT32  BTS:1;\r
    ///\r
    /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r
    /// Table 35-2.\r
    ///\r
    UINT32  PEBS:1;\r
    ///\r
    /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r
    /// thermal sensor indicates that the die temperature is at the\r
    /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.\r
    /// TM2 will reduce the bus to core ratio and voltage according to the\r
    /// value last written to MSR_THERM2_CTL bits 15:0.\r
    ///   When this bit is clear (0, default), the processor does not change\r
    ///   the VID signals or the bus to core ratio when the processor enters a\r
    ///   thermally managed state. The BIOS must enable this feature if the\r
    ///   TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is\r
    ///   not set, this feature is not supported and BIOS must not alter the\r
    ///   contents of the TM2 bit location. The processor is operating out of\r
    ///   specification if both this bit and the TM1 bit are set to 0.\r
    ///\r
    UINT32  TM2:1;\r
    UINT32  Reserved5:2;\r
    ///\r
    /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
    /// Table 35-2.\r
    ///\r
    UINT32  EIST:1;\r
    UINT32  Reserved6:1;\r
    ///\r
    /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.\r
    ///\r
    UINT32  MONITOR:1;\r
    UINT32  Reserved7:1;\r
    ///\r
    /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock\r
    /// (R/WO) When set, this bit causes the following bits to become\r
    /// read-only: -  Enhanced Intel SpeedStep Technology Select Lock (this\r
    /// bit), -  Enhanced Intel SpeedStep Technology Enable bit. The bit must\r
    /// be set before an Enhanced Intel SpeedStep Technology transition is\r
    /// requested. This bit is cleared on reset.\r
    ///\r
    UINT32  EISTLock:1;\r
    UINT32  Reserved8:1;\r
    ///\r
    /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 35-2.\r
    ///\r
    UINT32  LimitCpuidMaxval:1;\r
    ///\r
    /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.\r
    ///\r
    UINT32  xTPR_Message_Disable:1;\r
    UINT32  Reserved9:8;\r
    UINT32  Reserved10:2;\r
    ///\r
    /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.\r
    ///\r
    UINT32  XD:1;\r
    UINT32  Reserved11:29;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_ATOM_IA32_MISC_ENABLE_REGISTER;\r
\r
\r
/**\r
  Unique. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-2)\r
  that points to the MSR containing the most recent branch record. See\r
  MSR_LASTBRANCH_0_FROM_IP (at 40H).\r
\r
  @param  ECX  MSR_ATOM_LASTBRANCH_TOS (0x000001C9)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);\r
  AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);\r
  @endcode\r
  @note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
#define MSR_ATOM_LASTBRANCH_TOS                  0x000001C9\r
\r
\r
/**\r
  Unique. Last Exception Record From Linear IP (R)  Contains a pointer to the\r
  last branch instruction that the processor executed prior to the last\r
  exception that was generated or the last interrupt that was handled.\r
\r
  @param  ECX  MSR_ATOM_LER_FROM_LIP (0x000001DD)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);\r
  @endcode\r
  @note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
#define MSR_ATOM_LER_FROM_LIP                    0x000001DD\r
\r
\r
/**\r
  Unique. Last Exception Record To Linear IP (R)  This area contains a pointer\r
  to the target of the last branch instruction that the processor executed\r
  prior to the last exception that was generated or the last interrupt that\r
  was handled.\r
\r
  @param  ECX  MSR_ATOM_LER_TO_LIP (0x000001DE)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);\r
  @endcode\r
  @note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
#define MSR_ATOM_LER_TO_LIP                      0x000001DE\r
\r
\r
/**\r
  Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling\r
  (PEBS).".\r
\r
  @param  ECX  MSR_ATOM_PEBS_ENABLE (0x000003F1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_ATOM_PEBS_ENABLE_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);\r
  AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);\r
  @endcode\r
  @note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
#define MSR_ATOM_PEBS_ENABLE                     0x000003F1\r
\r
/**\r
  MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
    ///\r
    UINT32  Enable:1;\r
    UINT32  Reserved1:31;\r
    UINT32  Reserved2:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_ATOM_PEBS_ENABLE_REGISTER;\r
\r
\r
/**\r
  Package. Package C2 Residency Note: C-state values are processor specific\r
  C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r
  C-States. Package. Package C2 Residency Counter. (R/O) Time that this\r
  package is in processor-specific C2 states since last reset. Counts at 1 Mhz\r
  frequency.\r
\r
  @param  ECX  MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);\r
  AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);\r
  @endcode\r
  @note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
**/\r
#define MSR_ATOM_PKG_C2_RESIDENCY                0x000003F8\r
\r
\r
/**\r
  Package. Package C4 Residency Note: C-state values are processor specific\r
  C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r
  C-States. Package. Package C4 Residency Counter. (R/O) Time that this\r
  package is in processor-specific C4 states since last reset. Counts at 1 Mhz\r
  frequency.\r
\r
  @param  ECX  MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);\r
  AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);\r
  @endcode\r
  @note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.\r
**/\r
#define MSR_ATOM_PKG_C4_RESIDENCY                0x000003F9\r
\r
\r
/**\r
  Package. Package C6 Residency Note: C-state values are processor specific\r
  C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r
  C-States. Package. Package C6 Residency Counter. (R/O) Time that this\r
  package is in processor-specific C6 states since last reset. Counts at 1 Mhz\r
  frequency.\r
\r
  @param  ECX  MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);\r
  AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);\r
  @endcode\r
  @note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
**/\r
#define MSR_ATOM_PKG_C6_RESIDENCY                0x000003FA\r
\r
#endif\r