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1 | /** @file\r |
| 2 | MSR Definitions for Intel Core Solo and Intel Core Duo Processors.\r | |
| 3 | \r | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| 9 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
| 10 | This program and the accompanying materials\r | |
| 11 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 12 | which accompanies this distribution. The full text of the license may be found at\r | |
| 13 | http://opensource.org/licenses/bsd-license.php\r | |
| 14 | \r | |
| 15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 17 | \r | |
| 18 | @par Specification Reference:\r | |
| 19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
| 20 | December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-17.\r | |
| 21 | \r | |
| 22 | **/\r | |
| 23 | \r | |
| 24 | #ifndef __CORE_MSR_H__\r | |
| 25 | #define __CORE_MSR_H__\r | |
| 26 | \r | |
| 27 | #include <Register/ArchitecturalMsr.h>\r | |
| 28 | \r | |
| 29 | /**\r | |
| 30 | Unique. See Section 35.20, "MSRs in Pentium Processors," and see Table 35-2.\r | |
| 31 | \r | |
| 32 | @param ECX MSR_CORE_P5_MC_ADDR (0x00000000)\r | |
| 33 | @param EAX Lower 32-bits of MSR value.\r | |
| 34 | @param EDX Upper 32-bits of MSR value.\r | |
| 35 | \r | |
| 36 | <b>Example usage</b>\r | |
| 37 | @code\r | |
| 38 | UINT64 Msr;\r | |
| 39 | \r | |
| 40 | Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);\r | |
| 41 | AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);\r | |
| 42 | @endcode\r | |
| 43 | **/\r | |
| 44 | #define MSR_CORE_P5_MC_ADDR 0x00000000\r | |
| 45 | \r | |
| 46 | \r | |
| 47 | /**\r | |
| 48 | Unique. See Section 35.20, "MSRs in Pentium Processors," and see Table 35-2.\r | |
| 49 | \r | |
| 50 | @param ECX MSR_CORE_P5_MC_TYPE (0x00000001)\r | |
| 51 | @param EAX Lower 32-bits of MSR value.\r | |
| 52 | @param EDX Upper 32-bits of MSR value.\r | |
| 53 | \r | |
| 54 | <b>Example usage</b>\r | |
| 55 | @code\r | |
| 56 | UINT64 Msr;\r | |
| 57 | \r | |
| 58 | Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);\r | |
| 59 | AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);\r | |
| 60 | @endcode\r | |
| 61 | **/\r | |
| 62 | #define MSR_CORE_P5_MC_TYPE 0x00000001\r | |
| 63 | \r | |
| 64 | \r | |
| 65 | /**\r | |
| 66 | Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r | |
| 67 | processor features; (R) indicates current processor configuration.\r | |
| 68 | \r | |
| 69 | @param ECX MSR_CORE_EBL_CR_POWERON (0x0000002A)\r | |
| 70 | @param EAX Lower 32-bits of MSR value.\r | |
| 71 | Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.\r | |
| 72 | @param EDX Upper 32-bits of MSR value.\r | |
| 73 | Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.\r | |
| 74 | \r | |
| 75 | <b>Example usage</b>\r | |
| 76 | @code\r | |
| 77 | MSR_CORE_EBL_CR_POWERON_REGISTER Msr;\r | |
| 78 | \r | |
| 79 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);\r | |
| 80 | AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);\r | |
| 81 | @endcode\r | |
| 82 | **/\r | |
| 83 | #define MSR_CORE_EBL_CR_POWERON 0x0000002A\r | |
| 84 | \r | |
| 85 | /**\r | |
| 86 | MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON\r | |
| 87 | **/\r | |
| 88 | typedef union {\r | |
| 89 | ///\r | |
| 90 | /// Individual bit fields\r | |
| 91 | ///\r | |
| 92 | struct {\r | |
| 93 | UINT32 Reserved1:1;\r | |
| 94 | ///\r | |
| 95 | /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r | |
| 96 | /// Note: Not all processor implements R/W.\r | |
| 97 | ///\r | |
| 98 | UINT32 DataErrorCheckingEnable:1;\r | |
| 99 | ///\r | |
| 100 | /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r | |
| 101 | /// Note: Not all processor implements R/W.\r | |
| 102 | ///\r | |
| 103 | UINT32 ResponseErrorCheckingEnable:1;\r | |
| 104 | ///\r | |
| 105 | /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r | |
| 106 | /// all processor implements R/W.\r | |
| 107 | ///\r | |
| 108 | UINT32 MCERR_DriveEnable:1;\r | |
| 109 | ///\r | |
| 110 | /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:\r | |
| 111 | /// Not all processor implements R/W.\r | |
| 112 | ///\r | |
| 113 | UINT32 AddressParityEnable:1;\r | |
| 114 | UINT32 Reserved2:2;\r | |
| 115 | ///\r | |
| 116 | /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r | |
| 117 | /// all processor implements R/W.\r | |
| 118 | ///\r | |
| 119 | UINT32 BINIT_DriverEnable:1;\r | |
| 120 | ///\r | |
| 121 | /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r | |
| 122 | ///\r | |
| 123 | UINT32 OutputTriStateEnable:1;\r | |
| 124 | ///\r | |
| 125 | /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r | |
| 126 | ///\r | |
| 127 | UINT32 ExecuteBIST:1;\r | |
| 128 | ///\r | |
| 129 | /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r | |
| 130 | ///\r | |
| 131 | UINT32 MCERR_ObservationEnabled:1;\r | |
| 132 | UINT32 Reserved3:1;\r | |
| 133 | ///\r | |
| 134 | /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r | |
| 135 | ///\r | |
| 136 | UINT32 BINIT_ObservationEnabled:1;\r | |
| 137 | UINT32 Reserved4:1;\r | |
| 138 | ///\r | |
| 139 | /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r | |
| 140 | ///\r | |
| 141 | UINT32 ResetVector:1;\r | |
| 142 | UINT32 Reserved5:1;\r | |
| 143 | ///\r | |
| 144 | /// [Bits 17:16] APIC Cluster ID (R/O).\r | |
| 145 | ///\r | |
| 146 | UINT32 APICClusterID:2;\r | |
| 147 | ///\r | |
| 148 | /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.\r | |
| 149 | ///\r | |
| 150 | UINT32 SystemBusFrequency:1;\r | |
| 151 | UINT32 Reserved6:1;\r | |
| 152 | ///\r | |
| 153 | /// [Bits 21:20] Symmetric Arbitration ID (R/O).\r | |
| 154 | ///\r | |
| 155 | UINT32 SymmetricArbitrationID:2;\r | |
| 156 | ///\r | |
| 157 | /// [Bits 26:22] Clock Frequency Ratio (R/O).\r | |
| 158 | ///\r | |
| 159 | UINT32 ClockFrequencyRatio:5;\r | |
| 160 | UINT32 Reserved7:5;\r | |
| 161 | UINT32 Reserved8:32;\r | |
| 162 | } Bits;\r | |
| 163 | ///\r | |
| 164 | /// All bit fields as a 32-bit value\r | |
| 165 | ///\r | |
| 166 | UINT32 Uint32;\r | |
| 167 | ///\r | |
| 168 | /// All bit fields as a 64-bit value\r | |
| 169 | ///\r | |
| 170 | UINT64 Uint64;\r | |
| 171 | } MSR_CORE_EBL_CR_POWERON_REGISTER;\r | |
| 172 | \r | |
| 173 | \r | |
| 174 | /**\r | |
| 175 | Unique. Last Branch Record n (R/W) One of 8 last branch record registers on\r | |
| 176 | the last branch record stack: bits 31-0 hold the 'from' address and bits\r | |
| 177 | 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at\r | |
| 178 | 1C9H - Section 17.12, "Last Branch, Interrupt, and Exception Recording\r | |
| 179 | (Pentium M Processors).".\r | |
| 180 | \r | |
| 181 | @param ECX MSR_CORE_LASTBRANCH_n\r | |
| 182 | @param EAX Lower 32-bits of MSR value.\r | |
| 183 | @param EDX Upper 32-bits of MSR value.\r | |
| 184 | \r | |
| 185 | <b>Example usage</b>\r | |
| 186 | @code\r | |
| 187 | UINT64 Msr;\r | |
| 188 | \r | |
| 189 | Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);\r | |
| 190 | AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);\r | |
| 191 | @endcode\r | |
| 192 | @{\r | |
| 193 | **/\r | |
| 194 | #define MSR_CORE_LASTBRANCH_0 0x00000040\r | |
| 195 | #define MSR_CORE_LASTBRANCH_1 0x00000041\r | |
| 196 | #define MSR_CORE_LASTBRANCH_2 0x00000042\r | |
| 197 | #define MSR_CORE_LASTBRANCH_3 0x00000043\r | |
| 198 | #define MSR_CORE_LASTBRANCH_4 0x00000044\r | |
| 199 | #define MSR_CORE_LASTBRANCH_5 0x00000045\r | |
| 200 | #define MSR_CORE_LASTBRANCH_6 0x00000046\r | |
| 201 | #define MSR_CORE_LASTBRANCH_7 0x00000047\r | |
| 202 | /// @}\r | |
| 203 | \r | |
| 204 | \r | |
| 205 | /**\r | |
| 206 | Shared. Scalable Bus Speed (RO) This field indicates the scalable bus\r | |
| 207 | clock speed:.\r | |
| 208 | \r | |
| 209 | @param ECX MSR_CORE_FSB_FREQ (0x000000CD)\r | |
| 210 | @param EAX Lower 32-bits of MSR value.\r | |
| 211 | Described by the type MSR_CORE_FSB_FREQ_REGISTER.\r | |
| 212 | @param EDX Upper 32-bits of MSR value.\r | |
| 213 | Described by the type MSR_CORE_FSB_FREQ_REGISTER.\r | |
| 214 | \r | |
| 215 | <b>Example usage</b>\r | |
| 216 | @code\r | |
| 217 | MSR_CORE_FSB_FREQ_REGISTER Msr;\r | |
| 218 | \r | |
| 219 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);\r | |
| 220 | @endcode\r | |
| 221 | **/\r | |
| 222 | #define MSR_CORE_FSB_FREQ 0x000000CD\r | |
| 223 | \r | |
| 224 | /**\r | |
| 225 | MSR information returned for MSR index #MSR_CORE_FSB_FREQ\r | |
| 226 | **/\r | |
| 227 | typedef union {\r | |
| 228 | ///\r | |
| 229 | /// Individual bit fields\r | |
| 230 | ///\r | |
| 231 | struct {\r | |
| 232 | ///\r | |
| 233 | /// [Bits 2:0] - Scalable Bus Speed\r | |
| 234 | /// 101B: 100 MHz (FSB 400)\r | |
| 235 | /// 001B: 133 MHz (FSB 533)\r | |
| 236 | /// 011B: 167 MHz (FSB 667)\r | |
| 237 | ///\r | |
| 238 | /// 133.33 MHz should be utilized if performing calculation with System Bus\r | |
| 239 | /// Speed when encoding is 101B. 166.67 MHz should be utilized if\r | |
| 240 | /// performing calculation with System Bus Speed when encoding is 001B.\r | |
| 241 | ///\r | |
| 242 | UINT32 ScalableBusSpeed:3;\r | |
| 243 | UINT32 Reserved1:29;\r | |
| 244 | UINT32 Reserved2:32;\r | |
| 245 | } Bits;\r | |
| 246 | ///\r | |
| 247 | /// All bit fields as a 32-bit value\r | |
| 248 | ///\r | |
| 249 | UINT32 Uint32;\r | |
| 250 | ///\r | |
| 251 | /// All bit fields as a 64-bit value\r | |
| 252 | ///\r | |
| 253 | UINT64 Uint64;\r | |
| 254 | } MSR_CORE_FSB_FREQ_REGISTER;\r | |
| 255 | \r | |
| 256 | \r | |
| 257 | /**\r | |
| 258 | Shared.\r | |
| 259 | \r | |
| 260 | @param ECX MSR_CORE_BBL_CR_CTL3 (0x0000011E)\r | |
| 261 | @param EAX Lower 32-bits of MSR value.\r | |
| 262 | Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.\r | |
| 263 | @param EDX Upper 32-bits of MSR value.\r | |
| 264 | Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.\r | |
| 265 | \r | |
| 266 | <b>Example usage</b>\r | |
| 267 | @code\r | |
| 268 | MSR_CORE_BBL_CR_CTL3_REGISTER Msr;\r | |
| 269 | \r | |
| 270 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);\r | |
| 271 | AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);\r | |
| 272 | @endcode\r | |
| 273 | **/\r | |
| 274 | #define MSR_CORE_BBL_CR_CTL3 0x0000011E\r | |
| 275 | \r | |
| 276 | /**\r | |
| 277 | MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3\r | |
| 278 | **/\r | |
| 279 | typedef union {\r | |
| 280 | ///\r | |
| 281 | /// Individual bit fields\r | |
| 282 | ///\r | |
| 283 | struct {\r | |
| 284 | ///\r | |
| 285 | /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r | |
| 286 | /// Indicates if the L2 is hardware-disabled.\r | |
| 287 | ///\r | |
| 288 | UINT32 L2HardwareEnabled:1;\r | |
| 289 | UINT32 Reserved1:7;\r | |
| 290 | ///\r | |
| 291 | /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =\r | |
| 292 | /// Disabled (default) Until this bit is set the processor will not\r | |
| 293 | /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r | |
| 294 | ///\r | |
| 295 | UINT32 L2Enabled:1;\r | |
| 296 | UINT32 Reserved2:14;\r | |
| 297 | ///\r | |
| 298 | /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r | |
| 299 | ///\r | |
| 300 | UINT32 L2NotPresent:1;\r | |
| 301 | UINT32 Reserved3:8;\r | |
| 302 | UINT32 Reserved4:32;\r | |
| 303 | } Bits;\r | |
| 304 | ///\r | |
| 305 | /// All bit fields as a 32-bit value\r | |
| 306 | ///\r | |
| 307 | UINT32 Uint32;\r | |
| 308 | ///\r | |
| 309 | /// All bit fields as a 64-bit value\r | |
| 310 | ///\r | |
| 311 | UINT64 Uint64;\r | |
| 312 | } MSR_CORE_BBL_CR_CTL3_REGISTER;\r | |
| 313 | \r | |
| 314 | \r | |
| 315 | /**\r | |
| 316 | Unique.\r | |
| 317 | \r | |
| 318 | @param ECX MSR_CORE_THERM2_CTL (0x0000019D)\r | |
| 319 | @param EAX Lower 32-bits of MSR value.\r | |
| 320 | Described by the type MSR_CORE_THERM2_CTL_REGISTER.\r | |
| 321 | @param EDX Upper 32-bits of MSR value.\r | |
| 322 | Described by the type MSR_CORE_THERM2_CTL_REGISTER.\r | |
| 323 | \r | |
| 324 | <b>Example usage</b>\r | |
| 325 | @code\r | |
| 326 | MSR_CORE_THERM2_CTL_REGISTER Msr;\r | |
| 327 | \r | |
| 328 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);\r | |
| 329 | AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);\r | |
| 330 | @endcode\r | |
| 331 | **/\r | |
| 332 | #define MSR_CORE_THERM2_CTL 0x0000019D\r | |
| 333 | \r | |
| 334 | /**\r | |
| 335 | MSR information returned for MSR index #MSR_CORE_THERM2_CTL\r | |
| 336 | **/\r | |
| 337 | typedef union {\r | |
| 338 | ///\r | |
| 339 | /// Individual bit fields\r | |
| 340 | ///\r | |
| 341 | struct {\r | |
| 342 | UINT32 Reserved1:16;\r | |
| 343 | ///\r | |
| 344 | /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r | |
| 345 | /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r | |
| 346 | /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r | |
| 347 | /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r | |
| 348 | /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.\r | |
| 349 | ///\r | |
| 350 | UINT32 TM_SELECT:1;\r | |
| 351 | UINT32 Reserved2:15;\r | |
| 352 | UINT32 Reserved3:32;\r | |
| 353 | } Bits;\r | |
| 354 | ///\r | |
| 355 | /// All bit fields as a 32-bit value\r | |
| 356 | ///\r | |
| 357 | UINT32 Uint32;\r | |
| 358 | ///\r | |
| 359 | /// All bit fields as a 64-bit value\r | |
| 360 | ///\r | |
| 361 | UINT64 Uint64;\r | |
| 362 | } MSR_CORE_THERM2_CTL_REGISTER;\r | |
| 363 | \r | |
| 364 | \r | |
| 365 | /**\r | |
| 366 | Enable Miscellaneous Processor Features (R/W) Allows a variety of processor\r | |
| 367 | functions to be enabled and disabled.\r | |
| 368 | \r | |
| 369 | @param ECX MSR_CORE_IA32_MISC_ENABLE (0x000001A0)\r | |
| 370 | @param EAX Lower 32-bits of MSR value.\r | |
| 371 | Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.\r | |
| 372 | @param EDX Upper 32-bits of MSR value.\r | |
| 373 | Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.\r | |
| 374 | \r | |
| 375 | <b>Example usage</b>\r | |
| 376 | @code\r | |
| 377 | MSR_CORE_IA32_MISC_ENABLE_REGISTER Msr;\r | |
| 378 | \r | |
| 379 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);\r | |
| 380 | AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);\r | |
| 381 | @endcode\r | |
| 382 | **/\r | |
| 383 | #define MSR_CORE_IA32_MISC_ENABLE 0x000001A0\r | |
| 384 | \r | |
| 385 | /**\r | |
| 386 | MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE\r | |
| 387 | **/\r | |
| 388 | typedef union {\r | |
| 389 | ///\r | |
| 390 | /// Individual bit fields\r | |
| 391 | ///\r | |
| 392 | struct {\r | |
| 393 | UINT32 Reserved1:3;\r | |
| 394 | ///\r | |
| 395 | /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r | |
| 396 | /// Table 35-2.\r | |
| 397 | ///\r | |
| 398 | UINT32 AutomaticThermalControlCircuit:1;\r | |
| 399 | UINT32 Reserved2:3;\r | |
| 400 | ///\r | |
| 401 | /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.\r | |
| 402 | ///\r | |
| 403 | UINT32 PerformanceMonitoring:1;\r | |
| 404 | UINT32 Reserved3:2;\r | |
| 405 | ///\r | |
| 406 | /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r | |
| 407 | /// the processor to indicate a pending break event within the processor 0\r | |
| 408 | /// = Indicates compatible FERR# signaling behavior This bit must be set\r | |
| 409 | /// to 1 to support XAPIC interrupt model usage.\r | |
| 410 | ///\r | |
| 411 | UINT32 FERR:1;\r | |
| 412 | ///\r | |
| 413 | /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.\r | |
| 414 | ///\r | |
| 415 | UINT32 BTS:1;\r | |
| 416 | UINT32 Reserved4:1;\r | |
| 417 | ///\r | |
| 418 | /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r | |
| 419 | /// thermal sensor indicates that the die temperature is at the\r | |
| 420 | /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.\r | |
| 421 | /// TM2 will reduce the bus to core ratio and voltage according to the\r | |
| 422 | /// value last written to MSR_THERM2_CTL bits 15:0.\r | |
| 423 | /// When this bit is clear (0, default), the processor does not change\r | |
| 424 | /// the VID signals or the bus to core ratio when the processor enters a\r | |
| 425 | /// thermal managed state. If the TM2 feature flag (ECX[8]) is not set\r | |
| 426 | /// to 1 after executing CPUID with EAX = 1, then this feature is not\r | |
| 427 | /// supported and BIOS must not alter the contents of this bit location.\r | |
| 428 | /// The processor is operating out of spec if both this bit and the TM1\r | |
| 429 | /// bit are set to disabled states.\r | |
| 430 | ///\r | |
| 431 | UINT32 TM2:1;\r | |
| 432 | UINT32 Reserved5:2;\r | |
| 433 | ///\r | |
| 434 | /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 =\r | |
| 435 | /// Enhanced Intel SpeedStep Technology enabled.\r | |
| 436 | ///\r | |
| 437 | UINT32 EIST:1;\r | |
| 438 | UINT32 Reserved6:1;\r | |
| 439 | ///\r | |
| 440 | /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.\r | |
| 441 | ///\r | |
| 442 | UINT32 MONITOR:1;\r | |
| 443 | UINT32 Reserved7:1;\r | |
| 444 | UINT32 Reserved8:2;\r | |
| 445 | ///\r | |
| 446 | /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2. Setting this\r | |
| 447 | /// bit may cause behavior in software that depends on the availability of\r | |
| 448 | /// CPUID leaves greater than 3.\r | |
| 449 | ///\r | |
| 450 | UINT32 LimitCpuidMaxval:1;\r | |
| 451 | UINT32 Reserved9:9;\r | |
| 452 | UINT32 Reserved10:2;\r | |
| 453 | ///\r | |
| 454 | /// [Bit 34] Shared. XD Bit Disable (R/W) See Table 35-2.\r | |
| 455 | ///\r | |
| 456 | UINT32 XD:1;\r | |
| 457 | UINT32 Reserved11:29;\r | |
| 458 | } Bits;\r | |
| 459 | ///\r | |
| 460 | /// All bit fields as a 64-bit value\r | |
| 461 | ///\r | |
| 462 | UINT64 Uint64;\r | |
| 463 | } MSR_CORE_IA32_MISC_ENABLE_REGISTER;\r | |
| 464 | \r | |
| 465 | \r | |
| 466 | /**\r | |
| 467 | Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r | |
| 468 | that points to the MSR containing the most recent branch record. See\r | |
| 469 | MSR_LASTBRANCH_0_FROM_IP (at 40H).\r | |
| 470 | \r | |
| 471 | @param ECX MSR_CORE_LASTBRANCH_TOS (0x000001C9)\r | |
| 472 | @param EAX Lower 32-bits of MSR value.\r | |
| 473 | @param EDX Upper 32-bits of MSR value.\r | |
| 474 | \r | |
| 475 | <b>Example usage</b>\r | |
| 476 | @code\r | |
| 477 | UINT64 Msr;\r | |
| 478 | \r | |
| 479 | Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);\r | |
| 480 | AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);\r | |
| 481 | @endcode\r | |
| 482 | **/\r | |
| 483 | #define MSR_CORE_LASTBRANCH_TOS 0x000001C9\r | |
| 484 | \r | |
| 485 | \r | |
| 486 | /**\r | |
| 487 | Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r | |
| 488 | last branch instruction that the processor executed prior to the last\r | |
| 489 | exception that was generated or the last interrupt that was handled.\r | |
| 490 | \r | |
| 491 | @param ECX MSR_CORE_LER_FROM_LIP (0x000001DD)\r | |
| 492 | @param EAX Lower 32-bits of MSR value.\r | |
| 493 | @param EDX Upper 32-bits of MSR value.\r | |
| 494 | \r | |
| 495 | <b>Example usage</b>\r | |
| 496 | @code\r | |
| 497 | UINT64 Msr;\r | |
| 498 | \r | |
| 499 | Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);\r | |
| 500 | @endcode\r | |
| 501 | **/\r | |
| 502 | #define MSR_CORE_LER_FROM_LIP 0x000001DD\r | |
| 503 | \r | |
| 504 | \r | |
| 505 | /**\r | |
| 506 | Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r | |
| 507 | to the target of the last branch instruction that the processor executed\r | |
| 508 | prior to the last exception that was generated or the last interrupt that\r | |
| 509 | was handled.\r | |
| 510 | \r | |
| 511 | @param ECX MSR_CORE_LER_TO_LIP (0x000001DE)\r | |
| 512 | @param EAX Lower 32-bits of MSR value.\r | |
| 513 | @param EDX Upper 32-bits of MSR value.\r | |
| 514 | \r | |
| 515 | <b>Example usage</b>\r | |
| 516 | @code\r | |
| 517 | UINT64 Msr;\r | |
| 518 | \r | |
| 519 | Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);\r | |
| 520 | @endcode\r | |
| 521 | **/\r | |
| 522 | #define MSR_CORE_LER_TO_LIP 0x000001DE\r | |
| 523 | \r | |
| 524 | \r | |
| 525 | /**\r | |
| 526 | Unique.\r | |
| 527 | \r | |
| 528 | @param ECX MSR_CORE_ROB_CR_BKUPTMPDR6 (0x000001E0)\r | |
| 529 | @param EAX Lower 32-bits of MSR value.\r | |
| 530 | Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.\r | |
| 531 | @param EDX Upper 32-bits of MSR value.\r | |
| 532 | Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.\r | |
| 533 | \r | |
| 534 | <b>Example usage</b>\r | |
| 535 | @code\r | |
| 536 | MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER Msr;\r | |
| 537 | \r | |
| 538 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6);\r | |
| 539 | AsmWriteMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6, Msr.Uint64);\r | |
| 540 | @endcode\r | |
| 541 | **/\r | |
| 542 | #define MSR_CORE_ROB_CR_BKUPTMPDR6 0x000001E0\r | |
| 543 | \r | |
| 544 | /**\r | |
| 545 | MSR information returned for MSR index #MSR_CORE_ROB_CR_BKUPTMPDR6\r | |
| 546 | **/\r | |
| 547 | typedef union {\r | |
| 548 | ///\r | |
| 549 | /// Individual bit fields\r | |
| 550 | ///\r | |
| 551 | struct {\r | |
| 552 | UINT32 Reserved1:2;\r | |
| 553 | ///\r | |
| 554 | /// [Bit 2] Fast Strings Enable bit. (Default, enabled).\r | |
| 555 | ///\r | |
| 556 | UINT32 FastStrings:1;\r | |
| 557 | UINT32 Reserved2:29;\r | |
| 558 | UINT32 Reserved3:32;\r | |
| 559 | } Bits;\r | |
| 560 | ///\r | |
| 561 | /// All bit fields as a 32-bit value\r | |
| 562 | ///\r | |
| 563 | UINT32 Uint32;\r | |
| 564 | ///\r | |
| 565 | /// All bit fields as a 64-bit value\r | |
| 566 | ///\r | |
| 567 | UINT64 Uint64;\r | |
| 568 | } MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER;\r | |
| 569 | \r | |
| 570 | \r | |
| 571 | /**\r | |
| 572 | Unique.\r | |
| 573 | \r | |
| 574 | @param ECX MSR_CORE_MTRRPHYSBASEn\r | |
| 575 | @param EAX Lower 32-bits of MSR value.\r | |
| 576 | @param EDX Upper 32-bits of MSR value.\r | |
| 577 | \r | |
| 578 | <b>Example usage</b>\r | |
| 579 | @code\r | |
| 580 | UINT64 Msr;\r | |
| 581 | \r | |
| 582 | Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);\r | |
| 583 | AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);\r | |
| 584 | @endcode\r | |
| 585 | @{\r | |
| 586 | **/\r | |
| 587 | #define MSR_CORE_MTRRPHYSBASE0 0x00000200\r | |
| 588 | #define MSR_CORE_MTRRPHYSBASE1 0x00000202\r | |
| 589 | #define MSR_CORE_MTRRPHYSBASE2 0x00000204\r | |
| 590 | #define MSR_CORE_MTRRPHYSBASE3 0x00000206\r | |
| 591 | #define MSR_CORE_MTRRPHYSBASE4 0x00000208\r | |
| 592 | #define MSR_CORE_MTRRPHYSBASE5 0x0000020A\r | |
| 593 | #define MSR_CORE_MTRRPHYSMASK6 0x0000020D\r | |
| 594 | #define MSR_CORE_MTRRPHYSMASK7 0x0000020F\r | |
| 595 | /// @}\r | |
| 596 | \r | |
| 597 | \r | |
| 598 | /**\r | |
| 599 | Unique.\r | |
| 600 | \r | |
| 601 | @param ECX MSR_CORE_MTRRPHYSMASKn (0x00000201)\r | |
| 602 | @param EAX Lower 32-bits of MSR value.\r | |
| 603 | @param EDX Upper 32-bits of MSR value.\r | |
| 604 | \r | |
| 605 | <b>Example usage</b>\r | |
| 606 | @code\r | |
| 607 | UINT64 Msr;\r | |
| 608 | \r | |
| 609 | Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);\r | |
| 610 | AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);\r | |
| 611 | @endcode\r | |
| 612 | @{\r | |
| 613 | **/\r | |
| 614 | #define MSR_CORE_MTRRPHYSMASK0 0x00000201\r | |
| 615 | #define MSR_CORE_MTRRPHYSMASK1 0x00000203\r | |
| 616 | #define MSR_CORE_MTRRPHYSMASK2 0x00000205\r | |
| 617 | #define MSR_CORE_MTRRPHYSMASK3 0x00000207\r | |
| 618 | #define MSR_CORE_MTRRPHYSMASK4 0x00000209\r | |
| 619 | #define MSR_CORE_MTRRPHYSMASK5 0x0000020B\r | |
| 620 | #define MSR_CORE_MTRRPHYSBASE6 0x0000020C\r | |
| 621 | #define MSR_CORE_MTRRPHYSBASE7 0x0000020E\r | |
| 622 | /// @}\r | |
| 623 | \r | |
| 624 | \r | |
| 625 | /**\r | |
| 626 | Unique.\r | |
| 627 | \r | |
| 628 | @param ECX MSR_CORE_MTRRFIX64K_00000 (0x00000250)\r | |
| 629 | @param EAX Lower 32-bits of MSR value.\r | |
| 630 | @param EDX Upper 32-bits of MSR value.\r | |
| 631 | \r | |
| 632 | <b>Example usage</b>\r | |
| 633 | @code\r | |
| 634 | UINT64 Msr;\r | |
| 635 | \r | |
| 636 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000);\r | |
| 637 | AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr);\r | |
| 638 | @endcode\r | |
| 639 | **/\r | |
| 640 | #define MSR_CORE_MTRRFIX64K_00000 0x00000250\r | |
| 641 | \r | |
| 642 | \r | |
| 643 | /**\r | |
| 644 | Unique.\r | |
| 645 | \r | |
| 646 | @param ECX MSR_CORE_MTRRFIX16K_80000 (0x00000258)\r | |
| 647 | @param EAX Lower 32-bits of MSR value.\r | |
| 648 | @param EDX Upper 32-bits of MSR value.\r | |
| 649 | \r | |
| 650 | <b>Example usage</b>\r | |
| 651 | @code\r | |
| 652 | UINT64 Msr;\r | |
| 653 | \r | |
| 654 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000);\r | |
| 655 | AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr);\r | |
| 656 | @endcode\r | |
| 657 | **/\r | |
| 658 | #define MSR_CORE_MTRRFIX16K_80000 0x00000258\r | |
| 659 | \r | |
| 660 | \r | |
| 661 | /**\r | |
| 662 | Unique.\r | |
| 663 | \r | |
| 664 | @param ECX MSR_CORE_MTRRFIX16K_A0000 (0x00000259)\r | |
| 665 | @param EAX Lower 32-bits of MSR value.\r | |
| 666 | @param EDX Upper 32-bits of MSR value.\r | |
| 667 | \r | |
| 668 | <b>Example usage</b>\r | |
| 669 | @code\r | |
| 670 | UINT64 Msr;\r | |
| 671 | \r | |
| 672 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000);\r | |
| 673 | AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr);\r | |
| 674 | @endcode\r | |
| 675 | **/\r | |
| 676 | #define MSR_CORE_MTRRFIX16K_A0000 0x00000259\r | |
| 677 | \r | |
| 678 | \r | |
| 679 | /**\r | |
| 680 | Unique.\r | |
| 681 | \r | |
| 682 | @param ECX MSR_CORE_MTRRFIX4K_C0000 (0x00000268)\r | |
| 683 | @param EAX Lower 32-bits of MSR value.\r | |
| 684 | @param EDX Upper 32-bits of MSR value.\r | |
| 685 | \r | |
| 686 | <b>Example usage</b>\r | |
| 687 | @code\r | |
| 688 | UINT64 Msr;\r | |
| 689 | \r | |
| 690 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000);\r | |
| 691 | AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr);\r | |
| 692 | @endcode\r | |
| 693 | **/\r | |
| 694 | #define MSR_CORE_MTRRFIX4K_C0000 0x00000268\r | |
| 695 | \r | |
| 696 | \r | |
| 697 | /**\r | |
| 698 | Unique.\r | |
| 699 | \r | |
| 700 | @param ECX MSR_CORE_MTRRFIX4K_C8000 (0x00000269)\r | |
| 701 | @param EAX Lower 32-bits of MSR value.\r | |
| 702 | @param EDX Upper 32-bits of MSR value.\r | |
| 703 | \r | |
| 704 | <b>Example usage</b>\r | |
| 705 | @code\r | |
| 706 | UINT64 Msr;\r | |
| 707 | \r | |
| 708 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000);\r | |
| 709 | AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr);\r | |
| 710 | @endcode\r | |
| 711 | **/\r | |
| 712 | #define MSR_CORE_MTRRFIX4K_C8000 0x00000269\r | |
| 713 | \r | |
| 714 | \r | |
| 715 | /**\r | |
| 716 | Unique.\r | |
| 717 | \r | |
| 718 | @param ECX MSR_CORE_MTRRFIX4K_D0000 (0x0000026A)\r | |
| 719 | @param EAX Lower 32-bits of MSR value.\r | |
| 720 | @param EDX Upper 32-bits of MSR value.\r | |
| 721 | \r | |
| 722 | <b>Example usage</b>\r | |
| 723 | @code\r | |
| 724 | UINT64 Msr;\r | |
| 725 | \r | |
| 726 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000);\r | |
| 727 | AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr);\r | |
| 728 | @endcode\r | |
| 729 | **/\r | |
| 730 | #define MSR_CORE_MTRRFIX4K_D0000 0x0000026A\r | |
| 731 | \r | |
| 732 | \r | |
| 733 | /**\r | |
| 734 | Unique.\r | |
| 735 | \r | |
| 736 | @param ECX MSR_CORE_MTRRFIX4K_D8000 (0x0000026B)\r | |
| 737 | @param EAX Lower 32-bits of MSR value.\r | |
| 738 | @param EDX Upper 32-bits of MSR value.\r | |
| 739 | \r | |
| 740 | <b>Example usage</b>\r | |
| 741 | @code\r | |
| 742 | UINT64 Msr;\r | |
| 743 | \r | |
| 744 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000);\r | |
| 745 | AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr);\r | |
| 746 | @endcode\r | |
| 747 | **/\r | |
| 748 | #define MSR_CORE_MTRRFIX4K_D8000 0x0000026B\r | |
| 749 | \r | |
| 750 | \r | |
| 751 | /**\r | |
| 752 | Unique.\r | |
| 753 | \r | |
| 754 | @param ECX MSR_CORE_MTRRFIX4K_E0000 (0x0000026C)\r | |
| 755 | @param EAX Lower 32-bits of MSR value.\r | |
| 756 | @param EDX Upper 32-bits of MSR value.\r | |
| 757 | \r | |
| 758 | <b>Example usage</b>\r | |
| 759 | @code\r | |
| 760 | UINT64 Msr;\r | |
| 761 | \r | |
| 762 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000);\r | |
| 763 | AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr);\r | |
| 764 | @endcode\r | |
| 765 | **/\r | |
| 766 | #define MSR_CORE_MTRRFIX4K_E0000 0x0000026C\r | |
| 767 | \r | |
| 768 | \r | |
| 769 | /**\r | |
| 770 | Unique.\r | |
| 771 | \r | |
| 772 | @param ECX MSR_CORE_MTRRFIX4K_E8000 (0x0000026D)\r | |
| 773 | @param EAX Lower 32-bits of MSR value.\r | |
| 774 | @param EDX Upper 32-bits of MSR value.\r | |
| 775 | \r | |
| 776 | <b>Example usage</b>\r | |
| 777 | @code\r | |
| 778 | UINT64 Msr;\r | |
| 779 | \r | |
| 780 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000);\r | |
| 781 | AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr);\r | |
| 782 | @endcode\r | |
| 783 | **/\r | |
| 784 | #define MSR_CORE_MTRRFIX4K_E8000 0x0000026D\r | |
| 785 | \r | |
| 786 | \r | |
| 787 | /**\r | |
| 788 | Unique.\r | |
| 789 | \r | |
| 790 | @param ECX MSR_CORE_MTRRFIX4K_F0000 (0x0000026E)\r | |
| 791 | @param EAX Lower 32-bits of MSR value.\r | |
| 792 | @param EDX Upper 32-bits of MSR value.\r | |
| 793 | \r | |
| 794 | <b>Example usage</b>\r | |
| 795 | @code\r | |
| 796 | UINT64 Msr;\r | |
| 797 | \r | |
| 798 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000);\r | |
| 799 | AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr);\r | |
| 800 | @endcode\r | |
| 801 | **/\r | |
| 802 | #define MSR_CORE_MTRRFIX4K_F0000 0x0000026E\r | |
| 803 | \r | |
| 804 | \r | |
| 805 | /**\r | |
| 806 | Unique.\r | |
| 807 | \r | |
| 808 | @param ECX MSR_CORE_MTRRFIX4K_F8000 (0x0000026F)\r | |
| 809 | @param EAX Lower 32-bits of MSR value.\r | |
| 810 | @param EDX Upper 32-bits of MSR value.\r | |
| 811 | \r | |
| 812 | <b>Example usage</b>\r | |
| 813 | @code\r | |
| 814 | UINT64 Msr;\r | |
| 815 | \r | |
| 816 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000);\r | |
| 817 | AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr);\r | |
| 818 | @endcode\r | |
| 819 | **/\r | |
| 820 | #define MSR_CORE_MTRRFIX4K_F8000 0x0000026F\r | |
| 821 | \r | |
| 822 | \r | |
| 823 | /**\r | |
| 824 | Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r | |
| 825 | \r | |
| 826 | @param ECX MSR_CORE_MC4_CTL (0x0000040C)\r | |
| 827 | @param EAX Lower 32-bits of MSR value.\r | |
| 828 | @param EDX Upper 32-bits of MSR value.\r | |
| 829 | \r | |
| 830 | <b>Example usage</b>\r | |
| 831 | @code\r | |
| 832 | UINT64 Msr;\r | |
| 833 | \r | |
| 834 | Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL);\r | |
| 835 | AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr);\r | |
| 836 | @endcode\r | |
| 837 | **/\r | |
| 838 | #define MSR_CORE_MC4_CTL 0x0000040C\r | |
| 839 | \r | |
| 840 | \r | |
| 841 | /**\r | |
| 842 | Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r | |
| 843 | \r | |
| 844 | @param ECX MSR_CORE_MC4_STATUS (0x0000040D)\r | |
| 845 | @param EAX Lower 32-bits of MSR value.\r | |
| 846 | @param EDX Upper 32-bits of MSR value.\r | |
| 847 | \r | |
| 848 | <b>Example usage</b>\r | |
| 849 | @code\r | |
| 850 | UINT64 Msr;\r | |
| 851 | \r | |
| 852 | Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS);\r | |
| 853 | AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr);\r | |
| 854 | @endcode\r | |
| 855 | **/\r | |
| 856 | #define MSR_CORE_MC4_STATUS 0x0000040D\r | |
| 857 | \r | |
| 858 | \r | |
| 859 | /**\r | |
| 860 | Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR\r | |
| 861 | register is either not implemented or contains no address if the ADDRV flag\r | |
| 862 | in the MSR_MC4_STATUS register is clear. When not implemented in the\r | |
| 863 | processor, all reads and writes to this MSR will cause a general-protection\r | |
| 864 | exception.\r | |
| 865 | \r | |
| 866 | @param ECX MSR_CORE_MC4_ADDR (0x0000040E)\r | |
| 867 | @param EAX Lower 32-bits of MSR value.\r | |
| 868 | @param EDX Upper 32-bits of MSR value.\r | |
| 869 | \r | |
| 870 | <b>Example usage</b>\r | |
| 871 | @code\r | |
| 872 | UINT64 Msr;\r | |
| 873 | \r | |
| 874 | Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR);\r | |
| 875 | AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr);\r | |
| 876 | @endcode\r | |
| 877 | **/\r | |
| 878 | #define MSR_CORE_MC4_ADDR 0x0000040E\r | |
| 879 | \r | |
| 880 | \r | |
| 881 | /**\r | |
| 882 | See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r | |
| 883 | \r | |
| 884 | @param ECX MSR_CORE_MC3_CTL (0x00000410)\r | |
| 885 | @param EAX Lower 32-bits of MSR value.\r | |
| 886 | @param EDX Upper 32-bits of MSR value.\r | |
| 887 | \r | |
| 888 | <b>Example usage</b>\r | |
| 889 | @code\r | |
| 890 | UINT64 Msr;\r | |
| 891 | \r | |
| 892 | Msr = AsmReadMsr64 (MSR_CORE_MC3_CTL);\r | |
| 893 | AsmWriteMsr64 (MSR_CORE_MC3_CTL, Msr);\r | |
| 894 | @endcode\r | |
| 895 | **/\r | |
| 896 | #define MSR_CORE_MC3_CTL 0x00000410\r | |
| 897 | \r | |
| 898 | \r | |
| 899 | /**\r | |
| 900 | See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r | |
| 901 | \r | |
| 902 | @param ECX MSR_CORE_MC3_STATUS (0x00000411)\r | |
| 903 | @param EAX Lower 32-bits of MSR value.\r | |
| 904 | @param EDX Upper 32-bits of MSR value.\r | |
| 905 | \r | |
| 906 | <b>Example usage</b>\r | |
| 907 | @code\r | |
| 908 | UINT64 Msr;\r | |
| 909 | \r | |
| 910 | Msr = AsmReadMsr64 (MSR_CORE_MC3_STATUS);\r | |
| 911 | AsmWriteMsr64 (MSR_CORE_MC3_STATUS, Msr);\r | |
| 912 | @endcode\r | |
| 913 | **/\r | |
| 914 | #define MSR_CORE_MC3_STATUS 0x00000411\r | |
| 915 | \r | |
| 916 | \r | |
| 917 | /**\r | |
| 918 | Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR\r | |
| 919 | register is either not implemented or contains no address if the ADDRV flag\r | |
| 920 | in the MSR_MC3_STATUS register is clear. When not implemented in the\r | |
| 921 | processor, all reads and writes to this MSR will cause a general-protection\r | |
| 922 | exception.\r | |
| 923 | \r | |
| 924 | @param ECX MSR_CORE_MC3_ADDR (0x00000412)\r | |
| 925 | @param EAX Lower 32-bits of MSR value.\r | |
| 926 | @param EDX Upper 32-bits of MSR value.\r | |
| 927 | \r | |
| 928 | <b>Example usage</b>\r | |
| 929 | @code\r | |
| 930 | UINT64 Msr;\r | |
| 931 | \r | |
| 932 | Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR);\r | |
| 933 | AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr);\r | |
| 934 | @endcode\r | |
| 935 | **/\r | |
| 936 | #define MSR_CORE_MC3_ADDR 0x00000412\r | |
| 937 | \r | |
| 938 | \r | |
| 939 | /**\r | |
| 940 | Unique.\r | |
| 941 | \r | |
| 942 | @param ECX MSR_CORE_MC3_MISC (0x00000413)\r | |
| 943 | @param EAX Lower 32-bits of MSR value.\r | |
| 944 | @param EDX Upper 32-bits of MSR value.\r | |
| 945 | \r | |
| 946 | <b>Example usage</b>\r | |
| 947 | @code\r | |
| 948 | UINT64 Msr;\r | |
| 949 | \r | |
| 950 | Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC);\r | |
| 951 | AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr);\r | |
| 952 | @endcode\r | |
| 953 | **/\r | |
| 954 | #define MSR_CORE_MC3_MISC 0x00000413\r | |
| 955 | \r | |
| 956 | \r | |
| 957 | /**\r | |
| 958 | Unique.\r | |
| 959 | \r | |
| 960 | @param ECX MSR_CORE_MC5_CTL (0x00000414)\r | |
| 961 | @param EAX Lower 32-bits of MSR value.\r | |
| 962 | @param EDX Upper 32-bits of MSR value.\r | |
| 963 | \r | |
| 964 | <b>Example usage</b>\r | |
| 965 | @code\r | |
| 966 | UINT64 Msr;\r | |
| 967 | \r | |
| 968 | Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL);\r | |
| 969 | AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr);\r | |
| 970 | @endcode\r | |
| 971 | **/\r | |
| 972 | #define MSR_CORE_MC5_CTL 0x00000414\r | |
| 973 | \r | |
| 974 | \r | |
| 975 | /**\r | |
| 976 | Unique.\r | |
| 977 | \r | |
| 978 | @param ECX MSR_CORE_MC5_STATUS (0x00000415)\r | |
| 979 | @param EAX Lower 32-bits of MSR value.\r | |
| 980 | @param EDX Upper 32-bits of MSR value.\r | |
| 981 | \r | |
| 982 | <b>Example usage</b>\r | |
| 983 | @code\r | |
| 984 | UINT64 Msr;\r | |
| 985 | \r | |
| 986 | Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS);\r | |
| 987 | AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr);\r | |
| 988 | @endcode\r | |
| 989 | **/\r | |
| 990 | #define MSR_CORE_MC5_STATUS 0x00000415\r | |
| 991 | \r | |
| 992 | \r | |
| 993 | /**\r | |
| 994 | Unique.\r | |
| 995 | \r | |
| 996 | @param ECX MSR_CORE_MC5_ADDR (0x00000416)\r | |
| 997 | @param EAX Lower 32-bits of MSR value.\r | |
| 998 | @param EDX Upper 32-bits of MSR value.\r | |
| 999 | \r | |
| 1000 | <b>Example usage</b>\r | |
| 1001 | @code\r | |
| 1002 | UINT64 Msr;\r | |
| 1003 | \r | |
| 1004 | Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR);\r | |
| 1005 | AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr);\r | |
| 1006 | @endcode\r | |
| 1007 | **/\r | |
| 1008 | #define MSR_CORE_MC5_ADDR 0x00000416\r | |
| 1009 | \r | |
| 1010 | \r | |
| 1011 | /**\r | |
| 1012 | Unique.\r | |
| 1013 | \r | |
| 1014 | @param ECX MSR_CORE_MC5_MISC (0x00000417)\r | |
| 1015 | @param EAX Lower 32-bits of MSR value.\r | |
| 1016 | @param EDX Upper 32-bits of MSR value.\r | |
| 1017 | \r | |
| 1018 | <b>Example usage</b>\r | |
| 1019 | @code\r | |
| 1020 | UINT64 Msr;\r | |
| 1021 | \r | |
| 1022 | Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC);\r | |
| 1023 | AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr);\r | |
| 1024 | @endcode\r | |
| 1025 | **/\r | |
| 1026 | #define MSR_CORE_MC5_MISC 0x00000417\r | |
| 1027 | \r | |
| 1028 | \r | |
| 1029 | /**\r | |
| 1030 | Unique. See Table 35-2.\r | |
| 1031 | \r | |
| 1032 | @param ECX MSR_CORE_IA32_EFER (0xC0000080)\r | |
| 1033 | @param EAX Lower 32-bits of MSR value.\r | |
| 1034 | Described by the type MSR_CORE_IA32_EFER_REGISTER.\r | |
| 1035 | @param EDX Upper 32-bits of MSR value.\r | |
| 1036 | Described by the type MSR_CORE_IA32_EFER_REGISTER.\r | |
| 1037 | \r | |
| 1038 | <b>Example usage</b>\r | |
| 1039 | @code\r | |
| 1040 | MSR_CORE_IA32_EFER_REGISTER Msr;\r | |
| 1041 | \r | |
| 1042 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);\r | |
| 1043 | AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64);\r | |
| 1044 | @endcode\r | |
| 1045 | **/\r | |
| 1046 | #define MSR_CORE_IA32_EFER 0xC0000080\r | |
| 1047 | \r | |
| 1048 | /**\r | |
| 1049 | MSR information returned for MSR index #MSR_CORE_IA32_EFER\r | |
| 1050 | **/\r | |
| 1051 | typedef union {\r | |
| 1052 | ///\r | |
| 1053 | /// Individual bit fields\r | |
| 1054 | ///\r | |
| 1055 | struct {\r | |
| 1056 | UINT32 Reserved1:11;\r | |
| 1057 | ///\r | |
| 1058 | /// [Bit 11] Execute Disable Bit Enable.\r | |
| 1059 | ///\r | |
| 1060 | UINT32 NXE:1;\r | |
| 1061 | UINT32 Reserved2:20;\r | |
| 1062 | UINT32 Reserved3:32;\r | |
| 1063 | } Bits;\r | |
| 1064 | ///\r | |
| 1065 | /// All bit fields as a 32-bit value\r | |
| 1066 | ///\r | |
| 1067 | UINT32 Uint32;\r | |
| 1068 | ///\r | |
| 1069 | /// All bit fields as a 64-bit value\r | |
| 1070 | ///\r | |
| 1071 | UINT64 Uint64;\r | |
| 1072 | } MSR_CORE_IA32_EFER_REGISTER;\r | |
| 1073 | \r | |
| 1074 | #endif\r |