]>
Commit | Line | Data |
---|---|---|
e0d87abe MK |
1 | /** @file\r |
2 | MSR Definitions for Intel Core Solo and Intel Core Duo Processors.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
f4c982bf | 9 | Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r |
e0d87abe MK |
10 | This program and the accompanying materials\r |
11 | are licensed and made available under the terms and conditions of the BSD License\r | |
12 | which accompanies this distribution. The full text of the license may be found at\r | |
13 | http://opensource.org/licenses/bsd-license.php\r | |
14 | \r | |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | \r | |
18 | @par Specification Reference:\r | |
19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
0f16be6d | 20 | September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.19.\r |
e0d87abe MK |
21 | \r |
22 | **/\r | |
23 | \r | |
24 | #ifndef __CORE_MSR_H__\r | |
25 | #define __CORE_MSR_H__\r | |
26 | \r | |
27 | #include <Register/ArchitecturalMsr.h>\r | |
28 | \r | |
f4c982bf JF |
29 | /**\r |
30 | Is Intel Core Solo and Intel Core Duo Processors?\r | |
31 | \r | |
32 | @param DisplayFamily Display Family ID\r | |
33 | @param DisplayModel Display Model ID\r | |
34 | \r | |
35 | @retval TRUE Yes, it is.\r | |
36 | @retval FALSE No, it isn't.\r | |
37 | **/\r | |
38 | #define IS_CORE_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
39 | (DisplayFamily == 0x06 && \\r | |
40 | ( \\r | |
41 | DisplayModel == 0x0E \\r | |
42 | ) \\r | |
43 | )\r | |
44 | \r | |
e0d87abe | 45 | /**\r |
0f16be6d | 46 | Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.\r |
e0d87abe MK |
47 | \r |
48 | @param ECX MSR_CORE_P5_MC_ADDR (0x00000000)\r | |
49 | @param EAX Lower 32-bits of MSR value.\r | |
50 | @param EDX Upper 32-bits of MSR value.\r | |
51 | \r | |
52 | <b>Example usage</b>\r | |
53 | @code\r | |
54 | UINT64 Msr;\r | |
55 | \r | |
56 | Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);\r | |
57 | AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);\r | |
58 | @endcode\r | |
adf10974 | 59 | @note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r |
e0d87abe MK |
60 | **/\r |
61 | #define MSR_CORE_P5_MC_ADDR 0x00000000\r | |
62 | \r | |
63 | \r | |
64 | /**\r | |
0f16be6d | 65 | Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.\r |
e0d87abe MK |
66 | \r |
67 | @param ECX MSR_CORE_P5_MC_TYPE (0x00000001)\r | |
68 | @param EAX Lower 32-bits of MSR value.\r | |
69 | @param EDX Upper 32-bits of MSR value.\r | |
70 | \r | |
71 | <b>Example usage</b>\r | |
72 | @code\r | |
73 | UINT64 Msr;\r | |
74 | \r | |
75 | Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);\r | |
76 | AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);\r | |
77 | @endcode\r | |
adf10974 | 78 | @note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r |
e0d87abe MK |
79 | **/\r |
80 | #define MSR_CORE_P5_MC_TYPE 0x00000001\r | |
81 | \r | |
82 | \r | |
83 | /**\r | |
84 | Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r | |
85 | processor features; (R) indicates current processor configuration.\r | |
86 | \r | |
87 | @param ECX MSR_CORE_EBL_CR_POWERON (0x0000002A)\r | |
88 | @param EAX Lower 32-bits of MSR value.\r | |
89 | Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.\r | |
90 | @param EDX Upper 32-bits of MSR value.\r | |
91 | Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.\r | |
92 | \r | |
93 | <b>Example usage</b>\r | |
94 | @code\r | |
95 | MSR_CORE_EBL_CR_POWERON_REGISTER Msr;\r | |
96 | \r | |
97 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);\r | |
98 | AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);\r | |
99 | @endcode\r | |
adf10974 | 100 | @note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r |
e0d87abe MK |
101 | **/\r |
102 | #define MSR_CORE_EBL_CR_POWERON 0x0000002A\r | |
103 | \r | |
104 | /**\r | |
105 | MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON\r | |
106 | **/\r | |
107 | typedef union {\r | |
108 | ///\r | |
109 | /// Individual bit fields\r | |
110 | ///\r | |
111 | struct {\r | |
112 | UINT32 Reserved1:1;\r | |
113 | ///\r | |
114 | /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r | |
115 | /// Note: Not all processor implements R/W.\r | |
116 | ///\r | |
117 | UINT32 DataErrorCheckingEnable:1;\r | |
118 | ///\r | |
119 | /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r | |
120 | /// Note: Not all processor implements R/W.\r | |
121 | ///\r | |
122 | UINT32 ResponseErrorCheckingEnable:1;\r | |
123 | ///\r | |
124 | /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r | |
125 | /// all processor implements R/W.\r | |
126 | ///\r | |
127 | UINT32 MCERR_DriveEnable:1;\r | |
128 | ///\r | |
129 | /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:\r | |
130 | /// Not all processor implements R/W.\r | |
131 | ///\r | |
132 | UINT32 AddressParityEnable:1;\r | |
133 | UINT32 Reserved2:2;\r | |
134 | ///\r | |
135 | /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r | |
136 | /// all processor implements R/W.\r | |
137 | ///\r | |
138 | UINT32 BINIT_DriverEnable:1;\r | |
139 | ///\r | |
140 | /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r | |
141 | ///\r | |
142 | UINT32 OutputTriStateEnable:1;\r | |
143 | ///\r | |
144 | /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r | |
145 | ///\r | |
146 | UINT32 ExecuteBIST:1;\r | |
147 | ///\r | |
148 | /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r | |
149 | ///\r | |
150 | UINT32 MCERR_ObservationEnabled:1;\r | |
151 | UINT32 Reserved3:1;\r | |
152 | ///\r | |
153 | /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r | |
154 | ///\r | |
155 | UINT32 BINIT_ObservationEnabled:1;\r | |
156 | UINT32 Reserved4:1;\r | |
157 | ///\r | |
158 | /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r | |
159 | ///\r | |
160 | UINT32 ResetVector:1;\r | |
161 | UINT32 Reserved5:1;\r | |
162 | ///\r | |
163 | /// [Bits 17:16] APIC Cluster ID (R/O).\r | |
164 | ///\r | |
165 | UINT32 APICClusterID:2;\r | |
166 | ///\r | |
167 | /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.\r | |
168 | ///\r | |
169 | UINT32 SystemBusFrequency:1;\r | |
170 | UINT32 Reserved6:1;\r | |
171 | ///\r | |
172 | /// [Bits 21:20] Symmetric Arbitration ID (R/O).\r | |
173 | ///\r | |
174 | UINT32 SymmetricArbitrationID:2;\r | |
175 | ///\r | |
176 | /// [Bits 26:22] Clock Frequency Ratio (R/O).\r | |
177 | ///\r | |
178 | UINT32 ClockFrequencyRatio:5;\r | |
179 | UINT32 Reserved7:5;\r | |
180 | UINT32 Reserved8:32;\r | |
181 | } Bits;\r | |
182 | ///\r | |
183 | /// All bit fields as a 32-bit value\r | |
184 | ///\r | |
185 | UINT32 Uint32;\r | |
186 | ///\r | |
187 | /// All bit fields as a 64-bit value\r | |
188 | ///\r | |
189 | UINT64 Uint64;\r | |
190 | } MSR_CORE_EBL_CR_POWERON_REGISTER;\r | |
191 | \r | |
192 | \r | |
193 | /**\r | |
194 | Unique. Last Branch Record n (R/W) One of 8 last branch record registers on\r | |
195 | the last branch record stack: bits 31-0 hold the 'from' address and bits\r | |
196 | 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at\r | |
0f16be6d | 197 | 1C9H - Section 17.13, "Last Branch, Interrupt, and Exception Recording\r |
e0d87abe MK |
198 | (Pentium M Processors).".\r |
199 | \r | |
200 | @param ECX MSR_CORE_LASTBRANCH_n\r | |
201 | @param EAX Lower 32-bits of MSR value.\r | |
202 | @param EDX Upper 32-bits of MSR value.\r | |
203 | \r | |
204 | <b>Example usage</b>\r | |
205 | @code\r | |
206 | UINT64 Msr;\r | |
207 | \r | |
208 | Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);\r | |
209 | AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);\r | |
210 | @endcode\r | |
adf10974 JF |
211 | @note MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.\r |
212 | MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.\r | |
213 | MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.\r | |
214 | MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r | |
215 | MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.\r | |
216 | MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.\r | |
217 | MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.\r | |
218 | MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.\r | |
e0d87abe MK |
219 | @{\r |
220 | **/\r | |
221 | #define MSR_CORE_LASTBRANCH_0 0x00000040\r | |
222 | #define MSR_CORE_LASTBRANCH_1 0x00000041\r | |
223 | #define MSR_CORE_LASTBRANCH_2 0x00000042\r | |
224 | #define MSR_CORE_LASTBRANCH_3 0x00000043\r | |
225 | #define MSR_CORE_LASTBRANCH_4 0x00000044\r | |
226 | #define MSR_CORE_LASTBRANCH_5 0x00000045\r | |
227 | #define MSR_CORE_LASTBRANCH_6 0x00000046\r | |
228 | #define MSR_CORE_LASTBRANCH_7 0x00000047\r | |
229 | /// @}\r | |
230 | \r | |
231 | \r | |
232 | /**\r | |
233 | Shared. Scalable Bus Speed (RO) This field indicates the scalable bus\r | |
234 | clock speed:.\r | |
235 | \r | |
236 | @param ECX MSR_CORE_FSB_FREQ (0x000000CD)\r | |
237 | @param EAX Lower 32-bits of MSR value.\r | |
238 | Described by the type MSR_CORE_FSB_FREQ_REGISTER.\r | |
239 | @param EDX Upper 32-bits of MSR value.\r | |
240 | Described by the type MSR_CORE_FSB_FREQ_REGISTER.\r | |
241 | \r | |
242 | <b>Example usage</b>\r | |
243 | @code\r | |
244 | MSR_CORE_FSB_FREQ_REGISTER Msr;\r | |
245 | \r | |
246 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);\r | |
247 | @endcode\r | |
adf10974 | 248 | @note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r |
e0d87abe MK |
249 | **/\r |
250 | #define MSR_CORE_FSB_FREQ 0x000000CD\r | |
251 | \r | |
252 | /**\r | |
253 | MSR information returned for MSR index #MSR_CORE_FSB_FREQ\r | |
254 | **/\r | |
255 | typedef union {\r | |
256 | ///\r | |
257 | /// Individual bit fields\r | |
258 | ///\r | |
259 | struct {\r | |
260 | ///\r | |
261 | /// [Bits 2:0] - Scalable Bus Speed\r | |
262 | /// 101B: 100 MHz (FSB 400)\r | |
263 | /// 001B: 133 MHz (FSB 533)\r | |
264 | /// 011B: 167 MHz (FSB 667)\r | |
265 | ///\r | |
266 | /// 133.33 MHz should be utilized if performing calculation with System Bus\r | |
267 | /// Speed when encoding is 101B. 166.67 MHz should be utilized if\r | |
268 | /// performing calculation with System Bus Speed when encoding is 001B.\r | |
269 | ///\r | |
270 | UINT32 ScalableBusSpeed:3;\r | |
271 | UINT32 Reserved1:29;\r | |
272 | UINT32 Reserved2:32;\r | |
273 | } Bits;\r | |
274 | ///\r | |
275 | /// All bit fields as a 32-bit value\r | |
276 | ///\r | |
277 | UINT32 Uint32;\r | |
278 | ///\r | |
279 | /// All bit fields as a 64-bit value\r | |
280 | ///\r | |
281 | UINT64 Uint64;\r | |
282 | } MSR_CORE_FSB_FREQ_REGISTER;\r | |
283 | \r | |
284 | \r | |
285 | /**\r | |
286 | Shared.\r | |
287 | \r | |
288 | @param ECX MSR_CORE_BBL_CR_CTL3 (0x0000011E)\r | |
289 | @param EAX Lower 32-bits of MSR value.\r | |
290 | Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.\r | |
291 | @param EDX Upper 32-bits of MSR value.\r | |
292 | Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.\r | |
293 | \r | |
294 | <b>Example usage</b>\r | |
295 | @code\r | |
296 | MSR_CORE_BBL_CR_CTL3_REGISTER Msr;\r | |
297 | \r | |
298 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);\r | |
299 | AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);\r | |
300 | @endcode\r | |
adf10974 | 301 | @note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r |
e0d87abe MK |
302 | **/\r |
303 | #define MSR_CORE_BBL_CR_CTL3 0x0000011E\r | |
304 | \r | |
305 | /**\r | |
306 | MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3\r | |
307 | **/\r | |
308 | typedef union {\r | |
309 | ///\r | |
310 | /// Individual bit fields\r | |
311 | ///\r | |
312 | struct {\r | |
313 | ///\r | |
314 | /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r | |
315 | /// Indicates if the L2 is hardware-disabled.\r | |
316 | ///\r | |
317 | UINT32 L2HardwareEnabled:1;\r | |
318 | UINT32 Reserved1:7;\r | |
319 | ///\r | |
320 | /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =\r | |
321 | /// Disabled (default) Until this bit is set the processor will not\r | |
322 | /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r | |
323 | ///\r | |
324 | UINT32 L2Enabled:1;\r | |
325 | UINT32 Reserved2:14;\r | |
326 | ///\r | |
327 | /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r | |
328 | ///\r | |
329 | UINT32 L2NotPresent:1;\r | |
330 | UINT32 Reserved3:8;\r | |
331 | UINT32 Reserved4:32;\r | |
332 | } Bits;\r | |
333 | ///\r | |
334 | /// All bit fields as a 32-bit value\r | |
335 | ///\r | |
336 | UINT32 Uint32;\r | |
337 | ///\r | |
338 | /// All bit fields as a 64-bit value\r | |
339 | ///\r | |
340 | UINT64 Uint64;\r | |
341 | } MSR_CORE_BBL_CR_CTL3_REGISTER;\r | |
342 | \r | |
343 | \r | |
344 | /**\r | |
345 | Unique.\r | |
346 | \r | |
347 | @param ECX MSR_CORE_THERM2_CTL (0x0000019D)\r | |
348 | @param EAX Lower 32-bits of MSR value.\r | |
349 | Described by the type MSR_CORE_THERM2_CTL_REGISTER.\r | |
350 | @param EDX Upper 32-bits of MSR value.\r | |
351 | Described by the type MSR_CORE_THERM2_CTL_REGISTER.\r | |
352 | \r | |
353 | <b>Example usage</b>\r | |
354 | @code\r | |
355 | MSR_CORE_THERM2_CTL_REGISTER Msr;\r | |
356 | \r | |
357 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);\r | |
358 | AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);\r | |
359 | @endcode\r | |
adf10974 | 360 | @note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r |
e0d87abe MK |
361 | **/\r |
362 | #define MSR_CORE_THERM2_CTL 0x0000019D\r | |
363 | \r | |
364 | /**\r | |
365 | MSR information returned for MSR index #MSR_CORE_THERM2_CTL\r | |
366 | **/\r | |
367 | typedef union {\r | |
368 | ///\r | |
369 | /// Individual bit fields\r | |
370 | ///\r | |
371 | struct {\r | |
372 | UINT32 Reserved1:16;\r | |
373 | ///\r | |
374 | /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r | |
375 | /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r | |
376 | /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r | |
377 | /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r | |
378 | /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.\r | |
379 | ///\r | |
380 | UINT32 TM_SELECT:1;\r | |
381 | UINT32 Reserved2:15;\r | |
382 | UINT32 Reserved3:32;\r | |
383 | } Bits;\r | |
384 | ///\r | |
385 | /// All bit fields as a 32-bit value\r | |
386 | ///\r | |
387 | UINT32 Uint32;\r | |
388 | ///\r | |
389 | /// All bit fields as a 64-bit value\r | |
390 | ///\r | |
391 | UINT64 Uint64;\r | |
392 | } MSR_CORE_THERM2_CTL_REGISTER;\r | |
393 | \r | |
394 | \r | |
395 | /**\r | |
396 | Enable Miscellaneous Processor Features (R/W) Allows a variety of processor\r | |
397 | functions to be enabled and disabled.\r | |
398 | \r | |
399 | @param ECX MSR_CORE_IA32_MISC_ENABLE (0x000001A0)\r | |
400 | @param EAX Lower 32-bits of MSR value.\r | |
401 | Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.\r | |
402 | @param EDX Upper 32-bits of MSR value.\r | |
403 | Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.\r | |
404 | \r | |
405 | <b>Example usage</b>\r | |
406 | @code\r | |
407 | MSR_CORE_IA32_MISC_ENABLE_REGISTER Msr;\r | |
408 | \r | |
409 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);\r | |
410 | AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);\r | |
411 | @endcode\r | |
adf10974 | 412 | @note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r |
e0d87abe MK |
413 | **/\r |
414 | #define MSR_CORE_IA32_MISC_ENABLE 0x000001A0\r | |
415 | \r | |
416 | /**\r | |
417 | MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE\r | |
418 | **/\r | |
419 | typedef union {\r | |
420 | ///\r | |
421 | /// Individual bit fields\r | |
422 | ///\r | |
423 | struct {\r | |
424 | UINT32 Reserved1:3;\r | |
425 | ///\r | |
426 | /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r | |
427 | /// Table 35-2.\r | |
428 | ///\r | |
429 | UINT32 AutomaticThermalControlCircuit:1;\r | |
430 | UINT32 Reserved2:3;\r | |
431 | ///\r | |
432 | /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.\r | |
433 | ///\r | |
434 | UINT32 PerformanceMonitoring:1;\r | |
435 | UINT32 Reserved3:2;\r | |
436 | ///\r | |
437 | /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r | |
438 | /// the processor to indicate a pending break event within the processor 0\r | |
439 | /// = Indicates compatible FERR# signaling behavior This bit must be set\r | |
440 | /// to 1 to support XAPIC interrupt model usage.\r | |
441 | ///\r | |
442 | UINT32 FERR:1;\r | |
443 | ///\r | |
444 | /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.\r | |
445 | ///\r | |
446 | UINT32 BTS:1;\r | |
447 | UINT32 Reserved4:1;\r | |
448 | ///\r | |
449 | /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r | |
450 | /// thermal sensor indicates that the die temperature is at the\r | |
451 | /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.\r | |
452 | /// TM2 will reduce the bus to core ratio and voltage according to the\r | |
0f16be6d HW |
453 | /// value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear\r |
454 | /// (0, default), the processor does not change the VID signals or the bus\r | |
455 | /// to core ratio when the processor enters a thermal managed state. If\r | |
456 | /// the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID\r | |
457 | /// with EAX = 1, then this feature is not supported and BIOS must not\r | |
458 | /// alter the contents of this bit location. The processor is operating\r | |
459 | /// out of spec if both this bit and the TM1 bit are set to disabled\r | |
460 | /// states.\r | |
e0d87abe MK |
461 | ///\r |
462 | UINT32 TM2:1;\r | |
463 | UINT32 Reserved5:2;\r | |
464 | ///\r | |
465 | /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 =\r | |
466 | /// Enhanced Intel SpeedStep Technology enabled.\r | |
467 | ///\r | |
468 | UINT32 EIST:1;\r | |
469 | UINT32 Reserved6:1;\r | |
470 | ///\r | |
471 | /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.\r | |
472 | ///\r | |
473 | UINT32 MONITOR:1;\r | |
474 | UINT32 Reserved7:1;\r | |
475 | UINT32 Reserved8:2;\r | |
476 | ///\r | |
477 | /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2. Setting this\r | |
478 | /// bit may cause behavior in software that depends on the availability of\r | |
0f16be6d | 479 | /// CPUID leaves greater than 2.\r |
e0d87abe MK |
480 | ///\r |
481 | UINT32 LimitCpuidMaxval:1;\r | |
482 | UINT32 Reserved9:9;\r | |
483 | UINT32 Reserved10:2;\r | |
484 | ///\r | |
485 | /// [Bit 34] Shared. XD Bit Disable (R/W) See Table 35-2.\r | |
486 | ///\r | |
487 | UINT32 XD:1;\r | |
488 | UINT32 Reserved11:29;\r | |
489 | } Bits;\r | |
490 | ///\r | |
491 | /// All bit fields as a 64-bit value\r | |
492 | ///\r | |
493 | UINT64 Uint64;\r | |
494 | } MSR_CORE_IA32_MISC_ENABLE_REGISTER;\r | |
495 | \r | |
496 | \r | |
497 | /**\r | |
498 | Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r | |
499 | that points to the MSR containing the most recent branch record. See\r | |
500 | MSR_LASTBRANCH_0_FROM_IP (at 40H).\r | |
501 | \r | |
502 | @param ECX MSR_CORE_LASTBRANCH_TOS (0x000001C9)\r | |
503 | @param EAX Lower 32-bits of MSR value.\r | |
504 | @param EDX Upper 32-bits of MSR value.\r | |
505 | \r | |
506 | <b>Example usage</b>\r | |
507 | @code\r | |
508 | UINT64 Msr;\r | |
509 | \r | |
510 | Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);\r | |
511 | AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);\r | |
512 | @endcode\r | |
adf10974 | 513 | @note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r |
e0d87abe MK |
514 | **/\r |
515 | #define MSR_CORE_LASTBRANCH_TOS 0x000001C9\r | |
516 | \r | |
517 | \r | |
518 | /**\r | |
519 | Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r | |
520 | last branch instruction that the processor executed prior to the last\r | |
521 | exception that was generated or the last interrupt that was handled.\r | |
522 | \r | |
523 | @param ECX MSR_CORE_LER_FROM_LIP (0x000001DD)\r | |
524 | @param EAX Lower 32-bits of MSR value.\r | |
525 | @param EDX Upper 32-bits of MSR value.\r | |
526 | \r | |
527 | <b>Example usage</b>\r | |
528 | @code\r | |
529 | UINT64 Msr;\r | |
530 | \r | |
531 | Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);\r | |
532 | @endcode\r | |
adf10974 | 533 | @note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r |
e0d87abe MK |
534 | **/\r |
535 | #define MSR_CORE_LER_FROM_LIP 0x000001DD\r | |
536 | \r | |
537 | \r | |
538 | /**\r | |
539 | Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r | |
540 | to the target of the last branch instruction that the processor executed\r | |
541 | prior to the last exception that was generated or the last interrupt that\r | |
542 | was handled.\r | |
543 | \r | |
544 | @param ECX MSR_CORE_LER_TO_LIP (0x000001DE)\r | |
545 | @param EAX Lower 32-bits of MSR value.\r | |
546 | @param EDX Upper 32-bits of MSR value.\r | |
547 | \r | |
548 | <b>Example usage</b>\r | |
549 | @code\r | |
550 | UINT64 Msr;\r | |
551 | \r | |
552 | Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);\r | |
553 | @endcode\r | |
adf10974 | 554 | @note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r |
e0d87abe MK |
555 | **/\r |
556 | #define MSR_CORE_LER_TO_LIP 0x000001DE\r | |
557 | \r | |
558 | \r | |
559 | /**\r | |
560 | Unique.\r | |
561 | \r | |
562 | @param ECX MSR_CORE_ROB_CR_BKUPTMPDR6 (0x000001E0)\r | |
563 | @param EAX Lower 32-bits of MSR value.\r | |
564 | Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.\r | |
565 | @param EDX Upper 32-bits of MSR value.\r | |
566 | Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.\r | |
567 | \r | |
568 | <b>Example usage</b>\r | |
569 | @code\r | |
570 | MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER Msr;\r | |
571 | \r | |
572 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6);\r | |
573 | AsmWriteMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6, Msr.Uint64);\r | |
574 | @endcode\r | |
adf10974 | 575 | @note MSR_CORE_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM.\r |
e0d87abe MK |
576 | **/\r |
577 | #define MSR_CORE_ROB_CR_BKUPTMPDR6 0x000001E0\r | |
578 | \r | |
579 | /**\r | |
580 | MSR information returned for MSR index #MSR_CORE_ROB_CR_BKUPTMPDR6\r | |
581 | **/\r | |
582 | typedef union {\r | |
583 | ///\r | |
584 | /// Individual bit fields\r | |
585 | ///\r | |
586 | struct {\r | |
587 | UINT32 Reserved1:2;\r | |
588 | ///\r | |
589 | /// [Bit 2] Fast Strings Enable bit. (Default, enabled).\r | |
590 | ///\r | |
591 | UINT32 FastStrings:1;\r | |
592 | UINT32 Reserved2:29;\r | |
593 | UINT32 Reserved3:32;\r | |
594 | } Bits;\r | |
595 | ///\r | |
596 | /// All bit fields as a 32-bit value\r | |
597 | ///\r | |
598 | UINT32 Uint32;\r | |
599 | ///\r | |
600 | /// All bit fields as a 64-bit value\r | |
601 | ///\r | |
602 | UINT64 Uint64;\r | |
603 | } MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER;\r | |
604 | \r | |
605 | \r | |
606 | /**\r | |
607 | Unique.\r | |
608 | \r | |
609 | @param ECX MSR_CORE_MTRRPHYSBASEn\r | |
610 | @param EAX Lower 32-bits of MSR value.\r | |
611 | @param EDX Upper 32-bits of MSR value.\r | |
612 | \r | |
613 | <b>Example usage</b>\r | |
614 | @code\r | |
615 | UINT64 Msr;\r | |
616 | \r | |
617 | Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);\r | |
618 | AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);\r | |
619 | @endcode\r | |
adf10974 JF |
620 | @note MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.\r |
621 | MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.\r | |
622 | MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.\r | |
623 | MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.\r | |
624 | MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.\r | |
625 | MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.\r | |
626 | MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.\r | |
627 | MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.\r | |
e0d87abe MK |
628 | @{\r |
629 | **/\r | |
630 | #define MSR_CORE_MTRRPHYSBASE0 0x00000200\r | |
631 | #define MSR_CORE_MTRRPHYSBASE1 0x00000202\r | |
632 | #define MSR_CORE_MTRRPHYSBASE2 0x00000204\r | |
633 | #define MSR_CORE_MTRRPHYSBASE3 0x00000206\r | |
634 | #define MSR_CORE_MTRRPHYSBASE4 0x00000208\r | |
635 | #define MSR_CORE_MTRRPHYSBASE5 0x0000020A\r | |
636 | #define MSR_CORE_MTRRPHYSMASK6 0x0000020D\r | |
637 | #define MSR_CORE_MTRRPHYSMASK7 0x0000020F\r | |
638 | /// @}\r | |
639 | \r | |
640 | \r | |
641 | /**\r | |
642 | Unique.\r | |
643 | \r | |
644 | @param ECX MSR_CORE_MTRRPHYSMASKn (0x00000201)\r | |
645 | @param EAX Lower 32-bits of MSR value.\r | |
646 | @param EDX Upper 32-bits of MSR value.\r | |
647 | \r | |
648 | <b>Example usage</b>\r | |
649 | @code\r | |
650 | UINT64 Msr;\r | |
651 | \r | |
652 | Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);\r | |
653 | AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);\r | |
654 | @endcode\r | |
adf10974 JF |
655 | @note MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.\r |
656 | MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.\r | |
657 | MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.\r | |
658 | MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.\r | |
659 | MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.\r | |
660 | MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.\r | |
661 | MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.\r | |
662 | MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.\r | |
e0d87abe MK |
663 | @{\r |
664 | **/\r | |
665 | #define MSR_CORE_MTRRPHYSMASK0 0x00000201\r | |
666 | #define MSR_CORE_MTRRPHYSMASK1 0x00000203\r | |
667 | #define MSR_CORE_MTRRPHYSMASK2 0x00000205\r | |
668 | #define MSR_CORE_MTRRPHYSMASK3 0x00000207\r | |
669 | #define MSR_CORE_MTRRPHYSMASK4 0x00000209\r | |
670 | #define MSR_CORE_MTRRPHYSMASK5 0x0000020B\r | |
671 | #define MSR_CORE_MTRRPHYSBASE6 0x0000020C\r | |
672 | #define MSR_CORE_MTRRPHYSBASE7 0x0000020E\r | |
673 | /// @}\r | |
674 | \r | |
675 | \r | |
676 | /**\r | |
677 | Unique.\r | |
678 | \r | |
679 | @param ECX MSR_CORE_MTRRFIX64K_00000 (0x00000250)\r | |
680 | @param EAX Lower 32-bits of MSR value.\r | |
681 | @param EDX Upper 32-bits of MSR value.\r | |
682 | \r | |
683 | <b>Example usage</b>\r | |
684 | @code\r | |
685 | UINT64 Msr;\r | |
686 | \r | |
687 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000);\r | |
688 | AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr);\r | |
689 | @endcode\r | |
adf10974 | 690 | @note MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.\r |
e0d87abe MK |
691 | **/\r |
692 | #define MSR_CORE_MTRRFIX64K_00000 0x00000250\r | |
693 | \r | |
694 | \r | |
695 | /**\r | |
696 | Unique.\r | |
697 | \r | |
698 | @param ECX MSR_CORE_MTRRFIX16K_80000 (0x00000258)\r | |
699 | @param EAX Lower 32-bits of MSR value.\r | |
700 | @param EDX Upper 32-bits of MSR value.\r | |
701 | \r | |
702 | <b>Example usage</b>\r | |
703 | @code\r | |
704 | UINT64 Msr;\r | |
705 | \r | |
706 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000);\r | |
707 | AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr);\r | |
708 | @endcode\r | |
adf10974 | 709 | @note MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.\r |
e0d87abe MK |
710 | **/\r |
711 | #define MSR_CORE_MTRRFIX16K_80000 0x00000258\r | |
712 | \r | |
713 | \r | |
714 | /**\r | |
715 | Unique.\r | |
716 | \r | |
717 | @param ECX MSR_CORE_MTRRFIX16K_A0000 (0x00000259)\r | |
718 | @param EAX Lower 32-bits of MSR value.\r | |
719 | @param EDX Upper 32-bits of MSR value.\r | |
720 | \r | |
721 | <b>Example usage</b>\r | |
722 | @code\r | |
723 | UINT64 Msr;\r | |
724 | \r | |
725 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000);\r | |
726 | AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr);\r | |
727 | @endcode\r | |
adf10974 | 728 | @note MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.\r |
e0d87abe MK |
729 | **/\r |
730 | #define MSR_CORE_MTRRFIX16K_A0000 0x00000259\r | |
731 | \r | |
732 | \r | |
733 | /**\r | |
734 | Unique.\r | |
735 | \r | |
736 | @param ECX MSR_CORE_MTRRFIX4K_C0000 (0x00000268)\r | |
737 | @param EAX Lower 32-bits of MSR value.\r | |
738 | @param EDX Upper 32-bits of MSR value.\r | |
739 | \r | |
740 | <b>Example usage</b>\r | |
741 | @code\r | |
742 | UINT64 Msr;\r | |
743 | \r | |
744 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000);\r | |
745 | AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr);\r | |
746 | @endcode\r | |
adf10974 | 747 | @note MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.\r |
e0d87abe MK |
748 | **/\r |
749 | #define MSR_CORE_MTRRFIX4K_C0000 0x00000268\r | |
750 | \r | |
751 | \r | |
752 | /**\r | |
753 | Unique.\r | |
754 | \r | |
755 | @param ECX MSR_CORE_MTRRFIX4K_C8000 (0x00000269)\r | |
756 | @param EAX Lower 32-bits of MSR value.\r | |
757 | @param EDX Upper 32-bits of MSR value.\r | |
758 | \r | |
759 | <b>Example usage</b>\r | |
760 | @code\r | |
761 | UINT64 Msr;\r | |
762 | \r | |
763 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000);\r | |
764 | AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr);\r | |
765 | @endcode\r | |
adf10974 | 766 | @note MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.\r |
e0d87abe MK |
767 | **/\r |
768 | #define MSR_CORE_MTRRFIX4K_C8000 0x00000269\r | |
769 | \r | |
770 | \r | |
771 | /**\r | |
772 | Unique.\r | |
773 | \r | |
774 | @param ECX MSR_CORE_MTRRFIX4K_D0000 (0x0000026A)\r | |
775 | @param EAX Lower 32-bits of MSR value.\r | |
776 | @param EDX Upper 32-bits of MSR value.\r | |
777 | \r | |
778 | <b>Example usage</b>\r | |
779 | @code\r | |
780 | UINT64 Msr;\r | |
781 | \r | |
782 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000);\r | |
783 | AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr);\r | |
784 | @endcode\r | |
adf10974 | 785 | @note MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.\r |
e0d87abe MK |
786 | **/\r |
787 | #define MSR_CORE_MTRRFIX4K_D0000 0x0000026A\r | |
788 | \r | |
789 | \r | |
790 | /**\r | |
791 | Unique.\r | |
792 | \r | |
793 | @param ECX MSR_CORE_MTRRFIX4K_D8000 (0x0000026B)\r | |
794 | @param EAX Lower 32-bits of MSR value.\r | |
795 | @param EDX Upper 32-bits of MSR value.\r | |
796 | \r | |
797 | <b>Example usage</b>\r | |
798 | @code\r | |
799 | UINT64 Msr;\r | |
800 | \r | |
801 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000);\r | |
802 | AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr);\r | |
803 | @endcode\r | |
adf10974 | 804 | @note MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.\r |
e0d87abe MK |
805 | **/\r |
806 | #define MSR_CORE_MTRRFIX4K_D8000 0x0000026B\r | |
807 | \r | |
808 | \r | |
809 | /**\r | |
810 | Unique.\r | |
811 | \r | |
812 | @param ECX MSR_CORE_MTRRFIX4K_E0000 (0x0000026C)\r | |
813 | @param EAX Lower 32-bits of MSR value.\r | |
814 | @param EDX Upper 32-bits of MSR value.\r | |
815 | \r | |
816 | <b>Example usage</b>\r | |
817 | @code\r | |
818 | UINT64 Msr;\r | |
819 | \r | |
820 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000);\r | |
821 | AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr);\r | |
822 | @endcode\r | |
adf10974 | 823 | @note MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.\r |
e0d87abe MK |
824 | **/\r |
825 | #define MSR_CORE_MTRRFIX4K_E0000 0x0000026C\r | |
826 | \r | |
827 | \r | |
828 | /**\r | |
829 | Unique.\r | |
830 | \r | |
831 | @param ECX MSR_CORE_MTRRFIX4K_E8000 (0x0000026D)\r | |
832 | @param EAX Lower 32-bits of MSR value.\r | |
833 | @param EDX Upper 32-bits of MSR value.\r | |
834 | \r | |
835 | <b>Example usage</b>\r | |
836 | @code\r | |
837 | UINT64 Msr;\r | |
838 | \r | |
839 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000);\r | |
840 | AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr);\r | |
841 | @endcode\r | |
adf10974 | 842 | @note MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.\r |
e0d87abe MK |
843 | **/\r |
844 | #define MSR_CORE_MTRRFIX4K_E8000 0x0000026D\r | |
845 | \r | |
846 | \r | |
847 | /**\r | |
848 | Unique.\r | |
849 | \r | |
850 | @param ECX MSR_CORE_MTRRFIX4K_F0000 (0x0000026E)\r | |
851 | @param EAX Lower 32-bits of MSR value.\r | |
852 | @param EDX Upper 32-bits of MSR value.\r | |
853 | \r | |
854 | <b>Example usage</b>\r | |
855 | @code\r | |
856 | UINT64 Msr;\r | |
857 | \r | |
858 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000);\r | |
859 | AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr);\r | |
860 | @endcode\r | |
adf10974 | 861 | @note MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.\r |
e0d87abe MK |
862 | **/\r |
863 | #define MSR_CORE_MTRRFIX4K_F0000 0x0000026E\r | |
864 | \r | |
865 | \r | |
866 | /**\r | |
867 | Unique.\r | |
868 | \r | |
869 | @param ECX MSR_CORE_MTRRFIX4K_F8000 (0x0000026F)\r | |
870 | @param EAX Lower 32-bits of MSR value.\r | |
871 | @param EDX Upper 32-bits of MSR value.\r | |
872 | \r | |
873 | <b>Example usage</b>\r | |
874 | @code\r | |
875 | UINT64 Msr;\r | |
876 | \r | |
877 | Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000);\r | |
878 | AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr);\r | |
879 | @endcode\r | |
adf10974 | 880 | @note MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.\r |
e0d87abe MK |
881 | **/\r |
882 | #define MSR_CORE_MTRRFIX4K_F8000 0x0000026F\r | |
883 | \r | |
884 | \r | |
885 | /**\r | |
886 | Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r | |
887 | \r | |
888 | @param ECX MSR_CORE_MC4_CTL (0x0000040C)\r | |
889 | @param EAX Lower 32-bits of MSR value.\r | |
890 | @param EDX Upper 32-bits of MSR value.\r | |
891 | \r | |
892 | <b>Example usage</b>\r | |
893 | @code\r | |
894 | UINT64 Msr;\r | |
895 | \r | |
896 | Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL);\r | |
897 | AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr);\r | |
898 | @endcode\r | |
adf10974 | 899 | @note MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r |
e0d87abe MK |
900 | **/\r |
901 | #define MSR_CORE_MC4_CTL 0x0000040C\r | |
902 | \r | |
903 | \r | |
904 | /**\r | |
905 | Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r | |
906 | \r | |
907 | @param ECX MSR_CORE_MC4_STATUS (0x0000040D)\r | |
908 | @param EAX Lower 32-bits of MSR value.\r | |
909 | @param EDX Upper 32-bits of MSR value.\r | |
910 | \r | |
911 | <b>Example usage</b>\r | |
912 | @code\r | |
913 | UINT64 Msr;\r | |
914 | \r | |
915 | Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS);\r | |
916 | AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr);\r | |
917 | @endcode\r | |
adf10974 | 918 | @note MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r |
e0d87abe MK |
919 | **/\r |
920 | #define MSR_CORE_MC4_STATUS 0x0000040D\r | |
921 | \r | |
922 | \r | |
923 | /**\r | |
924 | Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR\r | |
925 | register is either not implemented or contains no address if the ADDRV flag\r | |
926 | in the MSR_MC4_STATUS register is clear. When not implemented in the\r | |
927 | processor, all reads and writes to this MSR will cause a general-protection\r | |
928 | exception.\r | |
929 | \r | |
930 | @param ECX MSR_CORE_MC4_ADDR (0x0000040E)\r | |
931 | @param EAX Lower 32-bits of MSR value.\r | |
932 | @param EDX Upper 32-bits of MSR value.\r | |
933 | \r | |
934 | <b>Example usage</b>\r | |
935 | @code\r | |
936 | UINT64 Msr;\r | |
937 | \r | |
938 | Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR);\r | |
939 | AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr);\r | |
940 | @endcode\r | |
adf10974 | 941 | @note MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r |
e0d87abe MK |
942 | **/\r |
943 | #define MSR_CORE_MC4_ADDR 0x0000040E\r | |
944 | \r | |
945 | \r | |
e0d87abe MK |
946 | /**\r |
947 | Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR\r | |
948 | register is either not implemented or contains no address if the ADDRV flag\r | |
949 | in the MSR_MC3_STATUS register is clear. When not implemented in the\r | |
950 | processor, all reads and writes to this MSR will cause a general-protection\r | |
951 | exception.\r | |
952 | \r | |
953 | @param ECX MSR_CORE_MC3_ADDR (0x00000412)\r | |
954 | @param EAX Lower 32-bits of MSR value.\r | |
955 | @param EDX Upper 32-bits of MSR value.\r | |
956 | \r | |
957 | <b>Example usage</b>\r | |
958 | @code\r | |
959 | UINT64 Msr;\r | |
960 | \r | |
961 | Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR);\r | |
962 | AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr);\r | |
963 | @endcode\r | |
adf10974 | 964 | @note MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r |
e0d87abe MK |
965 | **/\r |
966 | #define MSR_CORE_MC3_ADDR 0x00000412\r | |
967 | \r | |
968 | \r | |
969 | /**\r | |
970 | Unique.\r | |
971 | \r | |
972 | @param ECX MSR_CORE_MC3_MISC (0x00000413)\r | |
973 | @param EAX Lower 32-bits of MSR value.\r | |
974 | @param EDX Upper 32-bits of MSR value.\r | |
975 | \r | |
976 | <b>Example usage</b>\r | |
977 | @code\r | |
978 | UINT64 Msr;\r | |
979 | \r | |
980 | Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC);\r | |
981 | AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr);\r | |
982 | @endcode\r | |
adf10974 | 983 | @note MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM.\r |
e0d87abe MK |
984 | **/\r |
985 | #define MSR_CORE_MC3_MISC 0x00000413\r | |
986 | \r | |
987 | \r | |
988 | /**\r | |
989 | Unique.\r | |
990 | \r | |
991 | @param ECX MSR_CORE_MC5_CTL (0x00000414)\r | |
992 | @param EAX Lower 32-bits of MSR value.\r | |
993 | @param EDX Upper 32-bits of MSR value.\r | |
994 | \r | |
995 | <b>Example usage</b>\r | |
996 | @code\r | |
997 | UINT64 Msr;\r | |
998 | \r | |
999 | Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL);\r | |
1000 | AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr);\r | |
1001 | @endcode\r | |
adf10974 | 1002 | @note MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r |
e0d87abe MK |
1003 | **/\r |
1004 | #define MSR_CORE_MC5_CTL 0x00000414\r | |
1005 | \r | |
1006 | \r | |
1007 | /**\r | |
1008 | Unique.\r | |
1009 | \r | |
1010 | @param ECX MSR_CORE_MC5_STATUS (0x00000415)\r | |
1011 | @param EAX Lower 32-bits of MSR value.\r | |
1012 | @param EDX Upper 32-bits of MSR value.\r | |
1013 | \r | |
1014 | <b>Example usage</b>\r | |
1015 | @code\r | |
1016 | UINT64 Msr;\r | |
1017 | \r | |
1018 | Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS);\r | |
1019 | AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr);\r | |
1020 | @endcode\r | |
adf10974 | 1021 | @note MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r |
e0d87abe MK |
1022 | **/\r |
1023 | #define MSR_CORE_MC5_STATUS 0x00000415\r | |
1024 | \r | |
1025 | \r | |
1026 | /**\r | |
1027 | Unique.\r | |
1028 | \r | |
1029 | @param ECX MSR_CORE_MC5_ADDR (0x00000416)\r | |
1030 | @param EAX Lower 32-bits of MSR value.\r | |
1031 | @param EDX Upper 32-bits of MSR value.\r | |
1032 | \r | |
1033 | <b>Example usage</b>\r | |
1034 | @code\r | |
1035 | UINT64 Msr;\r | |
1036 | \r | |
1037 | Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR);\r | |
1038 | AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr);\r | |
1039 | @endcode\r | |
adf10974 | 1040 | @note MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r |
e0d87abe MK |
1041 | **/\r |
1042 | #define MSR_CORE_MC5_ADDR 0x00000416\r | |
1043 | \r | |
1044 | \r | |
1045 | /**\r | |
1046 | Unique.\r | |
1047 | \r | |
1048 | @param ECX MSR_CORE_MC5_MISC (0x00000417)\r | |
1049 | @param EAX Lower 32-bits of MSR value.\r | |
1050 | @param EDX Upper 32-bits of MSR value.\r | |
1051 | \r | |
1052 | <b>Example usage</b>\r | |
1053 | @code\r | |
1054 | UINT64 Msr;\r | |
1055 | \r | |
1056 | Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC);\r | |
1057 | AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr);\r | |
1058 | @endcode\r | |
adf10974 | 1059 | @note MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r |
e0d87abe MK |
1060 | **/\r |
1061 | #define MSR_CORE_MC5_MISC 0x00000417\r | |
1062 | \r | |
1063 | \r | |
1064 | /**\r | |
1065 | Unique. See Table 35-2.\r | |
1066 | \r | |
1067 | @param ECX MSR_CORE_IA32_EFER (0xC0000080)\r | |
1068 | @param EAX Lower 32-bits of MSR value.\r | |
1069 | Described by the type MSR_CORE_IA32_EFER_REGISTER.\r | |
1070 | @param EDX Upper 32-bits of MSR value.\r | |
1071 | Described by the type MSR_CORE_IA32_EFER_REGISTER.\r | |
1072 | \r | |
1073 | <b>Example usage</b>\r | |
1074 | @code\r | |
1075 | MSR_CORE_IA32_EFER_REGISTER Msr;\r | |
1076 | \r | |
1077 | Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);\r | |
1078 | AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64);\r | |
1079 | @endcode\r | |
adf10974 | 1080 | @note MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM.\r |
e0d87abe MK |
1081 | **/\r |
1082 | #define MSR_CORE_IA32_EFER 0xC0000080\r | |
1083 | \r | |
1084 | /**\r | |
1085 | MSR information returned for MSR index #MSR_CORE_IA32_EFER\r | |
1086 | **/\r | |
1087 | typedef union {\r | |
1088 | ///\r | |
1089 | /// Individual bit fields\r | |
1090 | ///\r | |
1091 | struct {\r | |
1092 | UINT32 Reserved1:11;\r | |
1093 | ///\r | |
1094 | /// [Bit 11] Execute Disable Bit Enable.\r | |
1095 | ///\r | |
1096 | UINT32 NXE:1;\r | |
1097 | UINT32 Reserved2:20;\r | |
1098 | UINT32 Reserved3:32;\r | |
1099 | } Bits;\r | |
1100 | ///\r | |
1101 | /// All bit fields as a 32-bit value\r | |
1102 | ///\r | |
1103 | UINT32 Uint32;\r | |
1104 | ///\r | |
1105 | /// All bit fields as a 64-bit value\r | |
1106 | ///\r | |
1107 | UINT64 Uint64;\r | |
1108 | } MSR_CORE_IA32_EFER_REGISTER;\r | |
1109 | \r | |
1110 | #endif\r |