[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / GoldmontPlusMsr.h

/** @file\r
  MSR Defintions for Intel Atom processors based on the Goldmont Plus microarchitecture.\r
\r
  Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
  are provided for MSRs that contain one or more bit fields.  If the MSR value\r
  returned is a single 32-bit or 64-bit value, then a data structure is not\r
  provided for that MSR.\r
\r
  Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
  @par Specification Reference:\r
  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
  May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
#ifndef __GOLDMONT_PLUS_MSR_H__\r
#define __GOLDMONT_PLUS_MSR_H__\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
/**\r
  Is Intel Atom processors based on the Goldmont plus microarchitecture?\r
\r
  @param   DisplayFamily  Display Family ID\r
  @param   DisplayModel   Display Model ID\r
\r
  @retval  TRUE   Yes, it is.\r
  @retval  FALSE  No, it isn't.\r
**/\r
#define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \\r
  (DisplayFamily == 0x06 && \\r
   (                        \\r
    DisplayModel == 0x7A    \\r
    )                       \\r
   )\r
\r
/**\r
  Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based\r
  Sampling (PEBS).".\r
\r
  @param  ECX  MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x000003F1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE);\r
  AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);\r
  @endcode\r
**/\r
#define MSR_GOLDMONT_PLUS_PEBS_ENABLE            0x000003F1\r
\r
/**\r
  MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Enable PEBS trigger and recording for the programmed event\r
    /// (precise or otherwise) on IA32_PMC0.\r
    ///\r
    UINT32  Fix_Me_1:1;\r
    ///\r
    /// [Bit 1] Enable PEBS trigger and recording for the programmed event\r
    /// (precise or otherwise) on IA32_PMC1.\r
    ///\r
    UINT32  Fix_Me_2:1;\r
    ///\r
    /// [Bit 2] Enable PEBS trigger and recording for the programmed event\r
    /// (precise or otherwise) on IA32_PMC2.\r
    ///\r
    UINT32  Fix_Me_3:1;\r
    ///\r
    /// [Bit 3] Enable PEBS trigger and recording for the programmed event\r
    /// (precise or otherwise) on IA32_PMC3.\r
    ///\r
    UINT32  Fix_Me_4:1;\r
    UINT32  Reserved1:28;\r
    ///\r
    /// [Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0.\r
    ///\r
    UINT32  Fix_Me_5:1;\r
    ///\r
    /// [Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1.\r
    ///\r
    UINT32  Fix_Me_6:1;\r
    ///\r
    /// [Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2.\r
    ///\r
    UINT32  Fix_Me_7:1;\r
    UINT32  Reserved2:29;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER;\r
\r
\r
/**\r
  Core. Last Branch Record N From IP (R/W) One of the three MSRs that make up\r
  the first entry of the 32-entry LBR stack. The From_IP part of the stack\r
  contains pointers to the source instruction. See also: -  Last Branch Record\r
  Stack TOS at 1C9H. -  Section 17.7, "Last Branch, Call Stack, Interrupt, and\r
  .. Exception Recording for Processors based on Goldmont Plus\r
  Microarchitecture.".\r
\r
  @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP (0x0000068N)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP);\r
  AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP, Msr);\r
  @endcode\r
**/\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP    0x00000680\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_FROM_IP    0x00000681\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_FROM_IP    0x00000682\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_FROM_IP    0x00000683\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_FROM_IP    0x00000684\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_FROM_IP    0x00000685\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_FROM_IP    0x00000686\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_FROM_IP    0x00000687\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_FROM_IP    0x00000688\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_FROM_IP    0x00000689\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_FROM_IP   0x0000068A\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_FROM_IP   0x0000068B\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_FROM_IP   0x0000068C\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_FROM_IP   0x0000068D\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_FROM_IP   0x0000068E\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_FROM_IP   0x0000068F\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_FROM_IP   0x00000690\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_FROM_IP   0x00000691\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_FROM_IP   0x00000692\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_FROM_IP   0x00000693\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_FROM_IP   0x00000694\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_FROM_IP   0x00000695\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_FROM_IP   0x00000696\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_FROM_IP   0x00000697\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_FROM_IP   0x00000698\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_FROM_IP   0x00000699\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_FROM_IP   0x0000069A\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_FROM_IP   0x0000069B\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_FROM_IP   0x0000069C\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_FROM_IP   0x0000069D\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_FROM_IP   0x0000069E\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_FROM_IP   0x0000069F\r
\r
/**\r
  Core. Last Branch Record N To IP (R/W) One of the three MSRs that make up\r
  the first entry of the 32-entry LBR stack. The To_IP part of the stack\r
  contains pointers to the Destination instruction. See also: - Section 17.7,\r
  "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors\r
  based on Goldmont Plus Microarchitecture.".\r
\r
  @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP (0x000006C0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP);\r
  AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP, Msr);\r
  @endcode\r
**/\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP      0x000006C0\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_TO_IP      0x000006C1\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_TO_IP      0x000006C2\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_TO_IP      0x000006C3\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_TO_IP      0x000006C4\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_TO_IP      0x000006C5\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_TO_IP      0x000006C6\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_TO_IP      0x000006C7\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_TO_IP      0x000006C8\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_TO_IP      0x000006C9\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_TO_IP     0x000006CA\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_TO_IP     0x000006CB\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_TO_IP     0x000006CC\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_TO_IP     0x000006CD\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_TO_IP     0x000006CE\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_TO_IP     0x000006CF\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_TO_IP     0x000006D0\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_TO_IP     0x000006D1\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_TO_IP     0x000006D2\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_TO_IP     0x000006D3\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_TO_IP     0x000006D4\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_TO_IP     0x000006D5\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_TO_IP     0x000006D6\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_TO_IP     0x000006D7\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_TO_IP     0x000006D8\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_TO_IP     0x000006D9\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_TO_IP     0x000006DA\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_TO_IP     0x000006DB\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_TO_IP     0x000006DC\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_TO_IP     0x000006DD\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_TO_IP     0x000006DE\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_TO_IP     0x000006DF\r
\r
\r
/**\r
  Core. Last Branch Record N Additional Information (R/W) One of the three\r
  MSRs that make up the first entry of the 32-entry LBR stack. This part of\r
  the stack contains flag and elapsed cycle information. See also: -  Last\r
  Branch Record Stack TOS at 1C9H. -  Section 17.9.1, "LBR Stack.".\r
\r
  @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N (0x00000DCN)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N);\r
  AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N, Msr);\r
  @endcode\r
**/\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0      0x00000DC0\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_1      0x00000DC1\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_2      0x00000DC2\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_3      0x00000DC3\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_4      0x00000DC4\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_5      0x00000DC5\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_6      0x00000DC6\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_7      0x00000DC7\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_8      0x00000DC8\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_9      0x00000DC9\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_10     0x00000DCA\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_11     0x00000DCB\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_12     0x00000DCC\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_13     0x00000DCD\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_14     0x00000DCE\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_15     0x00000DCF\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_16     0x00000DD0\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_17     0x00000DD1\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_18     0x00000DD2\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_19     0x00000DD3\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_20     0x00000DD4\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_21     0x00000DD5\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_22     0x00000DD6\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_23     0x00000DD7\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_24     0x00000DD8\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_25     0x00000DD9\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_26     0x00000DDA\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_27     0x00000DDB\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_28     0x00000DDC\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_29     0x00000DDD\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_30     0x00000DDE\r
#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_31     0x00000DDF\r
\r
#endif\r
Commit	Line	Data
cc73a7ec ED	1	/** @file\r
	2	MSR Defintions for Intel Atom processors based on the Goldmont Plus microarchitecture.\r
	3	\r
	4	Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
	5	are provided for MSRs that contain one or more bit fields. If the MSR value\r
	6	returned is a single 32-bit or 64-bit value, then a data structure is not\r
	7	provided for that MSR.\r
	8	\r
	9	Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>\r
0acd8697	10	SPDX-License-Identifier: BSD-2-Clause-Patent\r
cc73a7ec ED	11	\r
	12	@par Specification Reference:\r
	13	Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
	14	May 2018, Volume 4: Model-Specific-Registers (MSR)\r
	15	\r
	16	**/\r
	17	\r
	18	#ifndef __GOLDMONT_PLUS_MSR_H__\r
	19	#define __GOLDMONT_PLUS_MSR_H__\r
	20	\r
	21	#include <Register/ArchitecturalMsr.h>\r
	22	\r
	23	/**\r
	24	Is Intel Atom processors based on the Goldmont plus microarchitecture?\r
	25	\r
	26	@param DisplayFamily Display Family ID\r
	27	@param DisplayModel Display Model ID\r
	28	\r
	29	@retval TRUE Yes, it is.\r
	30	@retval FALSE No, it isn't.\r
	31	**/\r
	32	#define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \\r
	33	(DisplayFamily == 0x06 && \\r
	34	( \\r
	35	DisplayModel == 0x7A \\r
	36	) \\r
	37	)\r
	38	\r
	39	/**\r
	40	Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based\r
	41	Sampling (PEBS).".\r
	42	\r
	43	@param ECX MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x000003F1)\r
	44	@param EAX Lower 32-bits of MSR value.\r
	45	Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.\r
	46	@param EDX Upper 32-bits of MSR value.\r
	47	Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.\r
	48	\r
	49	<b>Example usage</b>\r
	50	@code\r
	51	MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER Msr;\r
	52	\r
	53	Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE);\r
	54	AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);\r
	55	@endcode\r
	56	**/\r
	57	#define MSR_GOLDMONT_PLUS_PEBS_ENABLE 0x000003F1\r
	58	\r
	59	/**\r
	60	MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE\r
	61	**/\r
	62	typedef union {\r
	63	///\r
	64	/// Individual bit fields\r
	65	///\r
	66	struct {\r
	67	///\r
	68	/// [Bit 0] Enable PEBS trigger and recording for the programmed event\r
	69	/// (precise or otherwise) on IA32_PMC0.\r
	70	///\r
	71	UINT32 Fix_Me_1:1;\r
	72	///\r
	73	/// [Bit 1] Enable PEBS trigger and recording for the programmed event\r
	74	/// (precise or otherwise) on IA32_PMC1.\r
75	///\r
76	UINT32 Fix_Me_2:1;\r
77	///\r
78	/// [Bit 2] Enable PEBS trigger and recording for the programmed event\r
79	/// (precise or otherwise) on IA32_PMC2.\r
80	///\r
81	UINT32 Fix_Me_3:1;\r
82	///\r
83	/// [Bit 3] Enable PEBS trigger and recording for the programmed event\r
84	/// (precise or otherwise) on IA32_PMC3.\r
85	///\r
86	UINT32 Fix_Me_4:1;\r
87	UINT32 Reserved1:28;\r
88	///\r
89	/// [Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0.\r
90	///\r
91	UINT32 Fix_Me_5:1;\r
92	///\r
93	/// [Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1.\r
94	///\r
95	UINT32 Fix_Me_6:1;\r
96	///\r
97	/// [Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2.\r
98	///\r
99	UINT32 Fix_Me_7:1;\r
100	UINT32 Reserved2:29;\r
101	} Bits;\r
102	///\r
103	/// All bit fields as a 64-bit value\r
104	///\r
105	UINT64 Uint64;\r
106	} MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER;\r
107	\r
108	\r
109	/**\r
110	Core. Last Branch Record N From IP (R/W) One of the three MSRs that make up\r
111	the first entry of the 32-entry LBR stack. The From_IP part of the stack\r
112	contains pointers to the source instruction. See also: - Last Branch Record\r
113	Stack TOS at 1C9H. - Section 17.7, "Last Branch, Call Stack, Interrupt, and\r
114	.. Exception Recording for Processors based on Goldmont Plus\r
115	Microarchitecture.".\r
116	\r
117	@param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP (0x0000068N)\r
118	@param EAX Lower 32-bits of MSR value.\r
119	@param EDX Upper 32-bits of MSR value.\r
120	\r
121	<b>Example usage</b>\r
122	@code\r
123	UINT64 Msr;\r
124	\r
125	Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP);\r
126	AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP, Msr);\r
127	@endcode\r
128	**/\r
129	#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP 0x00000680\r
130	#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_FROM_IP 0x00000681\r
131	#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_FROM_IP 0x00000682\r
132	#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_FROM_IP 0x00000683\r
133	#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_FROM_IP 0x00000684\r
134	#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_FROM_IP 0x00000685\r
135	#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_FROM_IP 0x00000686\r
136	#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_FROM_IP 0x00000687\r
137	#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_FROM_IP 0x00000688\r
138	#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_FROM_IP 0x00000689\r
139	#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_FROM_IP 0x0000068A\r
140	#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_FROM_IP 0x0000068B\r
141	#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_FROM_IP 0x0000068C\r
142	#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_FROM_IP 0x0000068D\r
143	#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_FROM_IP 0x0000068E\r
144	#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_FROM_IP 0x0000068F\r
145	#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_FROM_IP 0x00000690\r
146	#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_FROM_IP 0x00000691\r
147	#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_FROM_IP 0x00000692\r
148	#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_FROM_IP 0x00000693\r
149	#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_FROM_IP 0x00000694\r
150	#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_FROM_IP 0x00000695\r
151	#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_FROM_IP 0x00000696\r
152	#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_FROM_IP 0x00000697\r
153	#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_FROM_IP 0x00000698\r
154	#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_FROM_IP 0x00000699\r
155	#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_FROM_IP 0x0000069A\r
156	#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_FROM_IP 0x0000069B\r
157	#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_FROM_IP 0x0000069C\r
158	#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_FROM_IP 0x0000069D\r
159	#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_FROM_IP 0x0000069E\r
160	#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_FROM_IP 0x0000069F\r
161	\r
162	/**\r
163	Core. Last Branch Record N To IP (R/W) One of the three MSRs that make up\r
164	the first entry of the 32-entry LBR stack. The To_IP part of the stack\r
165	contains pointers to the Destination instruction. See also: - Section 17.7,\r
166	"Last Branch, Call Stack, Interrupt, and Exception Recording for Processors\r
167	based on Goldmont Plus Microarchitecture.".\r
168	\r
169	@param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP (0x000006C0)\r
170	@param EAX Lower 32-bits of MSR value.\r
171	@param EDX Upper 32-bits of MSR value.\r
172	\r
173	<b>Example usage</b>\r
174	@code\r
175	UINT64 Msr;\r
176	\r
177	Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP);\r
178	AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP, Msr);\r
179	@endcode\r
180	**/\r
181	#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP 0x000006C0\r
182	#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_TO_IP 0x000006C1\r
183	#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_TO_IP 0x000006C2\r
184	#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_TO_IP 0x000006C3\r
185	#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_TO_IP 0x000006C4\r
186	#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_TO_IP 0x000006C5\r
187	#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_TO_IP 0x000006C6\r
188	#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_TO_IP 0x000006C7\r
189	#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_TO_IP 0x000006C8\r
190	#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_TO_IP 0x000006C9\r
191	#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_TO_IP 0x000006CA\r
192	#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_TO_IP 0x000006CB\r
193	#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_TO_IP 0x000006CC\r
194	#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_TO_IP 0x000006CD\r
195	#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_TO_IP 0x000006CE\r
196	#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_TO_IP 0x000006CF\r
197	#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_TO_IP 0x000006D0\r
198	#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_TO_IP 0x000006D1\r
199	#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_TO_IP 0x000006D2\r
200	#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_TO_IP 0x000006D3\r
201	#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_TO_IP 0x000006D4\r
202	#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_TO_IP 0x000006D5\r
203	#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_TO_IP 0x000006D6\r
204	#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_TO_IP 0x000006D7\r
205	#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_TO_IP 0x000006D8\r
206	#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_TO_IP 0x000006D9\r
207	#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_TO_IP 0x000006DA\r
208	#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_TO_IP 0x000006DB\r
209	#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_TO_IP 0x000006DC\r
210	#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_TO_IP 0x000006DD\r
211	#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_TO_IP 0x000006DE\r
212	#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_TO_IP 0x000006DF\r
213	\r
214	\r
215	/**\r
216	Core. Last Branch Record N Additional Information (R/W) One of the three\r
217	MSRs that make up the first entry of the 32-entry LBR stack. This part of\r
218	the stack contains flag and elapsed cycle information. See also: - Last\r
219	Branch Record Stack TOS at 1C9H. - Section 17.9.1, "LBR Stack.".\r
220	\r
221	@param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N (0x00000DCN)\r
222	@param EAX Lower 32-bits of MSR value.\r
223	@param EDX Upper 32-bits of MSR value.\r
224	\r
225	<b>Example usage</b>\r
226	@code\r
227	UINT64 Msr;\r
228	\r
229	Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N);\r
230	AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N, Msr);\r
231	@endcode\r
232	**/\r
233	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0 0x00000DC0\r
234	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_1 0x00000DC1\r
235	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_2 0x00000DC2\r
236	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_3 0x00000DC3\r
237	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_4 0x00000DC4\r
238	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_5 0x00000DC5\r
239	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_6 0x00000DC6\r
240	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_7 0x00000DC7\r
241	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_8 0x00000DC8\r
242	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_9 0x00000DC9\r
243	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_10 0x00000DCA\r
244	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_11 0x00000DCB\r
245	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_12 0x00000DCC\r
246	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_13 0x00000DCD\r
247	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_14 0x00000DCE\r
248	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_15 0x00000DCF\r
249	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_16 0x00000DD0\r
250	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_17 0x00000DD1\r
251	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_18 0x00000DD2\r
252	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_19 0x00000DD3\r
253	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_20 0x00000DD4\r
254	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_21 0x00000DD5\r
255	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_22 0x00000DD6\r
256	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_23 0x00000DD7\r
257	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_24 0x00000DD8\r
258	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_25 0x00000DD9\r
259	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_26 0x00000DDA\r
260	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_27 0x00000DDB\r
261	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_28 0x00000DDC\r
262	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_29 0x00000DDD\r
263	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_30 0x00000DDE\r
264	#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_31 0x00000DDF\r
265	\r
266	#endif\r