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UefiCpuPkg/Include: Add Ivy Bridge MSR include file
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / IvyBridgeMsr.h
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84ada87c
MK		 1/** @file\r
2 MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
10 This program and the accompanying materials\r
11 are licensed and made available under the terms and conditions of the BSD License\r
12 which accompanies this distribution. The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-9.\r
21\r
22**/\r
23\r
24#ifndef __IVY_BRIDGE_MSR_H__\r
25#define __IVY_BRIDGE_MSR_H__\r
26\r
27#include <Register/ArchitecturalMsr.h>\r
28\r
29/**\r
30 Package. See http://biosbits.org.\r
31\r
32 @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)\r
33 @param EAX Lower 32-bits of MSR value.\r
34 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.\r
35 @param EDX Upper 32-bits of MSR value.\r
36 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.\r
37\r
38 <b>Example usage</b>\r
39 @code\r
40 MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER Msr;\r
41\r
42 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);\r
43 AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);\r
44 @endcode\r
45**/\r
46#define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE\r
47\r
48/**\r
49 MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO\r
50**/\r
51typedef union {\r
52 ///\r
53 /// Individual bit fields\r
54 ///\r
55 struct {\r
56 UINT32 Reserved1:8;\r
57 ///\r
58 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
59 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
60 /// MHz.\r
61 ///\r
62 UINT32 MaximumNonTurboRatio:8;\r
63 UINT32 Reserved2:12;\r
64 ///\r
65 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
66 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
67 /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
68 /// Turbo mode is disabled.\r
69 ///\r
70 UINT32 RatioLimit:1;\r
71 ///\r
72 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
73 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
74 /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
75 /// programmable.\r
76 ///\r
77 UINT32 TDPLimit:1;\r
78 UINT32 Reserved3:2;\r
79 ///\r
80 /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,\r
81 /// indicates that LPM is supported, and when set to 0, indicates LPM is\r
82 /// not supported.\r
83 ///\r
84 UINT32 LowPowerModeSupport:1;\r
85 ///\r
86 /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base\r
87 /// TDP level available. 01: One additional TDP level available. 02: Two\r
88 /// additional TDP level available. 11: Reserved.\r
89 ///\r
90 UINT32 ConfigTDPLevels:2;\r
91 UINT32 Reserved4:5;\r
92 ///\r
93 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
94 /// minimum ratio (maximum efficiency) that the processor can operates, in\r
95 /// units of 100MHz.\r
96 ///\r
97 UINT32 MaximumEfficiencyRatio:8;\r
98 ///\r
99 /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the\r
100 /// minimum supported operating ratio in units of 100 MHz.\r
101 ///\r
102 UINT32 MinimumOperatingRatio:8;\r
103 UINT32 Reserved5:8;\r
104 } Bits;\r
105 ///\r
106 /// All bit fields as a 64-bit value\r
107 ///\r
108 UINT64 Uint64;\r
109} MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;\r
110\r
111\r
112/**\r
113 Core. C-State Configuration Control (R/W) Note: C-state values are\r
114 processor specific C-state code names, unrelated to MWAIT extension C-state\r
115 parameters or ACPI C-States. See http://biosbits.org.\r
116\r
117 @param ECX MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
118 @param EAX Lower 32-bits of MSR value.\r
119 Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
120 @param EDX Upper 32-bits of MSR value.\r
121 Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
122\r
123 <b>Example usage</b>\r
124 @code\r
125 MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
126\r
127 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);\r
128 AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
129 @endcode\r
130**/\r
131#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
132\r
133/**\r
134 MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL\r
135**/\r
136typedef union {\r
137 ///\r
138 /// Individual bit fields\r
139 ///\r
140 struct {\r
141 ///\r
142 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
143 /// processor-specific C-state code name (consuming the least power). for\r
144 /// the package. The default is set as factory-configured package C-state\r
145 /// limit. The following C-state code name encodings are supported: 000b:\r
146 /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:\r
147 /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:\r
148 /// This field cannot be used to limit package C-state to C3.\r
149 ///\r
150 UINT32 Limit:3;\r
151 UINT32 Reserved1:7;\r
152 ///\r
153 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
154 /// IO_read instructions sent to IO register specified by\r
155 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
156 ///\r
157 UINT32 IO_MWAIT:1;\r
158 UINT32 Reserved2:4;\r
159 ///\r
160 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
161 /// until next reset.\r
162 ///\r
163 UINT32 CFGLock:1;\r
164 UINT32 Reserved3:9;\r
165 ///\r
166 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r
167 /// will conditionally demote C6/C7 requests to C3 based on uncore\r
168 /// auto-demote information.\r
169 ///\r
170 UINT32 C3AutoDemotion:1;\r
171 ///\r
172 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r
173 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
174 /// auto-demote information.\r
175 ///\r
176 UINT32 C1AutoDemotion:1;\r
177 ///\r
178 /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from\r
179 /// demoted C3.\r
180 ///\r
181 UINT32 C3Undemotion:1;\r
182 ///\r
183 /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from\r
184 /// demoted C1.\r
185 ///\r
186 UINT32 C1Undemotion:1;\r
187 UINT32 Reserved4:3;\r
188 UINT32 Reserved5:32;\r
189 } Bits;\r
190 ///\r
191 /// All bit fields as a 32-bit value\r
192 ///\r
193 UINT32 Uint32;\r
194 ///\r
195 /// All bit fields as a 64-bit value\r
196 ///\r
197 UINT64 Uint64;\r
198} MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
199\r
200\r
201/**\r
202 Package. Base TDP Ratio (R/O).\r
203\r
204 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648)\r
205 @param EAX Lower 32-bits of MSR value.\r
206 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.\r
207 @param EDX Upper 32-bits of MSR value.\r
208 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.\r
209\r
210 <b>Example usage</b>\r
211 @code\r
212 MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER Msr;\r
213\r
214 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);\r
215 @endcode\r
216**/\r
217#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648\r
218\r
219/**\r
220 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL\r
221**/\r
222typedef union {\r
223 ///\r
224 /// Individual bit fields\r
225 ///\r
226 struct {\r
227 ///\r
228 /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this\r
229 /// specific processor (in units of 100 MHz).\r
230 ///\r
231 UINT32 Config_TDP_Base:8;\r
232 UINT32 Reserved1:24;\r
233 UINT32 Reserved2:32;\r
234 } Bits;\r
235 ///\r
236 /// All bit fields as a 32-bit value\r
237 ///\r
238 UINT32 Uint32;\r
239 ///\r
240 /// All bit fields as a 64-bit value\r
241 ///\r
242 UINT64 Uint64;\r
243} MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER;\r
244\r
245\r
246/**\r
247 Package. ConfigTDP Level 1 ratio and power level (R/O).\r
248\r
249 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649)\r
250 @param EAX Lower 32-bits of MSR value.\r
251 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.\r
252 @param EDX Upper 32-bits of MSR value.\r
253 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.\r
254\r
255 <b>Example usage</b>\r
256 @code\r
257 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER Msr;\r
258\r
259 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);\r
260 @endcode\r
261**/\r
262#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649\r
263\r
264/**\r
265 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1\r
266**/\r
267typedef union {\r
268 ///\r
269 /// Individual bit fields\r
270 ///\r
271 struct {\r
272 ///\r
273 /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.\r
274 ///\r
275 UINT32 PKG_TDP_LVL1:15;\r
276 UINT32 Reserved1:1;\r
277 ///\r
278 /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used\r
279 /// for this specific processor.\r
280 ///\r
281 UINT32 Config_TDP_LVL1_Ratio:8;\r
282 UINT32 Reserved2:8;\r
283 ///\r
284 /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP\r
285 /// Level 1.\r
286 ///\r
287 UINT32 PKG_MAX_PWR_LVL1:15;\r
288 UINT32 Reserved3:1;\r
289 ///\r
290 /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP\r
291 /// Level 1.\r
292 ///\r
293 UINT32 PKG_MIN_PWR_LVL1:15;\r
294 UINT32 Reserved4:1;\r
295 } Bits;\r
296 ///\r
297 /// All bit fields as a 64-bit value\r
298 ///\r
299 UINT64 Uint64;\r
300} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER;\r
301\r
302\r
303/**\r
304 Package. ConfigTDP Level 2 ratio and power level (R/O).\r
305\r
306 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A)\r
307 @param EAX Lower 32-bits of MSR value.\r
308 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.\r
309 @param EDX Upper 32-bits of MSR value.\r
310 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.\r
311\r
312 <b>Example usage</b>\r
313 @code\r
314 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER Msr;\r
315\r
316 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);\r
317 @endcode\r
318**/\r
319#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A\r
320\r
321/**\r
322 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2\r
323**/\r
324typedef union {\r
325 ///\r
326 /// Individual bit fields\r
327 ///\r
328 struct {\r
329 ///\r
330 /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.\r
331 ///\r
332 UINT32 PKG_TDP_LVL2:15;\r
333 UINT32 Reserved1:1;\r
334 ///\r
335 /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used\r
336 /// for this specific processor.\r
337 ///\r
338 UINT32 Config_TDP_LVL2_Ratio:8;\r
339 UINT32 Reserved2:8;\r
340 ///\r
341 /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP\r
342 /// Level 2.\r
343 ///\r
344 UINT32 PKG_MAX_PWR_LVL2:15;\r
345 UINT32 Reserved3:1;\r
346 ///\r
347 /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP\r
348 /// Level 2.\r
349 ///\r
350 UINT32 PKG_MIN_PWR_LVL2:15;\r
351 UINT32 Reserved4:1;\r
352 } Bits;\r
353 ///\r
354 /// All bit fields as a 64-bit value\r
355 ///\r
356 UINT64 Uint64;\r
357} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER;\r
358\r
359\r
360/**\r
361 Package. ConfigTDP Control (R/W).\r
362\r
363 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B)\r
364 @param EAX Lower 32-bits of MSR value.\r
365 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.\r
366 @param EDX Upper 32-bits of MSR value.\r
367 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.\r
368\r
369 <b>Example usage</b>\r
370 @code\r
371 MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER Msr;\r
372\r
373 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);\r
374 AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);\r
375 @endcode\r
376**/\r
377#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B\r
378\r
379/**\r
380 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL\r
381**/\r
382typedef union {\r
383 ///\r
384 /// Individual bit fields\r
385 ///\r
386 struct {\r
387 ///\r
388 /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.\r
389 ///\r
390 UINT32 TDP_LEVEL:2;\r
391 UINT32 Reserved1:29;\r
392 ///\r
393 /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of\r
394 /// this register is locked until a reset.\r
395 ///\r
396 UINT32 Config_TDP_Lock:1;\r
397 UINT32 Reserved2:32;\r
398 } Bits;\r
399 ///\r
400 /// All bit fields as a 32-bit value\r
401 ///\r
402 UINT32 Uint32;\r
403 ///\r
404 /// All bit fields as a 64-bit value\r
405 ///\r
406 UINT64 Uint64;\r
407} MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER;\r
408\r
409\r
410/**\r
411 Package. ConfigTDP Control (R/W).\r
412\r
413 @param ECX MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C)\r
414 @param EAX Lower 32-bits of MSR value.\r
415 Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.\r
416 @param EDX Upper 32-bits of MSR value.\r
417 Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.\r
418\r
419 <b>Example usage</b>\r
420 @code\r
421 MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER Msr;\r
422\r
423 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);\r
424 AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r
425 @endcode\r
426**/\r
427#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C\r
428\r
429/**\r
430 MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO\r
431**/\r
432typedef union {\r
433 ///\r
434 /// Individual bit fields\r
435 ///\r
436 struct {\r
437 ///\r
438 /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r
439 /// field.\r
440 ///\r
441 UINT32 MAX_NON_TURBO_RATIO:8;\r
442 UINT32 Reserved1:23;\r
443 ///\r
444 /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r
445 /// content of this register is locked until a reset.\r
446 ///\r
447 UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r
448 UINT32 Reserved2:32;\r
449 } Bits;\r
450 ///\r
451 /// All bit fields as a 32-bit value\r
452 ///\r
453 UINT32 Uint32;\r
454 ///\r
455 /// All bit fields as a 64-bit value\r
456 ///\r
457 UINT64 Uint64;\r
458} MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER;\r
459\r
460\r
461/**\r
462 Package. Protected Processor Inventory Number Enable Control (R/W).\r
463\r
464 @param ECX MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E)\r
465 @param EAX Lower 32-bits of MSR value.\r
466 Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.\r
467 @param EDX Upper 32-bits of MSR value.\r
468 Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.\r
469\r
470 <b>Example usage</b>\r
471 @code\r
472 MSR_IVY_BRIDGE_PPIN_CTL_REGISTER Msr;\r
473\r
474 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);\r
475 AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);\r
476 @endcode\r
477**/\r
478#define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E\r
479\r
480/**\r
481 MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL\r
482**/\r
483typedef union {\r
484 ///\r
485 /// Individual bit fields\r
486 ///\r
487 struct {\r
488 ///\r
489 /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL.\r
490 /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit\r
491 /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to\r
492 /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged\r
493 /// inventory initialization agent to access MSR_PPIN. After reading\r
494 /// MSR_PPIN, the privileged inventory initialization agent should write\r
495 /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and\r
496 /// prevent unauthorized modification to MSR_PPIN_CTL.\r
497 ///\r
498 UINT32 LockOut:1;\r
499 ///\r
500 /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible\r
501 /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will\r
502 /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default\r
503 /// is 0.\r
504 ///\r
505 UINT32 Enable_PPIN:1;\r
506 UINT32 Reserved1:30;\r
507 UINT32 Reserved2:32;\r
508 } Bits;\r
509 ///\r
510 /// All bit fields as a 32-bit value\r
511 ///\r
512 UINT32 Uint32;\r
513 ///\r
514 /// All bit fields as a 64-bit value\r
515 ///\r
516 UINT64 Uint64;\r
517} MSR_IVY_BRIDGE_PPIN_CTL_REGISTER;\r
518\r
519\r
520/**\r
521 Package. Protected Processor Inventory Number (R/O). Protected Processor\r
522 Inventory Number (R/O) A unique value within a given CPUID\r
523 family/model/stepping signature that a privileged inventory initialization\r
524 agent can access to identify each physical processor, when access to\r
525 MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if\r
526 MSR_PPIN_CTL[bits 1:0] = '10b'.\r
527\r
528 @param ECX MSR_IVY_BRIDGE_PPIN (0x0000004F)\r
529 @param EAX Lower 32-bits of MSR value.\r
530 @param EDX Upper 32-bits of MSR value.\r
531\r
532 <b>Example usage</b>\r
533 @code\r
534 UINT64 Msr;\r
535\r
536 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);\r
537 @endcode\r
538**/\r
539#define MSR_IVY_BRIDGE_PPIN 0x0000004F\r
540\r
541\r
542/**\r
543 Package. See http://biosbits.org.\r
544\r
545 @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE)\r
546 @param EAX Lower 32-bits of MSR value.\r
547 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.\r
548 @param EDX Upper 32-bits of MSR value.\r
549 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.\r
550\r
551 <b>Example usage</b>\r
552 @code\r
553 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER Msr;\r
554\r
555 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);\r
556 AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);\r
557 @endcode\r
558**/\r
559#define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE\r
560\r
561/**\r
562 MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1\r
563**/\r
564typedef union {\r
565 ///\r
566 /// Individual bit fields\r
567 ///\r
568 struct {\r
569 UINT32 Reserved1:8;\r
570 ///\r
571 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
572 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
573 /// MHz.\r
574 ///\r
575 UINT32 MaximumNonTurboRatio:8;\r
576 UINT32 Reserved2:7;\r
577 ///\r
578 /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that\r
579 /// Protected Processor Inventory Number (PPIN) capability can be enabled\r
580 /// for privileged system inventory agent to read PPIN from MSR_PPIN. When\r
581 /// set to 0, PPIN capability is not supported. An attempt to access\r
582 /// MSR_PPIN_CTL or MSR_PPIN will cause #GP.\r
583 ///\r
584 UINT32 PPIN_CAP:1;\r
585 UINT32 Reserved3:4;\r
586 ///\r
587 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
588 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
589 /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
590 /// Turbo mode is disabled.\r
591 ///\r
592 UINT32 RatioLimit:1;\r
593 ///\r
594 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
595 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
596 /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
597 /// programmable.\r
598 ///\r
599 UINT32 TDPLimit:1;\r
600 ///\r
601 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,\r
602 /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to\r
603 /// specify an temperature offset.\r
604 ///\r
605 UINT32 TJOFFSET:1;\r
606 UINT32 Reserved4:1;\r
607 UINT32 Reserved5:8;\r
608 ///\r
609 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
610 /// minimum ratio (maximum efficiency) that the processor can operates, in\r
611 /// units of 100MHz.\r
612 ///\r
613 UINT32 MaximumEfficiencyRatio:8;\r
614 UINT32 Reserved6:16;\r
615 } Bits;\r
616 ///\r
617 /// All bit fields as a 64-bit value\r
618 ///\r
619 UINT64 Uint64;\r
620} MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER;\r
621\r
622\r
623/**\r
624 Package. MC Bank Error Configuration (R/W).\r
625\r
626 @param ECX MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F)\r
627 @param EAX Lower 32-bits of MSR value.\r
628 Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.\r
629 @param EDX Upper 32-bits of MSR value.\r
630 Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.\r
631\r
632 <b>Example usage</b>\r
633 @code\r
634 MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER Msr;\r
635\r
636 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);\r
637 AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);\r
638 @endcode\r
639**/\r
640#define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F\r
641\r
642/**\r
643 MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL\r
644**/\r
645typedef union {\r
646 ///\r
647 /// Individual bit fields\r
648 ///\r
649 struct {\r
650 UINT32 Reserved1:1;\r
651 ///\r
652 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r
653 /// to log additional info in bits 36:32.\r
654 ///\r
655 UINT32 MemErrorLogEnable:1;\r
656 UINT32 Reserved2:30;\r
657 UINT32 Reserved3:32;\r
658 } Bits;\r
659 ///\r
660 /// All bit fields as a 32-bit value\r
661 ///\r
662 UINT32 Uint32;\r
663 ///\r
664 /// All bit fields as a 64-bit value\r
665 ///\r
666 UINT64 Uint64;\r
667} MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER;\r
668\r
669\r
670/**\r
671 Package.\r
672\r
673 @param ECX MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)\r
674 @param EAX Lower 32-bits of MSR value.\r
675 Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r
676 @param EDX Upper 32-bits of MSR value.\r
677 Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r
678\r
679 <b>Example usage</b>\r
680 @code\r
681 MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;\r
682\r
683 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);\r
684 AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);\r
685 @endcode\r
686**/\r
687#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r
688\r
689/**\r
690 MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET\r
691**/\r
692typedef union {\r
693 ///\r
694 /// Individual bit fields\r
695 ///\r
696 struct {\r
697 UINT32 Reserved1:16;\r
698 ///\r
699 /// [Bits 23:16] Temperature Target (RO) The minimum temperature at which\r
700 /// PROCHOT# will be asserted. The value is degree C.\r
701 ///\r
702 UINT32 TemperatureTarget:8;\r
703 ///\r
704 /// [Bits 27:24] TCC Activation Offset (R/W) Specifies a temperature\r
705 /// offset in degrees C from the temperature target (bits 23:16). PROCHOT#\r
706 /// will assert at the offset target temperature. Write is permitted only\r
707 /// MSR_PLATFORM_INFO.[30] is set.\r
708 ///\r
709 UINT32 TCCActivationOffset:4;\r
710 UINT32 Reserved2:4;\r
711 UINT32 Reserved3:32;\r
712 } Bits;\r
713 ///\r
714 /// All bit fields as a 32-bit value\r
715 ///\r
716 UINT32 Uint32;\r
717 ///\r
718 /// All bit fields as a 64-bit value\r
719 ///\r
720 UINT64 Uint64;\r
721} MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER;\r
722\r
723\r
724/**\r
725 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
726 RW if MSR_PLATFORM_INFO.[28] = 1.\r
727\r
728 @param ECX MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE)\r
729 @param EAX Lower 32-bits of MSR value.\r
730 Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.\r
731 @param EDX Upper 32-bits of MSR value.\r
732 Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.\r
733\r
734 <b>Example usage</b>\r
735 @code\r
736 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER Msr;\r
737\r
738 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);\r
739 @endcode\r
740**/\r
741#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE\r
742\r
743/**\r
744 MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1\r
745**/\r
746typedef union {\r
747 ///\r
748 /// Individual bit fields\r
749 ///\r
750 struct {\r
751 ///\r
752 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio\r
753 /// limit of 9 core active.\r
754 ///\r
755 UINT32 Maximum9C:8;\r
756 ///\r
757 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio\r
758 /// limit of 10core active.\r
759 ///\r
760 UINT32 Maximum10C:8;\r
761 ///\r
762 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio\r
763 /// limit of 11 core active.\r
764 ///\r
765 UINT32 Maximum11C:8;\r
766 ///\r
767 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio\r
768 /// limit of 12 core active.\r
769 ///\r
770 UINT32 Maximum12C:8;\r
771 ///\r
772 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio\r
773 /// limit of 13 core active.\r
774 ///\r
775 UINT32 Maximum13C:8;\r
776 ///\r
777 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio\r
778 /// limit of 14 core active.\r
779 ///\r
780 UINT32 Maximum14C:8;\r
781 ///\r
782 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio\r
783 /// limit of 15 core active.\r
784 ///\r
785 UINT32 Maximum15C:8;\r
786 UINT32 Reserved:7;\r
787 ///\r
788 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
789 /// the processor uses override configuration specified in\r
790 /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r
791 /// uses factory-set configuration (Default).\r
792 ///\r
793 UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
794 } Bits;\r
795 ///\r
796 /// All bit fields as a 64-bit value\r
797 ///\r
798 UINT64 Uint64;\r
799} MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER;\r
800\r
801\r
802/**\r
803 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
804 15.3.2.4, "IA32_MCi_MISC MSRs.". Bank MC5 reports MC error from the Intel\r
805 QPI module.\r
806\r
807 * Bank MC6 reports MC error from the integrated I/O module.\r
808 * Banks MC7 and MC 8 report MC error from the two home agents.\r
809 * Banks MC9 through MC 16 report MC error from each channel of the integrated\r
810 memory controllers.\r
811 * Banks MC17 through MC31 reports MC error from a specific CBo\r
812 (core broadcast) and its corresponding slice of L3.\r
813\r
814 @param ECX MSR_IVY_BRIDGE_MCi_CTL\r
815 @param EAX Lower 32-bits of MSR value.\r
816 @param EDX Upper 32-bits of MSR value.\r
817\r
818 <b>Example usage</b>\r
819 @code\r
820 UINT64 Msr;\r
821\r
822 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_CTL);\r
823 AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_CTL, Msr);\r
824 @endcode\r
825 @{\r
826**/\r
827#define MSR_IVY_BRIDGE_MC5_CTL 0x00000414\r
828#define MSR_IVY_BRIDGE_MC6_CTL 0x00000418\r
829#define MSR_IVY_BRIDGE_MC7_CTL 0x0000041C\r
830#define MSR_IVY_BRIDGE_MC8_CTL 0x00000420\r
831#define MSR_IVY_BRIDGE_MC9_CTL 0x00000424\r
832#define MSR_IVY_BRIDGE_MC10_CTL 0x00000428\r
833#define MSR_IVY_BRIDGE_MC11_CTL 0x0000042C\r
834#define MSR_IVY_BRIDGE_MC12_CTL 0x00000430\r
835#define MSR_IVY_BRIDGE_MC13_CTL 0x00000434\r
836#define MSR_IVY_BRIDGE_MC14_CTL 0x00000438\r
837#define MSR_IVY_BRIDGE_MC15_CTL 0x0000043C\r
838#define MSR_IVY_BRIDGE_MC16_CTL 0x00000440\r
839#define MSR_IVY_BRIDGE_MC17_CTL 0x00000444\r
840#define MSR_IVY_BRIDGE_MC18_CTL 0x00000448\r
841#define MSR_IVY_BRIDGE_MC19_CTL 0x0000044C\r
842#define MSR_IVY_BRIDGE_MC20_CTL 0x00000450\r
843#define MSR_IVY_BRIDGE_MC21_CTL 0x00000454\r
844#define MSR_IVY_BRIDGE_MC22_CTL 0x00000458\r
845#define MSR_IVY_BRIDGE_MC23_CTL 0x0000045C\r
846#define MSR_IVY_BRIDGE_MC24_CTL 0x00000460\r
847#define MSR_IVY_BRIDGE_MC25_CTL 0x00000464\r
848#define MSR_IVY_BRIDGE_MC26_CTL 0x00000468\r
849#define MSR_IVY_BRIDGE_MC27_CTL 0x0000046C\r
850#define MSR_IVY_BRIDGE_MC28_CTL 0x00000470\r
851#define MSR_IVY_BRIDGE_MC29_CTL 0x00000474\r
852#define MSR_IVY_BRIDGE_MC30_CTL 0x00000478\r
853#define MSR_IVY_BRIDGE_MC31_CTL 0x0000047C\r
854/// @}\r
855\r
856\r
857/**\r
858 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
859 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
860\r
861 Bank MC20 reports MC error from a specific CBo (core broadcast) and\r
862 its corresponding slice of L3.\r
863\r
864 @param ECX MSR_IVY_BRIDGE_MCi_STATUS\r
865 @param EAX Lower 32-bits of MSR value.\r
866 @param EDX Upper 32-bits of MSR value.\r
867\r
868 <b>Example usage</b>\r
869 @code\r
870 UINT64 Msr;\r
871\r
872 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_STATUS);\r
873 AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_STATUS, Msr);\r
874 @endcode\r
875 @{\r
876**/\r
877#define MSR_IVY_BRIDGE_MC5_STATUS 0x00000415\r
878#define MSR_IVY_BRIDGE_MC6_STATUS 0x00000419\r
879#define MSR_IVY_BRIDGE_MC7_STATUS 0x0000041D\r
880#define MSR_IVY_BRIDGE_MC8_STATUS 0x00000421\r
881#define MSR_IVY_BRIDGE_MC9_STATUS 0x00000425\r
882#define MSR_IVY_BRIDGE_MC10_STATUS 0x00000429\r
883#define MSR_IVY_BRIDGE_MC11_STATUS 0x0000042D\r
884#define MSR_IVY_BRIDGE_MC12_STATUS 0x00000431\r
885#define MSR_IVY_BRIDGE_MC13_STATUS 0x00000435\r
886#define MSR_IVY_BRIDGE_MC14_STATUS 0x00000439\r
887#define MSR_IVY_BRIDGE_MC15_STATUS 0x0000043D\r
888#define MSR_IVY_BRIDGE_MC16_STATUS 0x00000441\r
889#define MSR_IVY_BRIDGE_MC17_STATUS 0x00000445\r
890#define MSR_IVY_BRIDGE_MC18_STATUS 0x00000449\r
891#define MSR_IVY_BRIDGE_MC19_STATUS 0x0000044D\r
892#define MSR_IVY_BRIDGE_MC20_STATUS 0x00000451\r
893#define MSR_IVY_BRIDGE_MC21_STATUS 0x00000455\r
894#define MSR_IVY_BRIDGE_MC22_STATUS 0x00000459\r
895#define MSR_IVY_BRIDGE_MC23_STATUS 0x0000045D\r
896#define MSR_IVY_BRIDGE_MC24_STATUS 0x00000461\r
897#define MSR_IVY_BRIDGE_MC25_STATUS 0x00000465\r
898#define MSR_IVY_BRIDGE_MC26_STATUS 0x00000469\r
899#define MSR_IVY_BRIDGE_MC27_STATUS 0x0000046D\r
900#define MSR_IVY_BRIDGE_MC28_STATUS 0x00000471\r
901#define MSR_IVY_BRIDGE_MC29_STATUS 0x00000475\r
902#define MSR_IVY_BRIDGE_MC30_STATUS 0x00000479\r
903#define MSR_IVY_BRIDGE_MC31_STATUS 0x0000047D\r
904/// @}\r
905\r
906\r
907/**\r
908 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
909 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
910\r
911 @param ECX MSR_IVY_BRIDGE_MCi_ADDR\r
912 @param EAX Lower 32-bits of MSR value.\r
913 @param EDX Upper 32-bits of MSR value.\r
914\r
915 <b>Example usage</b>\r
916 @code\r
917 UINT64 Msr;\r
918\r
919 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_ADDR);\r
920 AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_ADDR, Msr);\r
921 @endcode\r
922 @{\r
923**/\r
924#define MSR_IVY_BRIDGE_MC5_ADDR 0x00000416\r
925#define MSR_IVY_BRIDGE_MC6_ADDR 0x0000041A\r
926#define MSR_IVY_BRIDGE_MC7_ADDR 0x0000041E\r
927#define MSR_IVY_BRIDGE_MC8_ADDR 0x00000422\r
928#define MSR_IVY_BRIDGE_MC9_ADDR 0x00000426\r
929#define MSR_IVY_BRIDGE_MC10_ADDR 0x0000042A\r
930#define MSR_IVY_BRIDGE_MC11_ADDR 0x0000042E\r
931#define MSR_IVY_BRIDGE_MC12_ADDR 0x00000432\r
932#define MSR_IVY_BRIDGE_MC13_ADDR 0x00000436\r
933#define MSR_IVY_BRIDGE_MC14_ADDR 0x0000043A\r
934#define MSR_IVY_BRIDGE_MC15_ADDR 0x0000043E\r
935#define MSR_IVY_BRIDGE_MC16_ADDR 0x00000442\r
936#define MSR_IVY_BRIDGE_MC17_ADDR 0x00000446\r
937#define MSR_IVY_BRIDGE_MC18_ADDR 0x0000044A\r
938#define MSR_IVY_BRIDGE_MC19_ADDR 0x0000044E\r
939#define MSR_IVY_BRIDGE_MC20_ADDR 0x00000452\r
940#define MSR_IVY_BRIDGE_MC21_ADDR 0x00000456\r
941#define MSR_IVY_BRIDGE_MC22_ADDR 0x0000045A\r
942#define MSR_IVY_BRIDGE_MC23_ADDR 0x0000045E\r
943#define MSR_IVY_BRIDGE_MC24_ADDR 0x00000462\r
944#define MSR_IVY_BRIDGE_MC25_ADDR 0x00000466\r
945#define MSR_IVY_BRIDGE_MC26_ADDR 0x0000046A\r
946#define MSR_IVY_BRIDGE_MC27_ADDR 0x0000046E\r
947#define MSR_IVY_BRIDGE_MC28_ADDR 0x00000472\r
948#define MSR_IVY_BRIDGE_MC29_ADDR 0x00000476\r
949#define MSR_IVY_BRIDGE_MC30_ADDR 0x0000047A\r
950#define MSR_IVY_BRIDGE_MC31_ADDR 0x0000047E\r
951/// @}\r
952\r
953\r
954/**\r
955 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
956 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
957\r
958 @param ECX MSR_IVY_BRIDGE_MCi_MISC\r
959 @param EAX Lower 32-bits of MSR value.\r
960 @param EDX Upper 32-bits of MSR value.\r
961\r
962 <b>Example usage</b>\r
963 @code\r
964 UINT64 Msr;\r
965\r
966 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_MISC);\r
967 AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_MISC, Msr);\r
968 @endcode\r
969 @{\r
970**/\r
971#define MSR_IVY_BRIDGE_MC5_MISC 0x00000417\r
972#define MSR_IVY_BRIDGE_MC6_MISC 0x0000041B\r
973#define MSR_IVY_BRIDGE_MC7_MISC 0x0000041F\r
974#define MSR_IVY_BRIDGE_MC8_MISC 0x00000423\r
975#define MSR_IVY_BRIDGE_MC9_MISC 0x00000427\r
976#define MSR_IVY_BRIDGE_MC10_MISC 0x0000042B\r
977#define MSR_IVY_BRIDGE_MC11_MISC 0x0000042F\r
978#define MSR_IVY_BRIDGE_MC12_MISC 0x00000433\r
979#define MSR_IVY_BRIDGE_MC13_MISC 0x00000437\r
980#define MSR_IVY_BRIDGE_MC14_MISC 0x0000043B\r
981#define MSR_IVY_BRIDGE_MC15_MISC 0x0000043F\r
982#define MSR_IVY_BRIDGE_MC16_MISC 0x00000443\r
983#define MSR_IVY_BRIDGE_MC17_MISC 0x00000447\r
984#define MSR_IVY_BRIDGE_MC18_MISC 0x0000044B\r
985#define MSR_IVY_BRIDGE_MC19_MISC 0x0000044F\r
986#define MSR_IVY_BRIDGE_MC20_MISC 0x00000453\r
987#define MSR_IVY_BRIDGE_MC21_MISC 0x00000457\r
988#define MSR_IVY_BRIDGE_MC22_MISC 0x0000045B\r
989#define MSR_IVY_BRIDGE_MC23_MISC 0x0000045F\r
990#define MSR_IVY_BRIDGE_MC24_MISC 0x00000463\r
991#define MSR_IVY_BRIDGE_MC25_MISC 0x00000467\r
992#define MSR_IVY_BRIDGE_MC26_MISC 0x0000046B\r
993#define MSR_IVY_BRIDGE_MC27_MISC 0x0000046F\r
994#define MSR_IVY_BRIDGE_MC28_MISC 0x00000473\r
995#define MSR_IVY_BRIDGE_MC29_MISC 0x00000477\r
996#define MSR_IVY_BRIDGE_MC30_MISC 0x0000047B\r
997#define MSR_IVY_BRIDGE_MC31_MISC 0x0000047F\r
998/// @}\r
999\r
1000\r
1001/**\r
1002 Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.\r
1003\r
1004 @param ECX MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)\r
1005 @param EAX Lower 32-bits of MSR value.\r
1006 Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.\r
1007 @param EDX Upper 32-bits of MSR value.\r
1008 Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.\r
1009\r
1010 <b>Example usage</b>\r
1011 @code\r
1012 MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Msr;\r
1013\r
1014 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);\r
1015 @endcode\r
1016**/\r
1017#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B\r
1018\r
1019/**\r
1020 MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC\r
1021**/\r
1022typedef union {\r
1023 ///\r
1024 /// Individual bit fields\r
1025 ///\r
1026 struct {\r
1027 ///\r
1028 /// [Bits 5:0] Recoverable Address LSB.\r
1029 ///\r
1030 UINT32 RecoverableAddressLSB:6;\r
1031 ///\r
1032 /// [Bits 8:6] Address Mode.\r
1033 ///\r
1034 UINT32 AddressMode:3;\r
1035 UINT32 Reserved1:7;\r
1036 ///\r
1037 /// [Bits 31:16] PCI Express Requestor ID.\r
1038 ///\r
1039 UINT32 PCIExpressRequestorID:16;\r
1040 ///\r
1041 /// [Bits 39:32] PCI Express Segment Number.\r
1042 ///\r
1043 UINT32 PCIExpressSegmentNumber:8;\r
1044 UINT32 Reserved2:24;\r
1045 } Bits;\r
1046 ///\r
1047 /// All bit fields as a 64-bit value\r
1048 ///\r
1049 UINT64 Uint64;\r
1050} MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;\r
1051\r
1052\r
1053/**\r
1054 Package. Package RAPL Perf Status (R/O).\r
1055\r
1056 @param ECX MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613)\r
1057 @param EAX Lower 32-bits of MSR value.\r
1058 @param EDX Upper 32-bits of MSR value.\r
1059\r
1060 <b>Example usage</b>\r
1061 @code\r
1062 UINT64 Msr;\r
1063\r
1064 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);\r
1065 @endcode\r
1066**/\r
1067#define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613\r
1068\r
1069\r
1070/**\r
1071 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
1072 Domain.".\r
1073\r
1074 @param ECX MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)\r
1075 @param EAX Lower 32-bits of MSR value.\r
1076 @param EDX Upper 32-bits of MSR value.\r
1077\r
1078 <b>Example usage</b>\r
1079 @code\r
1080 UINT64 Msr;\r
1081\r
1082 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);\r
1083 AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);\r
1084 @endcode\r
1085**/\r
1086#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r
1087\r
1088\r
1089/**\r
1090 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
1091\r
1092 @param ECX MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)\r
1093 @param EAX Lower 32-bits of MSR value.\r
1094 @param EDX Upper 32-bits of MSR value.\r
1095\r
1096 <b>Example usage</b>\r
1097 @code\r
1098 UINT64 Msr;\r
1099\r
1100 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);\r
1101 @endcode\r
1102**/\r
1103#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r
1104\r
1105\r
1106/**\r
1107 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
1108 RAPL Domain.".\r
1109\r
1110 @param ECX MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)\r
1111 @param EAX Lower 32-bits of MSR value.\r
1112 @param EDX Upper 32-bits of MSR value.\r
1113\r
1114 <b>Example usage</b>\r
1115 @code\r
1116 UINT64 Msr;\r
1117\r
1118 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);\r
1119 @endcode\r
1120**/\r
1121#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r
1122\r
1123\r
1124/**\r
1125 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
1126\r
1127 @param ECX MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C)\r
1128 @param EAX Lower 32-bits of MSR value.\r
1129 @param EDX Upper 32-bits of MSR value.\r
1130\r
1131 <b>Example usage</b>\r
1132 @code\r
1133 UINT64 Msr;\r
1134\r
1135 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);\r
1136 AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);\r
1137 @endcode\r
1138**/\r
1139#define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r
1140\r
1141\r
1142/**\r
1143 Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".\r
1144\r
1145 @param ECX MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)\r
1146 @param EAX Lower 32-bits of MSR value.\r
1147 Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.\r
1148 @param EDX Upper 32-bits of MSR value.\r
1149 Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.\r
1150\r
1151 <b>Example usage</b>\r
1152 @code\r
1153 MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER Msr;\r
1154\r
1155 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);\r
1156 AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);\r
1157 @endcode\r
1158**/\r
1159#define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1\r
1160\r
1161/**\r
1162 MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE\r
1163**/\r
1164typedef union {\r
1165 ///\r
1166 /// Individual bit fields\r
1167 ///\r
1168 struct {\r
1169 ///\r
1170 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
1171 ///\r
1172 UINT32 PEBS_EN_PMC0:1;\r
1173 ///\r
1174 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
1175 ///\r
1176 UINT32 PEBS_EN_PMC1:1;\r
1177 ///\r
1178 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
1179 ///\r
1180 UINT32 PEBS_EN_PMC2:1;\r
1181 ///\r
1182 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
1183 ///\r
1184 UINT32 PEBS_EN_PMC3:1;\r
1185 UINT32 Reserved1:28;\r
1186 ///\r
1187 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
1188 ///\r
1189 UINT32 LL_EN_PMC0:1;\r
1190 ///\r
1191 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
1192 ///\r
1193 UINT32 LL_EN_PMC1:1;\r
1194 ///\r
1195 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
1196 ///\r
1197 UINT32 LL_EN_PMC2:1;\r
1198 ///\r
1199 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
1200 ///\r
1201 UINT32 LL_EN_PMC3:1;\r
1202 UINT32 Reserved2:28;\r
1203 } Bits;\r
1204 ///\r
1205 /// All bit fields as a 64-bit value\r
1206 ///\r
1207 UINT64 Uint64;\r
1208} MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER;\r
1209\r
1210\r
1211/**\r
1212 Package. Uncore perfmon per-socket global control.\r
1213\r
1214 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00)\r
1215 @param EAX Lower 32-bits of MSR value.\r
1216 @param EDX Upper 32-bits of MSR value.\r
1217\r
1218 <b>Example usage</b>\r
1219 @code\r
1220 UINT64 Msr;\r
1221\r
1222 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);\r
1223 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);\r
1224 @endcode\r
1225**/\r
1226#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00\r
1227\r
1228\r
1229/**\r
1230 Package. Uncore perfmon per-socket global status.\r
1231\r
1232 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01)\r
1233 @param EAX Lower 32-bits of MSR value.\r
1234 @param EDX Upper 32-bits of MSR value.\r
1235\r
1236 <b>Example usage</b>\r
1237 @code\r
1238 UINT64 Msr;\r
1239\r
1240 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);\r
1241 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);\r
1242 @endcode\r
1243**/\r
1244#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01\r
1245\r
1246\r
1247/**\r
1248 Package. Uncore perfmon per-socket global configuration.\r
1249\r
1250 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06)\r
1251 @param EAX Lower 32-bits of MSR value.\r
1252 @param EDX Upper 32-bits of MSR value.\r
1253\r
1254 <b>Example usage</b>\r
1255 @code\r
1256 UINT64 Msr;\r
1257\r
1258 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);\r
1259 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);\r
1260 @endcode\r
1261**/\r
1262#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06\r
1263\r
1264\r
1265/**\r
1266 Package. Uncore U-box perfmon U-box wide status.\r
1267\r
1268 @param ECX MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15)\r
1269 @param EAX Lower 32-bits of MSR value.\r
1270 @param EDX Upper 32-bits of MSR value.\r
1271\r
1272 <b>Example usage</b>\r
1273 @code\r
1274 UINT64 Msr;\r
1275\r
1276 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);\r
1277 AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);\r
1278 @endcode\r
1279**/\r
1280#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15\r
1281\r
1282\r
1283/**\r
1284 Package. Uncore PCU perfmon box wide status.\r
1285\r
1286 @param ECX MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35)\r
1287 @param EAX Lower 32-bits of MSR value.\r
1288 @param EDX Upper 32-bits of MSR value.\r
1289\r
1290 <b>Example usage</b>\r
1291 @code\r
1292 UINT64 Msr;\r
1293\r
1294 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);\r
1295 AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);\r
1296 @endcode\r
1297**/\r
1298#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35\r
1299\r
1300\r
1301/**\r
1302 Package. Uncore C-box 0 perfmon box wide filter1.\r
1303\r
1304 @param ECX MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A)\r
1305 @param EAX Lower 32-bits of MSR value.\r
1306 @param EDX Upper 32-bits of MSR value.\r
1307\r
1308 <b>Example usage</b>\r
1309 @code\r
1310 UINT64 Msr;\r
1311\r
1312 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);\r
1313 AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);\r
1314 @endcode\r
1315**/\r
1316#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A\r
1317\r
1318\r
1319/**\r
1320 Package. Uncore C-box 1 perfmon box wide filter1.\r
1321\r
1322 @param ECX MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A)\r
1323 @param EAX Lower 32-bits of MSR value.\r
1324 @param EDX Upper 32-bits of MSR value.\r
1325\r
1326 <b>Example usage</b>\r
1327 @code\r
1328 UINT64 Msr;\r
1329\r
1330 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);\r
1331 AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);\r
1332 @endcode\r
1333**/\r
1334#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A\r
1335\r
1336\r
1337/**\r
1338 Package. Uncore C-box 2 perfmon box wide filter1.\r
1339\r
1340 @param ECX MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A)\r
1341 @param EAX Lower 32-bits of MSR value.\r
1342 @param EDX Upper 32-bits of MSR value.\r
1343\r
1344 <b>Example usage</b>\r
1345 @code\r
1346 UINT64 Msr;\r
1347\r
1348 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);\r
1349 AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);\r
1350 @endcode\r
1351**/\r
1352#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A\r
1353\r
1354\r
1355/**\r
1356 Package. Uncore C-box 3 perfmon box wide filter1.\r
1357\r
1358 @param ECX MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A)\r
1359 @param EAX Lower 32-bits of MSR value.\r
1360 @param EDX Upper 32-bits of MSR value.\r
1361\r
1362 <b>Example usage</b>\r
1363 @code\r
1364 UINT64 Msr;\r
1365\r
1366 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);\r
1367 AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);\r
1368 @endcode\r
1369**/\r
1370#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A\r
1371\r
1372\r
1373/**\r
1374 Package. Uncore C-box 4 perfmon box wide filter1.\r
1375\r
1376 @param ECX MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A)\r
1377 @param EAX Lower 32-bits of MSR value.\r
1378 @param EDX Upper 32-bits of MSR value.\r
1379\r
1380 <b>Example usage</b>\r
1381 @code\r
1382 UINT64 Msr;\r
1383\r
1384 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);\r
1385 AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);\r
1386 @endcode\r
1387**/\r
1388#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A\r
1389\r
1390\r
1391/**\r
1392 Package. Uncore C-box 5 perfmon box wide filter1.\r
1393\r
1394 @param ECX MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA)\r
1395 @param EAX Lower 32-bits of MSR value.\r
1396 @param EDX Upper 32-bits of MSR value.\r
1397\r
1398 <b>Example usage</b>\r
1399 @code\r
1400 UINT64 Msr;\r
1401\r
1402 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);\r
1403 AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);\r
1404 @endcode\r
1405**/\r
1406#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA\r
1407\r
1408\r
1409/**\r
1410 Package. Uncore C-box 6 perfmon box wide filter1.\r
1411\r
1412 @param ECX MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA)\r
1413 @param EAX Lower 32-bits of MSR value.\r
1414 @param EDX Upper 32-bits of MSR value.\r
1415\r
1416 <b>Example usage</b>\r
1417 @code\r
1418 UINT64 Msr;\r
1419\r
1420 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);\r
1421 AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);\r
1422 @endcode\r
1423**/\r
1424#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA\r
1425\r
1426\r
1427/**\r
1428 Package. Uncore C-box 7 perfmon box wide filter1.\r
1429\r
1430 @param ECX MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA)\r
1431 @param EAX Lower 32-bits of MSR value.\r
1432 @param EDX Upper 32-bits of MSR value.\r
1433\r
1434 <b>Example usage</b>\r
1435 @code\r
1436 UINT64 Msr;\r
1437\r
1438 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);\r
1439 AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);\r
1440 @endcode\r
1441**/\r
1442#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA\r
1443\r
1444\r
1445/**\r
1446 Package. Uncore C-box 8 perfmon local box wide control.\r
1447\r
1448 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04)\r
1449 @param EAX Lower 32-bits of MSR value.\r
1450 @param EDX Upper 32-bits of MSR value.\r
1451\r
1452 <b>Example usage</b>\r
1453 @code\r
1454 UINT64 Msr;\r
1455\r
1456 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);\r
1457 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);\r
1458 @endcode\r
1459**/\r
1460#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04\r
1461\r
1462\r
1463/**\r
1464 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.\r
1465\r
1466 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10)\r
1467 @param EAX Lower 32-bits of MSR value.\r
1468 @param EDX Upper 32-bits of MSR value.\r
1469\r
1470 <b>Example usage</b>\r
1471 @code\r
1472 UINT64 Msr;\r
1473\r
1474 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);\r
1475 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);\r
1476 @endcode\r
1477**/\r
1478#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10\r
1479\r
1480\r
1481/**\r
1482 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.\r
1483\r
1484 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11)\r
1485 @param EAX Lower 32-bits of MSR value.\r
1486 @param EDX Upper 32-bits of MSR value.\r
1487\r
1488 <b>Example usage</b>\r
1489 @code\r
1490 UINT64 Msr;\r
1491\r
1492 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);\r
1493 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);\r
1494 @endcode\r
1495**/\r
1496#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11\r
1497\r
1498\r
1499/**\r
1500 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.\r
1501\r
1502 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12)\r
1503 @param EAX Lower 32-bits of MSR value.\r
1504 @param EDX Upper 32-bits of MSR value.\r
1505\r
1506 <b>Example usage</b>\r
1507 @code\r
1508 UINT64 Msr;\r
1509\r
1510 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);\r
1511 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);\r
1512 @endcode\r
1513**/\r
1514#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12\r
1515\r
1516\r
1517/**\r
1518 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.\r
1519\r
1520 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13)\r
1521 @param EAX Lower 32-bits of MSR value.\r
1522 @param EDX Upper 32-bits of MSR value.\r
1523\r
1524 <b>Example usage</b>\r
1525 @code\r
1526 UINT64 Msr;\r
1527\r
1528 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);\r
1529 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);\r
1530 @endcode\r
1531**/\r
1532#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13\r
1533\r
1534\r
1535/**\r
1536 Package. Uncore C-box 8 perfmon box wide filter.\r
1537\r
1538 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14)\r
1539 @param EAX Lower 32-bits of MSR value.\r
1540 @param EDX Upper 32-bits of MSR value.\r
1541\r
1542 <b>Example usage</b>\r
1543 @code\r
1544 UINT64 Msr;\r
1545\r
1546 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);\r
1547 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);\r
1548 @endcode\r
1549**/\r
1550#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14\r
1551\r
1552\r
1553/**\r
1554 Package. Uncore C-box 8 perfmon counter 0.\r
1555\r
1556 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16)\r
1557 @param EAX Lower 32-bits of MSR value.\r
1558 @param EDX Upper 32-bits of MSR value.\r
1559\r
1560 <b>Example usage</b>\r
1561 @code\r
1562 UINT64 Msr;\r
1563\r
1564 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);\r
1565 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);\r
1566 @endcode\r
1567**/\r
1568#define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16\r
1569\r
1570\r
1571/**\r
1572 Package. Uncore C-box 8 perfmon counter 1.\r
1573\r
1574 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17)\r
1575 @param EAX Lower 32-bits of MSR value.\r
1576 @param EDX Upper 32-bits of MSR value.\r
1577\r
1578 <b>Example usage</b>\r
1579 @code\r
1580 UINT64 Msr;\r
1581\r
1582 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);\r
1583 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);\r
1584 @endcode\r
1585**/\r
1586#define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17\r
1587\r
1588\r
1589/**\r
1590 Package. Uncore C-box 8 perfmon counter 2.\r
1591\r
1592 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18)\r
1593 @param EAX Lower 32-bits of MSR value.\r
1594 @param EDX Upper 32-bits of MSR value.\r
1595\r
1596 <b>Example usage</b>\r
1597 @code\r
1598 UINT64 Msr;\r
1599\r
1600 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);\r
1601 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);\r
1602 @endcode\r
1603**/\r
1604#define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18\r
1605\r
1606\r
1607/**\r
1608 Package. Uncore C-box 8 perfmon counter 3.\r
1609\r
1610 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19)\r
1611 @param EAX Lower 32-bits of MSR value.\r
1612 @param EDX Upper 32-bits of MSR value.\r
1613\r
1614 <b>Example usage</b>\r
1615 @code\r
1616 UINT64 Msr;\r
1617\r
1618 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);\r
1619 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);\r
1620 @endcode\r
1621**/\r
1622#define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19\r
1623\r
1624\r
1625/**\r
1626 Package. Uncore C-box 8 perfmon box wide filter1.\r
1627\r
1628 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A)\r
1629 @param EAX Lower 32-bits of MSR value.\r
1630 @param EDX Upper 32-bits of MSR value.\r
1631\r
1632 <b>Example usage</b>\r
1633 @code\r
1634 UINT64 Msr;\r
1635\r
1636 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);\r
1637 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);\r
1638 @endcode\r
1639**/\r
1640#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A\r
1641\r
1642\r
1643/**\r
1644 Package. Uncore C-box 9 perfmon local box wide control.\r
1645\r
1646 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24)\r
1647 @param EAX Lower 32-bits of MSR value.\r
1648 @param EDX Upper 32-bits of MSR value.\r
1649\r
1650 <b>Example usage</b>\r
1651 @code\r
1652 UINT64 Msr;\r
1653\r
1654 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);\r
1655 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);\r
1656 @endcode\r
1657**/\r
1658#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24\r
1659\r
1660\r
1661/**\r
1662 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.\r
1663\r
1664 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30)\r
1665 @param EAX Lower 32-bits of MSR value.\r
1666 @param EDX Upper 32-bits of MSR value.\r
1667\r
1668 <b>Example usage</b>\r
1669 @code\r
1670 UINT64 Msr;\r
1671\r
1672 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);\r
1673 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);\r
1674 @endcode\r
1675**/\r
1676#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30\r
1677\r
1678\r
1679/**\r
1680 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.\r
1681\r
1682 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31)\r
1683 @param EAX Lower 32-bits of MSR value.\r
1684 @param EDX Upper 32-bits of MSR value.\r
1685\r
1686 <b>Example usage</b>\r
1687 @code\r
1688 UINT64 Msr;\r
1689\r
1690 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);\r
1691 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);\r
1692 @endcode\r
1693**/\r
1694#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31\r
1695\r
1696\r
1697/**\r
1698 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.\r
1699\r
1700 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32)\r
1701 @param EAX Lower 32-bits of MSR value.\r
1702 @param EDX Upper 32-bits of MSR value.\r
1703\r
1704 <b>Example usage</b>\r
1705 @code\r
1706 UINT64 Msr;\r
1707\r
1708 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);\r
1709 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);\r
1710 @endcode\r
1711**/\r
1712#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32\r
1713\r
1714\r
1715/**\r
1716 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.\r
1717\r
1718 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33)\r
1719 @param EAX Lower 32-bits of MSR value.\r
1720 @param EDX Upper 32-bits of MSR value.\r
1721\r
1722 <b>Example usage</b>\r
1723 @code\r
1724 UINT64 Msr;\r
1725\r
1726 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);\r
1727 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);\r
1728 @endcode\r
1729**/\r
1730#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33\r
1731\r
1732\r
1733/**\r
1734 Package. Uncore C-box 9 perfmon box wide filter.\r
1735\r
1736 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34)\r
1737 @param EAX Lower 32-bits of MSR value.\r
1738 @param EDX Upper 32-bits of MSR value.\r
1739\r
1740 <b>Example usage</b>\r
1741 @code\r
1742 UINT64 Msr;\r
1743\r
1744 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);\r
1745 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);\r
1746 @endcode\r
1747**/\r
1748#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34\r
1749\r
1750\r
1751/**\r
1752 Package. Uncore C-box 9 perfmon counter 0.\r
1753\r
1754 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36)\r
1755 @param EAX Lower 32-bits of MSR value.\r
1756 @param EDX Upper 32-bits of MSR value.\r
1757\r
1758 <b>Example usage</b>\r
1759 @code\r
1760 UINT64 Msr;\r
1761\r
1762 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);\r
1763 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);\r
1764 @endcode\r
1765**/\r
1766#define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36\r
1767\r
1768\r
1769/**\r
1770 Package. Uncore C-box 9 perfmon counter 1.\r
1771\r
1772 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37)\r
1773 @param EAX Lower 32-bits of MSR value.\r
1774 @param EDX Upper 32-bits of MSR value.\r
1775\r
1776 <b>Example usage</b>\r
1777 @code\r
1778 UINT64 Msr;\r
1779\r
1780 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);\r
1781 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);\r
1782 @endcode\r
1783**/\r
1784#define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37\r
1785\r
1786\r
1787/**\r
1788 Package. Uncore C-box 9 perfmon counter 2.\r
1789\r
1790 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38)\r
1791 @param EAX Lower 32-bits of MSR value.\r
1792 @param EDX Upper 32-bits of MSR value.\r
1793\r
1794 <b>Example usage</b>\r
1795 @code\r
1796 UINT64 Msr;\r
1797\r
1798 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);\r
1799 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);\r
1800 @endcode\r
1801**/\r
1802#define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38\r
1803\r
1804\r
1805/**\r
1806 Package. Uncore C-box 9 perfmon counter 3.\r
1807\r
1808 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39)\r
1809 @param EAX Lower 32-bits of MSR value.\r
1810 @param EDX Upper 32-bits of MSR value.\r
1811\r
1812 <b>Example usage</b>\r
1813 @code\r
1814 UINT64 Msr;\r
1815\r
1816 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);\r
1817 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);\r
1818 @endcode\r
1819**/\r
1820#define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39\r
1821\r
1822\r
1823/**\r
1824 Package. Uncore C-box 9 perfmon box wide filter1.\r
1825\r
1826 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A)\r
1827 @param EAX Lower 32-bits of MSR value.\r
1828 @param EDX Upper 32-bits of MSR value.\r
1829\r
1830 <b>Example usage</b>\r
1831 @code\r
1832 UINT64 Msr;\r
1833\r
1834 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);\r
1835 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);\r
1836 @endcode\r
1837**/\r
1838#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A\r
1839\r
1840\r
1841/**\r
1842 Package. Uncore C-box 10 perfmon local box wide control.\r
1843\r
1844 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44)\r
1845 @param EAX Lower 32-bits of MSR value.\r
1846 @param EDX Upper 32-bits of MSR value.\r
1847\r
1848 <b>Example usage</b>\r
1849 @code\r
1850 UINT64 Msr;\r
1851\r
1852 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);\r
1853 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);\r
1854 @endcode\r
1855**/\r
1856#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44\r
1857\r
1858\r
1859/**\r
1860 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.\r
1861\r
1862 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50)\r
1863 @param EAX Lower 32-bits of MSR value.\r
1864 @param EDX Upper 32-bits of MSR value.\r
1865\r
1866 <b>Example usage</b>\r
1867 @code\r
1868 UINT64 Msr;\r
1869\r
1870 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);\r
1871 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);\r
1872 @endcode\r
1873**/\r
1874#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50\r
1875\r
1876\r
1877/**\r
1878 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.\r
1879\r
1880 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51)\r
1881 @param EAX Lower 32-bits of MSR value.\r
1882 @param EDX Upper 32-bits of MSR value.\r
1883\r
1884 <b>Example usage</b>\r
1885 @code\r
1886 UINT64 Msr;\r
1887\r
1888 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);\r
1889 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);\r
1890 @endcode\r
1891**/\r
1892#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51\r
1893\r
1894\r
1895/**\r
1896 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.\r
1897\r
1898 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52)\r
1899 @param EAX Lower 32-bits of MSR value.\r
1900 @param EDX Upper 32-bits of MSR value.\r
1901\r
1902 <b>Example usage</b>\r
1903 @code\r
1904 UINT64 Msr;\r
1905\r
1906 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);\r
1907 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);\r
1908 @endcode\r
1909**/\r
1910#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52\r
1911\r
1912\r
1913/**\r
1914 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.\r
1915\r
1916 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53)\r
1917 @param EAX Lower 32-bits of MSR value.\r
1918 @param EDX Upper 32-bits of MSR value.\r
1919\r
1920 <b>Example usage</b>\r
1921 @code\r
1922 UINT64 Msr;\r
1923\r
1924 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);\r
1925 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);\r
1926 @endcode\r
1927**/\r
1928#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53\r
1929\r
1930\r
1931/**\r
1932 Package. Uncore C-box 10 perfmon box wide filter.\r
1933\r
1934 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54)\r
1935 @param EAX Lower 32-bits of MSR value.\r
1936 @param EDX Upper 32-bits of MSR value.\r
1937\r
1938 <b>Example usage</b>\r
1939 @code\r
1940 UINT64 Msr;\r
1941\r
1942 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);\r
1943 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);\r
1944 @endcode\r
1945**/\r
1946#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54\r
1947\r
1948\r
1949/**\r
1950 Package. Uncore C-box 10 perfmon counter 0.\r
1951\r
1952 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56)\r
1953 @param EAX Lower 32-bits of MSR value.\r
1954 @param EDX Upper 32-bits of MSR value.\r
1955\r
1956 <b>Example usage</b>\r
1957 @code\r
1958 UINT64 Msr;\r
1959\r
1960 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);\r
1961 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);\r
1962 @endcode\r
1963**/\r
1964#define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56\r
1965\r
1966\r
1967/**\r
1968 Package. Uncore C-box 10 perfmon counter 1.\r
1969\r
1970 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57)\r
1971 @param EAX Lower 32-bits of MSR value.\r
1972 @param EDX Upper 32-bits of MSR value.\r
1973\r
1974 <b>Example usage</b>\r
1975 @code\r
1976 UINT64 Msr;\r
1977\r
1978 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);\r
1979 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);\r
1980 @endcode\r
1981**/\r
1982#define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57\r
1983\r
1984\r
1985/**\r
1986 Package. Uncore C-box 10 perfmon counter 2.\r
1987\r
1988 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58)\r
1989 @param EAX Lower 32-bits of MSR value.\r
1990 @param EDX Upper 32-bits of MSR value.\r
1991\r
1992 <b>Example usage</b>\r
1993 @code\r
1994 UINT64 Msr;\r
1995\r
1996 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);\r
1997 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);\r
1998 @endcode\r
1999**/\r
2000#define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58\r
2001\r
2002\r
2003/**\r
2004 Package. Uncore C-box 10 perfmon counter 3.\r
2005\r
2006 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59)\r
2007 @param EAX Lower 32-bits of MSR value.\r
2008 @param EDX Upper 32-bits of MSR value.\r
2009\r
2010 <b>Example usage</b>\r
2011 @code\r
2012 UINT64 Msr;\r
2013\r
2014 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);\r
2015 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);\r
2016 @endcode\r
2017**/\r
2018#define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59\r
2019\r
2020\r
2021/**\r
2022 Package. Uncore C-box 10 perfmon box wide filter1.\r
2023\r
2024 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A)\r
2025 @param EAX Lower 32-bits of MSR value.\r
2026 @param EDX Upper 32-bits of MSR value.\r
2027\r
2028 <b>Example usage</b>\r
2029 @code\r
2030 UINT64 Msr;\r
2031\r
2032 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);\r
2033 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);\r
2034 @endcode\r
2035**/\r
2036#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A\r
2037\r
2038\r
2039/**\r
2040 Package. Uncore C-box 11 perfmon local box wide control.\r
2041\r
2042 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64)\r
2043 @param EAX Lower 32-bits of MSR value.\r
2044 @param EDX Upper 32-bits of MSR value.\r
2045\r
2046 <b>Example usage</b>\r
2047 @code\r
2048 UINT64 Msr;\r
2049\r
2050 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);\r
2051 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);\r
2052 @endcode\r
2053**/\r
2054#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64\r
2055\r
2056\r
2057/**\r
2058 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.\r
2059\r
2060 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70)\r
2061 @param EAX Lower 32-bits of MSR value.\r
2062 @param EDX Upper 32-bits of MSR value.\r
2063\r
2064 <b>Example usage</b>\r
2065 @code\r
2066 UINT64 Msr;\r
2067\r
2068 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);\r
2069 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);\r
2070 @endcode\r
2071**/\r
2072#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70\r
2073\r
2074\r
2075/**\r
2076 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.\r
2077\r
2078 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71)\r
2079 @param EAX Lower 32-bits of MSR value.\r
2080 @param EDX Upper 32-bits of MSR value.\r
2081\r
2082 <b>Example usage</b>\r
2083 @code\r
2084 UINT64 Msr;\r
2085\r
2086 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);\r
2087 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);\r
2088 @endcode\r
2089**/\r
2090#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71\r
2091\r
2092\r
2093/**\r
2094 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.\r
2095\r
2096 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72)\r
2097 @param EAX Lower 32-bits of MSR value.\r
2098 @param EDX Upper 32-bits of MSR value.\r
2099\r
2100 <b>Example usage</b>\r
2101 @code\r
2102 UINT64 Msr;\r
2103\r
2104 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);\r
2105 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);\r
2106 @endcode\r
2107**/\r
2108#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72\r
2109\r
2110\r
2111/**\r
2112 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.\r
2113\r
2114 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73)\r
2115 @param EAX Lower 32-bits of MSR value.\r
2116 @param EDX Upper 32-bits of MSR value.\r
2117\r
2118 <b>Example usage</b>\r
2119 @code\r
2120 UINT64 Msr;\r
2121\r
2122 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);\r
2123 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);\r
2124 @endcode\r
2125**/\r
2126#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73\r
2127\r
2128\r
2129/**\r
2130 Package. Uncore C-box 11 perfmon box wide filter.\r
2131\r
2132 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74)\r
2133 @param EAX Lower 32-bits of MSR value.\r
2134 @param EDX Upper 32-bits of MSR value.\r
2135\r
2136 <b>Example usage</b>\r
2137 @code\r
2138 UINT64 Msr;\r
2139\r
2140 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);\r
2141 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);\r
2142 @endcode\r
2143**/\r
2144#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74\r
2145\r
2146\r
2147/**\r
2148 Package. Uncore C-box 11 perfmon counter 0.\r
2149\r
2150 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76)\r
2151 @param EAX Lower 32-bits of MSR value.\r
2152 @param EDX Upper 32-bits of MSR value.\r
2153\r
2154 <b>Example usage</b>\r
2155 @code\r
2156 UINT64 Msr;\r
2157\r
2158 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);\r
2159 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);\r
2160 @endcode\r
2161**/\r
2162#define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76\r
2163\r
2164\r
2165/**\r
2166 Package. Uncore C-box 11 perfmon counter 1.\r
2167\r
2168 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77)\r
2169 @param EAX Lower 32-bits of MSR value.\r
2170 @param EDX Upper 32-bits of MSR value.\r
2171\r
2172 <b>Example usage</b>\r
2173 @code\r
2174 UINT64 Msr;\r
2175\r
2176 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);\r
2177 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);\r
2178 @endcode\r
2179**/\r
2180#define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77\r
2181\r
2182\r
2183/**\r
2184 Package. Uncore C-box 11 perfmon counter 2.\r
2185\r
2186 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78)\r
2187 @param EAX Lower 32-bits of MSR value.\r
2188 @param EDX Upper 32-bits of MSR value.\r
2189\r
2190 <b>Example usage</b>\r
2191 @code\r
2192 UINT64 Msr;\r
2193\r
2194 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);\r
2195 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);\r
2196 @endcode\r
2197**/\r
2198#define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78\r
2199\r
2200\r
2201/**\r
2202 Package. Uncore C-box 11 perfmon counter 3.\r
2203\r
2204 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79)\r
2205 @param EAX Lower 32-bits of MSR value.\r
2206 @param EDX Upper 32-bits of MSR value.\r
2207\r
2208 <b>Example usage</b>\r
2209 @code\r
2210 UINT64 Msr;\r
2211\r
2212 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);\r
2213 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);\r
2214 @endcode\r
2215**/\r
2216#define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79\r
2217\r
2218\r
2219/**\r
2220 Package. Uncore C-box 11 perfmon box wide filter1.\r
2221\r
2222 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A)\r
2223 @param EAX Lower 32-bits of MSR value.\r
2224 @param EDX Upper 32-bits of MSR value.\r
2225\r
2226 <b>Example usage</b>\r
2227 @code\r
2228 UINT64 Msr;\r
2229\r
2230 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);\r
2231 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);\r
2232 @endcode\r
2233**/\r
2234#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A\r
2235\r
2236\r
2237/**\r
2238 Package. Uncore C-box 12 perfmon local box wide control.\r
2239\r
2240 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84)\r
2241 @param EAX Lower 32-bits of MSR value.\r
2242 @param EDX Upper 32-bits of MSR value.\r
2243\r
2244 <b>Example usage</b>\r
2245 @code\r
2246 UINT64 Msr;\r
2247\r
2248 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);\r
2249 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);\r
2250 @endcode\r
2251**/\r
2252#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84\r
2253\r
2254\r
2255/**\r
2256 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.\r
2257\r
2258 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90)\r
2259 @param EAX Lower 32-bits of MSR value.\r
2260 @param EDX Upper 32-bits of MSR value.\r
2261\r
2262 <b>Example usage</b>\r
2263 @code\r
2264 UINT64 Msr;\r
2265\r
2266 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);\r
2267 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);\r
2268 @endcode\r
2269**/\r
2270#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90\r
2271\r
2272\r
2273/**\r
2274 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.\r
2275\r
2276 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91)\r
2277 @param EAX Lower 32-bits of MSR value.\r
2278 @param EDX Upper 32-bits of MSR value.\r
2279\r
2280 <b>Example usage</b>\r
2281 @code\r
2282 UINT64 Msr;\r
2283\r
2284 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);\r
2285 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);\r
2286 @endcode\r
2287**/\r
2288#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91\r
2289\r
2290\r
2291/**\r
2292 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.\r
2293\r
2294 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92)\r
2295 @param EAX Lower 32-bits of MSR value.\r
2296 @param EDX Upper 32-bits of MSR value.\r
2297\r
2298 <b>Example usage</b>\r
2299 @code\r
2300 UINT64 Msr;\r
2301\r
2302 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);\r
2303 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);\r
2304 @endcode\r
2305**/\r
2306#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92\r
2307\r
2308\r
2309/**\r
2310 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.\r
2311\r
2312 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93)\r
2313 @param EAX Lower 32-bits of MSR value.\r
2314 @param EDX Upper 32-bits of MSR value.\r
2315\r
2316 <b>Example usage</b>\r
2317 @code\r
2318 UINT64 Msr;\r
2319\r
2320 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);\r
2321 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);\r
2322 @endcode\r
2323**/\r
2324#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93\r
2325\r
2326\r
2327/**\r
2328 Package. Uncore C-box 12 perfmon box wide filter.\r
2329\r
2330 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94)\r
2331 @param EAX Lower 32-bits of MSR value.\r
2332 @param EDX Upper 32-bits of MSR value.\r
2333\r
2334 <b>Example usage</b>\r
2335 @code\r
2336 UINT64 Msr;\r
2337\r
2338 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);\r
2339 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);\r
2340 @endcode\r
2341**/\r
2342#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94\r
2343\r
2344\r
2345/**\r
2346 Package. Uncore C-box 12 perfmon counter 0.\r
2347\r
2348 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96)\r
2349 @param EAX Lower 32-bits of MSR value.\r
2350 @param EDX Upper 32-bits of MSR value.\r
2351\r
2352 <b>Example usage</b>\r
2353 @code\r
2354 UINT64 Msr;\r
2355\r
2356 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);\r
2357 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);\r
2358 @endcode\r
2359**/\r
2360#define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96\r
2361\r
2362\r
2363/**\r
2364 Package. Uncore C-box 12 perfmon counter 1.\r
2365\r
2366 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97)\r
2367 @param EAX Lower 32-bits of MSR value.\r
2368 @param EDX Upper 32-bits of MSR value.\r
2369\r
2370 <b>Example usage</b>\r
2371 @code\r
2372 UINT64 Msr;\r
2373\r
2374 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);\r
2375 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);\r
2376 @endcode\r
2377**/\r
2378#define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97\r
2379\r
2380\r
2381/**\r
2382 Package. Uncore C-box 12 perfmon counter 2.\r
2383\r
2384 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98)\r
2385 @param EAX Lower 32-bits of MSR value.\r
2386 @param EDX Upper 32-bits of MSR value.\r
2387\r
2388 <b>Example usage</b>\r
2389 @code\r
2390 UINT64 Msr;\r
2391\r
2392 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);\r
2393 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);\r
2394 @endcode\r
2395**/\r
2396#define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98\r
2397\r
2398\r
2399/**\r
2400 Package. Uncore C-box 12 perfmon counter 3.\r
2401\r
2402 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99)\r
2403 @param EAX Lower 32-bits of MSR value.\r
2404 @param EDX Upper 32-bits of MSR value.\r
2405\r
2406 <b>Example usage</b>\r
2407 @code\r
2408 UINT64 Msr;\r
2409\r
2410 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);\r
2411 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);\r
2412 @endcode\r
2413**/\r
2414#define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99\r
2415\r
2416\r
2417/**\r
2418 Package. Uncore C-box 12 perfmon box wide filter1.\r
2419\r
2420 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A)\r
2421 @param EAX Lower 32-bits of MSR value.\r
2422 @param EDX Upper 32-bits of MSR value.\r
2423\r
2424 <b>Example usage</b>\r
2425 @code\r
2426 UINT64 Msr;\r
2427\r
2428 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);\r
2429 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);\r
2430 @endcode\r
2431**/\r
2432#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A\r
2433\r
2434\r
2435/**\r
2436 Package. Uncore C-box 13 perfmon local box wide control.\r
2437\r
2438 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4)\r
2439 @param EAX Lower 32-bits of MSR value.\r
2440 @param EDX Upper 32-bits of MSR value.\r
2441\r
2442 <b>Example usage</b>\r
2443 @code\r
2444 UINT64 Msr;\r
2445\r
2446 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);\r
2447 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);\r
2448 @endcode\r
2449**/\r
2450#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4\r
2451\r
2452\r
2453/**\r
2454 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.\r
2455\r
2456 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0)\r
2457 @param EAX Lower 32-bits of MSR value.\r
2458 @param EDX Upper 32-bits of MSR value.\r
2459\r
2460 <b>Example usage</b>\r
2461 @code\r
2462 UINT64 Msr;\r
2463\r
2464 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);\r
2465 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);\r
2466 @endcode\r
2467**/\r
2468#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0\r
2469\r
2470\r
2471/**\r
2472 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.\r
2473\r
2474 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1)\r
2475 @param EAX Lower 32-bits of MSR value.\r
2476 @param EDX Upper 32-bits of MSR value.\r
2477\r
2478 <b>Example usage</b>\r
2479 @code\r
2480 UINT64 Msr;\r
2481\r
2482 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);\r
2483 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);\r
2484 @endcode\r
2485**/\r
2486#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1\r
2487\r
2488\r
2489/**\r
2490 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.\r
2491\r
2492 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2)\r
2493 @param EAX Lower 32-bits of MSR value.\r
2494 @param EDX Upper 32-bits of MSR value.\r
2495\r
2496 <b>Example usage</b>\r
2497 @code\r
2498 UINT64 Msr;\r
2499\r
2500 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);\r
2501 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);\r
2502 @endcode\r
2503**/\r
2504#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2\r
2505\r
2506\r
2507/**\r
2508 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.\r
2509\r
2510 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3)\r
2511 @param EAX Lower 32-bits of MSR value.\r
2512 @param EDX Upper 32-bits of MSR value.\r
2513\r
2514 <b>Example usage</b>\r
2515 @code\r
2516 UINT64 Msr;\r
2517\r
2518 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);\r
2519 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);\r
2520 @endcode\r
2521**/\r
2522#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3\r
2523\r
2524\r
2525/**\r
2526 Package. Uncore C-box 13 perfmon box wide filter.\r
2527\r
2528 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4)\r
2529 @param EAX Lower 32-bits of MSR value.\r
2530 @param EDX Upper 32-bits of MSR value.\r
2531\r
2532 <b>Example usage</b>\r
2533 @code\r
2534 UINT64 Msr;\r
2535\r
2536 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);\r
2537 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);\r
2538 @endcode\r
2539**/\r
2540#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4\r
2541\r
2542\r
2543/**\r
2544 Package. Uncore C-box 13 perfmon counter 0.\r
2545\r
2546 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6)\r
2547 @param EAX Lower 32-bits of MSR value.\r
2548 @param EDX Upper 32-bits of MSR value.\r
2549\r
2550 <b>Example usage</b>\r
2551 @code\r
2552 UINT64 Msr;\r
2553\r
2554 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);\r
2555 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);\r
2556 @endcode\r
2557**/\r
2558#define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6\r
2559\r
2560\r
2561/**\r
2562 Package. Uncore C-box 13 perfmon counter 1.\r
2563\r
2564 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7)\r
2565 @param EAX Lower 32-bits of MSR value.\r
2566 @param EDX Upper 32-bits of MSR value.\r
2567\r
2568 <b>Example usage</b>\r
2569 @code\r
2570 UINT64 Msr;\r
2571\r
2572 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);\r
2573 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);\r
2574 @endcode\r
2575**/\r
2576#define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7\r
2577\r
2578\r
2579/**\r
2580 Package. Uncore C-box 13 perfmon counter 2.\r
2581\r
2582 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8)\r
2583 @param EAX Lower 32-bits of MSR value.\r
2584 @param EDX Upper 32-bits of MSR value.\r
2585\r
2586 <b>Example usage</b>\r
2587 @code\r
2588 UINT64 Msr;\r
2589\r
2590 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);\r
2591 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);\r
2592 @endcode\r
2593**/\r
2594#define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8\r
2595\r
2596\r
2597/**\r
2598 Package. Uncore C-box 13 perfmon counter 3.\r
2599\r
2600 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9)\r
2601 @param EAX Lower 32-bits of MSR value.\r
2602 @param EDX Upper 32-bits of MSR value.\r
2603\r
2604 <b>Example usage</b>\r
2605 @code\r
2606 UINT64 Msr;\r
2607\r
2608 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);\r
2609 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);\r
2610 @endcode\r
2611**/\r
2612#define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9\r
2613\r
2614\r
2615/**\r
2616 Package. Uncore C-box 13 perfmon box wide filter1.\r
2617\r
2618 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA)\r
2619 @param EAX Lower 32-bits of MSR value.\r
2620 @param EDX Upper 32-bits of MSR value.\r
2621\r
2622 <b>Example usage</b>\r
2623 @code\r
2624 UINT64 Msr;\r
2625\r
2626 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);\r
2627 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);\r
2628 @endcode\r
2629**/\r
2630#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA\r
2631\r
2632\r
2633/**\r
2634 Package. Uncore C-box 14 perfmon local box wide control.\r
2635\r
2636 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4)\r
2637 @param EAX Lower 32-bits of MSR value.\r
2638 @param EDX Upper 32-bits of MSR value.\r
2639\r
2640 <b>Example usage</b>\r
2641 @code\r
2642 UINT64 Msr;\r
2643\r
2644 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);\r
2645 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);\r
2646 @endcode\r
2647**/\r
2648#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4\r
2649\r
2650\r
2651/**\r
2652 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.\r
2653\r
2654 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0)\r
2655 @param EAX Lower 32-bits of MSR value.\r
2656 @param EDX Upper 32-bits of MSR value.\r
2657\r
2658 <b>Example usage</b>\r
2659 @code\r
2660 UINT64 Msr;\r
2661\r
2662 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);\r
2663 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);\r
2664 @endcode\r
2665**/\r
2666#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0\r
2667\r
2668\r
2669/**\r
2670 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.\r
2671\r
2672 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1)\r
2673 @param EAX Lower 32-bits of MSR value.\r
2674 @param EDX Upper 32-bits of MSR value.\r
2675\r
2676 <b>Example usage</b>\r
2677 @code\r
2678 UINT64 Msr;\r
2679\r
2680 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);\r
2681 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);\r
2682 @endcode\r
2683**/\r
2684#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1\r
2685\r
2686\r
2687/**\r
2688 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.\r
2689\r
2690 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2)\r
2691 @param EAX Lower 32-bits of MSR value.\r
2692 @param EDX Upper 32-bits of MSR value.\r
2693\r
2694 <b>Example usage</b>\r
2695 @code\r
2696 UINT64 Msr;\r
2697\r
2698 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);\r
2699 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);\r
2700 @endcode\r
2701**/\r
2702#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2\r
2703\r
2704\r
2705/**\r
2706 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.\r
2707\r
2708 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3)\r
2709 @param EAX Lower 32-bits of MSR value.\r
2710 @param EDX Upper 32-bits of MSR value.\r
2711\r
2712 <b>Example usage</b>\r
2713 @code\r
2714 UINT64 Msr;\r
2715\r
2716 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);\r
2717 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);\r
2718 @endcode\r
2719**/\r
2720#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3\r
2721\r
2722\r
2723/**\r
2724 Package. Uncore C-box 14 perfmon box wide filter.\r
2725\r
2726 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4)\r
2727 @param EAX Lower 32-bits of MSR value.\r
2728 @param EDX Upper 32-bits of MSR value.\r
2729\r
2730 <b>Example usage</b>\r
2731 @code\r
2732 UINT64 Msr;\r
2733\r
2734 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);\r
2735 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);\r
2736 @endcode\r
2737**/\r
2738#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4\r
2739\r
2740\r
2741/**\r
2742 Package. Uncore C-box 14 perfmon counter 0.\r
2743\r
2744 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6)\r
2745 @param EAX Lower 32-bits of MSR value.\r
2746 @param EDX Upper 32-bits of MSR value.\r
2747\r
2748 <b>Example usage</b>\r
2749 @code\r
2750 UINT64 Msr;\r
2751\r
2752 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);\r
2753 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);\r
2754 @endcode\r
2755**/\r
2756#define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6\r
2757\r
2758\r
2759/**\r
2760 Package. Uncore C-box 14 perfmon counter 1.\r
2761\r
2762 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7)\r
2763 @param EAX Lower 32-bits of MSR value.\r
2764 @param EDX Upper 32-bits of MSR value.\r
2765\r
2766 <b>Example usage</b>\r
2767 @code\r
2768 UINT64 Msr;\r
2769\r
2770 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);\r
2771 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);\r
2772 @endcode\r
2773**/\r
2774#define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7\r
2775\r
2776\r
2777/**\r
2778 Package. Uncore C-box 14 perfmon counter 2.\r
2779\r
2780 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8)\r
2781 @param EAX Lower 32-bits of MSR value.\r
2782 @param EDX Upper 32-bits of MSR value.\r
2783\r
2784 <b>Example usage</b>\r
2785 @code\r
2786 UINT64 Msr;\r
2787\r
2788 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);\r
2789 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);\r
2790 @endcode\r
2791**/\r
2792#define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8\r
2793\r
2794\r
2795/**\r
2796 Package. Uncore C-box 14 perfmon counter 3.\r
2797\r
2798 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9)\r
2799 @param EAX Lower 32-bits of MSR value.\r
2800 @param EDX Upper 32-bits of MSR value.\r
2801\r
2802 <b>Example usage</b>\r
2803 @code\r
2804 UINT64 Msr;\r
2805\r
2806 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);\r
2807 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);\r
2808 @endcode\r
2809**/\r
2810#define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9\r
2811\r
2812\r
2813/**\r
2814 Package. Uncore C-box 14 perfmon box wide filter1.\r
2815\r
2816 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA)\r
2817 @param EAX Lower 32-bits of MSR value.\r
2818 @param EDX Upper 32-bits of MSR value.\r
2819\r
2820 <b>Example usage</b>\r
2821 @code\r
2822 UINT64 Msr;\r
2823\r
2824 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);\r
2825 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);\r
2826 @endcode\r
2827**/\r
2828#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA\r
2829\r
2830#endif\r
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