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UefiCpuPkg/Include: Add Nehalem MSR include file
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / NehalemMsr.h
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MK		 1/** @file\r
2 MSR Definitions for Intel processors based on the Nehalem microarchitecture.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
10 This program and the accompanying materials\r
11 are licensed and made available under the terms and conditions of the BSD License\r
12 which accompanies this distribution. The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-5.\r
21\r
22**/\r
23\r
24#ifndef __NEHALEM_MSR_H__\r
25#define __NEHALEM_MSR_H__\r
26\r
27#include <Register/ArchitecturalMsr.h>\r
28\r
29/**\r
30 Package. Model Specific Platform ID (R).\r
31\r
32 @param ECX MSR_NEHALEM_PLATFORM_ID (0x00000017)\r
33 @param EAX Lower 32-bits of MSR value.\r
34 Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.\r
35 @param EDX Upper 32-bits of MSR value.\r
36 Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.\r
37\r
38 <b>Example usage</b>\r
39 @code\r
40 MSR_NEHALEM_PLATFORM_ID_REGISTER Msr;\r
41\r
42 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);\r
43 @endcode\r
44**/\r
45#define MSR_NEHALEM_PLATFORM_ID 0x00000017\r
46\r
47/**\r
48 MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID\r
49**/\r
50typedef union {\r
51 ///\r
52 /// Individual bit fields\r
53 ///\r
54 struct {\r
55 UINT32 Reserved1:32;\r
56 UINT32 Reserved2:18;\r
57 ///\r
58 /// [Bits 52:50] See Table 35-2.\r
59 ///\r
60 UINT32 PlatformId:3;\r
61 UINT32 Reserved3:11;\r
62 } Bits;\r
63 ///\r
64 /// All bit fields as a 64-bit value\r
65 ///\r
66 UINT64 Uint64;\r
67} MSR_NEHALEM_PLATFORM_ID_REGISTER;\r
68\r
69\r
70/**\r
71 Thread. SMI Counter (R/O).\r
72\r
73 @param ECX MSR_NEHALEM_SMI_COUNT (0x00000034)\r
74 @param EAX Lower 32-bits of MSR value.\r
75 Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.\r
76 @param EDX Upper 32-bits of MSR value.\r
77 Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.\r
78\r
79 <b>Example usage</b>\r
80 @code\r
81 MSR_NEHALEM_SMI_COUNT_REGISTER Msr;\r
82\r
83 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);\r
84 @endcode\r
85**/\r
86#define MSR_NEHALEM_SMI_COUNT 0x00000034\r
87\r
88/**\r
89 MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT\r
90**/\r
91typedef union {\r
92 ///\r
93 /// Individual bit fields\r
94 ///\r
95 struct {\r
96 ///\r
97 /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last\r
98 /// RESET.\r
99 ///\r
100 UINT32 SMICount:32;\r
101 UINT32 Reserved:32;\r
102 } Bits;\r
103 ///\r
104 /// All bit fields as a 32-bit value\r
105 ///\r
106 UINT32 Uint32;\r
107 ///\r
108 /// All bit fields as a 64-bit value\r
109 ///\r
110 UINT64 Uint64;\r
111} MSR_NEHALEM_SMI_COUNT_REGISTER;\r
112\r
113\r
114/**\r
115 Package. see http://biosbits.org.\r
116\r
117 @param ECX MSR_NEHALEM_PLATFORM_INFO (0x000000CE)\r
118 @param EAX Lower 32-bits of MSR value.\r
119 Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.\r
120 @param EDX Upper 32-bits of MSR value.\r
121 Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.\r
122\r
123 <b>Example usage</b>\r
124 @code\r
125 MSR_NEHALEM_PLATFORM_INFO_REGISTER Msr;\r
126\r
127 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);\r
128 AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);\r
129 @endcode\r
130**/\r
131#define MSR_NEHALEM_PLATFORM_INFO 0x000000CE\r
132\r
133/**\r
134 MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO\r
135**/\r
136typedef union {\r
137 ///\r
138 /// Individual bit fields\r
139 ///\r
140 struct {\r
141 UINT32 Reserved1:8;\r
142 ///\r
143 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
144 /// of the frequency that invariant TSC runs at. The invariant TSC\r
145 /// frequency can be computed by multiplying this ratio by 133.33 MHz.\r
146 ///\r
147 UINT32 MaximumNonTurboRatio:8;\r
148 UINT32 Reserved2:12;\r
149 ///\r
150 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
151 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
152 /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
153 /// Turbo mode is disabled.\r
154 ///\r
155 UINT32 RatioLimit:1;\r
156 ///\r
157 /// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O)\r
158 /// When set to 1, indicates that TDC/TDP Limits for Turbo mode are\r
159 /// programmable, and when set to 0, indicates TDC and TDP Limits for\r
160 /// Turbo mode are not programmable.\r
161 ///\r
162 UINT32 TDC_TDPLimit:1;\r
163 UINT32 Reserved3:2;\r
164 UINT32 Reserved4:8;\r
165 ///\r
166 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
167 /// minimum ratio (maximum efficiency) that the processor can operates, in\r
168 /// units of 133.33MHz.\r
169 ///\r
170 UINT32 MaximumEfficiencyRatio:8;\r
171 UINT32 Reserved5:16;\r
172 } Bits;\r
173 ///\r
174 /// All bit fields as a 64-bit value\r
175 ///\r
176 UINT64 Uint64;\r
177} MSR_NEHALEM_PLATFORM_INFO_REGISTER;\r
178\r
179\r
180/**\r
181 Core. C-State Configuration Control (R/W) Note: C-state values are\r
182 processor specific C-state code names, unrelated to MWAIT extension C-state\r
183 parameters or ACPI CStates. See http://biosbits.org.\r
184\r
185 @param ECX MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
186 @param EAX Lower 32-bits of MSR value.\r
187 Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.\r
188 @param EDX Upper 32-bits of MSR value.\r
189 Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.\r
190\r
191 <b>Example usage</b>\r
192 @code\r
193 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
194\r
195 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);\r
196 AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
197 @endcode\r
198**/\r
199#define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2\r
200\r
201/**\r
202 MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL\r
203**/\r
204typedef union {\r
205 ///\r
206 /// Individual bit fields\r
207 ///\r
208 struct {\r
209 ///\r
210 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
211 /// processor-specific C-state code name (consuming the least power). for\r
212 /// the package. The default is set as factory-configured package C-state\r
213 /// limit. The following C-state code name encodings are supported: 000b:\r
214 /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)\r
215 /// 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package\r
216 /// C-state limit. Note: This field cannot be used to limit package\r
217 /// C-state to C3.\r
218 ///\r
219 UINT32 Limit:3;\r
220 UINT32 Reserved1:7;\r
221 ///\r
222 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
223 /// IO_read instructions sent to IO register specified by\r
224 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
225 ///\r
226 UINT32 IO_MWAIT:1;\r
227 UINT32 Reserved2:4;\r
228 ///\r
229 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
230 /// until next reset.\r
231 ///\r
232 UINT32 CFGLock:1;\r
233 UINT32 Reserved3:8;\r
234 ///\r
235 /// [Bit 24] Interrupt filtering enable (R/W) When set, processor cores\r
236 /// in a deep C-State will wake only when the event message is destined\r
237 /// for that core. When 0, all processor cores in a deep C-State will wake\r
238 /// for an event message.\r
239 ///\r
240 UINT32 InterruptFiltering:1;\r
241 ///\r
242 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r
243 /// will conditionally demote C6/C7 requests to C3 based on uncore\r
244 /// auto-demote information.\r
245 ///\r
246 UINT32 C3AutoDemotion:1;\r
247 ///\r
248 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r
249 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
250 /// auto-demote information.\r
251 ///\r
252 UINT32 C1AutoDemotion:1;\r
253 UINT32 Reserved4:5;\r
254 UINT32 Reserved5:32;\r
255 } Bits;\r
256 ///\r
257 /// All bit fields as a 32-bit value\r
258 ///\r
259 UINT32 Uint32;\r
260 ///\r
261 /// All bit fields as a 64-bit value\r
262 ///\r
263 UINT64 Uint64;\r
264} MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER;\r
265\r
266\r
267/**\r
268 Core. Power Management IO Redirection in C-state (R/W) See\r
269 http://biosbits.org.\r
270\r
271 @param ECX MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4)\r
272 @param EAX Lower 32-bits of MSR value.\r
273 Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.\r
274 @param EDX Upper 32-bits of MSR value.\r
275 Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.\r
276\r
277 <b>Example usage</b>\r
278 @code\r
279 MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r
280\r
281 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);\r
282 AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
283 @endcode\r
284**/\r
285#define MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4\r
286\r
287/**\r
288 MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE\r
289**/\r
290typedef union {\r
291 ///\r
292 /// Individual bit fields\r
293 ///\r
294 struct {\r
295 ///\r
296 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address\r
297 /// visible to software for IO redirection. If IO MWAIT Redirection is\r
298 /// enabled, reads to this address will be consumed by the power\r
299 /// management logic and decoded to MWAIT instructions. When IO port\r
300 /// address redirection is enabled, this is the IO port address reported\r
301 /// to the OS/software.\r
302 ///\r
303 UINT32 Lvl2Base:16;\r
304 ///\r
305 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
306 /// maximum C-State code name to be included when IO read to MWAIT\r
307 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3\r
308 /// is the max C-State to include 001b - C6 is the max C-State to include\r
309 /// 010b - C7 is the max C-State to include.\r
310 ///\r
311 UINT32 CStateRange:3;\r
312 UINT32 Reserved1:13;\r
313 UINT32 Reserved2:32;\r
314 } Bits;\r
315 ///\r
316 /// All bit fields as a 32-bit value\r
317 ///\r
318 UINT32 Uint32;\r
319 ///\r
320 /// All bit fields as a 64-bit value\r
321 ///\r
322 UINT64 Uint64;\r
323} MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER;\r
324\r
325\r
326/**\r
327 Enable Misc. Processor Features (R/W) Allows a variety of processor\r
328 functions to be enabled and disabled.\r
329\r
330 @param ECX MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0)\r
331 @param EAX Lower 32-bits of MSR value.\r
332 Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.\r
333 @param EDX Upper 32-bits of MSR value.\r
334 Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.\r
335\r
336 <b>Example usage</b>\r
337 @code\r
338 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER Msr;\r
339\r
340 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);\r
341 AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);\r
342 @endcode\r
343**/\r
344#define MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0\r
345\r
346/**\r
347 MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE\r
348**/\r
349typedef union {\r
350 ///\r
351 /// Individual bit fields\r
352 ///\r
353 struct {\r
354 ///\r
355 /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.\r
356 ///\r
357 UINT32 FastStrings:1;\r
358 UINT32 Reserved1:2;\r
359 ///\r
360 /// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See\r
361 /// Table 35-2.\r
362 ///\r
363 UINT32 AutomaticThermalControlCircuit:1;\r
364 UINT32 Reserved2:3;\r
365 ///\r
366 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.\r
367 ///\r
368 UINT32 PerformanceMonitoring:1;\r
369 UINT32 Reserved3:3;\r
370 ///\r
371 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.\r
372 ///\r
373 UINT32 BTS:1;\r
374 ///\r
375 /// [Bit 12] Thread. Precise Event Based Sampling Unavailable (RO) See\r
376 /// Table 35-2.\r
377 ///\r
378 UINT32 PEBS:1;\r
379 UINT32 Reserved4:3;\r
380 ///\r
381 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
382 /// Table 35-2.\r
383 ///\r
384 UINT32 EIST:1;\r
385 UINT32 Reserved5:1;\r
386 ///\r
387 /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.\r
388 ///\r
389 UINT32 MONITOR:1;\r
390 UINT32 Reserved6:3;\r
391 ///\r
392 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.\r
393 ///\r
394 UINT32 LimitCpuidMaxval:1;\r
395 ///\r
396 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.\r
397 ///\r
398 UINT32 xTPR_Message_Disable:1;\r
399 UINT32 Reserved7:8;\r
400 UINT32 Reserved8:2;\r
401 ///\r
402 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.\r
403 ///\r
404 UINT32 XD:1;\r
405 UINT32 Reserved9:3;\r
406 ///\r
407 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r
408 /// that support Intel Turbo Boost Technology, the turbo mode feature is\r
409 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r
410 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r
411 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r
412 /// the power-on default value is used by BIOS to detect hardware support\r
413 /// of turbo mode. If power-on default value is 1, turbo mode is available\r
414 /// in the processor. If power-on default value is 0, turbo mode is not\r
415 /// available.\r
416 ///\r
417 UINT32 TurboModeDisable:1;\r
418 UINT32 Reserved10:25;\r
419 } Bits;\r
420 ///\r
421 /// All bit fields as a 64-bit value\r
422 ///\r
423 UINT64 Uint64;\r
424} MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER;\r
425\r
426\r
427/**\r
428 Thread.\r
429\r
430 @param ECX MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2)\r
431 @param EAX Lower 32-bits of MSR value.\r
432 Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.\r
433 @param EDX Upper 32-bits of MSR value.\r
434 Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.\r
435\r
436 <b>Example usage</b>\r
437 @code\r
438 MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER Msr;\r
439\r
440 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);\r
441 AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);\r
442 @endcode\r
443**/\r
444#define MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2\r
445\r
446/**\r
447 MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET\r
448**/\r
449typedef union {\r
450 ///\r
451 /// Individual bit fields\r
452 ///\r
453 struct {\r
454 UINT32 Reserved1:16;\r
455 ///\r
456 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which\r
457 /// PROCHOT# will be asserted. The value is degree C.\r
458 ///\r
459 UINT32 TemperatureTarget:8;\r
460 UINT32 Reserved2:8;\r
461 UINT32 Reserved3:32;\r
462 } Bits;\r
463 ///\r
464 /// All bit fields as a 32-bit value\r
465 ///\r
466 UINT32 Uint32;\r
467 ///\r
468 /// All bit fields as a 64-bit value\r
469 ///\r
470 UINT64 Uint64;\r
471} MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER;\r
472\r
473\r
474/**\r
475 Miscellaneous Feature Control (R/W).\r
476\r
477 @param ECX MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4)\r
478 @param EAX Lower 32-bits of MSR value.\r
479 Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.\r
480 @param EDX Upper 32-bits of MSR value.\r
481 Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.\r
482\r
483 <b>Example usage</b>\r
484 @code\r
485 MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER Msr;\r
486\r
487 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);\r
488 AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);\r
489 @endcode\r
490**/\r
491#define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4\r
492\r
493/**\r
494 MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL\r
495**/\r
496typedef union {\r
497 ///\r
498 /// Individual bit fields\r
499 ///\r
500 struct {\r
501 ///\r
502 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
503 /// L2 hardware prefetcher, which fetches additional lines of code or data\r
504 /// into the L2 cache.\r
505 ///\r
506 UINT32 L2HardwarePrefetcherDisable:1;\r
507 ///\r
508 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,\r
509 /// disables the adjacent cache line prefetcher, which fetches the cache\r
510 /// line that comprises a cache line pair (128 bytes).\r
511 ///\r
512 UINT32 L2AdjacentCacheLinePrefetcherDisable:1;\r
513 ///\r
514 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
515 /// the L1 data cache prefetcher, which fetches the next cache line into\r
516 /// L1 data cache.\r
517 ///\r
518 UINT32 DCUHardwarePrefetcherDisable:1;\r
519 ///\r
520 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1\r
521 /// data cache IP prefetcher, which uses sequential load history (based on\r
522 /// instruction Pointer of previous loads) to determine whether to\r
523 /// prefetch additional lines.\r
524 ///\r
525 UINT32 DCUIPPrefetcherDisable:1;\r
526 UINT32 Reserved1:28;\r
527 UINT32 Reserved2:32;\r
528 } Bits;\r
529 ///\r
530 /// All bit fields as a 32-bit value\r
531 ///\r
532 UINT32 Uint32;\r
533 ///\r
534 /// All bit fields as a 64-bit value\r
535 ///\r
536 UINT64 Uint64;\r
537} MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER;\r
538\r
539\r
540/**\r
541 Thread. Offcore Response Event Select Register (R/W).\r
542\r
543 @param ECX MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6)\r
544 @param EAX Lower 32-bits of MSR value.\r
545 @param EDX Upper 32-bits of MSR value.\r
546\r
547 <b>Example usage</b>\r
548 @code\r
549 UINT64 Msr;\r
550\r
551 Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);\r
552 AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);\r
553 @endcode\r
554**/\r
555#define MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6\r
556\r
557\r
558/**\r
559 See http://biosbits.org.\r
560\r
561 @param ECX MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA)\r
562 @param EAX Lower 32-bits of MSR value.\r
563 Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.\r
564 @param EDX Upper 32-bits of MSR value.\r
565 Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.\r
566\r
567 <b>Example usage</b>\r
568 @code\r
569 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER Msr;\r
570\r
571 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);\r
572 AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);\r
573 @endcode\r
574**/\r
575#define MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA\r
576\r
577/**\r
578 MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT\r
579**/\r
580typedef union {\r
581 ///\r
582 /// Individual bit fields\r
583 ///\r
584 struct {\r
585 ///\r
586 /// [Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0,\r
587 /// enables hardware coordination of Enhanced Intel Speedstep Technology\r
588 /// request from processor cores; When 1, disables hardware coordination\r
589 /// of Enhanced Intel Speedstep Technology requests.\r
590 ///\r
591 UINT32 EISTHardwareCoordinationDisable:1;\r
592 ///\r
593 /// [Bit 1] Thread. Energy/Performance Bias Enable (R/W) This bit makes\r
594 /// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with\r
595 /// Ring 0 privileges. This bit's status (1 or 0) is also reflected by\r
596 /// CPUID.(EAX=06h):ECX[3].\r
597 ///\r
598 UINT32 EnergyPerformanceBiasEnable:1;\r
599 UINT32 Reserved1:30;\r
600 UINT32 Reserved2:32;\r
601 } Bits;\r
602 ///\r
603 /// All bit fields as a 32-bit value\r
604 ///\r
605 UINT32 Uint32;\r
606 ///\r
607 /// All bit fields as a 64-bit value\r
608 ///\r
609 UINT64 Uint64;\r
610} MSR_NEHALEM_MISC_PWR_MGMT_REGISTER;\r
611\r
612\r
613/**\r
614 See http://biosbits.org.\r
615\r
616 @param ECX MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC)\r
617 @param EAX Lower 32-bits of MSR value.\r
618 Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.\r
619 @param EDX Upper 32-bits of MSR value.\r
620 Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.\r
621\r
622 <b>Example usage</b>\r
623 @code\r
624 MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER Msr;\r
625\r
626 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);\r
627 AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);\r
628 @endcode\r
629**/\r
630#define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC\r
631\r
632/**\r
633 MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT\r
634**/\r
635typedef union {\r
636 ///\r
637 /// Individual bit fields\r
638 ///\r
639 struct {\r
640 ///\r
641 /// [Bits 14:0] Package. TDP Limit (R/W) TDP limit in 1/8 Watt\r
642 /// granularity.\r
643 ///\r
644 UINT32 TDPLimit:15;\r
645 ///\r
646 /// [Bit 15] Package. TDP Limit Override Enable (R/W) A value = 0\r
647 /// indicates override is not active, and a value = 1 indicates active.\r
648 ///\r
649 UINT32 TDPLimitOverrideEnable:1;\r
650 ///\r
651 /// [Bits 30:16] Package. TDC Limit (R/W) TDC limit in 1/8 Amp\r
652 /// granularity.\r
653 ///\r
654 UINT32 TDCLimit:15;\r
655 ///\r
656 /// [Bit 31] Package. TDC Limit Override Enable (R/W) A value = 0\r
657 /// indicates override is not active, and a value = 1 indicates active.\r
658 ///\r
659 UINT32 TDCLimitOverrideEnable:1;\r
660 UINT32 Reserved:32;\r
661 } Bits;\r
662 ///\r
663 /// All bit fields as a 32-bit value\r
664 ///\r
665 UINT32 Uint32;\r
666 ///\r
667 /// All bit fields as a 64-bit value\r
668 ///\r
669 UINT64 Uint64;\r
670} MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER;\r
671\r
672\r
673/**\r
674 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
675 RW if MSR_PLATFORM_INFO.[28] = 1.\r
676\r
677 @param ECX MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD)\r
678 @param EAX Lower 32-bits of MSR value.\r
679 Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.\r
680 @param EDX Upper 32-bits of MSR value.\r
681 Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.\r
682\r
683 <b>Example usage</b>\r
684 @code\r
685 MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER Msr;\r
686\r
687 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);\r
688 @endcode\r
689**/\r
690#define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD\r
691\r
692/**\r
693 MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT\r
694**/\r
695typedef union {\r
696 ///\r
697 /// Individual bit fields\r
698 ///\r
699 struct {\r
700 ///\r
701 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
702 /// limit of 1 core active.\r
703 ///\r
704 UINT32 Maximum1C:8;\r
705 ///\r
706 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
707 /// limit of 2 core active.\r
708 ///\r
709 UINT32 Maximum2C:8;\r
710 ///\r
711 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
712 /// limit of 3 core active.\r
713 ///\r
714 UINT32 Maximum3C:8;\r
715 ///\r
716 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
717 /// limit of 4 core active.\r
718 ///\r
719 UINT32 Maximum4C:8;\r
720 UINT32 Reserved:32;\r
721 } Bits;\r
722 ///\r
723 /// All bit fields as a 32-bit value\r
724 ///\r
725 UINT32 Uint32;\r
726 ///\r
727 /// All bit fields as a 64-bit value\r
728 ///\r
729 UINT64 Uint64;\r
730} MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER;\r
731\r
732\r
733/**\r
734 Core. Last Branch Record Filtering Select Register (R/W) See Section\r
735 17.6.2, "Filtering of Last Branch Records.".\r
736\r
737 @param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8)\r
738 @param EAX Lower 32-bits of MSR value.\r
739 Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.\r
740 @param EDX Upper 32-bits of MSR value.\r
741 Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.\r
742\r
743 <b>Example usage</b>\r
744 @code\r
745 MSR_NEHALEM_LBR_SELECT_REGISTER Msr;\r
746\r
747 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);\r
748 AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);\r
749 @endcode\r
750**/\r
751#define MSR_NEHALEM_LBR_SELECT 0x000001C8\r
752\r
753/**\r
754 MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT\r
755**/\r
756typedef union {\r
757 ///\r
758 /// Individual bit fields\r
759 ///\r
760 struct {\r
761 ///\r
762 /// [Bit 0] CPL_EQ_0.\r
763 ///\r
764 UINT32 CPL_EQ_0:1;\r
765 ///\r
766 /// [Bit 1] CPL_NEQ_0.\r
767 ///\r
768 UINT32 CPL_NEQ_0:1;\r
769 ///\r
770 /// [Bit 2] JCC.\r
771 ///\r
772 UINT32 JCC:1;\r
773 ///\r
774 /// [Bit 3] NEAR_REL_CALL.\r
775 ///\r
776 UINT32 NEAR_REL_CALL:1;\r
777 ///\r
778 /// [Bit 4] NEAR_IND_CALL.\r
779 ///\r
780 UINT32 NEAR_IND_CALL:1;\r
781 ///\r
782 /// [Bit 5] NEAR_RET.\r
783 ///\r
784 UINT32 NEAR_RET:1;\r
785 ///\r
786 /// [Bit 6] NEAR_IND_JMP.\r
787 ///\r
788 UINT32 NEAR_IND_JMP:1;\r
789 ///\r
790 /// [Bit 7] NEAR_REL_JMP.\r
791 ///\r
792 UINT32 NEAR_REL_JMP:1;\r
793 ///\r
794 /// [Bit 8] FAR_BRANCH.\r
795 ///\r
796 UINT32 FAR_BRANCH:1;\r
797 UINT32 Reserved1:23;\r
798 UINT32 Reserved2:32;\r
799 } Bits;\r
800 ///\r
801 /// All bit fields as a 32-bit value\r
802 ///\r
803 UINT32 Uint32;\r
804 ///\r
805 /// All bit fields as a 64-bit value\r
806 ///\r
807 UINT64 Uint64;\r
808} MSR_NEHALEM_LBR_SELECT_REGISTER;\r
809\r
810\r
811/**\r
812 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
813 that points to the MSR containing the most recent branch record. See\r
814 MSR_LASTBRANCH_0_FROM_IP (at 680H).\r
815\r
816 @param ECX MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9)\r
817 @param EAX Lower 32-bits of MSR value.\r
818 @param EDX Upper 32-bits of MSR value.\r
819\r
820 <b>Example usage</b>\r
821 @code\r
822 UINT64 Msr;\r
823\r
824 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);\r
825 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);\r
826 @endcode\r
827**/\r
828#define MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9\r
829\r
830\r
831/**\r
832 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the\r
833 last branch instruction that the processor executed prior to the last\r
834 exception that was generated or the last interrupt that was handled.\r
835\r
836 @param ECX MSR_NEHALEM_LER_FROM_LIP (0x000001DD)\r
837 @param EAX Lower 32-bits of MSR value.\r
838 @param EDX Upper 32-bits of MSR value.\r
839\r
840 <b>Example usage</b>\r
841 @code\r
842 UINT64 Msr;\r
843\r
844 Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);\r
845 @endcode\r
846**/\r
847#define MSR_NEHALEM_LER_FROM_LIP 0x000001DD\r
848\r
849\r
850/**\r
851 Thread. Last Exception Record To Linear IP (R) This area contains a pointer\r
852 to the target of the last branch instruction that the processor executed\r
853 prior to the last exception that was generated or the last interrupt that\r
854 was handled.\r
855\r
856 @param ECX MSR_NEHALEM_LER_TO_LIP (0x000001DE)\r
857 @param EAX Lower 32-bits of MSR value.\r
858 @param EDX Upper 32-bits of MSR value.\r
859\r
860 <b>Example usage</b>\r
861 @code\r
862 UINT64 Msr;\r
863\r
864 Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP);\r
865 @endcode\r
866**/\r
867#define MSR_NEHALEM_LER_TO_LIP 0x000001DE\r
868\r
869\r
870/**\r
871 Core. Power Control Register. See http://biosbits.org.\r
872\r
873 @param ECX MSR_NEHALEM_POWER_CTL (0x000001FC)\r
874 @param EAX Lower 32-bits of MSR value.\r
875 Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.\r
876 @param EDX Upper 32-bits of MSR value.\r
877 Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.\r
878\r
879 <b>Example usage</b>\r
880 @code\r
881 MSR_NEHALEM_POWER_CTL_REGISTER Msr;\r
882\r
883 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL);\r
884 AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64);\r
885 @endcode\r
886**/\r
887#define MSR_NEHALEM_POWER_CTL 0x000001FC\r
888\r
889/**\r
890 MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL\r
891**/\r
892typedef union {\r
893 ///\r
894 /// Individual bit fields\r
895 ///\r
896 struct {\r
897 UINT32 Reserved1:1;\r
898 ///\r
899 /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the\r
900 /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology\r
901 /// operating point when all execution cores enter MWAIT (C1).\r
902 ///\r
903 UINT32 C1EEnable:1;\r
904 UINT32 Reserved2:30;\r
905 UINT32 Reserved3:32;\r
906 } Bits;\r
907 ///\r
908 /// All bit fields as a 32-bit value\r
909 ///\r
910 UINT32 Uint32;\r
911 ///\r
912 /// All bit fields as a 64-bit value\r
913 ///\r
914 UINT64 Uint64;\r
915} MSR_NEHALEM_POWER_CTL_REGISTER;\r
916\r
917\r
918/**\r
919 Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
920 Facilities.".\r
921\r
922 @param ECX MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
923 @param EAX Lower 32-bits of MSR value.\r
924 @param EDX Upper 32-bits of MSR value.\r
925\r
926 <b>Example usage</b>\r
927 @code\r
928 UINT64 Msr;\r
929\r
930 Msr = AsmReadMsr64 (MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS);\r
931 AsmWriteMsr64 (MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS, Msr);\r
932 @endcode\r
933**/\r
934#define MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
935\r
936\r
937/**\r
938 Thread. (RO).\r
939\r
940 @param ECX MSR_NEHALEM_PERF_GLOBAL_STAUS (0x0000038E)\r
941 @param EAX Lower 32-bits of MSR value.\r
942 Described by the type MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER.\r
943 @param EDX Upper 32-bits of MSR value.\r
944 Described by the type MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER.\r
945\r
946 <b>Example usage</b>\r
947 @code\r
948 MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER Msr;\r
949\r
950 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STAUS);\r
951 @endcode\r
952**/\r
953#define MSR_NEHALEM_PERF_GLOBAL_STAUS 0x0000038E\r
954\r
955/**\r
956 MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STAUS\r
957**/\r
958typedef union {\r
959 ///\r
960 /// Individual bit fields\r
961 ///\r
962 struct {\r
963 UINT32 Reserved1:32;\r
964 UINT32 Reserved2:29;\r
965 ///\r
966 /// [Bit 61] UNC_Ovf Uncore overflowed if 1.\r
967 ///\r
968 UINT32 Ovf_Uncore:1;\r
969 UINT32 Reserved3:2;\r
970 } Bits;\r
971 ///\r
972 /// All bit fields as a 64-bit value\r
973 ///\r
974 UINT64 Uint64;\r
975} MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER;\r
976\r
977\r
978/**\r
979 Thread. (R/W).\r
980\r
981 @param ECX MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
982 @param EAX Lower 32-bits of MSR value.\r
983 Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
984 @param EDX Upper 32-bits of MSR value.\r
985 Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
986\r
987 <b>Example usage</b>\r
988 @code\r
989 MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r
990\r
991 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL);\r
992 AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r
993 @endcode\r
994**/\r
995#define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390\r
996\r
997/**\r
998 MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL\r
999**/\r
1000typedef union {\r
1001 ///\r
1002 /// Individual bit fields\r
1003 ///\r
1004 struct {\r
1005 UINT32 Reserved1:32;\r
1006 UINT32 Reserved2:29;\r
1007 ///\r
1008 /// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf.\r
1009 ///\r
1010 UINT32 Ovf_Uncore:1;\r
1011 UINT32 Reserved3:2;\r
1012 } Bits;\r
1013 ///\r
1014 /// All bit fields as a 64-bit value\r
1015 ///\r
1016 UINT64 Uint64;\r
1017} MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
1018\r
1019\r
1020/**\r
1021 Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".\r
1022\r
1023 @param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1)\r
1024 @param EAX Lower 32-bits of MSR value.\r
1025 Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.\r
1026 @param EDX Upper 32-bits of MSR value.\r
1027 Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.\r
1028\r
1029 <b>Example usage</b>\r
1030 @code\r
1031 MSR_NEHALEM_PEBS_ENABLE_REGISTER Msr;\r
1032\r
1033 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE);\r
1034 AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64);\r
1035 @endcode\r
1036**/\r
1037#define MSR_NEHALEM_PEBS_ENABLE 0x000003F1\r
1038\r
1039/**\r
1040 MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE\r
1041**/\r
1042typedef union {\r
1043 ///\r
1044 /// Individual bit fields\r
1045 ///\r
1046 struct {\r
1047 ///\r
1048 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
1049 ///\r
1050 UINT32 PEBS_EN_PMC0:1;\r
1051 ///\r
1052 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
1053 ///\r
1054 UINT32 PEBS_EN_PMC1:1;\r
1055 ///\r
1056 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
1057 ///\r
1058 UINT32 PEBS_EN_PMC2:1;\r
1059 ///\r
1060 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
1061 ///\r
1062 UINT32 PEBS_EN_PMC3:1;\r
1063 UINT32 Reserved1:28;\r
1064 ///\r
1065 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
1066 ///\r
1067 UINT32 LL_EN_PMC0:1;\r
1068 ///\r
1069 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
1070 ///\r
1071 UINT32 LL_EN_PMC1:1;\r
1072 ///\r
1073 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
1074 ///\r
1075 UINT32 LL_EN_PMC2:1;\r
1076 ///\r
1077 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
1078 ///\r
1079 UINT32 LL_EN_PMC3:1;\r
1080 UINT32 Reserved2:28;\r
1081 } Bits;\r
1082 ///\r
1083 /// All bit fields as a 64-bit value\r
1084 ///\r
1085 UINT64 Uint64;\r
1086} MSR_NEHALEM_PEBS_ENABLE_REGISTER;\r
1087\r
1088\r
1089/**\r
1090 Thread. See Section 18.7.1.2, "Load Latency Performance Monitoring\r
1091 Facility.".\r
1092\r
1093 @param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)\r
1094 @param EAX Lower 32-bits of MSR value.\r
1095 Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.\r
1096 @param EDX Upper 32-bits of MSR value.\r
1097 Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.\r
1098\r
1099 <b>Example usage</b>\r
1100 @code\r
1101 MSR_NEHALEM_PEBS_LD_LAT_REGISTER Msr;\r
1102\r
1103 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT);\r
1104 AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64);\r
1105 @endcode\r
1106**/\r
1107#define MSR_NEHALEM_PEBS_LD_LAT 0x000003F6\r
1108\r
1109/**\r
1110 MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT\r
1111**/\r
1112typedef union {\r
1113 ///\r
1114 /// Individual bit fields\r
1115 ///\r
1116 struct {\r
1117 ///\r
1118 /// [Bits 15:0] Minimum threshold latency value of tagged load operation\r
1119 /// that will be counted. (R/W).\r
1120 ///\r
1121 UINT32 MinimumThreshold:16;\r
1122 UINT32 Reserved1:16;\r
1123 UINT32 Reserved2:32;\r
1124 } Bits;\r
1125 ///\r
1126 /// All bit fields as a 32-bit value\r
1127 ///\r
1128 UINT32 Uint32;\r
1129 ///\r
1130 /// All bit fields as a 64-bit value\r
1131 ///\r
1132 UINT64 Uint64;\r
1133} MSR_NEHALEM_PEBS_LD_LAT_REGISTER;\r
1134\r
1135\r
1136/**\r
1137 Package. Note: C-state values are processor specific C-state code names,\r
1138 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r
1139 Residency Counter. (R/O) Value since last reset that this package is in\r
1140 processor-specific C3 states. Count at the same frequency as the TSC.\r
1141\r
1142 @param ECX MSR_NEHALEM_PKG_C3_RESIDENCY (0x000003F8)\r
1143 @param EAX Lower 32-bits of MSR value.\r
1144 @param EDX Upper 32-bits of MSR value.\r
1145\r
1146 <b>Example usage</b>\r
1147 @code\r
1148 UINT64 Msr;\r
1149\r
1150 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY);\r
1151 AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr);\r
1152 @endcode\r
1153**/\r
1154#define MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8\r
1155\r
1156\r
1157/**\r
1158 Package. Note: C-state values are processor specific C-state code names,\r
1159 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r
1160 Residency Counter. (R/O) Value since last reset that this package is in\r
1161 processor-specific C6 states. Count at the same frequency as the TSC.\r
1162\r
1163 @param ECX MSR_NEHALEM_PKG_C6_RESIDENCY (0x000003F9)\r
1164 @param EAX Lower 32-bits of MSR value.\r
1165 @param EDX Upper 32-bits of MSR value.\r
1166\r
1167 <b>Example usage</b>\r
1168 @code\r
1169 UINT64 Msr;\r
1170\r
1171 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY);\r
1172 AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr);\r
1173 @endcode\r
1174**/\r
1175#define MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9\r
1176\r
1177\r
1178/**\r
1179 Package. Note: C-state values are processor specific C-state code names,\r
1180 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7\r
1181 Residency Counter. (R/O) Value since last reset that this package is in\r
1182 processor-specific C7 states. Count at the same frequency as the TSC.\r
1183\r
1184 @param ECX MSR_NEHALEM_PKG_C7_RESIDENCY (0x000003FA)\r
1185 @param EAX Lower 32-bits of MSR value.\r
1186 @param EDX Upper 32-bits of MSR value.\r
1187\r
1188 <b>Example usage</b>\r
1189 @code\r
1190 UINT64 Msr;\r
1191\r
1192 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY);\r
1193 AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr);\r
1194 @endcode\r
1195**/\r
1196#define MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA\r
1197\r
1198\r
1199/**\r
1200 Core. Note: C-state values are processor specific C-state code names,\r
1201 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3\r
1202 Residency Counter. (R/O) Value since last reset that this core is in\r
1203 processor-specific C3 states. Count at the same frequency as the TSC.\r
1204\r
1205 @param ECX MSR_NEHALEM_CORE_C3_RESIDENCY (0x000003FC)\r
1206 @param EAX Lower 32-bits of MSR value.\r
1207 @param EDX Upper 32-bits of MSR value.\r
1208\r
1209 <b>Example usage</b>\r
1210 @code\r
1211 UINT64 Msr;\r
1212\r
1213 Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY);\r
1214 AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr);\r
1215 @endcode\r
1216**/\r
1217#define MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC\r
1218\r
1219\r
1220/**\r
1221 Core. Note: C-state values are processor specific C-state code names,\r
1222 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6\r
1223 Residency Counter. (R/O) Value since last reset that this core is in\r
1224 processor-specific C6 states. Count at the same frequency as the TSC.\r
1225\r
1226 @param ECX MSR_NEHALEM_CORE_C6_RESIDENCY (0x000003FD)\r
1227 @param EAX Lower 32-bits of MSR value.\r
1228 @param EDX Upper 32-bits of MSR value.\r
1229\r
1230 <b>Example usage</b>\r
1231 @code\r
1232 UINT64 Msr;\r
1233\r
1234 Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY);\r
1235 AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr);\r
1236 @endcode\r
1237**/\r
1238#define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD\r
1239\r
1240\r
1241/**\r
1242 See Section 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
1243\r
1244 @param ECX MSR_NEHALEM_MCi_MISC\r
1245 @param EAX Lower 32-bits of MSR value.\r
1246 @param EDX Upper 32-bits of MSR value.\r
1247\r
1248 <b>Example usage</b>\r
1249 @code\r
1250 UINT64 Msr;\r
1251\r
1252 Msr = AsmReadMsr64 (MSR_NEHALEM_MC0_MISC);\r
1253 AsmWriteMsr64 (MSR_NEHALEM_MC0_MISC, Msr);\r
1254 @endcode\r
1255 @{\r
1256**/\r
1257#define MSR_NEHALEM_MC0_MISC 0x00000403\r
1258#define MSR_NEHALEM_MC1_MISC 0x00000407\r
1259#define MSR_NEHALEM_MC2_MISC 0x0000040B\r
1260#define MSR_NEHALEM_MC3_MISC 0x0000040F\r
1261#define MSR_NEHALEM_MC4_MISC 0x00000413\r
1262#define MSR_NEHALEM_MC5_MISC 0x00000417\r
1263#define MSR_NEHALEM_MC6_MISC 0x0000041B\r
1264#define MSR_NEHALEM_MC7_MISC 0x0000041F\r
1265#define MSR_NEHALEM_MC8_MISC 0x00000423\r
1266#define MSR_NEHALEM_MC9_MISC 0x00000427\r
1267#define MSR_NEHALEM_MC10_MISC 0x0000042B\r
1268#define MSR_NEHALEM_MC11_MISC 0x0000042F\r
1269#define MSR_NEHALEM_MC12_MISC 0x00000433\r
1270#define MSR_NEHALEM_MC13_MISC 0x00000437\r
1271#define MSR_NEHALEM_MC14_MISC 0x0000043B\r
1272#define MSR_NEHALEM_MC15_MISC 0x0000043F\r
1273#define MSR_NEHALEM_MC16_MISC 0x00000443\r
1274#define MSR_NEHALEM_MC17_MISC 0x00000447\r
1275#define MSR_NEHALEM_MC18_MISC 0x0000044B\r
1276#define MSR_NEHALEM_MC19_MISC 0x0000044F\r
1277#define MSR_NEHALEM_MC20_MISC 0x00000453\r
1278#define MSR_NEHALEM_MC21_MISC 0x00000457\r
1279/// @}\r
1280\r
1281\r
1282/**\r
1283 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
1284\r
1285 @param ECX MSR_NEHALEM_MCi_CTL\r
1286 @param EAX Lower 32-bits of MSR value.\r
1287 @param EDX Upper 32-bits of MSR value.\r
1288\r
1289 <b>Example usage</b>\r
1290 @code\r
1291 UINT64 Msr;\r
1292\r
1293 Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_CTL);\r
1294 AsmWriteMsr64 (MSR_NEHALEM_MC3_CTL, Msr);\r
1295 @endcode\r
1296 @{\r
1297**/\r
1298#define MSR_NEHALEM_MC3_CTL 0x0000040C\r
1299#define MSR_NEHALEM_MC4_CTL 0x00000410\r
1300#define MSR_NEHALEM_MC5_CTL 0x00000414\r
1301#define MSR_NEHALEM_MC6_CTL 0x00000418\r
1302#define MSR_NEHALEM_MC7_CTL 0x0000041C\r
1303#define MSR_NEHALEM_MC8_CTL 0x00000420\r
1304#define MSR_NEHALEM_MC9_CTL 0x00000424\r
1305#define MSR_NEHALEM_MC10_CTL 0x00000428\r
1306#define MSR_NEHALEM_MC11_CTL 0x0000042C\r
1307#define MSR_NEHALEM_MC12_CTL 0x00000430\r
1308#define MSR_NEHALEM_MC13_CTL 0x00000434\r
1309#define MSR_NEHALEM_MC14_CTL 0x00000438\r
1310#define MSR_NEHALEM_MC15_CTL 0x0000043C\r
1311#define MSR_NEHALEM_MC16_CTL 0x00000440\r
1312#define MSR_NEHALEM_MC17_CTL 0x00000444\r
1313#define MSR_NEHALEM_MC18_CTL 0x00000448\r
1314#define MSR_NEHALEM_MC19_CTL 0x0000044C\r
1315#define MSR_NEHALEM_MC20_CTL 0x00000450\r
1316#define MSR_NEHALEM_MC21_CTL 0x00000454\r
1317/// @}\r
1318\r
1319\r
1320/**\r
1321 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS," and Chapter 16.\r
1322\r
1323 @param ECX MSR_NEHALEM_MCi_STATUS (0x0000040D)\r
1324 @param EAX Lower 32-bits of MSR value.\r
1325 @param EDX Upper 32-bits of MSR value.\r
1326\r
1327 <b>Example usage</b>\r
1328 @code\r
1329 UINT64 Msr;\r
1330\r
1331 Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_STATUS);\r
1332 AsmWriteMsr64 (MSR_NEHALEM_MC3_STATUS, Msr);\r
1333 @endcode\r
1334 @{\r
1335**/\r
1336#define MSR_NEHALEM_MC3_STATUS 0x0000040D\r
1337#define MSR_NEHALEM_MC4_STATUS 0x00000411\r
1338#define MSR_NEHALEM_MC5_STATUS 0x00000415\r
1339#define MSR_NEHALEM_MC6_STATUS 0x00000419\r
1340#define MSR_NEHALEM_MC7_STATUS 0x0000041D\r
1341#define MSR_NEHALEM_MC8_STATUS 0x00000421\r
1342#define MSR_NEHALEM_MC9_STATUS 0x00000425\r
1343#define MSR_NEHALEM_MC10_STATUS 0x00000429\r
1344#define MSR_NEHALEM_MC11_STATUS 0x0000042D\r
1345#define MSR_NEHALEM_MC12_STATUS 0x00000431\r
1346#define MSR_NEHALEM_MC13_STATUS 0x00000435\r
1347#define MSR_NEHALEM_MC14_STATUS 0x00000439\r
1348#define MSR_NEHALEM_MC15_STATUS 0x0000043D\r
1349#define MSR_NEHALEM_MC16_STATUS 0x00000441\r
1350#define MSR_NEHALEM_MC17_STATUS 0x00000445\r
1351#define MSR_NEHALEM_MC18_STATUS 0x00000449\r
1352#define MSR_NEHALEM_MC19_STATUS 0x0000044D\r
1353#define MSR_NEHALEM_MC20_STATUS 0x00000451\r
1354#define MSR_NEHALEM_MC21_STATUS 0x00000455\r
1355/// @}\r
1356\r
1357\r
1358/**\r
1359 Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs."\r
1360\r
1361 The MSR_MC3_ADDR register is either not implemented or contains no address\r
1362 if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not\r
1363 implemented in the processor, all reads and writes to this MSR will cause a\r
1364 general-protection exception.\r
1365\r
1366 The MSR_MC4_ADDR register is either not implemented or contains no address\r
1367 if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not\r
1368 implemented in the processor, all reads and writes to this MSR will cause a\r
1369 general-protection exception.\r
1370\r
1371 @param ECX MSR_NEHALEM_MC3_ADDR (0x0000040E)\r
1372 @param EAX Lower 32-bits of MSR value.\r
1373 @param EDX Upper 32-bits of MSR value.\r
1374\r
1375 <b>Example usage</b>\r
1376 @code\r
1377 UINT64 Msr;\r
1378\r
1379 Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_ADDR);\r
1380 AsmWriteMsr64 (MSR_NEHALEM_MC3_ADDR, Msr);\r
1381 @endcode\r
1382 @{\r
1383**/\r
1384#define MSR_NEHALEM_MC3_ADDR 0x0000040E\r
1385#define MSR_NEHALEM_MC4_ADDR 0x00000412\r
1386#define MSR_NEHALEM_MC5_ADDR 0x00000416\r
1387#define MSR_NEHALEM_MC6_ADDR 0x0000041A\r
1388#define MSR_NEHALEM_MC7_ADDR 0x0000041E\r
1389#define MSR_NEHALEM_MC8_ADDR 0x00000422\r
1390#define MSR_NEHALEM_MC9_ADDR 0x00000426\r
1391#define MSR_NEHALEM_MC10_ADDR 0x0000042A\r
1392#define MSR_NEHALEM_MC11_ADDR 0x0000042E\r
1393#define MSR_NEHALEM_MC12_ADDR 0x00000432\r
1394#define MSR_NEHALEM_MC13_ADDR 0x00000436\r
1395#define MSR_NEHALEM_MC14_ADDR 0x0000043A\r
1396#define MSR_NEHALEM_MC15_ADDR 0x0000043E\r
1397#define MSR_NEHALEM_MC16_ADDR 0x00000442\r
1398#define MSR_NEHALEM_MC17_ADDR 0x00000446\r
1399#define MSR_NEHALEM_MC18_ADDR 0x0000044A\r
1400#define MSR_NEHALEM_MC19_ADDR 0x0000044E\r
1401#define MSR_NEHALEM_MC20_ADDR 0x00000452\r
1402#define MSR_NEHALEM_MC21_ADDR 0x00000456\r
1403/// @}\r
1404\r
1405\r
1406/**\r
1407 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r
1408 branch record registers on the last branch record stack. This part of the\r
1409 stack contains pointers to the source instruction for one of the last\r
1410 sixteen branches, exceptions, or interrupts taken by the processor. See\r
1411 also: - Last Branch Record Stack TOS at 1C9H - Section 17.6.1, "LBR\r
1412 Stack.".\r
1413\r
1414 @param ECX MSR_NEHALEM_LASTBRANCH_n_FROM_IP\r
1415 @param EAX Lower 32-bits of MSR value.\r
1416 @param EDX Upper 32-bits of MSR value.\r
1417\r
1418 <b>Example usage</b>\r
1419 @code\r
1420 UINT64 Msr;\r
1421\r
1422 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);\r
1423 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);\r
1424 @endcode\r
1425 @{\r
1426**/\r
1427#define MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680\r
1428#define MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681\r
1429#define MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682\r
1430#define MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683\r
1431#define MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684\r
1432#define MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685\r
1433#define MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686\r
1434#define MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687\r
1435#define MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688\r
1436#define MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689\r
1437#define MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A\r
1438#define MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B\r
1439#define MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C\r
1440#define MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D\r
1441#define MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E\r
1442#define MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F\r
1443/// @}\r
1444\r
1445\r
1446/**\r
1447 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch\r
1448 record registers on the last branch record stack. This part of the stack\r
1449 contains pointers to the destination instruction for one of the last sixteen\r
1450 branches, exceptions, or interrupts taken by the processor.\r
1451\r
1452 @param ECX MSR_NEHALEM_LASTBRANCH_n_TO_IP\r
1453 @param EAX Lower 32-bits of MSR value.\r
1454 @param EDX Upper 32-bits of MSR value.\r
1455\r
1456 <b>Example usage</b>\r
1457 @code\r
1458 UINT64 Msr;\r
1459\r
1460 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);\r
1461 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);\r
1462 @endcode\r
1463 @{\r
1464**/\r
1465#define MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0\r
1466#define MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1\r
1467#define MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2\r
1468#define MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3\r
1469#define MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4\r
1470#define MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5\r
1471#define MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6\r
1472#define MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7\r
1473#define MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8\r
1474#define MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9\r
1475#define MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA\r
1476#define MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB\r
1477#define MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC\r
1478#define MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD\r
1479#define MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE\r
1480#define MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF\r
1481/// @}\r
1482\r
1483\r
1484/**\r
1485 Package.\r
1486\r
1487 @param ECX MSR_NEHALEM_GQ_SNOOP_MESF (0x00000301)\r
1488 @param EAX Lower 32-bits of MSR value.\r
1489 Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.\r
1490 @param EDX Upper 32-bits of MSR value.\r
1491 Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.\r
1492\r
1493 <b>Example usage</b>\r
1494 @code\r
1495 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER Msr;\r
1496\r
1497 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF);\r
1498 AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64);\r
1499 @endcode\r
1500**/\r
1501#define MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301\r
1502\r
1503/**\r
1504 MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF\r
1505**/\r
1506typedef union {\r
1507 ///\r
1508 /// Individual bit fields\r
1509 ///\r
1510 struct {\r
1511 ///\r
1512 /// [Bit 0] From M to S (R/W).\r
1513 ///\r
1514 UINT32 FromMtoS:1;\r
1515 ///\r
1516 /// [Bit 1] From E to S (R/W).\r
1517 ///\r
1518 UINT32 FromEtoS:1;\r
1519 ///\r
1520 /// [Bit 2] From S to S (R/W).\r
1521 ///\r
1522 UINT32 FromStoS:1;\r
1523 ///\r
1524 /// [Bit 3] From F to S (R/W).\r
1525 ///\r
1526 UINT32 FromFtoS:1;\r
1527 ///\r
1528 /// [Bit 4] From M to I (R/W).\r
1529 ///\r
1530 UINT32 FromMtoI:1;\r
1531 ///\r
1532 /// [Bit 5] From E to I (R/W).\r
1533 ///\r
1534 UINT32 FromEtoI:1;\r
1535 ///\r
1536 /// [Bit 6] From S to I (R/W).\r
1537 ///\r
1538 UINT32 FromStoI:1;\r
1539 ///\r
1540 /// [Bit 7] From F to I (R/W).\r
1541 ///\r
1542 UINT32 FromFtoI:1;\r
1543 UINT32 Reserved1:24;\r
1544 UINT32 Reserved2:32;\r
1545 } Bits;\r
1546 ///\r
1547 /// All bit fields as a 32-bit value\r
1548 ///\r
1549 UINT32 Uint32;\r
1550 ///\r
1551 /// All bit fields as a 64-bit value\r
1552 ///\r
1553 UINT64 Uint64;\r
1554} MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER;\r
1555\r
1556\r
1557/**\r
1558 Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management\r
1559 Facility.".\r
1560\r
1561 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)\r
1562 @param EAX Lower 32-bits of MSR value.\r
1563 @param EDX Upper 32-bits of MSR value.\r
1564\r
1565 <b>Example usage</b>\r
1566 @code\r
1567 UINT64 Msr;\r
1568\r
1569 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL);\r
1570 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr);\r
1571 @endcode\r
1572**/\r
1573#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391\r
1574\r
1575\r
1576/**\r
1577 Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management\r
1578 Facility.".\r
1579\r
1580 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)\r
1581 @param EAX Lower 32-bits of MSR value.\r
1582 @param EDX Upper 32-bits of MSR value.\r
1583\r
1584 <b>Example usage</b>\r
1585 @code\r
1586 UINT64 Msr;\r
1587\r
1588 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS);\r
1589 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr);\r
1590 @endcode\r
1591**/\r
1592#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392\r
1593\r
1594\r
1595/**\r
1596 Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management\r
1597 Facility.".\r
1598\r
1599 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)\r
1600 @param EAX Lower 32-bits of MSR value.\r
1601 @param EDX Upper 32-bits of MSR value.\r
1602\r
1603 <b>Example usage</b>\r
1604 @code\r
1605 UINT64 Msr;\r
1606\r
1607 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL);\r
1608 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr);\r
1609 @endcode\r
1610**/\r
1611#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393\r
1612\r
1613\r
1614/**\r
1615 Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management\r
1616 Facility.".\r
1617\r
1618 @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)\r
1619 @param EAX Lower 32-bits of MSR value.\r
1620 @param EDX Upper 32-bits of MSR value.\r
1621\r
1622 <b>Example usage</b>\r
1623 @code\r
1624 UINT64 Msr;\r
1625\r
1626 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0);\r
1627 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr);\r
1628 @endcode\r
1629**/\r
1630#define MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394\r
1631\r
1632\r
1633/**\r
1634 Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management\r
1635 Facility.".\r
1636\r
1637 @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)\r
1638 @param EAX Lower 32-bits of MSR value.\r
1639 @param EDX Upper 32-bits of MSR value.\r
1640\r
1641 <b>Example usage</b>\r
1642 @code\r
1643 UINT64 Msr;\r
1644\r
1645 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL);\r
1646 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr);\r
1647 @endcode\r
1648**/\r
1649#define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395\r
1650\r
1651\r
1652/**\r
1653 Package. See Section 18.7.2.3, "Uncore Address/Opcode Match MSR.".\r
1654\r
1655 @param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)\r
1656 @param EAX Lower 32-bits of MSR value.\r
1657 @param EDX Upper 32-bits of MSR value.\r
1658\r
1659 <b>Example usage</b>\r
1660 @code\r
1661 UINT64 Msr;\r
1662\r
1663 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH);\r
1664 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr);\r
1665 @endcode\r
1666**/\r
1667#define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396\r
1668\r
1669\r
1670/**\r
1671 Package. See Section 18.7.2.2, "Uncore Performance Event Configuration\r
1672 Facility.".\r
1673\r
1674 @param ECX MSR_NEHALEM_UNCORE_PMCi\r
1675 @param EAX Lower 32-bits of MSR value.\r
1676 @param EDX Upper 32-bits of MSR value.\r
1677\r
1678 <b>Example usage</b>\r
1679 @code\r
1680 UINT64 Msr;\r
1681\r
1682 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);\r
1683 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);\r
1684 @endcode\r
1685 @{\r
1686**/\r
1687#define MSR_NEHALEM_UNCORE_PMC0 0x000003B0\r
1688#define MSR_NEHALEM_UNCORE_PMC1 0x000003B1\r
1689#define MSR_NEHALEM_UNCORE_PMC2 0x000003B2\r
1690#define MSR_NEHALEM_UNCORE_PMC3 0x000003B3\r
1691#define MSR_NEHALEM_UNCORE_PMC4 0x000003B4\r
1692#define MSR_NEHALEM_UNCORE_PMC5 0x000003B5\r
1693#define MSR_NEHALEM_UNCORE_PMC6 0x000003B6\r
1694#define MSR_NEHALEM_UNCORE_PMC7 0x000003B7\r
1695/// @}\r
1696\r
1697/**\r
1698 Package. See Section 18.7.2.2, "Uncore Performance Event Configuration\r
1699 Facility.".\r
1700\r
1701 @param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi\r
1702 @param EAX Lower 32-bits of MSR value.\r
1703 @param EDX Upper 32-bits of MSR value.\r
1704\r
1705 <b>Example usage</b>\r
1706 @code\r
1707 UINT64 Msr;\r
1708\r
1709 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);\r
1710 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);\r
1711 @endcode\r
1712 @{\r
1713**/\r
1714#define MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0\r
1715#define MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1\r
1716#define MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2\r
1717#define MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3\r
1718#define MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4\r
1719#define MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5\r
1720#define MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6\r
1721#define MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7\r
1722/// @}\r
1723\r
1724\r
1725/**\r
1726 Package. Uncore W-box perfmon fixed counter.\r
1727\r
1728 @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR (0x00000394)\r
1729 @param EAX Lower 32-bits of MSR value.\r
1730 @param EDX Upper 32-bits of MSR value.\r
1731\r
1732 <b>Example usage</b>\r
1733 @code\r
1734 UINT64 Msr;\r
1735\r
1736 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR);\r
1737 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr);\r
1738 @endcode\r
1739**/\r
1740#define MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394\r
1741\r
1742\r
1743/**\r
1744 Package. Uncore U-box perfmon fixed counter control MSR.\r
1745\r
1746 @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR_CTL (0x00000395)\r
1747 @param EAX Lower 32-bits of MSR value.\r
1748 @param EDX Upper 32-bits of MSR value.\r
1749\r
1750 <b>Example usage</b>\r
1751 @code\r
1752 UINT64 Msr;\r
1753\r
1754 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL);\r
1755 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr);\r
1756 @endcode\r
1757**/\r
1758#define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395\r
1759\r
1760\r
1761/**\r
1762 Package. Uncore U-box perfmon global control MSR.\r
1763\r
1764 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_CTRL (0x00000C00)\r
1765 @param EAX Lower 32-bits of MSR value.\r
1766 @param EDX Upper 32-bits of MSR value.\r
1767\r
1768 <b>Example usage</b>\r
1769 @code\r
1770 UINT64 Msr;\r
1771\r
1772 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL);\r
1773 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr);\r
1774 @endcode\r
1775**/\r
1776#define MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00\r
1777\r
1778\r
1779/**\r
1780 Package. Uncore U-box perfmon global status MSR.\r
1781\r
1782 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_STATUS (0x00000C01)\r
1783 @param EAX Lower 32-bits of MSR value.\r
1784 @param EDX Upper 32-bits of MSR value.\r
1785\r
1786 <b>Example usage</b>\r
1787 @code\r
1788 UINT64 Msr;\r
1789\r
1790 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS);\r
1791 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr);\r
1792 @endcode\r
1793**/\r
1794#define MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01\r
1795\r
1796\r
1797/**\r
1798 Package. Uncore U-box perfmon global overflow control MSR.\r
1799\r
1800 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL (0x00000C02)\r
1801 @param EAX Lower 32-bits of MSR value.\r
1802 @param EDX Upper 32-bits of MSR value.\r
1803\r
1804 <b>Example usage</b>\r
1805 @code\r
1806 UINT64 Msr;\r
1807\r
1808 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL);\r
1809 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr);\r
1810 @endcode\r
1811**/\r
1812#define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02\r
1813\r
1814\r
1815/**\r
1816 Package. Uncore U-box perfmon event select MSR.\r
1817\r
1818 @param ECX MSR_NEHALEM_U_PMON_EVNT_SEL (0x00000C10)\r
1819 @param EAX Lower 32-bits of MSR value.\r
1820 @param EDX Upper 32-bits of MSR value.\r
1821\r
1822 <b>Example usage</b>\r
1823 @code\r
1824 UINT64 Msr;\r
1825\r
1826 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL);\r
1827 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr);\r
1828 @endcode\r
1829**/\r
1830#define MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10\r
1831\r
1832\r
1833/**\r
1834 Package. Uncore U-box perfmon counter MSR.\r
1835\r
1836 @param ECX MSR_NEHALEM_U_PMON_CTR (0x00000C11)\r
1837 @param EAX Lower 32-bits of MSR value.\r
1838 @param EDX Upper 32-bits of MSR value.\r
1839\r
1840 <b>Example usage</b>\r
1841 @code\r
1842 UINT64 Msr;\r
1843\r
1844 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR);\r
1845 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr);\r
1846 @endcode\r
1847**/\r
1848#define MSR_NEHALEM_U_PMON_CTR 0x00000C11\r
1849\r
1850\r
1851/**\r
1852 Package. Uncore B-box 0 perfmon local box control MSR.\r
1853\r
1854 @param ECX MSR_NEHALEM_B0_PMON_BOX_CTRL (0x00000C20)\r
1855 @param EAX Lower 32-bits of MSR value.\r
1856 @param EDX Upper 32-bits of MSR value.\r
1857\r
1858 <b>Example usage</b>\r
1859 @code\r
1860 UINT64 Msr;\r
1861\r
1862 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL);\r
1863 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr);\r
1864 @endcode\r
1865**/\r
1866#define MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20\r
1867\r
1868\r
1869/**\r
1870 Package. Uncore B-box 0 perfmon local box status MSR.\r
1871\r
1872 @param ECX MSR_NEHALEM_B0_PMON_BOX_STATUS (0x00000C21)\r
1873 @param EAX Lower 32-bits of MSR value.\r
1874 @param EDX Upper 32-bits of MSR value.\r
1875\r
1876 <b>Example usage</b>\r
1877 @code\r
1878 UINT64 Msr;\r
1879\r
1880 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS);\r
1881 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr);\r
1882 @endcode\r
1883**/\r
1884#define MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21\r
1885\r
1886\r
1887/**\r
1888 Package. Uncore B-box 0 perfmon local box overflow control MSR.\r
1889\r
1890 @param ECX MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL (0x00000C22)\r
1891 @param EAX Lower 32-bits of MSR value.\r
1892 @param EDX Upper 32-bits of MSR value.\r
1893\r
1894 <b>Example usage</b>\r
1895 @code\r
1896 UINT64 Msr;\r
1897\r
1898 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL);\r
1899 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr);\r
1900 @endcode\r
1901**/\r
1902#define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22\r
1903\r
1904\r
1905/**\r
1906 Package. Uncore B-box 0 perfmon event select MSR.\r
1907\r
1908 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL0 (0x00000C30)\r
1909 @param EAX Lower 32-bits of MSR value.\r
1910 @param EDX Upper 32-bits of MSR value.\r
1911\r
1912 <b>Example usage</b>\r
1913 @code\r
1914 UINT64 Msr;\r
1915\r
1916 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0);\r
1917 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr);\r
1918 @endcode\r
1919**/\r
1920#define MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30\r
1921\r
1922\r
1923/**\r
1924 Package. Uncore B-box 0 perfmon counter MSR.\r
1925\r
1926 @param ECX MSR_NEHALEM_B0_PMON_CTR0 (0x00000C31)\r
1927 @param EAX Lower 32-bits of MSR value.\r
1928 @param EDX Upper 32-bits of MSR value.\r
1929\r
1930 <b>Example usage</b>\r
1931 @code\r
1932 UINT64 Msr;\r
1933\r
1934 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0);\r
1935 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr);\r
1936 @endcode\r
1937**/\r
1938#define MSR_NEHALEM_B0_PMON_CTR0 0x00000C31\r
1939\r
1940\r
1941/**\r
1942 Package. Uncore B-box 0 perfmon event select MSR.\r
1943\r
1944 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL1 (0x00000C32)\r
1945 @param EAX Lower 32-bits of MSR value.\r
1946 @param EDX Upper 32-bits of MSR value.\r
1947\r
1948 <b>Example usage</b>\r
1949 @code\r
1950 UINT64 Msr;\r
1951\r
1952 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1);\r
1953 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr);\r
1954 @endcode\r
1955**/\r
1956#define MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32\r
1957\r
1958\r
1959/**\r
1960 Package. Uncore B-box 0 perfmon counter MSR.\r
1961\r
1962 @param ECX MSR_NEHALEM_B0_PMON_CTR1 (0x00000C33)\r
1963 @param EAX Lower 32-bits of MSR value.\r
1964 @param EDX Upper 32-bits of MSR value.\r
1965\r
1966 <b>Example usage</b>\r
1967 @code\r
1968 UINT64 Msr;\r
1969\r
1970 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1);\r
1971 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr);\r
1972 @endcode\r
1973**/\r
1974#define MSR_NEHALEM_B0_PMON_CTR1 0x00000C33\r
1975\r
1976\r
1977/**\r
1978 Package. Uncore B-box 0 perfmon event select MSR.\r
1979\r
1980 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL2 (0x00000C34)\r
1981 @param EAX Lower 32-bits of MSR value.\r
1982 @param EDX Upper 32-bits of MSR value.\r
1983\r
1984 <b>Example usage</b>\r
1985 @code\r
1986 UINT64 Msr;\r
1987\r
1988 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2);\r
1989 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr);\r
1990 @endcode\r
1991**/\r
1992#define MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34\r
1993\r
1994\r
1995/**\r
1996 Package. Uncore B-box 0 perfmon counter MSR.\r
1997\r
1998 @param ECX MSR_NEHALEM_B0_PMON_CTR2 (0x00000C35)\r
1999 @param EAX Lower 32-bits of MSR value.\r
2000 @param EDX Upper 32-bits of MSR value.\r
2001\r
2002 <b>Example usage</b>\r
2003 @code\r
2004 UINT64 Msr;\r
2005\r
2006 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2);\r
2007 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr);\r
2008 @endcode\r
2009**/\r
2010#define MSR_NEHALEM_B0_PMON_CTR2 0x00000C35\r
2011\r
2012\r
2013/**\r
2014 Package. Uncore B-box 0 perfmon event select MSR.\r
2015\r
2016 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL3 (0x00000C36)\r
2017 @param EAX Lower 32-bits of MSR value.\r
2018 @param EDX Upper 32-bits of MSR value.\r
2019\r
2020 <b>Example usage</b>\r
2021 @code\r
2022 UINT64 Msr;\r
2023\r
2024 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3);\r
2025 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr);\r
2026 @endcode\r
2027**/\r
2028#define MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36\r
2029\r
2030\r
2031/**\r
2032 Package. Uncore B-box 0 perfmon counter MSR.\r
2033\r
2034 @param ECX MSR_NEHALEM_B0_PMON_CTR3 (0x00000C37)\r
2035 @param EAX Lower 32-bits of MSR value.\r
2036 @param EDX Upper 32-bits of MSR value.\r
2037\r
2038 <b>Example usage</b>\r
2039 @code\r
2040 UINT64 Msr;\r
2041\r
2042 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3);\r
2043 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr);\r
2044 @endcode\r
2045**/\r
2046#define MSR_NEHALEM_B0_PMON_CTR3 0x00000C37\r
2047\r
2048\r
2049/**\r
2050 Package. Uncore S-box 0 perfmon local box control MSR.\r
2051\r
2052 @param ECX MSR_NEHALEM_S0_PMON_BOX_CTRL (0x00000C40)\r
2053 @param EAX Lower 32-bits of MSR value.\r
2054 @param EDX Upper 32-bits of MSR value.\r
2055\r
2056 <b>Example usage</b>\r
2057 @code\r
2058 UINT64 Msr;\r
2059\r
2060 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL);\r
2061 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr);\r
2062 @endcode\r
2063**/\r
2064#define MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40\r
2065\r
2066\r
2067/**\r
2068 Package. Uncore S-box 0 perfmon local box status MSR.\r
2069\r
2070 @param ECX MSR_NEHALEM_S0_PMON_BOX_STATUS (0x00000C41)\r
2071 @param EAX Lower 32-bits of MSR value.\r
2072 @param EDX Upper 32-bits of MSR value.\r
2073\r
2074 <b>Example usage</b>\r
2075 @code\r
2076 UINT64 Msr;\r
2077\r
2078 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS);\r
2079 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr);\r
2080 @endcode\r
2081**/\r
2082#define MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41\r
2083\r
2084\r
2085/**\r
2086 Package. Uncore S-box 0 perfmon local box overflow control MSR.\r
2087\r
2088 @param ECX MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL (0x00000C42)\r
2089 @param EAX Lower 32-bits of MSR value.\r
2090 @param EDX Upper 32-bits of MSR value.\r
2091\r
2092 <b>Example usage</b>\r
2093 @code\r
2094 UINT64 Msr;\r
2095\r
2096 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL);\r
2097 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr);\r
2098 @endcode\r
2099**/\r
2100#define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42\r
2101\r
2102\r
2103/**\r
2104 Package. Uncore S-box 0 perfmon event select MSR.\r
2105\r
2106 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL0 (0x00000C50)\r
2107 @param EAX Lower 32-bits of MSR value.\r
2108 @param EDX Upper 32-bits of MSR value.\r
2109\r
2110 <b>Example usage</b>\r
2111 @code\r
2112 UINT64 Msr;\r
2113\r
2114 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0);\r
2115 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr);\r
2116 @endcode\r
2117**/\r
2118#define MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50\r
2119\r
2120\r
2121/**\r
2122 Package. Uncore S-box 0 perfmon counter MSR.\r
2123\r
2124 @param ECX MSR_NEHALEM_S0_PMON_CTR0 (0x00000C51)\r
2125 @param EAX Lower 32-bits of MSR value.\r
2126 @param EDX Upper 32-bits of MSR value.\r
2127\r
2128 <b>Example usage</b>\r
2129 @code\r
2130 UINT64 Msr;\r
2131\r
2132 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0);\r
2133 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr);\r
2134 @endcode\r
2135**/\r
2136#define MSR_NEHALEM_S0_PMON_CTR0 0x00000C51\r
2137\r
2138\r
2139/**\r
2140 Package. Uncore S-box 0 perfmon event select MSR.\r
2141\r
2142 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL1 (0x00000C52)\r
2143 @param EAX Lower 32-bits of MSR value.\r
2144 @param EDX Upper 32-bits of MSR value.\r
2145\r
2146 <b>Example usage</b>\r
2147 @code\r
2148 UINT64 Msr;\r
2149\r
2150 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1);\r
2151 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr);\r
2152 @endcode\r
2153**/\r
2154#define MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52\r
2155\r
2156\r
2157/**\r
2158 Package. Uncore S-box 0 perfmon counter MSR.\r
2159\r
2160 @param ECX MSR_NEHALEM_S0_PMON_CTR1 (0x00000C53)\r
2161 @param EAX Lower 32-bits of MSR value.\r
2162 @param EDX Upper 32-bits of MSR value.\r
2163\r
2164 <b>Example usage</b>\r
2165 @code\r
2166 UINT64 Msr;\r
2167\r
2168 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1);\r
2169 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr);\r
2170 @endcode\r
2171**/\r
2172#define MSR_NEHALEM_S0_PMON_CTR1 0x00000C53\r
2173\r
2174\r
2175/**\r
2176 Package. Uncore S-box 0 perfmon event select MSR.\r
2177\r
2178 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL2 (0x00000C54)\r
2179 @param EAX Lower 32-bits of MSR value.\r
2180 @param EDX Upper 32-bits of MSR value.\r
2181\r
2182 <b>Example usage</b>\r
2183 @code\r
2184 UINT64 Msr;\r
2185\r
2186 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2);\r
2187 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr);\r
2188 @endcode\r
2189**/\r
2190#define MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54\r
2191\r
2192\r
2193/**\r
2194 Package. Uncore S-box 0 perfmon counter MSR.\r
2195\r
2196 @param ECX MSR_NEHALEM_S0_PMON_CTR2 (0x00000C55)\r
2197 @param EAX Lower 32-bits of MSR value.\r
2198 @param EDX Upper 32-bits of MSR value.\r
2199\r
2200 <b>Example usage</b>\r
2201 @code\r
2202 UINT64 Msr;\r
2203\r
2204 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2);\r
2205 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr);\r
2206 @endcode\r
2207**/\r
2208#define MSR_NEHALEM_S0_PMON_CTR2 0x00000C55\r
2209\r
2210\r
2211/**\r
2212 Package. Uncore S-box 0 perfmon event select MSR.\r
2213\r
2214 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL3 (0x00000C56)\r
2215 @param EAX Lower 32-bits of MSR value.\r
2216 @param EDX Upper 32-bits of MSR value.\r
2217\r
2218 <b>Example usage</b>\r
2219 @code\r
2220 UINT64 Msr;\r
2221\r
2222 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3);\r
2223 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr);\r
2224 @endcode\r
2225**/\r
2226#define MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56\r
2227\r
2228\r
2229/**\r
2230 Package. Uncore S-box 0 perfmon counter MSR.\r
2231\r
2232 @param ECX MSR_NEHALEM_S0_PMON_CTR3 (0x00000C57)\r
2233 @param EAX Lower 32-bits of MSR value.\r
2234 @param EDX Upper 32-bits of MSR value.\r
2235\r
2236 <b>Example usage</b>\r
2237 @code\r
2238 UINT64 Msr;\r
2239\r
2240 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3);\r
2241 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr);\r
2242 @endcode\r
2243**/\r
2244#define MSR_NEHALEM_S0_PMON_CTR3 0x00000C57\r
2245\r
2246\r
2247/**\r
2248 Package. Uncore B-box 1 perfmon local box control MSR.\r
2249\r
2250 @param ECX MSR_NEHALEM_B1_PMON_BOX_CTRL (0x00000C60)\r
2251 @param EAX Lower 32-bits of MSR value.\r
2252 @param EDX Upper 32-bits of MSR value.\r
2253\r
2254 <b>Example usage</b>\r
2255 @code\r
2256 UINT64 Msr;\r
2257\r
2258 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL);\r
2259 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr);\r
2260 @endcode\r
2261**/\r
2262#define MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60\r
2263\r
2264\r
2265/**\r
2266 Package. Uncore B-box 1 perfmon local box status MSR.\r
2267\r
2268 @param ECX MSR_NEHALEM_B1_PMON_BOX_STATUS (0x00000C61)\r
2269 @param EAX Lower 32-bits of MSR value.\r
2270 @param EDX Upper 32-bits of MSR value.\r
2271\r
2272 <b>Example usage</b>\r
2273 @code\r
2274 UINT64 Msr;\r
2275\r
2276 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS);\r
2277 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr);\r
2278 @endcode\r
2279**/\r
2280#define MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61\r
2281\r
2282\r
2283/**\r
2284 Package. Uncore B-box 1 perfmon local box overflow control MSR.\r
2285\r
2286 @param ECX MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL (0x00000C62)\r
2287 @param EAX Lower 32-bits of MSR value.\r
2288 @param EDX Upper 32-bits of MSR value.\r
2289\r
2290 <b>Example usage</b>\r
2291 @code\r
2292 UINT64 Msr;\r
2293\r
2294 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL);\r
2295 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr);\r
2296 @endcode\r
2297**/\r
2298#define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62\r
2299\r
2300\r
2301/**\r
2302 Package. Uncore B-box 1 perfmon event select MSR.\r
2303\r
2304 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL0 (0x00000C70)\r
2305 @param EAX Lower 32-bits of MSR value.\r
2306 @param EDX Upper 32-bits of MSR value.\r
2307\r
2308 <b>Example usage</b>\r
2309 @code\r
2310 UINT64 Msr;\r
2311\r
2312 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0);\r
2313 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr);\r
2314 @endcode\r
2315**/\r
2316#define MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70\r
2317\r
2318\r
2319/**\r
2320 Package. Uncore B-box 1 perfmon counter MSR.\r
2321\r
2322 @param ECX MSR_NEHALEM_B1_PMON_CTR0 (0x00000C71)\r
2323 @param EAX Lower 32-bits of MSR value.\r
2324 @param EDX Upper 32-bits of MSR value.\r
2325\r
2326 <b>Example usage</b>\r
2327 @code\r
2328 UINT64 Msr;\r
2329\r
2330 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0);\r
2331 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr);\r
2332 @endcode\r
2333**/\r
2334#define MSR_NEHALEM_B1_PMON_CTR0 0x00000C71\r
2335\r
2336\r
2337/**\r
2338 Package. Uncore B-box 1 perfmon event select MSR.\r
2339\r
2340 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL1 (0x00000C72)\r
2341 @param EAX Lower 32-bits of MSR value.\r
2342 @param EDX Upper 32-bits of MSR value.\r
2343\r
2344 <b>Example usage</b>\r
2345 @code\r
2346 UINT64 Msr;\r
2347\r
2348 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1);\r
2349 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr);\r
2350 @endcode\r
2351**/\r
2352#define MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72\r
2353\r
2354\r
2355/**\r
2356 Package. Uncore B-box 1 perfmon counter MSR.\r
2357\r
2358 @param ECX MSR_NEHALEM_B1_PMON_CTR1 (0x00000C73)\r
2359 @param EAX Lower 32-bits of MSR value.\r
2360 @param EDX Upper 32-bits of MSR value.\r
2361\r
2362 <b>Example usage</b>\r
2363 @code\r
2364 UINT64 Msr;\r
2365\r
2366 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1);\r
2367 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr);\r
2368 @endcode\r
2369**/\r
2370#define MSR_NEHALEM_B1_PMON_CTR1 0x00000C73\r
2371\r
2372\r
2373/**\r
2374 Package. Uncore B-box 1 perfmon event select MSR.\r
2375\r
2376 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL2 (0x00000C74)\r
2377 @param EAX Lower 32-bits of MSR value.\r
2378 @param EDX Upper 32-bits of MSR value.\r
2379\r
2380 <b>Example usage</b>\r
2381 @code\r
2382 UINT64 Msr;\r
2383\r
2384 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2);\r
2385 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr);\r
2386 @endcode\r
2387**/\r
2388#define MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74\r
2389\r
2390\r
2391/**\r
2392 Package. Uncore B-box 1 perfmon counter MSR.\r
2393\r
2394 @param ECX MSR_NEHALEM_B1_PMON_CTR2 (0x00000C75)\r
2395 @param EAX Lower 32-bits of MSR value.\r
2396 @param EDX Upper 32-bits of MSR value.\r
2397\r
2398 <b>Example usage</b>\r
2399 @code\r
2400 UINT64 Msr;\r
2401\r
2402 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2);\r
2403 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr);\r
2404 @endcode\r
2405**/\r
2406#define MSR_NEHALEM_B1_PMON_CTR2 0x00000C75\r
2407\r
2408\r
2409/**\r
2410 Package. Uncore B-box 1vperfmon event select MSR.\r
2411\r
2412 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL3 (0x00000C76)\r
2413 @param EAX Lower 32-bits of MSR value.\r
2414 @param EDX Upper 32-bits of MSR value.\r
2415\r
2416 <b>Example usage</b>\r
2417 @code\r
2418 UINT64 Msr;\r
2419\r
2420 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3);\r
2421 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr);\r
2422 @endcode\r
2423**/\r
2424#define MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76\r
2425\r
2426\r
2427/**\r
2428 Package. Uncore B-box 1 perfmon counter MSR.\r
2429\r
2430 @param ECX MSR_NEHALEM_B1_PMON_CTR3 (0x00000C77)\r
2431 @param EAX Lower 32-bits of MSR value.\r
2432 @param EDX Upper 32-bits of MSR value.\r
2433\r
2434 <b>Example usage</b>\r
2435 @code\r
2436 UINT64 Msr;\r
2437\r
2438 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3);\r
2439 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr);\r
2440 @endcode\r
2441**/\r
2442#define MSR_NEHALEM_B1_PMON_CTR3 0x00000C77\r
2443\r
2444\r
2445/**\r
2446 Package. Uncore W-box perfmon local box control MSR.\r
2447\r
2448 @param ECX MSR_NEHALEM_W_PMON_BOX_CTRL (0x00000C80)\r
2449 @param EAX Lower 32-bits of MSR value.\r
2450 @param EDX Upper 32-bits of MSR value.\r
2451\r
2452 <b>Example usage</b>\r
2453 @code\r
2454 UINT64 Msr;\r
2455\r
2456 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL);\r
2457 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr);\r
2458 @endcode\r
2459**/\r
2460#define MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80\r
2461\r
2462\r
2463/**\r
2464 Package. Uncore W-box perfmon local box status MSR.\r
2465\r
2466 @param ECX MSR_NEHALEM_W_PMON_BOX_STATUS (0x00000C81)\r
2467 @param EAX Lower 32-bits of MSR value.\r
2468 @param EDX Upper 32-bits of MSR value.\r
2469\r
2470 <b>Example usage</b>\r
2471 @code\r
2472 UINT64 Msr;\r
2473\r
2474 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS);\r
2475 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr);\r
2476 @endcode\r
2477**/\r
2478#define MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81\r
2479\r
2480\r
2481/**\r
2482 Package. Uncore W-box perfmon local box overflow control MSR.\r
2483\r
2484 @param ECX MSR_NEHALEM_W_PMON_BOX_OVF_CTRL (0x00000C82)\r
2485 @param EAX Lower 32-bits of MSR value.\r
2486 @param EDX Upper 32-bits of MSR value.\r
2487\r
2488 <b>Example usage</b>\r
2489 @code\r
2490 UINT64 Msr;\r
2491\r
2492 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL);\r
2493 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr);\r
2494 @endcode\r
2495**/\r
2496#define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82\r
2497\r
2498\r
2499/**\r
2500 Package. Uncore W-box perfmon event select MSR.\r
2501\r
2502 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL0 (0x00000C90)\r
2503 @param EAX Lower 32-bits of MSR value.\r
2504 @param EDX Upper 32-bits of MSR value.\r
2505\r
2506 <b>Example usage</b>\r
2507 @code\r
2508 UINT64 Msr;\r
2509\r
2510 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0);\r
2511 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr);\r
2512 @endcode\r
2513**/\r
2514#define MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90\r
2515\r
2516\r
2517/**\r
2518 Package. Uncore W-box perfmon counter MSR.\r
2519\r
2520 @param ECX MSR_NEHALEM_W_PMON_CTR0 (0x00000C91)\r
2521 @param EAX Lower 32-bits of MSR value.\r
2522 @param EDX Upper 32-bits of MSR value.\r
2523\r
2524 <b>Example usage</b>\r
2525 @code\r
2526 UINT64 Msr;\r
2527\r
2528 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0);\r
2529 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr);\r
2530 @endcode\r
2531**/\r
2532#define MSR_NEHALEM_W_PMON_CTR0 0x00000C91\r
2533\r
2534\r
2535/**\r
2536 Package. Uncore W-box perfmon event select MSR.\r
2537\r
2538 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL1 (0x00000C92)\r
2539 @param EAX Lower 32-bits of MSR value.\r
2540 @param EDX Upper 32-bits of MSR value.\r
2541\r
2542 <b>Example usage</b>\r
2543 @code\r
2544 UINT64 Msr;\r
2545\r
2546 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1);\r
2547 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr);\r
2548 @endcode\r
2549**/\r
2550#define MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92\r
2551\r
2552\r
2553/**\r
2554 Package. Uncore W-box perfmon counter MSR.\r
2555\r
2556 @param ECX MSR_NEHALEM_W_PMON_CTR1 (0x00000C93)\r
2557 @param EAX Lower 32-bits of MSR value.\r
2558 @param EDX Upper 32-bits of MSR value.\r
2559\r
2560 <b>Example usage</b>\r
2561 @code\r
2562 UINT64 Msr;\r
2563\r
2564 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1);\r
2565 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr);\r
2566 @endcode\r
2567**/\r
2568#define MSR_NEHALEM_W_PMON_CTR1 0x00000C93\r
2569\r
2570\r
2571/**\r
2572 Package. Uncore W-box perfmon event select MSR.\r
2573\r
2574 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL2 (0x00000C94)\r
2575 @param EAX Lower 32-bits of MSR value.\r
2576 @param EDX Upper 32-bits of MSR value.\r
2577\r
2578 <b>Example usage</b>\r
2579 @code\r
2580 UINT64 Msr;\r
2581\r
2582 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2);\r
2583 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr);\r
2584 @endcode\r
2585**/\r
2586#define MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94\r
2587\r
2588\r
2589/**\r
2590 Package. Uncore W-box perfmon counter MSR.\r
2591\r
2592 @param ECX MSR_NEHALEM_W_PMON_CTR2 (0x00000C95)\r
2593 @param EAX Lower 32-bits of MSR value.\r
2594 @param EDX Upper 32-bits of MSR value.\r
2595\r
2596 <b>Example usage</b>\r
2597 @code\r
2598 UINT64 Msr;\r
2599\r
2600 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2);\r
2601 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr);\r
2602 @endcode\r
2603**/\r
2604#define MSR_NEHALEM_W_PMON_CTR2 0x00000C95\r
2605\r
2606\r
2607/**\r
2608 Package. Uncore W-box perfmon event select MSR.\r
2609\r
2610 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL3 (0x00000C96)\r
2611 @param EAX Lower 32-bits of MSR value.\r
2612 @param EDX Upper 32-bits of MSR value.\r
2613\r
2614 <b>Example usage</b>\r
2615 @code\r
2616 UINT64 Msr;\r
2617\r
2618 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3);\r
2619 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr);\r
2620 @endcode\r
2621**/\r
2622#define MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96\r
2623\r
2624\r
2625/**\r
2626 Package. Uncore W-box perfmon counter MSR.\r
2627\r
2628 @param ECX MSR_NEHALEM_W_PMON_CTR3 (0x00000C97)\r
2629 @param EAX Lower 32-bits of MSR value.\r
2630 @param EDX Upper 32-bits of MSR value.\r
2631\r
2632 <b>Example usage</b>\r
2633 @code\r
2634 UINT64 Msr;\r
2635\r
2636 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3);\r
2637 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr);\r
2638 @endcode\r
2639**/\r
2640#define MSR_NEHALEM_W_PMON_CTR3 0x00000C97\r
2641\r
2642\r
2643/**\r
2644 Package. Uncore M-box 0 perfmon local box control MSR.\r
2645\r
2646 @param ECX MSR_NEHALEM_M0_PMON_BOX_CTRL (0x00000CA0)\r
2647 @param EAX Lower 32-bits of MSR value.\r
2648 @param EDX Upper 32-bits of MSR value.\r
2649\r
2650 <b>Example usage</b>\r
2651 @code\r
2652 UINT64 Msr;\r
2653\r
2654 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL);\r
2655 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr);\r
2656 @endcode\r
2657**/\r
2658#define MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0\r
2659\r
2660\r
2661/**\r
2662 Package. Uncore M-box 0 perfmon local box status MSR.\r
2663\r
2664 @param ECX MSR_NEHALEM_M0_PMON_BOX_STATUS (0x00000CA1)\r
2665 @param EAX Lower 32-bits of MSR value.\r
2666 @param EDX Upper 32-bits of MSR value.\r
2667\r
2668 <b>Example usage</b>\r
2669 @code\r
2670 UINT64 Msr;\r
2671\r
2672 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS);\r
2673 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr);\r
2674 @endcode\r
2675**/\r
2676#define MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1\r
2677\r
2678\r
2679/**\r
2680 Package. Uncore M-box 0 perfmon local box overflow control MSR.\r
2681\r
2682 @param ECX MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL (0x00000CA2)\r
2683 @param EAX Lower 32-bits of MSR value.\r
2684 @param EDX Upper 32-bits of MSR value.\r
2685\r
2686 <b>Example usage</b>\r
2687 @code\r
2688 UINT64 Msr;\r
2689\r
2690 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL);\r
2691 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr);\r
2692 @endcode\r
2693**/\r
2694#define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2\r
2695\r
2696\r
2697/**\r
2698 Package. Uncore M-box 0 perfmon time stamp unit select MSR.\r
2699\r
2700 @param ECX MSR_NEHALEM_M0_PMON_TIMESTAMP (0x00000CA4)\r
2701 @param EAX Lower 32-bits of MSR value.\r
2702 @param EDX Upper 32-bits of MSR value.\r
2703\r
2704 <b>Example usage</b>\r
2705 @code\r
2706 UINT64 Msr;\r
2707\r
2708 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP);\r
2709 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr);\r
2710 @endcode\r
2711**/\r
2712#define MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4\r
2713\r
2714\r
2715/**\r
2716 Package. Uncore M-box 0 perfmon DSP unit select MSR.\r
2717\r
2718 @param ECX MSR_NEHALEM_M0_PMON_DSP (0x00000CA5)\r
2719 @param EAX Lower 32-bits of MSR value.\r
2720 @param EDX Upper 32-bits of MSR value.\r
2721\r
2722 <b>Example usage</b>\r
2723 @code\r
2724 UINT64 Msr;\r
2725\r
2726 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP);\r
2727 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr);\r
2728 @endcode\r
2729**/\r
2730#define MSR_NEHALEM_M0_PMON_DSP 0x00000CA5\r
2731\r
2732\r
2733/**\r
2734 Package. Uncore M-box 0 perfmon ISS unit select MSR.\r
2735\r
2736 @param ECX MSR_NEHALEM_M0_PMON_ISS (0x00000CA6)\r
2737 @param EAX Lower 32-bits of MSR value.\r
2738 @param EDX Upper 32-bits of MSR value.\r
2739\r
2740 <b>Example usage</b>\r
2741 @code\r
2742 UINT64 Msr;\r
2743\r
2744 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS);\r
2745 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr);\r
2746 @endcode\r
2747**/\r
2748#define MSR_NEHALEM_M0_PMON_ISS 0x00000CA6\r
2749\r
2750\r
2751/**\r
2752 Package. Uncore M-box 0 perfmon MAP unit select MSR.\r
2753\r
2754 @param ECX MSR_NEHALEM_M0_PMON_MAP (0x00000CA7)\r
2755 @param EAX Lower 32-bits of MSR value.\r
2756 @param EDX Upper 32-bits of MSR value.\r
2757\r
2758 <b>Example usage</b>\r
2759 @code\r
2760 UINT64 Msr;\r
2761\r
2762 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP);\r
2763 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr);\r
2764 @endcode\r
2765**/\r
2766#define MSR_NEHALEM_M0_PMON_MAP 0x00000CA7\r
2767\r
2768\r
2769/**\r
2770 Package. Uncore M-box 0 perfmon MIC THR select MSR.\r
2771\r
2772 @param ECX MSR_NEHALEM_M0_PMON_MSC_THR (0x00000CA8)\r
2773 @param EAX Lower 32-bits of MSR value.\r
2774 @param EDX Upper 32-bits of MSR value.\r
2775\r
2776 <b>Example usage</b>\r
2777 @code\r
2778 UINT64 Msr;\r
2779\r
2780 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR);\r
2781 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr);\r
2782 @endcode\r
2783**/\r
2784#define MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8\r
2785\r
2786\r
2787/**\r
2788 Package. Uncore M-box 0 perfmon PGT unit select MSR.\r
2789\r
2790 @param ECX MSR_NEHALEM_M0_PMON_PGT (0x00000CA9)\r
2791 @param EAX Lower 32-bits of MSR value.\r
2792 @param EDX Upper 32-bits of MSR value.\r
2793\r
2794 <b>Example usage</b>\r
2795 @code\r
2796 UINT64 Msr;\r
2797\r
2798 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT);\r
2799 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr);\r
2800 @endcode\r
2801**/\r
2802#define MSR_NEHALEM_M0_PMON_PGT 0x00000CA9\r
2803\r
2804\r
2805/**\r
2806 Package. Uncore M-box 0 perfmon PLD unit select MSR.\r
2807\r
2808 @param ECX MSR_NEHALEM_M0_PMON_PLD (0x00000CAA)\r
2809 @param EAX Lower 32-bits of MSR value.\r
2810 @param EDX Upper 32-bits of MSR value.\r
2811\r
2812 <b>Example usage</b>\r
2813 @code\r
2814 UINT64 Msr;\r
2815\r
2816 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD);\r
2817 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr);\r
2818 @endcode\r
2819**/\r
2820#define MSR_NEHALEM_M0_PMON_PLD 0x00000CAA\r
2821\r
2822\r
2823/**\r
2824 Package. Uncore M-box 0 perfmon ZDP unit select MSR.\r
2825\r
2826 @param ECX MSR_NEHALEM_M0_PMON_ZDP (0x00000CAB)\r
2827 @param EAX Lower 32-bits of MSR value.\r
2828 @param EDX Upper 32-bits of MSR value.\r
2829\r
2830 <b>Example usage</b>\r
2831 @code\r
2832 UINT64 Msr;\r
2833\r
2834 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP);\r
2835 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr);\r
2836 @endcode\r
2837**/\r
2838#define MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB\r
2839\r
2840\r
2841/**\r
2842 Package. Uncore M-box 0 perfmon event select MSR.\r
2843\r
2844 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL0 (0x00000CB0)\r
2845 @param EAX Lower 32-bits of MSR value.\r
2846 @param EDX Upper 32-bits of MSR value.\r
2847\r
2848 <b>Example usage</b>\r
2849 @code\r
2850 UINT64 Msr;\r
2851\r
2852 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0);\r
2853 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr);\r
2854 @endcode\r
2855**/\r
2856#define MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0\r
2857\r
2858\r
2859/**\r
2860 Package. Uncore M-box 0 perfmon counter MSR.\r
2861\r
2862 @param ECX MSR_NEHALEM_M0_PMON_CTR0 (0x00000CB1)\r
2863 @param EAX Lower 32-bits of MSR value.\r
2864 @param EDX Upper 32-bits of MSR value.\r
2865\r
2866 <b>Example usage</b>\r
2867 @code\r
2868 UINT64 Msr;\r
2869\r
2870 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0);\r
2871 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr);\r
2872 @endcode\r
2873**/\r
2874#define MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1\r
2875\r
2876\r
2877/**\r
2878 Package. Uncore M-box 0 perfmon event select MSR.\r
2879\r
2880 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL1 (0x00000CB2)\r
2881 @param EAX Lower 32-bits of MSR value.\r
2882 @param EDX Upper 32-bits of MSR value.\r
2883\r
2884 <b>Example usage</b>\r
2885 @code\r
2886 UINT64 Msr;\r
2887\r
2888 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1);\r
2889 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr);\r
2890 @endcode\r
2891**/\r
2892#define MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2\r
2893\r
2894\r
2895/**\r
2896 Package. Uncore M-box 0 perfmon counter MSR.\r
2897\r
2898 @param ECX MSR_NEHALEM_M0_PMON_CTR1 (0x00000CB3)\r
2899 @param EAX Lower 32-bits of MSR value.\r
2900 @param EDX Upper 32-bits of MSR value.\r
2901\r
2902 <b>Example usage</b>\r
2903 @code\r
2904 UINT64 Msr;\r
2905\r
2906 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1);\r
2907 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr);\r
2908 @endcode\r
2909**/\r
2910#define MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3\r
2911\r
2912\r
2913/**\r
2914 Package. Uncore M-box 0 perfmon event select MSR.\r
2915\r
2916 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL2 (0x00000CB4)\r
2917 @param EAX Lower 32-bits of MSR value.\r
2918 @param EDX Upper 32-bits of MSR value.\r
2919\r
2920 <b>Example usage</b>\r
2921 @code\r
2922 UINT64 Msr;\r
2923\r
2924 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2);\r
2925 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr);\r
2926 @endcode\r
2927**/\r
2928#define MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4\r
2929\r
2930\r
2931/**\r
2932 Package. Uncore M-box 0 perfmon counter MSR.\r
2933\r
2934 @param ECX MSR_NEHALEM_M0_PMON_CTR2 (0x00000CB5)\r
2935 @param EAX Lower 32-bits of MSR value.\r
2936 @param EDX Upper 32-bits of MSR value.\r
2937\r
2938 <b>Example usage</b>\r
2939 @code\r
2940 UINT64 Msr;\r
2941\r
2942 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2);\r
2943 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr);\r
2944 @endcode\r
2945**/\r
2946#define MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5\r
2947\r
2948\r
2949/**\r
2950 Package. Uncore M-box 0 perfmon event select MSR.\r
2951\r
2952 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL3 (0x00000CB6)\r
2953 @param EAX Lower 32-bits of MSR value.\r
2954 @param EDX Upper 32-bits of MSR value.\r
2955\r
2956 <b>Example usage</b>\r
2957 @code\r
2958 UINT64 Msr;\r
2959\r
2960 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3);\r
2961 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr);\r
2962 @endcode\r
2963**/\r
2964#define MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6\r
2965\r
2966\r
2967/**\r
2968 Package. Uncore M-box 0 perfmon counter MSR.\r
2969\r
2970 @param ECX MSR_NEHALEM_M0_PMON_CTR3 (0x00000CB7)\r
2971 @param EAX Lower 32-bits of MSR value.\r
2972 @param EDX Upper 32-bits of MSR value.\r
2973\r
2974 <b>Example usage</b>\r
2975 @code\r
2976 UINT64 Msr;\r
2977\r
2978 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3);\r
2979 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr);\r
2980 @endcode\r
2981**/\r
2982#define MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7\r
2983\r
2984\r
2985/**\r
2986 Package. Uncore M-box 0 perfmon event select MSR.\r
2987\r
2988 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL4 (0x00000CB8)\r
2989 @param EAX Lower 32-bits of MSR value.\r
2990 @param EDX Upper 32-bits of MSR value.\r
2991\r
2992 <b>Example usage</b>\r
2993 @code\r
2994 UINT64 Msr;\r
2995\r
2996 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4);\r
2997 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr);\r
2998 @endcode\r
2999**/\r
3000#define MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8\r
3001\r
3002\r
3003/**\r
3004 Package. Uncore M-box 0 perfmon counter MSR.\r
3005\r
3006 @param ECX MSR_NEHALEM_M0_PMON_CTR4 (0x00000CB9)\r
3007 @param EAX Lower 32-bits of MSR value.\r
3008 @param EDX Upper 32-bits of MSR value.\r
3009\r
3010 <b>Example usage</b>\r
3011 @code\r
3012 UINT64 Msr;\r
3013\r
3014 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4);\r
3015 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr);\r
3016 @endcode\r
3017**/\r
3018#define MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9\r
3019\r
3020\r
3021/**\r
3022 Package. Uncore M-box 0 perfmon event select MSR.\r
3023\r
3024 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL5 (0x00000CBA)\r
3025 @param EAX Lower 32-bits of MSR value.\r
3026 @param EDX Upper 32-bits of MSR value.\r
3027\r
3028 <b>Example usage</b>\r
3029 @code\r
3030 UINT64 Msr;\r
3031\r
3032 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5);\r
3033 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr);\r
3034 @endcode\r
3035**/\r
3036#define MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA\r
3037\r
3038\r
3039/**\r
3040 Package. Uncore M-box 0 perfmon counter MSR.\r
3041\r
3042 @param ECX MSR_NEHALEM_M0_PMON_CTR5 (0x00000CBB)\r
3043 @param EAX Lower 32-bits of MSR value.\r
3044 @param EDX Upper 32-bits of MSR value.\r
3045\r
3046 <b>Example usage</b>\r
3047 @code\r
3048 UINT64 Msr;\r
3049\r
3050 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5);\r
3051 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr);\r
3052 @endcode\r
3053**/\r
3054#define MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB\r
3055\r
3056\r
3057/**\r
3058 Package. Uncore S-box 1 perfmon local box control MSR.\r
3059\r
3060 @param ECX MSR_NEHALEM_S1_PMON_BOX_CTRL (0x00000CC0)\r
3061 @param EAX Lower 32-bits of MSR value.\r
3062 @param EDX Upper 32-bits of MSR value.\r
3063\r
3064 <b>Example usage</b>\r
3065 @code\r
3066 UINT64 Msr;\r
3067\r
3068 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL);\r
3069 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr);\r
3070 @endcode\r
3071**/\r
3072#define MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0\r
3073\r
3074\r
3075/**\r
3076 Package. Uncore S-box 1 perfmon local box status MSR.\r
3077\r
3078 @param ECX MSR_NEHALEM_S1_PMON_BOX_STATUS (0x00000CC1)\r
3079 @param EAX Lower 32-bits of MSR value.\r
3080 @param EDX Upper 32-bits of MSR value.\r
3081\r
3082 <b>Example usage</b>\r
3083 @code\r
3084 UINT64 Msr;\r
3085\r
3086 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS);\r
3087 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr);\r
3088 @endcode\r
3089**/\r
3090#define MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1\r
3091\r
3092\r
3093/**\r
3094 Package. Uncore S-box 1 perfmon local box overflow control MSR.\r
3095\r
3096 @param ECX MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL (0x00000CC2)\r
3097 @param EAX Lower 32-bits of MSR value.\r
3098 @param EDX Upper 32-bits of MSR value.\r
3099\r
3100 <b>Example usage</b>\r
3101 @code\r
3102 UINT64 Msr;\r
3103\r
3104 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL);\r
3105 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr);\r
3106 @endcode\r
3107**/\r
3108#define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2\r
3109\r
3110\r
3111/**\r
3112 Package. Uncore S-box 1 perfmon event select MSR.\r
3113\r
3114 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL0 (0x00000CD0)\r
3115 @param EAX Lower 32-bits of MSR value.\r
3116 @param EDX Upper 32-bits of MSR value.\r
3117\r
3118 <b>Example usage</b>\r
3119 @code\r
3120 UINT64 Msr;\r
3121\r
3122 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0);\r
3123 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr);\r
3124 @endcode\r
3125**/\r
3126#define MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0\r
3127\r
3128\r
3129/**\r
3130 Package. Uncore S-box 1 perfmon counter MSR.\r
3131\r
3132 @param ECX MSR_NEHALEM_S1_PMON_CTR0 (0x00000CD1)\r
3133 @param EAX Lower 32-bits of MSR value.\r
3134 @param EDX Upper 32-bits of MSR value.\r
3135\r
3136 <b>Example usage</b>\r
3137 @code\r
3138 UINT64 Msr;\r
3139\r
3140 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0);\r
3141 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr);\r
3142 @endcode\r
3143**/\r
3144#define MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1\r
3145\r
3146\r
3147/**\r
3148 Package. Uncore S-box 1 perfmon event select MSR.\r
3149\r
3150 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL1 (0x00000CD2)\r
3151 @param EAX Lower 32-bits of MSR value.\r
3152 @param EDX Upper 32-bits of MSR value.\r
3153\r
3154 <b>Example usage</b>\r
3155 @code\r
3156 UINT64 Msr;\r
3157\r
3158 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1);\r
3159 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr);\r
3160 @endcode\r
3161**/\r
3162#define MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2\r
3163\r
3164\r
3165/**\r
3166 Package. Uncore S-box 1 perfmon counter MSR.\r
3167\r
3168 @param ECX MSR_NEHALEM_S1_PMON_CTR1 (0x00000CD3)\r
3169 @param EAX Lower 32-bits of MSR value.\r
3170 @param EDX Upper 32-bits of MSR value.\r
3171\r
3172 <b>Example usage</b>\r
3173 @code\r
3174 UINT64 Msr;\r
3175\r
3176 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1);\r
3177 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr);\r
3178 @endcode\r
3179**/\r
3180#define MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3\r
3181\r
3182\r
3183/**\r
3184 Package. Uncore S-box 1 perfmon event select MSR.\r
3185\r
3186 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL2 (0x00000CD4)\r
3187 @param EAX Lower 32-bits of MSR value.\r
3188 @param EDX Upper 32-bits of MSR value.\r
3189\r
3190 <b>Example usage</b>\r
3191 @code\r
3192 UINT64 Msr;\r
3193\r
3194 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2);\r
3195 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr);\r
3196 @endcode\r
3197**/\r
3198#define MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4\r
3199\r
3200\r
3201/**\r
3202 Package. Uncore S-box 1 perfmon counter MSR.\r
3203\r
3204 @param ECX MSR_NEHALEM_S1_PMON_CTR2 (0x00000CD5)\r
3205 @param EAX Lower 32-bits of MSR value.\r
3206 @param EDX Upper 32-bits of MSR value.\r
3207\r
3208 <b>Example usage</b>\r
3209 @code\r
3210 UINT64 Msr;\r
3211\r
3212 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2);\r
3213 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr);\r
3214 @endcode\r
3215**/\r
3216#define MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5\r
3217\r
3218\r
3219/**\r
3220 Package. Uncore S-box 1 perfmon event select MSR.\r
3221\r
3222 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL3 (0x00000CD6)\r
3223 @param EAX Lower 32-bits of MSR value.\r
3224 @param EDX Upper 32-bits of MSR value.\r
3225\r
3226 <b>Example usage</b>\r
3227 @code\r
3228 UINT64 Msr;\r
3229\r
3230 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3);\r
3231 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr);\r
3232 @endcode\r
3233**/\r
3234#define MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6\r
3235\r
3236\r
3237/**\r
3238 Package. Uncore S-box 1 perfmon counter MSR.\r
3239\r
3240 @param ECX MSR_NEHALEM_S1_PMON_CTR3 (0x00000CD7)\r
3241 @param EAX Lower 32-bits of MSR value.\r
3242 @param EDX Upper 32-bits of MSR value.\r
3243\r
3244 <b>Example usage</b>\r
3245 @code\r
3246 UINT64 Msr;\r
3247\r
3248 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3);\r
3249 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr);\r
3250 @endcode\r
3251**/\r
3252#define MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7\r
3253\r
3254\r
3255/**\r
3256 Package. Uncore M-box 1 perfmon local box control MSR.\r
3257\r
3258 @param ECX MSR_NEHALEM_M1_PMON_BOX_CTRL (0x00000CE0)\r
3259 @param EAX Lower 32-bits of MSR value.\r
3260 @param EDX Upper 32-bits of MSR value.\r
3261\r
3262 <b>Example usage</b>\r
3263 @code\r
3264 UINT64 Msr;\r
3265\r
3266 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL);\r
3267 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr);\r
3268 @endcode\r
3269**/\r
3270#define MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0\r
3271\r
3272\r
3273/**\r
3274 Package. Uncore M-box 1 perfmon local box status MSR.\r
3275\r
3276 @param ECX MSR_NEHALEM_M1_PMON_BOX_STATUS (0x00000CE1)\r
3277 @param EAX Lower 32-bits of MSR value.\r
3278 @param EDX Upper 32-bits of MSR value.\r
3279\r
3280 <b>Example usage</b>\r
3281 @code\r
3282 UINT64 Msr;\r
3283\r
3284 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS);\r
3285 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr);\r
3286 @endcode\r
3287**/\r
3288#define MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1\r
3289\r
3290\r
3291/**\r
3292 Package. Uncore M-box 1 perfmon local box overflow control MSR.\r
3293\r
3294 @param ECX MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL (0x00000CE2)\r
3295 @param EAX Lower 32-bits of MSR value.\r
3296 @param EDX Upper 32-bits of MSR value.\r
3297\r
3298 <b>Example usage</b>\r
3299 @code\r
3300 UINT64 Msr;\r
3301\r
3302 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL);\r
3303 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr);\r
3304 @endcode\r
3305**/\r
3306#define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2\r
3307\r
3308\r
3309/**\r
3310 Package. Uncore M-box 1 perfmon time stamp unit select MSR.\r
3311\r
3312 @param ECX MSR_NEHALEM_M1_PMON_TIMESTAMP (0x00000CE4)\r
3313 @param EAX Lower 32-bits of MSR value.\r
3314 @param EDX Upper 32-bits of MSR value.\r
3315\r
3316 <b>Example usage</b>\r
3317 @code\r
3318 UINT64 Msr;\r
3319\r
3320 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP);\r
3321 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr);\r
3322 @endcode\r
3323**/\r
3324#define MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4\r
3325\r
3326\r
3327/**\r
3328 Package. Uncore M-box 1 perfmon DSP unit select MSR.\r
3329\r
3330 @param ECX MSR_NEHALEM_M1_PMON_DSP (0x00000CE5)\r
3331 @param EAX Lower 32-bits of MSR value.\r
3332 @param EDX Upper 32-bits of MSR value.\r
3333\r
3334 <b>Example usage</b>\r
3335 @code\r
3336 UINT64 Msr;\r
3337\r
3338 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP);\r
3339 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr);\r
3340 @endcode\r
3341**/\r
3342#define MSR_NEHALEM_M1_PMON_DSP 0x00000CE5\r
3343\r
3344\r
3345/**\r
3346 Package. Uncore M-box 1 perfmon ISS unit select MSR.\r
3347\r
3348 @param ECX MSR_NEHALEM_M1_PMON_ISS (0x00000CE6)\r
3349 @param EAX Lower 32-bits of MSR value.\r
3350 @param EDX Upper 32-bits of MSR value.\r
3351\r
3352 <b>Example usage</b>\r
3353 @code\r
3354 UINT64 Msr;\r
3355\r
3356 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS);\r
3357 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr);\r
3358 @endcode\r
3359**/\r
3360#define MSR_NEHALEM_M1_PMON_ISS 0x00000CE6\r
3361\r
3362\r
3363/**\r
3364 Package. Uncore M-box 1 perfmon MAP unit select MSR.\r
3365\r
3366 @param ECX MSR_NEHALEM_M1_PMON_MAP (0x00000CE7)\r
3367 @param EAX Lower 32-bits of MSR value.\r
3368 @param EDX Upper 32-bits of MSR value.\r
3369\r
3370 <b>Example usage</b>\r
3371 @code\r
3372 UINT64 Msr;\r
3373\r
3374 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP);\r
3375 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr);\r
3376 @endcode\r
3377**/\r
3378#define MSR_NEHALEM_M1_PMON_MAP 0x00000CE7\r
3379\r
3380\r
3381/**\r
3382 Package. Uncore M-box 1 perfmon MIC THR select MSR.\r
3383\r
3384 @param ECX MSR_NEHALEM_M1_PMON_MSC_THR (0x00000CE8)\r
3385 @param EAX Lower 32-bits of MSR value.\r
3386 @param EDX Upper 32-bits of MSR value.\r
3387\r
3388 <b>Example usage</b>\r
3389 @code\r
3390 UINT64 Msr;\r
3391\r
3392 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR);\r
3393 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr);\r
3394 @endcode\r
3395**/\r
3396#define MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8\r
3397\r
3398\r
3399/**\r
3400 Package. Uncore M-box 1 perfmon PGT unit select MSR.\r
3401\r
3402 @param ECX MSR_NEHALEM_M1_PMON_PGT (0x00000CE9)\r
3403 @param EAX Lower 32-bits of MSR value.\r
3404 @param EDX Upper 32-bits of MSR value.\r
3405\r
3406 <b>Example usage</b>\r
3407 @code\r
3408 UINT64 Msr;\r
3409\r
3410 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT);\r
3411 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr);\r
3412 @endcode\r
3413**/\r
3414#define MSR_NEHALEM_M1_PMON_PGT 0x00000CE9\r
3415\r
3416\r
3417/**\r
3418 Package. Uncore M-box 1 perfmon PLD unit select MSR.\r
3419\r
3420 @param ECX MSR_NEHALEM_M1_PMON_PLD (0x00000CEA)\r
3421 @param EAX Lower 32-bits of MSR value.\r
3422 @param EDX Upper 32-bits of MSR value.\r
3423\r
3424 <b>Example usage</b>\r
3425 @code\r
3426 UINT64 Msr;\r
3427\r
3428 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD);\r
3429 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr);\r
3430 @endcode\r
3431**/\r
3432#define MSR_NEHALEM_M1_PMON_PLD 0x00000CEA\r
3433\r
3434\r
3435/**\r
3436 Package. Uncore M-box 1 perfmon ZDP unit select MSR.\r
3437\r
3438 @param ECX MSR_NEHALEM_M1_PMON_ZDP (0x00000CEB)\r
3439 @param EAX Lower 32-bits of MSR value.\r
3440 @param EDX Upper 32-bits of MSR value.\r
3441\r
3442 <b>Example usage</b>\r
3443 @code\r
3444 UINT64 Msr;\r
3445\r
3446 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP);\r
3447 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr);\r
3448 @endcode\r
3449**/\r
3450#define MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB\r
3451\r
3452\r
3453/**\r
3454 Package. Uncore M-box 1 perfmon event select MSR.\r
3455\r
3456 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL0 (0x00000CF0)\r
3457 @param EAX Lower 32-bits of MSR value.\r
3458 @param EDX Upper 32-bits of MSR value.\r
3459\r
3460 <b>Example usage</b>\r
3461 @code\r
3462 UINT64 Msr;\r
3463\r
3464 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0);\r
3465 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr);\r
3466 @endcode\r
3467**/\r
3468#define MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0\r
3469\r
3470\r
3471/**\r
3472 Package. Uncore M-box 1 perfmon counter MSR.\r
3473\r
3474 @param ECX MSR_NEHALEM_M1_PMON_CTR0 (0x00000CF1)\r
3475 @param EAX Lower 32-bits of MSR value.\r
3476 @param EDX Upper 32-bits of MSR value.\r
3477\r
3478 <b>Example usage</b>\r
3479 @code\r
3480 UINT64 Msr;\r
3481\r
3482 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0);\r
3483 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr);\r
3484 @endcode\r
3485**/\r
3486#define MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1\r
3487\r
3488\r
3489/**\r
3490 Package. Uncore M-box 1 perfmon event select MSR.\r
3491\r
3492 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL1 (0x00000CF2)\r
3493 @param EAX Lower 32-bits of MSR value.\r
3494 @param EDX Upper 32-bits of MSR value.\r
3495\r
3496 <b>Example usage</b>\r
3497 @code\r
3498 UINT64 Msr;\r
3499\r
3500 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1);\r
3501 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr);\r
3502 @endcode\r
3503**/\r
3504#define MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2\r
3505\r
3506\r
3507/**\r
3508 Package. Uncore M-box 1 perfmon counter MSR.\r
3509\r
3510 @param ECX MSR_NEHALEM_M1_PMON_CTR1 (0x00000CF3)\r
3511 @param EAX Lower 32-bits of MSR value.\r
3512 @param EDX Upper 32-bits of MSR value.\r
3513\r
3514 <b>Example usage</b>\r
3515 @code\r
3516 UINT64 Msr;\r
3517\r
3518 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1);\r
3519 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr);\r
3520 @endcode\r
3521**/\r
3522#define MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3\r
3523\r
3524\r
3525/**\r
3526 Package. Uncore M-box 1 perfmon event select MSR.\r
3527\r
3528 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL2 (0x00000CF4)\r
3529 @param EAX Lower 32-bits of MSR value.\r
3530 @param EDX Upper 32-bits of MSR value.\r
3531\r
3532 <b>Example usage</b>\r
3533 @code\r
3534 UINT64 Msr;\r
3535\r
3536 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2);\r
3537 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr);\r
3538 @endcode\r
3539**/\r
3540#define MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4\r
3541\r
3542\r
3543/**\r
3544 Package. Uncore M-box 1 perfmon counter MSR.\r
3545\r
3546 @param ECX MSR_NEHALEM_M1_PMON_CTR2 (0x00000CF5)\r
3547 @param EAX Lower 32-bits of MSR value.\r
3548 @param EDX Upper 32-bits of MSR value.\r
3549\r
3550 <b>Example usage</b>\r
3551 @code\r
3552 UINT64 Msr;\r
3553\r
3554 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2);\r
3555 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr);\r
3556 @endcode\r
3557**/\r
3558#define MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5\r
3559\r
3560\r
3561/**\r
3562 Package. Uncore M-box 1 perfmon event select MSR.\r
3563\r
3564 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL3 (0x00000CF6)\r
3565 @param EAX Lower 32-bits of MSR value.\r
3566 @param EDX Upper 32-bits of MSR value.\r
3567\r
3568 <b>Example usage</b>\r
3569 @code\r
3570 UINT64 Msr;\r
3571\r
3572 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3);\r
3573 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr);\r
3574 @endcode\r
3575**/\r
3576#define MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6\r
3577\r
3578\r
3579/**\r
3580 Package. Uncore M-box 1 perfmon counter MSR.\r
3581\r
3582 @param ECX MSR_NEHALEM_M1_PMON_CTR3 (0x00000CF7)\r
3583 @param EAX Lower 32-bits of MSR value.\r
3584 @param EDX Upper 32-bits of MSR value.\r
3585\r
3586 <b>Example usage</b>\r
3587 @code\r
3588 UINT64 Msr;\r
3589\r
3590 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3);\r
3591 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr);\r
3592 @endcode\r
3593**/\r
3594#define MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7\r
3595\r
3596\r
3597/**\r
3598 Package. Uncore M-box 1 perfmon event select MSR.\r
3599\r
3600 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL4 (0x00000CF8)\r
3601 @param EAX Lower 32-bits of MSR value.\r
3602 @param EDX Upper 32-bits of MSR value.\r
3603\r
3604 <b>Example usage</b>\r
3605 @code\r
3606 UINT64 Msr;\r
3607\r
3608 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4);\r
3609 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr);\r
3610 @endcode\r
3611**/\r
3612#define MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8\r
3613\r
3614\r
3615/**\r
3616 Package. Uncore M-box 1 perfmon counter MSR.\r
3617\r
3618 @param ECX MSR_NEHALEM_M1_PMON_CTR4 (0x00000CF9)\r
3619 @param EAX Lower 32-bits of MSR value.\r
3620 @param EDX Upper 32-bits of MSR value.\r
3621\r
3622 <b>Example usage</b>\r
3623 @code\r
3624 UINT64 Msr;\r
3625\r
3626 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4);\r
3627 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr);\r
3628 @endcode\r
3629**/\r
3630#define MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9\r
3631\r
3632\r
3633/**\r
3634 Package. Uncore M-box 1 perfmon event select MSR.\r
3635\r
3636 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL5 (0x00000CFA)\r
3637 @param EAX Lower 32-bits of MSR value.\r
3638 @param EDX Upper 32-bits of MSR value.\r
3639\r
3640 <b>Example usage</b>\r
3641 @code\r
3642 UINT64 Msr;\r
3643\r
3644 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5);\r
3645 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr);\r
3646 @endcode\r
3647**/\r
3648#define MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA\r
3649\r
3650\r
3651/**\r
3652 Package. Uncore M-box 1 perfmon counter MSR.\r
3653\r
3654 @param ECX MSR_NEHALEM_M1_PMON_CTR5 (0x00000CFB)\r
3655 @param EAX Lower 32-bits of MSR value.\r
3656 @param EDX Upper 32-bits of MSR value.\r
3657\r
3658 <b>Example usage</b>\r
3659 @code\r
3660 UINT64 Msr;\r
3661\r
3662 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5);\r
3663 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr);\r
3664 @endcode\r
3665**/\r
3666#define MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB\r
3667\r
3668\r
3669/**\r
3670 Package. Uncore C-box 0 perfmon local box control MSR.\r
3671\r
3672 @param ECX MSR_NEHALEM_C0_PMON_BOX_CTRL (0x00000D00)\r
3673 @param EAX Lower 32-bits of MSR value.\r
3674 @param EDX Upper 32-bits of MSR value.\r
3675\r
3676 <b>Example usage</b>\r
3677 @code\r
3678 UINT64 Msr;\r
3679\r
3680 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL);\r
3681 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr);\r
3682 @endcode\r
3683**/\r
3684#define MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00\r
3685\r
3686\r
3687/**\r
3688 Package. Uncore C-box 0 perfmon local box status MSR.\r
3689\r
3690 @param ECX MSR_NEHALEM_C0_PMON_BOX_STATUS (0x00000D01)\r
3691 @param EAX Lower 32-bits of MSR value.\r
3692 @param EDX Upper 32-bits of MSR value.\r
3693\r
3694 <b>Example usage</b>\r
3695 @code\r
3696 UINT64 Msr;\r
3697\r
3698 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS);\r
3699 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr);\r
3700 @endcode\r
3701**/\r
3702#define MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01\r
3703\r
3704\r
3705/**\r
3706 Package. Uncore C-box 0 perfmon local box overflow control MSR.\r
3707\r
3708 @param ECX MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL (0x00000D02)\r
3709 @param EAX Lower 32-bits of MSR value.\r
3710 @param EDX Upper 32-bits of MSR value.\r
3711\r
3712 <b>Example usage</b>\r
3713 @code\r
3714 UINT64 Msr;\r
3715\r
3716 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL);\r
3717 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr);\r
3718 @endcode\r
3719**/\r
3720#define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02\r
3721\r
3722\r
3723/**\r
3724 Package. Uncore C-box 0 perfmon event select MSR.\r
3725\r
3726 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL0 (0x00000D10)\r
3727 @param EAX Lower 32-bits of MSR value.\r
3728 @param EDX Upper 32-bits of MSR value.\r
3729\r
3730 <b>Example usage</b>\r
3731 @code\r
3732 UINT64 Msr;\r
3733\r
3734 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0);\r
3735 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr);\r
3736 @endcode\r
3737**/\r
3738#define MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10\r
3739\r
3740\r
3741/**\r
3742 Package. Uncore C-box 0 perfmon counter MSR.\r
3743\r
3744 @param ECX MSR_NEHALEM_C0_PMON_CTR0 (0x00000D11)\r
3745 @param EAX Lower 32-bits of MSR value.\r
3746 @param EDX Upper 32-bits of MSR value.\r
3747\r
3748 <b>Example usage</b>\r
3749 @code\r
3750 UINT64 Msr;\r
3751\r
3752 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0);\r
3753 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr);\r
3754 @endcode\r
3755**/\r
3756#define MSR_NEHALEM_C0_PMON_CTR0 0x00000D11\r
3757\r
3758\r
3759/**\r
3760 Package. Uncore C-box 0 perfmon event select MSR.\r
3761\r
3762 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL1 (0x00000D12)\r
3763 @param EAX Lower 32-bits of MSR value.\r
3764 @param EDX Upper 32-bits of MSR value.\r
3765\r
3766 <b>Example usage</b>\r
3767 @code\r
3768 UINT64 Msr;\r
3769\r
3770 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1);\r
3771 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr);\r
3772 @endcode\r
3773**/\r
3774#define MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12\r
3775\r
3776\r
3777/**\r
3778 Package. Uncore C-box 0 perfmon counter MSR.\r
3779\r
3780 @param ECX MSR_NEHALEM_C0_PMON_CTR1 (0x00000D13)\r
3781 @param EAX Lower 32-bits of MSR value.\r
3782 @param EDX Upper 32-bits of MSR value.\r
3783\r
3784 <b>Example usage</b>\r
3785 @code\r
3786 UINT64 Msr;\r
3787\r
3788 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1);\r
3789 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr);\r
3790 @endcode\r
3791**/\r
3792#define MSR_NEHALEM_C0_PMON_CTR1 0x00000D13\r
3793\r
3794\r
3795/**\r
3796 Package. Uncore C-box 0 perfmon event select MSR.\r
3797\r
3798 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL2 (0x00000D14)\r
3799 @param EAX Lower 32-bits of MSR value.\r
3800 @param EDX Upper 32-bits of MSR value.\r
3801\r
3802 <b>Example usage</b>\r
3803 @code\r
3804 UINT64 Msr;\r
3805\r
3806 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2);\r
3807 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr);\r
3808 @endcode\r
3809**/\r
3810#define MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14\r
3811\r
3812\r
3813/**\r
3814 Package. Uncore C-box 0 perfmon counter MSR.\r
3815\r
3816 @param ECX MSR_NEHALEM_C0_PMON_CTR2 (0x00000D15)\r
3817 @param EAX Lower 32-bits of MSR value.\r
3818 @param EDX Upper 32-bits of MSR value.\r
3819\r
3820 <b>Example usage</b>\r
3821 @code\r
3822 UINT64 Msr;\r
3823\r
3824 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2);\r
3825 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr);\r
3826 @endcode\r
3827**/\r
3828#define MSR_NEHALEM_C0_PMON_CTR2 0x00000D15\r
3829\r
3830\r
3831/**\r
3832 Package. Uncore C-box 0 perfmon event select MSR.\r
3833\r
3834 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL3 (0x00000D16)\r
3835 @param EAX Lower 32-bits of MSR value.\r
3836 @param EDX Upper 32-bits of MSR value.\r
3837\r
3838 <b>Example usage</b>\r
3839 @code\r
3840 UINT64 Msr;\r
3841\r
3842 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3);\r
3843 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr);\r
3844 @endcode\r
3845**/\r
3846#define MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16\r
3847\r
3848\r
3849/**\r
3850 Package. Uncore C-box 0 perfmon counter MSR.\r
3851\r
3852 @param ECX MSR_NEHALEM_C0_PMON_CTR3 (0x00000D17)\r
3853 @param EAX Lower 32-bits of MSR value.\r
3854 @param EDX Upper 32-bits of MSR value.\r
3855\r
3856 <b>Example usage</b>\r
3857 @code\r
3858 UINT64 Msr;\r
3859\r
3860 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3);\r
3861 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr);\r
3862 @endcode\r
3863**/\r
3864#define MSR_NEHALEM_C0_PMON_CTR3 0x00000D17\r
3865\r
3866\r
3867/**\r
3868 Package. Uncore C-box 0 perfmon event select MSR.\r
3869\r
3870 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL4 (0x00000D18)\r
3871 @param EAX Lower 32-bits of MSR value.\r
3872 @param EDX Upper 32-bits of MSR value.\r
3873\r
3874 <b>Example usage</b>\r
3875 @code\r
3876 UINT64 Msr;\r
3877\r
3878 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4);\r
3879 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr);\r
3880 @endcode\r
3881**/\r
3882#define MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18\r
3883\r
3884\r
3885/**\r
3886 Package. Uncore C-box 0 perfmon counter MSR.\r
3887\r
3888 @param ECX MSR_NEHALEM_C0_PMON_CTR4 (0x00000D19)\r
3889 @param EAX Lower 32-bits of MSR value.\r
3890 @param EDX Upper 32-bits of MSR value.\r
3891\r
3892 <b>Example usage</b>\r
3893 @code\r
3894 UINT64 Msr;\r
3895\r
3896 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4);\r
3897 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr);\r
3898 @endcode\r
3899**/\r
3900#define MSR_NEHALEM_C0_PMON_CTR4 0x00000D19\r
3901\r
3902\r
3903/**\r
3904 Package. Uncore C-box 0 perfmon event select MSR.\r
3905\r
3906 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL5 (0x00000D1A)\r
3907 @param EAX Lower 32-bits of MSR value.\r
3908 @param EDX Upper 32-bits of MSR value.\r
3909\r
3910 <b>Example usage</b>\r
3911 @code\r
3912 UINT64 Msr;\r
3913\r
3914 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5);\r
3915 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr);\r
3916 @endcode\r
3917**/\r
3918#define MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A\r
3919\r
3920\r
3921/**\r
3922 Package. Uncore C-box 0 perfmon counter MSR.\r
3923\r
3924 @param ECX MSR_NEHALEM_C0_PMON_CTR5 (0x00000D1B)\r
3925 @param EAX Lower 32-bits of MSR value.\r
3926 @param EDX Upper 32-bits of MSR value.\r
3927\r
3928 <b>Example usage</b>\r
3929 @code\r
3930 UINT64 Msr;\r
3931\r
3932 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5);\r
3933 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr);\r
3934 @endcode\r
3935**/\r
3936#define MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B\r
3937\r
3938\r
3939/**\r
3940 Package. Uncore C-box 4 perfmon local box control MSR.\r
3941\r
3942 @param ECX MSR_NEHALEM_C4_PMON_BOX_CTRL (0x00000D20)\r
3943 @param EAX Lower 32-bits of MSR value.\r
3944 @param EDX Upper 32-bits of MSR value.\r
3945\r
3946 <b>Example usage</b>\r
3947 @code\r
3948 UINT64 Msr;\r
3949\r
3950 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL);\r
3951 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr);\r
3952 @endcode\r
3953**/\r
3954#define MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20\r
3955\r
3956\r
3957/**\r
3958 Package. Uncore C-box 4 perfmon local box status MSR.\r
3959\r
3960 @param ECX MSR_NEHALEM_C4_PMON_BOX_STATUS (0x00000D21)\r
3961 @param EAX Lower 32-bits of MSR value.\r
3962 @param EDX Upper 32-bits of MSR value.\r
3963\r
3964 <b>Example usage</b>\r
3965 @code\r
3966 UINT64 Msr;\r
3967\r
3968 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS);\r
3969 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr);\r
3970 @endcode\r
3971**/\r
3972#define MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21\r
3973\r
3974\r
3975/**\r
3976 Package. Uncore C-box 4 perfmon local box overflow control MSR.\r
3977\r
3978 @param ECX MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL (0x00000D22)\r
3979 @param EAX Lower 32-bits of MSR value.\r
3980 @param EDX Upper 32-bits of MSR value.\r
3981\r
3982 <b>Example usage</b>\r
3983 @code\r
3984 UINT64 Msr;\r
3985\r
3986 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL);\r
3987 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr);\r
3988 @endcode\r
3989**/\r
3990#define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22\r
3991\r
3992\r
3993/**\r
3994 Package. Uncore C-box 4 perfmon event select MSR.\r
3995\r
3996 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL0 (0x00000D30)\r
3997 @param EAX Lower 32-bits of MSR value.\r
3998 @param EDX Upper 32-bits of MSR value.\r
3999\r
4000 <b>Example usage</b>\r
4001 @code\r
4002 UINT64 Msr;\r
4003\r
4004 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0);\r
4005 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr);\r
4006 @endcode\r
4007**/\r
4008#define MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30\r
4009\r
4010\r
4011/**\r
4012 Package. Uncore C-box 4 perfmon counter MSR.\r
4013\r
4014 @param ECX MSR_NEHALEM_C4_PMON_CTR0 (0x00000D31)\r
4015 @param EAX Lower 32-bits of MSR value.\r
4016 @param EDX Upper 32-bits of MSR value.\r
4017\r
4018 <b>Example usage</b>\r
4019 @code\r
4020 UINT64 Msr;\r
4021\r
4022 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0);\r
4023 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr);\r
4024 @endcode\r
4025**/\r
4026#define MSR_NEHALEM_C4_PMON_CTR0 0x00000D31\r
4027\r
4028\r
4029/**\r
4030 Package. Uncore C-box 4 perfmon event select MSR.\r
4031\r
4032 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL1 (0x00000D32)\r
4033 @param EAX Lower 32-bits of MSR value.\r
4034 @param EDX Upper 32-bits of MSR value.\r
4035\r
4036 <b>Example usage</b>\r
4037 @code\r
4038 UINT64 Msr;\r
4039\r
4040 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1);\r
4041 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr);\r
4042 @endcode\r
4043**/\r
4044#define MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32\r
4045\r
4046\r
4047/**\r
4048 Package. Uncore C-box 4 perfmon counter MSR.\r
4049\r
4050 @param ECX MSR_NEHALEM_C4_PMON_CTR1 (0x00000D33)\r
4051 @param EAX Lower 32-bits of MSR value.\r
4052 @param EDX Upper 32-bits of MSR value.\r
4053\r
4054 <b>Example usage</b>\r
4055 @code\r
4056 UINT64 Msr;\r
4057\r
4058 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1);\r
4059 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr);\r
4060 @endcode\r
4061**/\r
4062#define MSR_NEHALEM_C4_PMON_CTR1 0x00000D33\r
4063\r
4064\r
4065/**\r
4066 Package. Uncore C-box 4 perfmon event select MSR.\r
4067\r
4068 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL2 (0x00000D34)\r
4069 @param EAX Lower 32-bits of MSR value.\r
4070 @param EDX Upper 32-bits of MSR value.\r
4071\r
4072 <b>Example usage</b>\r
4073 @code\r
4074 UINT64 Msr;\r
4075\r
4076 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2);\r
4077 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr);\r
4078 @endcode\r
4079**/\r
4080#define MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34\r
4081\r
4082\r
4083/**\r
4084 Package. Uncore C-box 4 perfmon counter MSR.\r
4085\r
4086 @param ECX MSR_NEHALEM_C4_PMON_CTR2 (0x00000D35)\r
4087 @param EAX Lower 32-bits of MSR value.\r
4088 @param EDX Upper 32-bits of MSR value.\r
4089\r
4090 <b>Example usage</b>\r
4091 @code\r
4092 UINT64 Msr;\r
4093\r
4094 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2);\r
4095 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr);\r
4096 @endcode\r
4097**/\r
4098#define MSR_NEHALEM_C4_PMON_CTR2 0x00000D35\r
4099\r
4100\r
4101/**\r
4102 Package. Uncore C-box 4 perfmon event select MSR.\r
4103\r
4104 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL3 (0x00000D36)\r
4105 @param EAX Lower 32-bits of MSR value.\r
4106 @param EDX Upper 32-bits of MSR value.\r
4107\r
4108 <b>Example usage</b>\r
4109 @code\r
4110 UINT64 Msr;\r
4111\r
4112 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3);\r
4113 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr);\r
4114 @endcode\r
4115**/\r
4116#define MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36\r
4117\r
4118\r
4119/**\r
4120 Package. Uncore C-box 4 perfmon counter MSR.\r
4121\r
4122 @param ECX MSR_NEHALEM_C4_PMON_CTR3 (0x00000D37)\r
4123 @param EAX Lower 32-bits of MSR value.\r
4124 @param EDX Upper 32-bits of MSR value.\r
4125\r
4126 <b>Example usage</b>\r
4127 @code\r
4128 UINT64 Msr;\r
4129\r
4130 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3);\r
4131 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr);\r
4132 @endcode\r
4133**/\r
4134#define MSR_NEHALEM_C4_PMON_CTR3 0x00000D37\r
4135\r
4136\r
4137/**\r
4138 Package. Uncore C-box 4 perfmon event select MSR.\r
4139\r
4140 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL4 (0x00000D38)\r
4141 @param EAX Lower 32-bits of MSR value.\r
4142 @param EDX Upper 32-bits of MSR value.\r
4143\r
4144 <b>Example usage</b>\r
4145 @code\r
4146 UINT64 Msr;\r
4147\r
4148 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4);\r
4149 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr);\r
4150 @endcode\r
4151**/\r
4152#define MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38\r
4153\r
4154\r
4155/**\r
4156 Package. Uncore C-box 4 perfmon counter MSR.\r
4157\r
4158 @param ECX MSR_NEHALEM_C4_PMON_CTR4 (0x00000D39)\r
4159 @param EAX Lower 32-bits of MSR value.\r
4160 @param EDX Upper 32-bits of MSR value.\r
4161\r
4162 <b>Example usage</b>\r
4163 @code\r
4164 UINT64 Msr;\r
4165\r
4166 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4);\r
4167 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr);\r
4168 @endcode\r
4169**/\r
4170#define MSR_NEHALEM_C4_PMON_CTR4 0x00000D39\r
4171\r
4172\r
4173/**\r
4174 Package. Uncore C-box 4 perfmon event select MSR.\r
4175\r
4176 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL5 (0x00000D3A)\r
4177 @param EAX Lower 32-bits of MSR value.\r
4178 @param EDX Upper 32-bits of MSR value.\r
4179\r
4180 <b>Example usage</b>\r
4181 @code\r
4182 UINT64 Msr;\r
4183\r
4184 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5);\r
4185 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr);\r
4186 @endcode\r
4187**/\r
4188#define MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A\r
4189\r
4190\r
4191/**\r
4192 Package. Uncore C-box 4 perfmon counter MSR.\r
4193\r
4194 @param ECX MSR_NEHALEM_C4_PMON_CTR5 (0x00000D3B)\r
4195 @param EAX Lower 32-bits of MSR value.\r
4196 @param EDX Upper 32-bits of MSR value.\r
4197\r
4198 <b>Example usage</b>\r
4199 @code\r
4200 UINT64 Msr;\r
4201\r
4202 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5);\r
4203 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr);\r
4204 @endcode\r
4205**/\r
4206#define MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B\r
4207\r
4208\r
4209/**\r
4210 Package. Uncore C-box 2 perfmon local box control MSR.\r
4211\r
4212 @param ECX MSR_NEHALEM_C2_PMON_BOX_CTRL (0x00000D40)\r
4213 @param EAX Lower 32-bits of MSR value.\r
4214 @param EDX Upper 32-bits of MSR value.\r
4215\r
4216 <b>Example usage</b>\r
4217 @code\r
4218 UINT64 Msr;\r
4219\r
4220 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL);\r
4221 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr);\r
4222 @endcode\r
4223**/\r
4224#define MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40\r
4225\r
4226\r
4227/**\r
4228 Package. Uncore C-box 2 perfmon local box status MSR.\r
4229\r
4230 @param ECX MSR_NEHALEM_C2_PMON_BOX_STATUS (0x00000D41)\r
4231 @param EAX Lower 32-bits of MSR value.\r
4232 @param EDX Upper 32-bits of MSR value.\r
4233\r
4234 <b>Example usage</b>\r
4235 @code\r
4236 UINT64 Msr;\r
4237\r
4238 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS);\r
4239 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr);\r
4240 @endcode\r
4241**/\r
4242#define MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41\r
4243\r
4244\r
4245/**\r
4246 Package. Uncore C-box 2 perfmon local box overflow control MSR.\r
4247\r
4248 @param ECX MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL (0x00000D42)\r
4249 @param EAX Lower 32-bits of MSR value.\r
4250 @param EDX Upper 32-bits of MSR value.\r
4251\r
4252 <b>Example usage</b>\r
4253 @code\r
4254 UINT64 Msr;\r
4255\r
4256 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL);\r
4257 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr);\r
4258 @endcode\r
4259**/\r
4260#define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42\r
4261\r
4262\r
4263/**\r
4264 Package. Uncore C-box 2 perfmon event select MSR.\r
4265\r
4266 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL0 (0x00000D50)\r
4267 @param EAX Lower 32-bits of MSR value.\r
4268 @param EDX Upper 32-bits of MSR value.\r
4269\r
4270 <b>Example usage</b>\r
4271 @code\r
4272 UINT64 Msr;\r
4273\r
4274 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0);\r
4275 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr);\r
4276 @endcode\r
4277**/\r
4278#define MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50\r
4279\r
4280\r
4281/**\r
4282 Package. Uncore C-box 2 perfmon counter MSR.\r
4283\r
4284 @param ECX MSR_NEHALEM_C2_PMON_CTR0 (0x00000D51)\r
4285 @param EAX Lower 32-bits of MSR value.\r
4286 @param EDX Upper 32-bits of MSR value.\r
4287\r
4288 <b>Example usage</b>\r
4289 @code\r
4290 UINT64 Msr;\r
4291\r
4292 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0);\r
4293 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr);\r
4294 @endcode\r
4295**/\r
4296#define MSR_NEHALEM_C2_PMON_CTR0 0x00000D51\r
4297\r
4298\r
4299/**\r
4300 Package. Uncore C-box 2 perfmon event select MSR.\r
4301\r
4302 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL1 (0x00000D52)\r
4303 @param EAX Lower 32-bits of MSR value.\r
4304 @param EDX Upper 32-bits of MSR value.\r
4305\r
4306 <b>Example usage</b>\r
4307 @code\r
4308 UINT64 Msr;\r
4309\r
4310 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1);\r
4311 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr);\r
4312 @endcode\r
4313**/\r
4314#define MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52\r
4315\r
4316\r
4317/**\r
4318 Package. Uncore C-box 2 perfmon counter MSR.\r
4319\r
4320 @param ECX MSR_NEHALEM_C2_PMON_CTR1 (0x00000D53)\r
4321 @param EAX Lower 32-bits of MSR value.\r
4322 @param EDX Upper 32-bits of MSR value.\r
4323\r
4324 <b>Example usage</b>\r
4325 @code\r
4326 UINT64 Msr;\r
4327\r
4328 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1);\r
4329 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr);\r
4330 @endcode\r
4331**/\r
4332#define MSR_NEHALEM_C2_PMON_CTR1 0x00000D53\r
4333\r
4334\r
4335/**\r
4336 Package. Uncore C-box 2 perfmon event select MSR.\r
4337\r
4338 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL2 (0x00000D54)\r
4339 @param EAX Lower 32-bits of MSR value.\r
4340 @param EDX Upper 32-bits of MSR value.\r
4341\r
4342 <b>Example usage</b>\r
4343 @code\r
4344 UINT64 Msr;\r
4345\r
4346 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2);\r
4347 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr);\r
4348 @endcode\r
4349**/\r
4350#define MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54\r
4351\r
4352\r
4353/**\r
4354 Package. Uncore C-box 2 perfmon counter MSR.\r
4355\r
4356 @param ECX MSR_NEHALEM_C2_PMON_CTR2 (0x00000D55)\r
4357 @param EAX Lower 32-bits of MSR value.\r
4358 @param EDX Upper 32-bits of MSR value.\r
4359\r
4360 <b>Example usage</b>\r
4361 @code\r
4362 UINT64 Msr;\r
4363\r
4364 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2);\r
4365 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr);\r
4366 @endcode\r
4367**/\r
4368#define MSR_NEHALEM_C2_PMON_CTR2 0x00000D55\r
4369\r
4370\r
4371/**\r
4372 Package. Uncore C-box 2 perfmon event select MSR.\r
4373\r
4374 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL3 (0x00000D56)\r
4375 @param EAX Lower 32-bits of MSR value.\r
4376 @param EDX Upper 32-bits of MSR value.\r
4377\r
4378 <b>Example usage</b>\r
4379 @code\r
4380 UINT64 Msr;\r
4381\r
4382 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3);\r
4383 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr);\r
4384 @endcode\r
4385**/\r
4386#define MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56\r
4387\r
4388\r
4389/**\r
4390 Package. Uncore C-box 2 perfmon counter MSR.\r
4391\r
4392 @param ECX MSR_NEHALEM_C2_PMON_CTR3 (0x00000D57)\r
4393 @param EAX Lower 32-bits of MSR value.\r
4394 @param EDX Upper 32-bits of MSR value.\r
4395\r
4396 <b>Example usage</b>\r
4397 @code\r
4398 UINT64 Msr;\r
4399\r
4400 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3);\r
4401 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr);\r
4402 @endcode\r
4403**/\r
4404#define MSR_NEHALEM_C2_PMON_CTR3 0x00000D57\r
4405\r
4406\r
4407/**\r
4408 Package. Uncore C-box 2 perfmon event select MSR.\r
4409\r
4410 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL4 (0x00000D58)\r
4411 @param EAX Lower 32-bits of MSR value.\r
4412 @param EDX Upper 32-bits of MSR value.\r
4413\r
4414 <b>Example usage</b>\r
4415 @code\r
4416 UINT64 Msr;\r
4417\r
4418 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4);\r
4419 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr);\r
4420 @endcode\r
4421**/\r
4422#define MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58\r
4423\r
4424\r
4425/**\r
4426 Package. Uncore C-box 2 perfmon counter MSR.\r
4427\r
4428 @param ECX MSR_NEHALEM_C2_PMON_CTR4 (0x00000D59)\r
4429 @param EAX Lower 32-bits of MSR value.\r
4430 @param EDX Upper 32-bits of MSR value.\r
4431\r
4432 <b>Example usage</b>\r
4433 @code\r
4434 UINT64 Msr;\r
4435\r
4436 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4);\r
4437 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr);\r
4438 @endcode\r
4439**/\r
4440#define MSR_NEHALEM_C2_PMON_CTR4 0x00000D59\r
4441\r
4442\r
4443/**\r
4444 Package. Uncore C-box 2 perfmon event select MSR.\r
4445\r
4446 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL5 (0x00000D5A)\r
4447 @param EAX Lower 32-bits of MSR value.\r
4448 @param EDX Upper 32-bits of MSR value.\r
4449\r
4450 <b>Example usage</b>\r
4451 @code\r
4452 UINT64 Msr;\r
4453\r
4454 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5);\r
4455 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr);\r
4456 @endcode\r
4457**/\r
4458#define MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A\r
4459\r
4460\r
4461/**\r
4462 Package. Uncore C-box 2 perfmon counter MSR.\r
4463\r
4464 @param ECX MSR_NEHALEM_C2_PMON_CTR5 (0x00000D5B)\r
4465 @param EAX Lower 32-bits of MSR value.\r
4466 @param EDX Upper 32-bits of MSR value.\r
4467\r
4468 <b>Example usage</b>\r
4469 @code\r
4470 UINT64 Msr;\r
4471\r
4472 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5);\r
4473 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr);\r
4474 @endcode\r
4475**/\r
4476#define MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B\r
4477\r
4478\r
4479/**\r
4480 Package. Uncore C-box 6 perfmon local box control MSR.\r
4481\r
4482 @param ECX MSR_NEHALEM_C6_PMON_BOX_CTRL (0x00000D60)\r
4483 @param EAX Lower 32-bits of MSR value.\r
4484 @param EDX Upper 32-bits of MSR value.\r
4485\r
4486 <b>Example usage</b>\r
4487 @code\r
4488 UINT64 Msr;\r
4489\r
4490 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL);\r
4491 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr);\r
4492 @endcode\r
4493**/\r
4494#define MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60\r
4495\r
4496\r
4497/**\r
4498 Package. Uncore C-box 6 perfmon local box status MSR.\r
4499\r
4500 @param ECX MSR_NEHALEM_C6_PMON_BOX_STATUS (0x00000D61)\r
4501 @param EAX Lower 32-bits of MSR value.\r
4502 @param EDX Upper 32-bits of MSR value.\r
4503\r
4504 <b>Example usage</b>\r
4505 @code\r
4506 UINT64 Msr;\r
4507\r
4508 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS);\r
4509 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr);\r
4510 @endcode\r
4511**/\r
4512#define MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61\r
4513\r
4514\r
4515/**\r
4516 Package. Uncore C-box 6 perfmon local box overflow control MSR.\r
4517\r
4518 @param ECX MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL (0x00000D62)\r
4519 @param EAX Lower 32-bits of MSR value.\r
4520 @param EDX Upper 32-bits of MSR value.\r
4521\r
4522 <b>Example usage</b>\r
4523 @code\r
4524 UINT64 Msr;\r
4525\r
4526 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL);\r
4527 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr);\r
4528 @endcode\r
4529**/\r
4530#define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62\r
4531\r
4532\r
4533/**\r
4534 Package. Uncore C-box 6 perfmon event select MSR.\r
4535\r
4536 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL0 (0x00000D70)\r
4537 @param EAX Lower 32-bits of MSR value.\r
4538 @param EDX Upper 32-bits of MSR value.\r
4539\r
4540 <b>Example usage</b>\r
4541 @code\r
4542 UINT64 Msr;\r
4543\r
4544 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0);\r
4545 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr);\r
4546 @endcode\r
4547**/\r
4548#define MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70\r
4549\r
4550\r
4551/**\r
4552 Package. Uncore C-box 6 perfmon counter MSR.\r
4553\r
4554 @param ECX MSR_NEHALEM_C6_PMON_CTR0 (0x00000D71)\r
4555 @param EAX Lower 32-bits of MSR value.\r
4556 @param EDX Upper 32-bits of MSR value.\r
4557\r
4558 <b>Example usage</b>\r
4559 @code\r
4560 UINT64 Msr;\r
4561\r
4562 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0);\r
4563 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr);\r
4564 @endcode\r
4565**/\r
4566#define MSR_NEHALEM_C6_PMON_CTR0 0x00000D71\r
4567\r
4568\r
4569/**\r
4570 Package. Uncore C-box 6 perfmon event select MSR.\r
4571\r
4572 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL1 (0x00000D72)\r
4573 @param EAX Lower 32-bits of MSR value.\r
4574 @param EDX Upper 32-bits of MSR value.\r
4575\r
4576 <b>Example usage</b>\r
4577 @code\r
4578 UINT64 Msr;\r
4579\r
4580 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1);\r
4581 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr);\r
4582 @endcode\r
4583**/\r
4584#define MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72\r
4585\r
4586\r
4587/**\r
4588 Package. Uncore C-box 6 perfmon counter MSR.\r
4589\r
4590 @param ECX MSR_NEHALEM_C6_PMON_CTR1 (0x00000D73)\r
4591 @param EAX Lower 32-bits of MSR value.\r
4592 @param EDX Upper 32-bits of MSR value.\r
4593\r
4594 <b>Example usage</b>\r
4595 @code\r
4596 UINT64 Msr;\r
4597\r
4598 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1);\r
4599 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr);\r
4600 @endcode\r
4601**/\r
4602#define MSR_NEHALEM_C6_PMON_CTR1 0x00000D73\r
4603\r
4604\r
4605/**\r
4606 Package. Uncore C-box 6 perfmon event select MSR.\r
4607\r
4608 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL2 (0x00000D74)\r
4609 @param EAX Lower 32-bits of MSR value.\r
4610 @param EDX Upper 32-bits of MSR value.\r
4611\r
4612 <b>Example usage</b>\r
4613 @code\r
4614 UINT64 Msr;\r
4615\r
4616 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2);\r
4617 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr);\r
4618 @endcode\r
4619**/\r
4620#define MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74\r
4621\r
4622\r
4623/**\r
4624 Package. Uncore C-box 6 perfmon counter MSR.\r
4625\r
4626 @param ECX MSR_NEHALEM_C6_PMON_CTR2 (0x00000D75)\r
4627 @param EAX Lower 32-bits of MSR value.\r
4628 @param EDX Upper 32-bits of MSR value.\r
4629\r
4630 <b>Example usage</b>\r
4631 @code\r
4632 UINT64 Msr;\r
4633\r
4634 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2);\r
4635 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr);\r
4636 @endcode\r
4637**/\r
4638#define MSR_NEHALEM_C6_PMON_CTR2 0x00000D75\r
4639\r
4640\r
4641/**\r
4642 Package. Uncore C-box 6 perfmon event select MSR.\r
4643\r
4644 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL3 (0x00000D76)\r
4645 @param EAX Lower 32-bits of MSR value.\r
4646 @param EDX Upper 32-bits of MSR value.\r
4647\r
4648 <b>Example usage</b>\r
4649 @code\r
4650 UINT64 Msr;\r
4651\r
4652 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3);\r
4653 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr);\r
4654 @endcode\r
4655**/\r
4656#define MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76\r
4657\r
4658\r
4659/**\r
4660 Package. Uncore C-box 6 perfmon counter MSR.\r
4661\r
4662 @param ECX MSR_NEHALEM_C6_PMON_CTR3 (0x00000D77)\r
4663 @param EAX Lower 32-bits of MSR value.\r
4664 @param EDX Upper 32-bits of MSR value.\r
4665\r
4666 <b>Example usage</b>\r
4667 @code\r
4668 UINT64 Msr;\r
4669\r
4670 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3);\r
4671 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr);\r
4672 @endcode\r
4673**/\r
4674#define MSR_NEHALEM_C6_PMON_CTR3 0x00000D77\r
4675\r
4676\r
4677/**\r
4678 Package. Uncore C-box 6 perfmon event select MSR.\r
4679\r
4680 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL4 (0x00000D78)\r
4681 @param EAX Lower 32-bits of MSR value.\r
4682 @param EDX Upper 32-bits of MSR value.\r
4683\r
4684 <b>Example usage</b>\r
4685 @code\r
4686 UINT64 Msr;\r
4687\r
4688 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4);\r
4689 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr);\r
4690 @endcode\r
4691**/\r
4692#define MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78\r
4693\r
4694\r
4695/**\r
4696 Package. Uncore C-box 6 perfmon counter MSR.\r
4697\r
4698 @param ECX MSR_NEHALEM_C6_PMON_CTR4 (0x00000D79)\r
4699 @param EAX Lower 32-bits of MSR value.\r
4700 @param EDX Upper 32-bits of MSR value.\r
4701\r
4702 <b>Example usage</b>\r
4703 @code\r
4704 UINT64 Msr;\r
4705\r
4706 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4);\r
4707 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr);\r
4708 @endcode\r
4709**/\r
4710#define MSR_NEHALEM_C6_PMON_CTR4 0x00000D79\r
4711\r
4712\r
4713/**\r
4714 Package. Uncore C-box 6 perfmon event select MSR.\r
4715\r
4716 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL5 (0x00000D7A)\r
4717 @param EAX Lower 32-bits of MSR value.\r
4718 @param EDX Upper 32-bits of MSR value.\r
4719\r
4720 <b>Example usage</b>\r
4721 @code\r
4722 UINT64 Msr;\r
4723\r
4724 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5);\r
4725 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr);\r
4726 @endcode\r
4727**/\r
4728#define MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A\r
4729\r
4730\r
4731/**\r
4732 Package. Uncore C-box 6 perfmon counter MSR.\r
4733\r
4734 @param ECX MSR_NEHALEM_C6_PMON_CTR5 (0x00000D7B)\r
4735 @param EAX Lower 32-bits of MSR value.\r
4736 @param EDX Upper 32-bits of MSR value.\r
4737\r
4738 <b>Example usage</b>\r
4739 @code\r
4740 UINT64 Msr;\r
4741\r
4742 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5);\r
4743 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr);\r
4744 @endcode\r
4745**/\r
4746#define MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B\r
4747\r
4748\r
4749/**\r
4750 Package. Uncore C-box 1 perfmon local box control MSR.\r
4751\r
4752 @param ECX MSR_NEHALEM_C1_PMON_BOX_CTRL (0x00000D80)\r
4753 @param EAX Lower 32-bits of MSR value.\r
4754 @param EDX Upper 32-bits of MSR value.\r
4755\r
4756 <b>Example usage</b>\r
4757 @code\r
4758 UINT64 Msr;\r
4759\r
4760 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL);\r
4761 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr);\r
4762 @endcode\r
4763**/\r
4764#define MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80\r
4765\r
4766\r
4767/**\r
4768 Package. Uncore C-box 1 perfmon local box status MSR.\r
4769\r
4770 @param ECX MSR_NEHALEM_C1_PMON_BOX_STATUS (0x00000D81)\r
4771 @param EAX Lower 32-bits of MSR value.\r
4772 @param EDX Upper 32-bits of MSR value.\r
4773\r
4774 <b>Example usage</b>\r
4775 @code\r
4776 UINT64 Msr;\r
4777\r
4778 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS);\r
4779 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr);\r
4780 @endcode\r
4781**/\r
4782#define MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81\r
4783\r
4784\r
4785/**\r
4786 Package. Uncore C-box 1 perfmon local box overflow control MSR.\r
4787\r
4788 @param ECX MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL (0x00000D82)\r
4789 @param EAX Lower 32-bits of MSR value.\r
4790 @param EDX Upper 32-bits of MSR value.\r
4791\r
4792 <b>Example usage</b>\r
4793 @code\r
4794 UINT64 Msr;\r
4795\r
4796 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL);\r
4797 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr);\r
4798 @endcode\r
4799**/\r
4800#define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82\r
4801\r
4802\r
4803/**\r
4804 Package. Uncore C-box 1 perfmon event select MSR.\r
4805\r
4806 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL0 (0x00000D90)\r
4807 @param EAX Lower 32-bits of MSR value.\r
4808 @param EDX Upper 32-bits of MSR value.\r
4809\r
4810 <b>Example usage</b>\r
4811 @code\r
4812 UINT64 Msr;\r
4813\r
4814 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0);\r
4815 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr);\r
4816 @endcode\r
4817**/\r
4818#define MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90\r
4819\r
4820\r
4821/**\r
4822 Package. Uncore C-box 1 perfmon counter MSR.\r
4823\r
4824 @param ECX MSR_NEHALEM_C1_PMON_CTR0 (0x00000D91)\r
4825 @param EAX Lower 32-bits of MSR value.\r
4826 @param EDX Upper 32-bits of MSR value.\r
4827\r
4828 <b>Example usage</b>\r
4829 @code\r
4830 UINT64 Msr;\r
4831\r
4832 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0);\r
4833 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr);\r
4834 @endcode\r
4835**/\r
4836#define MSR_NEHALEM_C1_PMON_CTR0 0x00000D91\r
4837\r
4838\r
4839/**\r
4840 Package. Uncore C-box 1 perfmon event select MSR.\r
4841\r
4842 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL1 (0x00000D92)\r
4843 @param EAX Lower 32-bits of MSR value.\r
4844 @param EDX Upper 32-bits of MSR value.\r
4845\r
4846 <b>Example usage</b>\r
4847 @code\r
4848 UINT64 Msr;\r
4849\r
4850 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1);\r
4851 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr);\r
4852 @endcode\r
4853**/\r
4854#define MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92\r
4855\r
4856\r
4857/**\r
4858 Package. Uncore C-box 1 perfmon counter MSR.\r
4859\r
4860 @param ECX MSR_NEHALEM_C1_PMON_CTR1 (0x00000D93)\r
4861 @param EAX Lower 32-bits of MSR value.\r
4862 @param EDX Upper 32-bits of MSR value.\r
4863\r
4864 <b>Example usage</b>\r
4865 @code\r
4866 UINT64 Msr;\r
4867\r
4868 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1);\r
4869 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr);\r
4870 @endcode\r
4871**/\r
4872#define MSR_NEHALEM_C1_PMON_CTR1 0x00000D93\r
4873\r
4874\r
4875/**\r
4876 Package. Uncore C-box 1 perfmon event select MSR.\r
4877\r
4878 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL2 (0x00000D94)\r
4879 @param EAX Lower 32-bits of MSR value.\r
4880 @param EDX Upper 32-bits of MSR value.\r
4881\r
4882 <b>Example usage</b>\r
4883 @code\r
4884 UINT64 Msr;\r
4885\r
4886 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2);\r
4887 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr);\r
4888 @endcode\r
4889**/\r
4890#define MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94\r
4891\r
4892\r
4893/**\r
4894 Package. Uncore C-box 1 perfmon counter MSR.\r
4895\r
4896 @param ECX MSR_NEHALEM_C1_PMON_CTR2 (0x00000D95)\r
4897 @param EAX Lower 32-bits of MSR value.\r
4898 @param EDX Upper 32-bits of MSR value.\r
4899\r
4900 <b>Example usage</b>\r
4901 @code\r
4902 UINT64 Msr;\r
4903\r
4904 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2);\r
4905 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr);\r
4906 @endcode\r
4907**/\r
4908#define MSR_NEHALEM_C1_PMON_CTR2 0x00000D95\r
4909\r
4910\r
4911/**\r
4912 Package. Uncore C-box 1 perfmon event select MSR.\r
4913\r
4914 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL3 (0x00000D96)\r
4915 @param EAX Lower 32-bits of MSR value.\r
4916 @param EDX Upper 32-bits of MSR value.\r
4917\r
4918 <b>Example usage</b>\r
4919 @code\r
4920 UINT64 Msr;\r
4921\r
4922 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3);\r
4923 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr);\r
4924 @endcode\r
4925**/\r
4926#define MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96\r
4927\r
4928\r
4929/**\r
4930 Package. Uncore C-box 1 perfmon counter MSR.\r
4931\r
4932 @param ECX MSR_NEHALEM_C1_PMON_CTR3 (0x00000D97)\r
4933 @param EAX Lower 32-bits of MSR value.\r
4934 @param EDX Upper 32-bits of MSR value.\r
4935\r
4936 <b>Example usage</b>\r
4937 @code\r
4938 UINT64 Msr;\r
4939\r
4940 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3);\r
4941 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr);\r
4942 @endcode\r
4943**/\r
4944#define MSR_NEHALEM_C1_PMON_CTR3 0x00000D97\r
4945\r
4946\r
4947/**\r
4948 Package. Uncore C-box 1 perfmon event select MSR.\r
4949\r
4950 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL4 (0x00000D98)\r
4951 @param EAX Lower 32-bits of MSR value.\r
4952 @param EDX Upper 32-bits of MSR value.\r
4953\r
4954 <b>Example usage</b>\r
4955 @code\r
4956 UINT64 Msr;\r
4957\r
4958 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4);\r
4959 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr);\r
4960 @endcode\r
4961**/\r
4962#define MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98\r
4963\r
4964\r
4965/**\r
4966 Package. Uncore C-box 1 perfmon counter MSR.\r
4967\r
4968 @param ECX MSR_NEHALEM_C1_PMON_CTR4 (0x00000D99)\r
4969 @param EAX Lower 32-bits of MSR value.\r
4970 @param EDX Upper 32-bits of MSR value.\r
4971\r
4972 <b>Example usage</b>\r
4973 @code\r
4974 UINT64 Msr;\r
4975\r
4976 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4);\r
4977 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr);\r
4978 @endcode\r
4979**/\r
4980#define MSR_NEHALEM_C1_PMON_CTR4 0x00000D99\r
4981\r
4982\r
4983/**\r
4984 Package. Uncore C-box 1 perfmon event select MSR.\r
4985\r
4986 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL5 (0x00000D9A)\r
4987 @param EAX Lower 32-bits of MSR value.\r
4988 @param EDX Upper 32-bits of MSR value.\r
4989\r
4990 <b>Example usage</b>\r
4991 @code\r
4992 UINT64 Msr;\r
4993\r
4994 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5);\r
4995 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr);\r
4996 @endcode\r
4997**/\r
4998#define MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A\r
4999\r
5000\r
5001/**\r
5002 Package. Uncore C-box 1 perfmon counter MSR.\r
5003\r
5004 @param ECX MSR_NEHALEM_C1_PMON_CTR5 (0x00000D9B)\r
5005 @param EAX Lower 32-bits of MSR value.\r
5006 @param EDX Upper 32-bits of MSR value.\r
5007\r
5008 <b>Example usage</b>\r
5009 @code\r
5010 UINT64 Msr;\r
5011\r
5012 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5);\r
5013 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr);\r
5014 @endcode\r
5015**/\r
5016#define MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B\r
5017\r
5018\r
5019/**\r
5020 Package. Uncore C-box 5 perfmon local box control MSR.\r
5021\r
5022 @param ECX MSR_NEHALEM_C5_PMON_BOX_CTRL (0x00000DA0)\r
5023 @param EAX Lower 32-bits of MSR value.\r
5024 @param EDX Upper 32-bits of MSR value.\r
5025\r
5026 <b>Example usage</b>\r
5027 @code\r
5028 UINT64 Msr;\r
5029\r
5030 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL);\r
5031 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr);\r
5032 @endcode\r
5033**/\r
5034#define MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0\r
5035\r
5036\r
5037/**\r
5038 Package. Uncore C-box 5 perfmon local box status MSR.\r
5039\r
5040 @param ECX MSR_NEHALEM_C5_PMON_BOX_STATUS (0x00000DA1)\r
5041 @param EAX Lower 32-bits of MSR value.\r
5042 @param EDX Upper 32-bits of MSR value.\r
5043\r
5044 <b>Example usage</b>\r
5045 @code\r
5046 UINT64 Msr;\r
5047\r
5048 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS);\r
5049 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr);\r
5050 @endcode\r
5051**/\r
5052#define MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1\r
5053\r
5054\r
5055/**\r
5056 Package. Uncore C-box 5 perfmon local box overflow control MSR.\r
5057\r
5058 @param ECX MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL (0x00000DA2)\r
5059 @param EAX Lower 32-bits of MSR value.\r
5060 @param EDX Upper 32-bits of MSR value.\r
5061\r
5062 <b>Example usage</b>\r
5063 @code\r
5064 UINT64 Msr;\r
5065\r
5066 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL);\r
5067 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr);\r
5068 @endcode\r
5069**/\r
5070#define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2\r
5071\r
5072\r
5073/**\r
5074 Package. Uncore C-box 5 perfmon event select MSR.\r
5075\r
5076 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL0 (0x00000DB0)\r
5077 @param EAX Lower 32-bits of MSR value.\r
5078 @param EDX Upper 32-bits of MSR value.\r
5079\r
5080 <b>Example usage</b>\r
5081 @code\r
5082 UINT64 Msr;\r
5083\r
5084 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0);\r
5085 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr);\r
5086 @endcode\r
5087**/\r
5088#define MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0\r
5089\r
5090\r
5091/**\r
5092 Package. Uncore C-box 5 perfmon counter MSR.\r
5093\r
5094 @param ECX MSR_NEHALEM_C5_PMON_CTR0 (0x00000DB1)\r
5095 @param EAX Lower 32-bits of MSR value.\r
5096 @param EDX Upper 32-bits of MSR value.\r
5097\r
5098 <b>Example usage</b>\r
5099 @code\r
5100 UINT64 Msr;\r
5101\r
5102 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0);\r
5103 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr);\r
5104 @endcode\r
5105**/\r
5106#define MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1\r
5107\r
5108\r
5109/**\r
5110 Package. Uncore C-box 5 perfmon event select MSR.\r
5111\r
5112 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL1 (0x00000DB2)\r
5113 @param EAX Lower 32-bits of MSR value.\r
5114 @param EDX Upper 32-bits of MSR value.\r
5115\r
5116 <b>Example usage</b>\r
5117 @code\r
5118 UINT64 Msr;\r
5119\r
5120 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1);\r
5121 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr);\r
5122 @endcode\r
5123**/\r
5124#define MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2\r
5125\r
5126\r
5127/**\r
5128 Package. Uncore C-box 5 perfmon counter MSR.\r
5129\r
5130 @param ECX MSR_NEHALEM_C5_PMON_CTR1 (0x00000DB3)\r
5131 @param EAX Lower 32-bits of MSR value.\r
5132 @param EDX Upper 32-bits of MSR value.\r
5133\r
5134 <b>Example usage</b>\r
5135 @code\r
5136 UINT64 Msr;\r
5137\r
5138 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1);\r
5139 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr);\r
5140 @endcode\r
5141**/\r
5142#define MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3\r
5143\r
5144\r
5145/**\r
5146 Package. Uncore C-box 5 perfmon event select MSR.\r
5147\r
5148 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL2 (0x00000DB4)\r
5149 @param EAX Lower 32-bits of MSR value.\r
5150 @param EDX Upper 32-bits of MSR value.\r
5151\r
5152 <b>Example usage</b>\r
5153 @code\r
5154 UINT64 Msr;\r
5155\r
5156 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2);\r
5157 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr);\r
5158 @endcode\r
5159**/\r
5160#define MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4\r
5161\r
5162\r
5163/**\r
5164 Package. Uncore C-box 5 perfmon counter MSR.\r
5165\r
5166 @param ECX MSR_NEHALEM_C5_PMON_CTR2 (0x00000DB5)\r
5167 @param EAX Lower 32-bits of MSR value.\r
5168 @param EDX Upper 32-bits of MSR value.\r
5169\r
5170 <b>Example usage</b>\r
5171 @code\r
5172 UINT64 Msr;\r
5173\r
5174 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2);\r
5175 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr);\r
5176 @endcode\r
5177**/\r
5178#define MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5\r
5179\r
5180\r
5181/**\r
5182 Package. Uncore C-box 5 perfmon event select MSR.\r
5183\r
5184 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL3 (0x00000DB6)\r
5185 @param EAX Lower 32-bits of MSR value.\r
5186 @param EDX Upper 32-bits of MSR value.\r
5187\r
5188 <b>Example usage</b>\r
5189 @code\r
5190 UINT64 Msr;\r
5191\r
5192 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3);\r
5193 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr);\r
5194 @endcode\r
5195**/\r
5196#define MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6\r
5197\r
5198\r
5199/**\r
5200 Package. Uncore C-box 5 perfmon counter MSR.\r
5201\r
5202 @param ECX MSR_NEHALEM_C5_PMON_CTR3 (0x00000DB7)\r
5203 @param EAX Lower 32-bits of MSR value.\r
5204 @param EDX Upper 32-bits of MSR value.\r
5205\r
5206 <b>Example usage</b>\r
5207 @code\r
5208 UINT64 Msr;\r
5209\r
5210 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3);\r
5211 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr);\r
5212 @endcode\r
5213**/\r
5214#define MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7\r
5215\r
5216\r
5217/**\r
5218 Package. Uncore C-box 5 perfmon event select MSR.\r
5219\r
5220 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL4 (0x00000DB8)\r
5221 @param EAX Lower 32-bits of MSR value.\r
5222 @param EDX Upper 32-bits of MSR value.\r
5223\r
5224 <b>Example usage</b>\r
5225 @code\r
5226 UINT64 Msr;\r
5227\r
5228 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4);\r
5229 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr);\r
5230 @endcode\r
5231**/\r
5232#define MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8\r
5233\r
5234\r
5235/**\r
5236 Package. Uncore C-box 5 perfmon counter MSR.\r
5237\r
5238 @param ECX MSR_NEHALEM_C5_PMON_CTR4 (0x00000DB9)\r
5239 @param EAX Lower 32-bits of MSR value.\r
5240 @param EDX Upper 32-bits of MSR value.\r
5241\r
5242 <b>Example usage</b>\r
5243 @code\r
5244 UINT64 Msr;\r
5245\r
5246 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4);\r
5247 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr);\r
5248 @endcode\r
5249**/\r
5250#define MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9\r
5251\r
5252\r
5253/**\r
5254 Package. Uncore C-box 5 perfmon event select MSR.\r
5255\r
5256 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL5 (0x00000DBA)\r
5257 @param EAX Lower 32-bits of MSR value.\r
5258 @param EDX Upper 32-bits of MSR value.\r
5259\r
5260 <b>Example usage</b>\r
5261 @code\r
5262 UINT64 Msr;\r
5263\r
5264 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5);\r
5265 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr);\r
5266 @endcode\r
5267**/\r
5268#define MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA\r
5269\r
5270\r
5271/**\r
5272 Package. Uncore C-box 5 perfmon counter MSR.\r
5273\r
5274 @param ECX MSR_NEHALEM_C5_PMON_CTR5 (0x00000DBB)\r
5275 @param EAX Lower 32-bits of MSR value.\r
5276 @param EDX Upper 32-bits of MSR value.\r
5277\r
5278 <b>Example usage</b>\r
5279 @code\r
5280 UINT64 Msr;\r
5281\r
5282 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5);\r
5283 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr);\r
5284 @endcode\r
5285**/\r
5286#define MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB\r
5287\r
5288\r
5289/**\r
5290 Package. Uncore C-box 3 perfmon local box control MSR.\r
5291\r
5292 @param ECX MSR_NEHALEM_C3_PMON_BOX_CTRL (0x00000DC0)\r
5293 @param EAX Lower 32-bits of MSR value.\r
5294 @param EDX Upper 32-bits of MSR value.\r
5295\r
5296 <b>Example usage</b>\r
5297 @code\r
5298 UINT64 Msr;\r
5299\r
5300 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL);\r
5301 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr);\r
5302 @endcode\r
5303**/\r
5304#define MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0\r
5305\r
5306\r
5307/**\r
5308 Package. Uncore C-box 3 perfmon local box status MSR.\r
5309\r
5310 @param ECX MSR_NEHALEM_C3_PMON_BOX_STATUS (0x00000DC1)\r
5311 @param EAX Lower 32-bits of MSR value.\r
5312 @param EDX Upper 32-bits of MSR value.\r
5313\r
5314 <b>Example usage</b>\r
5315 @code\r
5316 UINT64 Msr;\r
5317\r
5318 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS);\r
5319 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr);\r
5320 @endcode\r
5321**/\r
5322#define MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1\r
5323\r
5324\r
5325/**\r
5326 Package. Uncore C-box 3 perfmon local box overflow control MSR.\r
5327\r
5328 @param ECX MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL (0x00000DC2)\r
5329 @param EAX Lower 32-bits of MSR value.\r
5330 @param EDX Upper 32-bits of MSR value.\r
5331\r
5332 <b>Example usage</b>\r
5333 @code\r
5334 UINT64 Msr;\r
5335\r
5336 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL);\r
5337 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr);\r
5338 @endcode\r
5339**/\r
5340#define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2\r
5341\r
5342\r
5343/**\r
5344 Package. Uncore C-box 3 perfmon event select MSR.\r
5345\r
5346 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL0 (0x00000DD0)\r
5347 @param EAX Lower 32-bits of MSR value.\r
5348 @param EDX Upper 32-bits of MSR value.\r
5349\r
5350 <b>Example usage</b>\r
5351 @code\r
5352 UINT64 Msr;\r
5353\r
5354 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0);\r
5355 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr);\r
5356 @endcode\r
5357**/\r
5358#define MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0\r
5359\r
5360\r
5361/**\r
5362 Package. Uncore C-box 3 perfmon counter MSR.\r
5363\r
5364 @param ECX MSR_NEHALEM_C3_PMON_CTR0 (0x00000DD1)\r
5365 @param EAX Lower 32-bits of MSR value.\r
5366 @param EDX Upper 32-bits of MSR value.\r
5367\r
5368 <b>Example usage</b>\r
5369 @code\r
5370 UINT64 Msr;\r
5371\r
5372 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0);\r
5373 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr);\r
5374 @endcode\r
5375**/\r
5376#define MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1\r
5377\r
5378\r
5379/**\r
5380 Package. Uncore C-box 3 perfmon event select MSR.\r
5381\r
5382 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL1 (0x00000DD2)\r
5383 @param EAX Lower 32-bits of MSR value.\r
5384 @param EDX Upper 32-bits of MSR value.\r
5385\r
5386 <b>Example usage</b>\r
5387 @code\r
5388 UINT64 Msr;\r
5389\r
5390 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1);\r
5391 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr);\r
5392 @endcode\r
5393**/\r
5394#define MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2\r
5395\r
5396\r
5397/**\r
5398 Package. Uncore C-box 3 perfmon counter MSR.\r
5399\r
5400 @param ECX MSR_NEHALEM_C3_PMON_CTR1 (0x00000DD3)\r
5401 @param EAX Lower 32-bits of MSR value.\r
5402 @param EDX Upper 32-bits of MSR value.\r
5403\r
5404 <b>Example usage</b>\r
5405 @code\r
5406 UINT64 Msr;\r
5407\r
5408 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1);\r
5409 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr);\r
5410 @endcode\r
5411**/\r
5412#define MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3\r
5413\r
5414\r
5415/**\r
5416 Package. Uncore C-box 3 perfmon event select MSR.\r
5417\r
5418 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL2 (0x00000DD4)\r
5419 @param EAX Lower 32-bits of MSR value.\r
5420 @param EDX Upper 32-bits of MSR value.\r
5421\r
5422 <b>Example usage</b>\r
5423 @code\r
5424 UINT64 Msr;\r
5425\r
5426 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2);\r
5427 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr);\r
5428 @endcode\r
5429**/\r
5430#define MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4\r
5431\r
5432\r
5433/**\r
5434 Package. Uncore C-box 3 perfmon counter MSR.\r
5435\r
5436 @param ECX MSR_NEHALEM_C3_PMON_CTR2 (0x00000DD5)\r
5437 @param EAX Lower 32-bits of MSR value.\r
5438 @param EDX Upper 32-bits of MSR value.\r
5439\r
5440 <b>Example usage</b>\r
5441 @code\r
5442 UINT64 Msr;\r
5443\r
5444 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2);\r
5445 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr);\r
5446 @endcode\r
5447**/\r
5448#define MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5\r
5449\r
5450\r
5451/**\r
5452 Package. Uncore C-box 3 perfmon event select MSR.\r
5453\r
5454 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL3 (0x00000DD6)\r
5455 @param EAX Lower 32-bits of MSR value.\r
5456 @param EDX Upper 32-bits of MSR value.\r
5457\r
5458 <b>Example usage</b>\r
5459 @code\r
5460 UINT64 Msr;\r
5461\r
5462 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3);\r
5463 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr);\r
5464 @endcode\r
5465**/\r
5466#define MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6\r
5467\r
5468\r
5469/**\r
5470 Package. Uncore C-box 3 perfmon counter MSR.\r
5471\r
5472 @param ECX MSR_NEHALEM_C3_PMON_CTR3 (0x00000DD7)\r
5473 @param EAX Lower 32-bits of MSR value.\r
5474 @param EDX Upper 32-bits of MSR value.\r
5475\r
5476 <b>Example usage</b>\r
5477 @code\r
5478 UINT64 Msr;\r
5479\r
5480 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3);\r
5481 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr);\r
5482 @endcode\r
5483**/\r
5484#define MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7\r
5485\r
5486\r
5487/**\r
5488 Package. Uncore C-box 3 perfmon event select MSR.\r
5489\r
5490 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL4 (0x00000DD8)\r
5491 @param EAX Lower 32-bits of MSR value.\r
5492 @param EDX Upper 32-bits of MSR value.\r
5493\r
5494 <b>Example usage</b>\r
5495 @code\r
5496 UINT64 Msr;\r
5497\r
5498 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4);\r
5499 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr);\r
5500 @endcode\r
5501**/\r
5502#define MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8\r
5503\r
5504\r
5505/**\r
5506 Package. Uncore C-box 3 perfmon counter MSR.\r
5507\r
5508 @param ECX MSR_NEHALEM_C3_PMON_CTR4 (0x00000DD9)\r
5509 @param EAX Lower 32-bits of MSR value.\r
5510 @param EDX Upper 32-bits of MSR value.\r
5511\r
5512 <b>Example usage</b>\r
5513 @code\r
5514 UINT64 Msr;\r
5515\r
5516 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4);\r
5517 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr);\r
5518 @endcode\r
5519**/\r
5520#define MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9\r
5521\r
5522\r
5523/**\r
5524 Package. Uncore C-box 3 perfmon event select MSR.\r
5525\r
5526 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL5 (0x00000DDA)\r
5527 @param EAX Lower 32-bits of MSR value.\r
5528 @param EDX Upper 32-bits of MSR value.\r
5529\r
5530 <b>Example usage</b>\r
5531 @code\r
5532 UINT64 Msr;\r
5533\r
5534 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5);\r
5535 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr);\r
5536 @endcode\r
5537**/\r
5538#define MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA\r
5539\r
5540\r
5541/**\r
5542 Package. Uncore C-box 3 perfmon counter MSR.\r
5543\r
5544 @param ECX MSR_NEHALEM_C3_PMON_CTR5 (0x00000DDB)\r
5545 @param EAX Lower 32-bits of MSR value.\r
5546 @param EDX Upper 32-bits of MSR value.\r
5547\r
5548 <b>Example usage</b>\r
5549 @code\r
5550 UINT64 Msr;\r
5551\r
5552 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5);\r
5553 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr);\r
5554 @endcode\r
5555**/\r
5556#define MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB\r
5557\r
5558\r
5559/**\r
5560 Package. Uncore C-box 7 perfmon local box control MSR.\r
5561\r
5562 @param ECX MSR_NEHALEM_C7_PMON_BOX_CTRL (0x00000DE0)\r
5563 @param EAX Lower 32-bits of MSR value.\r
5564 @param EDX Upper 32-bits of MSR value.\r
5565\r
5566 <b>Example usage</b>\r
5567 @code\r
5568 UINT64 Msr;\r
5569\r
5570 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL);\r
5571 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr);\r
5572 @endcode\r
5573**/\r
5574#define MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0\r
5575\r
5576\r
5577/**\r
5578 Package. Uncore C-box 7 perfmon local box status MSR.\r
5579\r
5580 @param ECX MSR_NEHALEM_C7_PMON_BOX_STATUS (0x00000DE1)\r
5581 @param EAX Lower 32-bits of MSR value.\r
5582 @param EDX Upper 32-bits of MSR value.\r
5583\r
5584 <b>Example usage</b>\r
5585 @code\r
5586 UINT64 Msr;\r
5587\r
5588 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS);\r
5589 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr);\r
5590 @endcode\r
5591**/\r
5592#define MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1\r
5593\r
5594\r
5595/**\r
5596 Package. Uncore C-box 7 perfmon local box overflow control MSR.\r
5597\r
5598 @param ECX MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL (0x00000DE2)\r
5599 @param EAX Lower 32-bits of MSR value.\r
5600 @param EDX Upper 32-bits of MSR value.\r
5601\r
5602 <b>Example usage</b>\r
5603 @code\r
5604 UINT64 Msr;\r
5605\r
5606 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL);\r
5607 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr);\r
5608 @endcode\r
5609**/\r
5610#define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2\r
5611\r
5612\r
5613/**\r
5614 Package. Uncore C-box 7 perfmon event select MSR.\r
5615\r
5616 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL0 (0x00000DF0)\r
5617 @param EAX Lower 32-bits of MSR value.\r
5618 @param EDX Upper 32-bits of MSR value.\r
5619\r
5620 <b>Example usage</b>\r
5621 @code\r
5622 UINT64 Msr;\r
5623\r
5624 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0);\r
5625 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr);\r
5626 @endcode\r
5627**/\r
5628#define MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0\r
5629\r
5630\r
5631/**\r
5632 Package. Uncore C-box 7 perfmon counter MSR.\r
5633\r
5634 @param ECX MSR_NEHALEM_C7_PMON_CTR0 (0x00000DF1)\r
5635 @param EAX Lower 32-bits of MSR value.\r
5636 @param EDX Upper 32-bits of MSR value.\r
5637\r
5638 <b>Example usage</b>\r
5639 @code\r
5640 UINT64 Msr;\r
5641\r
5642 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0);\r
5643 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr);\r
5644 @endcode\r
5645**/\r
5646#define MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1\r
5647\r
5648\r
5649/**\r
5650 Package. Uncore C-box 7 perfmon event select MSR.\r
5651\r
5652 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL1 (0x00000DF2)\r
5653 @param EAX Lower 32-bits of MSR value.\r
5654 @param EDX Upper 32-bits of MSR value.\r
5655\r
5656 <b>Example usage</b>\r
5657 @code\r
5658 UINT64 Msr;\r
5659\r
5660 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1);\r
5661 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr);\r
5662 @endcode\r
5663**/\r
5664#define MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2\r
5665\r
5666\r
5667/**\r
5668 Package. Uncore C-box 7 perfmon counter MSR.\r
5669\r
5670 @param ECX MSR_NEHALEM_C7_PMON_CTR1 (0x00000DF3)\r
5671 @param EAX Lower 32-bits of MSR value.\r
5672 @param EDX Upper 32-bits of MSR value.\r
5673\r
5674 <b>Example usage</b>\r
5675 @code\r
5676 UINT64 Msr;\r
5677\r
5678 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1);\r
5679 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr);\r
5680 @endcode\r
5681**/\r
5682#define MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3\r
5683\r
5684\r
5685/**\r
5686 Package. Uncore C-box 7 perfmon event select MSR.\r
5687\r
5688 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL2 (0x00000DF4)\r
5689 @param EAX Lower 32-bits of MSR value.\r
5690 @param EDX Upper 32-bits of MSR value.\r
5691\r
5692 <b>Example usage</b>\r
5693 @code\r
5694 UINT64 Msr;\r
5695\r
5696 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2);\r
5697 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr);\r
5698 @endcode\r
5699**/\r
5700#define MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4\r
5701\r
5702\r
5703/**\r
5704 Package. Uncore C-box 7 perfmon counter MSR.\r
5705\r
5706 @param ECX MSR_NEHALEM_C7_PMON_CTR2 (0x00000DF5)\r
5707 @param EAX Lower 32-bits of MSR value.\r
5708 @param EDX Upper 32-bits of MSR value.\r
5709\r
5710 <b>Example usage</b>\r
5711 @code\r
5712 UINT64 Msr;\r
5713\r
5714 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2);\r
5715 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr);\r
5716 @endcode\r
5717**/\r
5718#define MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5\r
5719\r
5720\r
5721/**\r
5722 Package. Uncore C-box 7 perfmon event select MSR.\r
5723\r
5724 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL3 (0x00000DF6)\r
5725 @param EAX Lower 32-bits of MSR value.\r
5726 @param EDX Upper 32-bits of MSR value.\r
5727\r
5728 <b>Example usage</b>\r
5729 @code\r
5730 UINT64 Msr;\r
5731\r
5732 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3);\r
5733 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr);\r
5734 @endcode\r
5735**/\r
5736#define MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6\r
5737\r
5738\r
5739/**\r
5740 Package. Uncore C-box 7 perfmon counter MSR.\r
5741\r
5742 @param ECX MSR_NEHALEM_C7_PMON_CTR3 (0x00000DF7)\r
5743 @param EAX Lower 32-bits of MSR value.\r
5744 @param EDX Upper 32-bits of MSR value.\r
5745\r
5746 <b>Example usage</b>\r
5747 @code\r
5748 UINT64 Msr;\r
5749\r
5750 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3);\r
5751 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr);\r
5752 @endcode\r
5753**/\r
5754#define MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7\r
5755\r
5756\r
5757/**\r
5758 Package. Uncore C-box 7 perfmon event select MSR.\r
5759\r
5760 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL4 (0x00000DF8)\r
5761 @param EAX Lower 32-bits of MSR value.\r
5762 @param EDX Upper 32-bits of MSR value.\r
5763\r
5764 <b>Example usage</b>\r
5765 @code\r
5766 UINT64 Msr;\r
5767\r
5768 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4);\r
5769 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr);\r
5770 @endcode\r
5771**/\r
5772#define MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8\r
5773\r
5774\r
5775/**\r
5776 Package. Uncore C-box 7 perfmon counter MSR.\r
5777\r
5778 @param ECX MSR_NEHALEM_C7_PMON_CTR4 (0x00000DF9)\r
5779 @param EAX Lower 32-bits of MSR value.\r
5780 @param EDX Upper 32-bits of MSR value.\r
5781\r
5782 <b>Example usage</b>\r
5783 @code\r
5784 UINT64 Msr;\r
5785\r
5786 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4);\r
5787 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr);\r
5788 @endcode\r
5789**/\r
5790#define MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9\r
5791\r
5792\r
5793/**\r
5794 Package. Uncore C-box 7 perfmon event select MSR.\r
5795\r
5796 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL5 (0x00000DFA)\r
5797 @param EAX Lower 32-bits of MSR value.\r
5798 @param EDX Upper 32-bits of MSR value.\r
5799\r
5800 <b>Example usage</b>\r
5801 @code\r
5802 UINT64 Msr;\r
5803\r
5804 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5);\r
5805 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr);\r
5806 @endcode\r
5807**/\r
5808#define MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA\r
5809\r
5810\r
5811/**\r
5812 Package. Uncore C-box 7 perfmon counter MSR.\r
5813\r
5814 @param ECX MSR_NEHALEM_C7_PMON_CTR5 (0x00000DFB)\r
5815 @param EAX Lower 32-bits of MSR value.\r
5816 @param EDX Upper 32-bits of MSR value.\r
5817\r
5818 <b>Example usage</b>\r
5819 @code\r
5820 UINT64 Msr;\r
5821\r
5822 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5);\r
5823 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr);\r
5824 @endcode\r
5825**/\r
5826#define MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB\r
5827\r
5828\r
5829/**\r
5830 Package. Uncore R-box 0 perfmon local box control MSR.\r
5831\r
5832 @param ECX MSR_NEHALEM_R0_PMON_BOX_CTRL (0x00000E00)\r
5833 @param EAX Lower 32-bits of MSR value.\r
5834 @param EDX Upper 32-bits of MSR value.\r
5835\r
5836 <b>Example usage</b>\r
5837 @code\r
5838 UINT64 Msr;\r
5839\r
5840 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL);\r
5841 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr);\r
5842 @endcode\r
5843**/\r
5844#define MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00\r
5845\r
5846\r
5847/**\r
5848 Package. Uncore R-box 0 perfmon local box status MSR.\r
5849\r
5850 @param ECX MSR_NEHALEM_R0_PMON_BOX_STATUS (0x00000E01)\r
5851 @param EAX Lower 32-bits of MSR value.\r
5852 @param EDX Upper 32-bits of MSR value.\r
5853\r
5854 <b>Example usage</b>\r
5855 @code\r
5856 UINT64 Msr;\r
5857\r
5858 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS);\r
5859 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr);\r
5860 @endcode\r
5861**/\r
5862#define MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01\r
5863\r
5864\r
5865/**\r
5866 Package. Uncore R-box 0 perfmon local box overflow control MSR.\r
5867\r
5868 @param ECX MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL (0x00000E02)\r
5869 @param EAX Lower 32-bits of MSR value.\r
5870 @param EDX Upper 32-bits of MSR value.\r
5871\r
5872 <b>Example usage</b>\r
5873 @code\r
5874 UINT64 Msr;\r
5875\r
5876 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL);\r
5877 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr);\r
5878 @endcode\r
5879**/\r
5880#define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02\r
5881\r
5882\r
5883/**\r
5884 Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.\r
5885\r
5886 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P0 (0x00000E04)\r
5887 @param EAX Lower 32-bits of MSR value.\r
5888 @param EDX Upper 32-bits of MSR value.\r
5889\r
5890 <b>Example usage</b>\r
5891 @code\r
5892 UINT64 Msr;\r
5893\r
5894 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0);\r
5895 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr);\r
5896 @endcode\r
5897**/\r
5898#define MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04\r
5899\r
5900\r
5901/**\r
5902 Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.\r
5903\r
5904 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P1 (0x00000E05)\r
5905 @param EAX Lower 32-bits of MSR value.\r
5906 @param EDX Upper 32-bits of MSR value.\r
5907\r
5908 <b>Example usage</b>\r
5909 @code\r
5910 UINT64 Msr;\r
5911\r
5912 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1);\r
5913 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr);\r
5914 @endcode\r
5915**/\r
5916#define MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05\r
5917\r
5918\r
5919/**\r
5920 Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.\r
5921\r
5922 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P2 (0x00000E06)\r
5923 @param EAX Lower 32-bits of MSR value.\r
5924 @param EDX Upper 32-bits of MSR value.\r
5925\r
5926 <b>Example usage</b>\r
5927 @code\r
5928 UINT64 Msr;\r
5929\r
5930 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2);\r
5931 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr);\r
5932 @endcode\r
5933**/\r
5934#define MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06\r
5935\r
5936\r
5937/**\r
5938 Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.\r
5939\r
5940 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P3 (0x00000E07)\r
5941 @param EAX Lower 32-bits of MSR value.\r
5942 @param EDX Upper 32-bits of MSR value.\r
5943\r
5944 <b>Example usage</b>\r
5945 @code\r
5946 UINT64 Msr;\r
5947\r
5948 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3);\r
5949 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr);\r
5950 @endcode\r
5951**/\r
5952#define MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07\r
5953\r
5954\r
5955/**\r
5956 Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.\r
5957\r
5958 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P4 (0x00000E08)\r
5959 @param EAX Lower 32-bits of MSR value.\r
5960 @param EDX Upper 32-bits of MSR value.\r
5961\r
5962 <b>Example usage</b>\r
5963 @code\r
5964 UINT64 Msr;\r
5965\r
5966 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4);\r
5967 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr);\r
5968 @endcode\r
5969**/\r
5970#define MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08\r
5971\r
5972\r
5973/**\r
5974 Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.\r
5975\r
5976 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P5 (0x00000E09)\r
5977 @param EAX Lower 32-bits of MSR value.\r
5978 @param EDX Upper 32-bits of MSR value.\r
5979\r
5980 <b>Example usage</b>\r
5981 @code\r
5982 UINT64 Msr;\r
5983\r
5984 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5);\r
5985 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr);\r
5986 @endcode\r
5987**/\r
5988#define MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09\r
5989\r
5990\r
5991/**\r
5992 Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.\r
5993\r
5994 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P6 (0x00000E0A)\r
5995 @param EAX Lower 32-bits of MSR value.\r
5996 @param EDX Upper 32-bits of MSR value.\r
5997\r
5998 <b>Example usage</b>\r
5999 @code\r
6000 UINT64 Msr;\r
6001\r
6002 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6);\r
6003 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr);\r
6004 @endcode\r
6005**/\r
6006#define MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A\r
6007\r
6008\r
6009/**\r
6010 Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.\r
6011\r
6012 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P7 (0x00000E0B)\r
6013 @param EAX Lower 32-bits of MSR value.\r
6014 @param EDX Upper 32-bits of MSR value.\r
6015\r
6016 <b>Example usage</b>\r
6017 @code\r
6018 UINT64 Msr;\r
6019\r
6020 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7);\r
6021 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr);\r
6022 @endcode\r
6023**/\r
6024#define MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B\r
6025\r
6026\r
6027/**\r
6028 Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR.\r
6029\r
6030 @param ECX MSR_NEHALEM_R0_PMON_QLX_P0 (0x00000E0C)\r
6031 @param EAX Lower 32-bits of MSR value.\r
6032 @param EDX Upper 32-bits of MSR value.\r
6033\r
6034 <b>Example usage</b>\r
6035 @code\r
6036 UINT64 Msr;\r
6037\r
6038 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0);\r
6039 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr);\r
6040 @endcode\r
6041**/\r
6042#define MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C\r
6043\r
6044\r
6045/**\r
6046 Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR.\r
6047\r
6048 @param ECX MSR_NEHALEM_R0_PMON_QLX_P1 (0x00000E0D)\r
6049 @param EAX Lower 32-bits of MSR value.\r
6050 @param EDX Upper 32-bits of MSR value.\r
6051\r
6052 <b>Example usage</b>\r
6053 @code\r
6054 UINT64 Msr;\r
6055\r
6056 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1);\r
6057 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr);\r
6058 @endcode\r
6059**/\r
6060#define MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D\r
6061\r
6062\r
6063/**\r
6064 Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR.\r
6065\r
6066 @param ECX MSR_NEHALEM_R0_PMON_QLX_P2 (0x00000E0E)\r
6067 @param EAX Lower 32-bits of MSR value.\r
6068 @param EDX Upper 32-bits of MSR value.\r
6069\r
6070 <b>Example usage</b>\r
6071 @code\r
6072 UINT64 Msr;\r
6073\r
6074 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2);\r
6075 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr);\r
6076 @endcode\r
6077**/\r
6078#define MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E\r
6079\r
6080\r
6081/**\r
6082 Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR.\r
6083\r
6084 @param ECX MSR_NEHALEM_R0_PMON_QLX_P3 (0x00000E0F)\r
6085 @param EAX Lower 32-bits of MSR value.\r
6086 @param EDX Upper 32-bits of MSR value.\r
6087\r
6088 <b>Example usage</b>\r
6089 @code\r
6090 UINT64 Msr;\r
6091\r
6092 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3);\r
6093 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr);\r
6094 @endcode\r
6095**/\r
6096#define MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F\r
6097\r
6098\r
6099/**\r
6100 Package. Uncore R-box 0 perfmon event select MSR.\r
6101\r
6102 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL0 (0x00000E10)\r
6103 @param EAX Lower 32-bits of MSR value.\r
6104 @param EDX Upper 32-bits of MSR value.\r
6105\r
6106 <b>Example usage</b>\r
6107 @code\r
6108 UINT64 Msr;\r
6109\r
6110 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0);\r
6111 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr);\r
6112 @endcode\r
6113**/\r
6114#define MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10\r
6115\r
6116\r
6117/**\r
6118 Package. Uncore R-box 0 perfmon counter MSR.\r
6119\r
6120 @param ECX MSR_NEHALEM_R0_PMON_CTR0 (0x00000E11)\r
6121 @param EAX Lower 32-bits of MSR value.\r
6122 @param EDX Upper 32-bits of MSR value.\r
6123\r
6124 <b>Example usage</b>\r
6125 @code\r
6126 UINT64 Msr;\r
6127\r
6128 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0);\r
6129 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr);\r
6130 @endcode\r
6131**/\r
6132#define MSR_NEHALEM_R0_PMON_CTR0 0x00000E11\r
6133\r
6134\r
6135/**\r
6136 Package. Uncore R-box 0 perfmon event select MSR.\r
6137\r
6138 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL1 (0x00000E12)\r
6139 @param EAX Lower 32-bits of MSR value.\r
6140 @param EDX Upper 32-bits of MSR value.\r
6141\r
6142 <b>Example usage</b>\r
6143 @code\r
6144 UINT64 Msr;\r
6145\r
6146 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1);\r
6147 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr);\r
6148 @endcode\r
6149**/\r
6150#define MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12\r
6151\r
6152\r
6153/**\r
6154 Package. Uncore R-box 0 perfmon counter MSR.\r
6155\r
6156 @param ECX MSR_NEHALEM_R0_PMON_CTR1 (0x00000E13)\r
6157 @param EAX Lower 32-bits of MSR value.\r
6158 @param EDX Upper 32-bits of MSR value.\r
6159\r
6160 <b>Example usage</b>\r
6161 @code\r
6162 UINT64 Msr;\r
6163\r
6164 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1);\r
6165 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr);\r
6166 @endcode\r
6167**/\r
6168#define MSR_NEHALEM_R0_PMON_CTR1 0x00000E13\r
6169\r
6170\r
6171/**\r
6172 Package. Uncore R-box 0 perfmon event select MSR.\r
6173\r
6174 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL2 (0x00000E14)\r
6175 @param EAX Lower 32-bits of MSR value.\r
6176 @param EDX Upper 32-bits of MSR value.\r
6177\r
6178 <b>Example usage</b>\r
6179 @code\r
6180 UINT64 Msr;\r
6181\r
6182 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2);\r
6183 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr);\r
6184 @endcode\r
6185**/\r
6186#define MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14\r
6187\r
6188\r
6189/**\r
6190 Package. Uncore R-box 0 perfmon counter MSR.\r
6191\r
6192 @param ECX MSR_NEHALEM_R0_PMON_CTR2 (0x00000E15)\r
6193 @param EAX Lower 32-bits of MSR value.\r
6194 @param EDX Upper 32-bits of MSR value.\r
6195\r
6196 <b>Example usage</b>\r
6197 @code\r
6198 UINT64 Msr;\r
6199\r
6200 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2);\r
6201 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr);\r
6202 @endcode\r
6203**/\r
6204#define MSR_NEHALEM_R0_PMON_CTR2 0x00000E15\r
6205\r
6206\r
6207/**\r
6208 Package. Uncore R-box 0 perfmon event select MSR.\r
6209\r
6210 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL3 (0x00000E16)\r
6211 @param EAX Lower 32-bits of MSR value.\r
6212 @param EDX Upper 32-bits of MSR value.\r
6213\r
6214 <b>Example usage</b>\r
6215 @code\r
6216 UINT64 Msr;\r
6217\r
6218 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3);\r
6219 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr);\r
6220 @endcode\r
6221**/\r
6222#define MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16\r
6223\r
6224\r
6225/**\r
6226 Package. Uncore R-box 0 perfmon counter MSR.\r
6227\r
6228 @param ECX MSR_NEHALEM_R0_PMON_CTR3 (0x00000E17)\r
6229 @param EAX Lower 32-bits of MSR value.\r
6230 @param EDX Upper 32-bits of MSR value.\r
6231\r
6232 <b>Example usage</b>\r
6233 @code\r
6234 UINT64 Msr;\r
6235\r
6236 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3);\r
6237 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr);\r
6238 @endcode\r
6239**/\r
6240#define MSR_NEHALEM_R0_PMON_CTR3 0x00000E17\r
6241\r
6242\r
6243/**\r
6244 Package. Uncore R-box 0 perfmon event select MSR.\r
6245\r
6246 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL4 (0x00000E18)\r
6247 @param EAX Lower 32-bits of MSR value.\r
6248 @param EDX Upper 32-bits of MSR value.\r
6249\r
6250 <b>Example usage</b>\r
6251 @code\r
6252 UINT64 Msr;\r
6253\r
6254 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4);\r
6255 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr);\r
6256 @endcode\r
6257**/\r
6258#define MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18\r
6259\r
6260\r
6261/**\r
6262 Package. Uncore R-box 0 perfmon counter MSR.\r
6263\r
6264 @param ECX MSR_NEHALEM_R0_PMON_CTR4 (0x00000E19)\r
6265 @param EAX Lower 32-bits of MSR value.\r
6266 @param EDX Upper 32-bits of MSR value.\r
6267\r
6268 <b>Example usage</b>\r
6269 @code\r
6270 UINT64 Msr;\r
6271\r
6272 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4);\r
6273 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr);\r
6274 @endcode\r
6275**/\r
6276#define MSR_NEHALEM_R0_PMON_CTR4 0x00000E19\r
6277\r
6278\r
6279/**\r
6280 Package. Uncore R-box 0 perfmon event select MSR.\r
6281\r
6282 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL5 (0x00000E1A)\r
6283 @param EAX Lower 32-bits of MSR value.\r
6284 @param EDX Upper 32-bits of MSR value.\r
6285\r
6286 <b>Example usage</b>\r
6287 @code\r
6288 UINT64 Msr;\r
6289\r
6290 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5);\r
6291 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr);\r
6292 @endcode\r
6293**/\r
6294#define MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A\r
6295\r
6296\r
6297/**\r
6298 Package. Uncore R-box 0 perfmon counter MSR.\r
6299\r
6300 @param ECX MSR_NEHALEM_R0_PMON_CTR5 (0x00000E1B)\r
6301 @param EAX Lower 32-bits of MSR value.\r
6302 @param EDX Upper 32-bits of MSR value.\r
6303\r
6304 <b>Example usage</b>\r
6305 @code\r
6306 UINT64 Msr;\r
6307\r
6308 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5);\r
6309 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr);\r
6310 @endcode\r
6311**/\r
6312#define MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B\r
6313\r
6314\r
6315/**\r
6316 Package. Uncore R-box 0 perfmon event select MSR.\r
6317\r
6318 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL6 (0x00000E1C)\r
6319 @param EAX Lower 32-bits of MSR value.\r
6320 @param EDX Upper 32-bits of MSR value.\r
6321\r
6322 <b>Example usage</b>\r
6323 @code\r
6324 UINT64 Msr;\r
6325\r
6326 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6);\r
6327 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr);\r
6328 @endcode\r
6329**/\r
6330#define MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C\r
6331\r
6332\r
6333/**\r
6334 Package. Uncore R-box 0 perfmon counter MSR.\r
6335\r
6336 @param ECX MSR_NEHALEM_R0_PMON_CTR6 (0x00000E1D)\r
6337 @param EAX Lower 32-bits of MSR value.\r
6338 @param EDX Upper 32-bits of MSR value.\r
6339\r
6340 <b>Example usage</b>\r
6341 @code\r
6342 UINT64 Msr;\r
6343\r
6344 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6);\r
6345 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr);\r
6346 @endcode\r
6347**/\r
6348#define MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D\r
6349\r
6350\r
6351/**\r
6352 Package. Uncore R-box 0 perfmon event select MSR.\r
6353\r
6354 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL7 (0x00000E1E)\r
6355 @param EAX Lower 32-bits of MSR value.\r
6356 @param EDX Upper 32-bits of MSR value.\r
6357\r
6358 <b>Example usage</b>\r
6359 @code\r
6360 UINT64 Msr;\r
6361\r
6362 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7);\r
6363 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr);\r
6364 @endcode\r
6365**/\r
6366#define MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E\r
6367\r
6368\r
6369/**\r
6370 Package. Uncore R-box 0 perfmon counter MSR.\r
6371\r
6372 @param ECX MSR_NEHALEM_R0_PMON_CTR7 (0x00000E1F)\r
6373 @param EAX Lower 32-bits of MSR value.\r
6374 @param EDX Upper 32-bits of MSR value.\r
6375\r
6376 <b>Example usage</b>\r
6377 @code\r
6378 UINT64 Msr;\r
6379\r
6380 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7);\r
6381 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr);\r
6382 @endcode\r
6383**/\r
6384#define MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F\r
6385\r
6386\r
6387/**\r
6388 Package. Uncore R-box 1 perfmon local box control MSR.\r
6389\r
6390 @param ECX MSR_NEHALEM_R1_PMON_BOX_CTRL (0x00000E20)\r
6391 @param EAX Lower 32-bits of MSR value.\r
6392 @param EDX Upper 32-bits of MSR value.\r
6393\r
6394 <b>Example usage</b>\r
6395 @code\r
6396 UINT64 Msr;\r
6397\r
6398 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL);\r
6399 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr);\r
6400 @endcode\r
6401**/\r
6402#define MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20\r
6403\r
6404\r
6405/**\r
6406 Package. Uncore R-box 1 perfmon local box status MSR.\r
6407\r
6408 @param ECX MSR_NEHALEM_R1_PMON_BOX_STATUS (0x00000E21)\r
6409 @param EAX Lower 32-bits of MSR value.\r
6410 @param EDX Upper 32-bits of MSR value.\r
6411\r
6412 <b>Example usage</b>\r
6413 @code\r
6414 UINT64 Msr;\r
6415\r
6416 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS);\r
6417 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr);\r
6418 @endcode\r
6419**/\r
6420#define MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21\r
6421\r
6422\r
6423/**\r
6424 Package. Uncore R-box 1 perfmon local box overflow control MSR.\r
6425\r
6426 @param ECX MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL (0x00000E22)\r
6427 @param EAX Lower 32-bits of MSR value.\r
6428 @param EDX Upper 32-bits of MSR value.\r
6429\r
6430 <b>Example usage</b>\r
6431 @code\r
6432 UINT64 Msr;\r
6433\r
6434 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL);\r
6435 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr);\r
6436 @endcode\r
6437**/\r
6438#define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22\r
6439\r
6440\r
6441/**\r
6442 Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.\r
6443\r
6444 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P8 (0x00000E24)\r
6445 @param EAX Lower 32-bits of MSR value.\r
6446 @param EDX Upper 32-bits of MSR value.\r
6447\r
6448 <b>Example usage</b>\r
6449 @code\r
6450 UINT64 Msr;\r
6451\r
6452 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8);\r
6453 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr);\r
6454 @endcode\r
6455**/\r
6456#define MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24\r
6457\r
6458\r
6459/**\r
6460 Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.\r
6461\r
6462 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P9 (0x00000E25)\r
6463 @param EAX Lower 32-bits of MSR value.\r
6464 @param EDX Upper 32-bits of MSR value.\r
6465\r
6466 <b>Example usage</b>\r
6467 @code\r
6468 UINT64 Msr;\r
6469\r
6470 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9);\r
6471 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr);\r
6472 @endcode\r
6473**/\r
6474#define MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25\r
6475\r
6476\r
6477/**\r
6478 Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.\r
6479\r
6480 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P10 (0x00000E26)\r
6481 @param EAX Lower 32-bits of MSR value.\r
6482 @param EDX Upper 32-bits of MSR value.\r
6483\r
6484 <b>Example usage</b>\r
6485 @code\r
6486 UINT64 Msr;\r
6487\r
6488 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10);\r
6489 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr);\r
6490 @endcode\r
6491**/\r
6492#define MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26\r
6493\r
6494\r
6495/**\r
6496 Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.\r
6497\r
6498 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P11 (0x00000E27)\r
6499 @param EAX Lower 32-bits of MSR value.\r
6500 @param EDX Upper 32-bits of MSR value.\r
6501\r
6502 <b>Example usage</b>\r
6503 @code\r
6504 UINT64 Msr;\r
6505\r
6506 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11);\r
6507 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr);\r
6508 @endcode\r
6509**/\r
6510#define MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27\r
6511\r
6512\r
6513/**\r
6514 Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.\r
6515\r
6516 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P12 (0x00000E28)\r
6517 @param EAX Lower 32-bits of MSR value.\r
6518 @param EDX Upper 32-bits of MSR value.\r
6519\r
6520 <b>Example usage</b>\r
6521 @code\r
6522 UINT64 Msr;\r
6523\r
6524 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12);\r
6525 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr);\r
6526 @endcode\r
6527**/\r
6528#define MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28\r
6529\r
6530\r
6531/**\r
6532 Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.\r
6533\r
6534 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P13 (0x00000E29)\r
6535 @param EAX Lower 32-bits of MSR value.\r
6536 @param EDX Upper 32-bits of MSR value.\r
6537\r
6538 <b>Example usage</b>\r
6539 @code\r
6540 UINT64 Msr;\r
6541\r
6542 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13);\r
6543 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr);\r
6544 @endcode\r
6545**/\r
6546#define MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29\r
6547\r
6548\r
6549/**\r
6550 Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.\r
6551\r
6552 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P14 (0x00000E2A)\r
6553 @param EAX Lower 32-bits of MSR value.\r
6554 @param EDX Upper 32-bits of MSR value.\r
6555\r
6556 <b>Example usage</b>\r
6557 @code\r
6558 UINT64 Msr;\r
6559\r
6560 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14);\r
6561 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr);\r
6562 @endcode\r
6563**/\r
6564#define MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A\r
6565\r
6566\r
6567/**\r
6568 Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.\r
6569\r
6570 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P15 (0x00000E2B)\r
6571 @param EAX Lower 32-bits of MSR value.\r
6572 @param EDX Upper 32-bits of MSR value.\r
6573\r
6574 <b>Example usage</b>\r
6575 @code\r
6576 UINT64 Msr;\r
6577\r
6578 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15);\r
6579 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr);\r
6580 @endcode\r
6581**/\r
6582#define MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B\r
6583\r
6584\r
6585/**\r
6586 Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR.\r
6587\r
6588 @param ECX MSR_NEHALEM_R1_PMON_QLX_P4 (0x00000E2C)\r
6589 @param EAX Lower 32-bits of MSR value.\r
6590 @param EDX Upper 32-bits of MSR value.\r
6591\r
6592 <b>Example usage</b>\r
6593 @code\r
6594 UINT64 Msr;\r
6595\r
6596 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4);\r
6597 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr);\r
6598 @endcode\r
6599**/\r
6600#define MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C\r
6601\r
6602\r
6603/**\r
6604 Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR.\r
6605\r
6606 @param ECX MSR_NEHALEM_R1_PMON_QLX_P5 (0x00000E2D)\r
6607 @param EAX Lower 32-bits of MSR value.\r
6608 @param EDX Upper 32-bits of MSR value.\r
6609\r
6610 <b>Example usage</b>\r
6611 @code\r
6612 UINT64 Msr;\r
6613\r
6614 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5);\r
6615 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr);\r
6616 @endcode\r
6617**/\r
6618#define MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D\r
6619\r
6620\r
6621/**\r
6622 Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR.\r
6623\r
6624 @param ECX MSR_NEHALEM_R1_PMON_QLX_P6 (0x00000E2E)\r
6625 @param EAX Lower 32-bits of MSR value.\r
6626 @param EDX Upper 32-bits of MSR value.\r
6627\r
6628 <b>Example usage</b>\r
6629 @code\r
6630 UINT64 Msr;\r
6631\r
6632 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6);\r
6633 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr);\r
6634 @endcode\r
6635**/\r
6636#define MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E\r
6637\r
6638\r
6639/**\r
6640 Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR.\r
6641\r
6642 @param ECX MSR_NEHALEM_R1_PMON_QLX_P7 (0x00000E2F)\r
6643 @param EAX Lower 32-bits of MSR value.\r
6644 @param EDX Upper 32-bits of MSR value.\r
6645\r
6646 <b>Example usage</b>\r
6647 @code\r
6648 UINT64 Msr;\r
6649\r
6650 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7);\r
6651 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr);\r
6652 @endcode\r
6653**/\r
6654#define MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F\r
6655\r
6656\r
6657/**\r
6658 Package. Uncore R-box 1 perfmon event select MSR.\r
6659\r
6660 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL8 (0x00000E30)\r
6661 @param EAX Lower 32-bits of MSR value.\r
6662 @param EDX Upper 32-bits of MSR value.\r
6663\r
6664 <b>Example usage</b>\r
6665 @code\r
6666 UINT64 Msr;\r
6667\r
6668 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8);\r
6669 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr);\r
6670 @endcode\r
6671**/\r
6672#define MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30\r
6673\r
6674\r
6675/**\r
6676 Package. Uncore R-box 1 perfmon counter MSR.\r
6677\r
6678 @param ECX MSR_NEHALEM_R1_PMON_CTR8 (0x00000E31)\r
6679 @param EAX Lower 32-bits of MSR value.\r
6680 @param EDX Upper 32-bits of MSR value.\r
6681\r
6682 <b>Example usage</b>\r
6683 @code\r
6684 UINT64 Msr;\r
6685\r
6686 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8);\r
6687 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr);\r
6688 @endcode\r
6689**/\r
6690#define MSR_NEHALEM_R1_PMON_CTR8 0x00000E31\r
6691\r
6692\r
6693/**\r
6694 Package. Uncore R-box 1 perfmon event select MSR.\r
6695\r
6696 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL9 (0x00000E32)\r
6697 @param EAX Lower 32-bits of MSR value.\r
6698 @param EDX Upper 32-bits of MSR value.\r
6699\r
6700 <b>Example usage</b>\r
6701 @code\r
6702 UINT64 Msr;\r
6703\r
6704 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9);\r
6705 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr);\r
6706 @endcode\r
6707**/\r
6708#define MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32\r
6709\r
6710\r
6711/**\r
6712 Package. Uncore R-box 1 perfmon counter MSR.\r
6713\r
6714 @param ECX MSR_NEHALEM_R1_PMON_CTR9 (0x00000E33)\r
6715 @param EAX Lower 32-bits of MSR value.\r
6716 @param EDX Upper 32-bits of MSR value.\r
6717\r
6718 <b>Example usage</b>\r
6719 @code\r
6720 UINT64 Msr;\r
6721\r
6722 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9);\r
6723 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr);\r
6724 @endcode\r
6725**/\r
6726#define MSR_NEHALEM_R1_PMON_CTR9 0x00000E33\r
6727\r
6728\r
6729/**\r
6730 Package. Uncore R-box 1 perfmon event select MSR.\r
6731\r
6732 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL10 (0x00000E34)\r
6733 @param EAX Lower 32-bits of MSR value.\r
6734 @param EDX Upper 32-bits of MSR value.\r
6735\r
6736 <b>Example usage</b>\r
6737 @code\r
6738 UINT64 Msr;\r
6739\r
6740 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10);\r
6741 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr);\r
6742 @endcode\r
6743**/\r
6744#define MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34\r
6745\r
6746\r
6747/**\r
6748 Package. Uncore R-box 1 perfmon counter MSR.\r
6749\r
6750 @param ECX MSR_NEHALEM_R1_PMON_CTR10 (0x00000E35)\r
6751 @param EAX Lower 32-bits of MSR value.\r
6752 @param EDX Upper 32-bits of MSR value.\r
6753\r
6754 <b>Example usage</b>\r
6755 @code\r
6756 UINT64 Msr;\r
6757\r
6758 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10);\r
6759 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr);\r
6760 @endcode\r
6761**/\r
6762#define MSR_NEHALEM_R1_PMON_CTR10 0x00000E35\r
6763\r
6764\r
6765/**\r
6766 Package. Uncore R-box 1 perfmon event select MSR.\r
6767\r
6768 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL11 (0x00000E36)\r
6769 @param EAX Lower 32-bits of MSR value.\r
6770 @param EDX Upper 32-bits of MSR value.\r
6771\r
6772 <b>Example usage</b>\r
6773 @code\r
6774 UINT64 Msr;\r
6775\r
6776 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11);\r
6777 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr);\r
6778 @endcode\r
6779**/\r
6780#define MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36\r
6781\r
6782\r
6783/**\r
6784 Package. Uncore R-box 1 perfmon counter MSR.\r
6785\r
6786 @param ECX MSR_NEHALEM_R1_PMON_CTR11 (0x00000E37)\r
6787 @param EAX Lower 32-bits of MSR value.\r
6788 @param EDX Upper 32-bits of MSR value.\r
6789\r
6790 <b>Example usage</b>\r
6791 @code\r
6792 UINT64 Msr;\r
6793\r
6794 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11);\r
6795 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr);\r
6796 @endcode\r
6797**/\r
6798#define MSR_NEHALEM_R1_PMON_CTR11 0x00000E37\r
6799\r
6800\r
6801/**\r
6802 Package. Uncore R-box 1 perfmon event select MSR.\r
6803\r
6804 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL12 (0x00000E38)\r
6805 @param EAX Lower 32-bits of MSR value.\r
6806 @param EDX Upper 32-bits of MSR value.\r
6807\r
6808 <b>Example usage</b>\r
6809 @code\r
6810 UINT64 Msr;\r
6811\r
6812 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12);\r
6813 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr);\r
6814 @endcode\r
6815**/\r
6816#define MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38\r
6817\r
6818\r
6819/**\r
6820 Package. Uncore R-box 1 perfmon counter MSR.\r
6821\r
6822 @param ECX MSR_NEHALEM_R1_PMON_CTR12 (0x00000E39)\r
6823 @param EAX Lower 32-bits of MSR value.\r
6824 @param EDX Upper 32-bits of MSR value.\r
6825\r
6826 <b>Example usage</b>\r
6827 @code\r
6828 UINT64 Msr;\r
6829\r
6830 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12);\r
6831 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr);\r
6832 @endcode\r
6833**/\r
6834#define MSR_NEHALEM_R1_PMON_CTR12 0x00000E39\r
6835\r
6836\r
6837/**\r
6838 Package. Uncore R-box 1 perfmon event select MSR.\r
6839\r
6840 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL13 (0x00000E3A)\r
6841 @param EAX Lower 32-bits of MSR value.\r
6842 @param EDX Upper 32-bits of MSR value.\r
6843\r
6844 <b>Example usage</b>\r
6845 @code\r
6846 UINT64 Msr;\r
6847\r
6848 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13);\r
6849 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr);\r
6850 @endcode\r
6851**/\r
6852#define MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A\r
6853\r
6854\r
6855/**\r
6856 Package. Uncore R-box 1perfmon counter MSR.\r
6857\r
6858 @param ECX MSR_NEHALEM_R1_PMON_CTR13 (0x00000E3B)\r
6859 @param EAX Lower 32-bits of MSR value.\r
6860 @param EDX Upper 32-bits of MSR value.\r
6861\r
6862 <b>Example usage</b>\r
6863 @code\r
6864 UINT64 Msr;\r
6865\r
6866 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13);\r
6867 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr);\r
6868 @endcode\r
6869**/\r
6870#define MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B\r
6871\r
6872\r
6873/**\r
6874 Package. Uncore R-box 1 perfmon event select MSR.\r
6875\r
6876 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL14 (0x00000E3C)\r
6877 @param EAX Lower 32-bits of MSR value.\r
6878 @param EDX Upper 32-bits of MSR value.\r
6879\r
6880 <b>Example usage</b>\r
6881 @code\r
6882 UINT64 Msr;\r
6883\r
6884 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14);\r
6885 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr);\r
6886 @endcode\r
6887**/\r
6888#define MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C\r
6889\r
6890\r
6891/**\r
6892 Package. Uncore R-box 1 perfmon counter MSR.\r
6893\r
6894 @param ECX MSR_NEHALEM_R1_PMON_CTR14 (0x00000E3D)\r
6895 @param EAX Lower 32-bits of MSR value.\r
6896 @param EDX Upper 32-bits of MSR value.\r
6897\r
6898 <b>Example usage</b>\r
6899 @code\r
6900 UINT64 Msr;\r
6901\r
6902 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14);\r
6903 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr);\r
6904 @endcode\r
6905**/\r
6906#define MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D\r
6907\r
6908\r
6909/**\r
6910 Package. Uncore R-box 1 perfmon event select MSR.\r
6911\r
6912 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL15 (0x00000E3E)\r
6913 @param EAX Lower 32-bits of MSR value.\r
6914 @param EDX Upper 32-bits of MSR value.\r
6915\r
6916 <b>Example usage</b>\r
6917 @code\r
6918 UINT64 Msr;\r
6919\r
6920 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15);\r
6921 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr);\r
6922 @endcode\r
6923**/\r
6924#define MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E\r
6925\r
6926\r
6927/**\r
6928 Package. Uncore R-box 1 perfmon counter MSR.\r
6929\r
6930 @param ECX MSR_NEHALEM_R1_PMON_CTR15 (0x00000E3F)\r
6931 @param EAX Lower 32-bits of MSR value.\r
6932 @param EDX Upper 32-bits of MSR value.\r
6933\r
6934 <b>Example usage</b>\r
6935 @code\r
6936 UINT64 Msr;\r
6937\r
6938 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15);\r
6939 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr);\r
6940 @endcode\r
6941**/\r
6942#define MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F\r
6943\r
6944\r
6945/**\r
6946 Package. Uncore B-box 0 perfmon local box match MSR.\r
6947\r
6948 @param ECX MSR_NEHALEM_B0_PMON_MATCH (0x00000E45)\r
6949 @param EAX Lower 32-bits of MSR value.\r
6950 @param EDX Upper 32-bits of MSR value.\r
6951\r
6952 <b>Example usage</b>\r
6953 @code\r
6954 UINT64 Msr;\r
6955\r
6956 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH);\r
6957 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr);\r
6958 @endcode\r
6959**/\r
6960#define MSR_NEHALEM_B0_PMON_MATCH 0x00000E45\r
6961\r
6962\r
6963/**\r
6964 Package. Uncore B-box 0 perfmon local box mask MSR.\r
6965\r
6966 @param ECX MSR_NEHALEM_B0_PMON_MASK (0x00000E46)\r
6967 @param EAX Lower 32-bits of MSR value.\r
6968 @param EDX Upper 32-bits of MSR value.\r
6969\r
6970 <b>Example usage</b>\r
6971 @code\r
6972 UINT64 Msr;\r
6973\r
6974 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK);\r
6975 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr);\r
6976 @endcode\r
6977**/\r
6978#define MSR_NEHALEM_B0_PMON_MASK 0x00000E46\r
6979\r
6980\r
6981/**\r
6982 Package. Uncore S-box 0 perfmon local box match MSR.\r
6983\r
6984 @param ECX MSR_NEHALEM_S0_PMON_MATCH (0x00000E49)\r
6985 @param EAX Lower 32-bits of MSR value.\r
6986 @param EDX Upper 32-bits of MSR value.\r
6987\r
6988 <b>Example usage</b>\r
6989 @code\r
6990 UINT64 Msr;\r
6991\r
6992 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH);\r
6993 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr);\r
6994 @endcode\r
6995**/\r
6996#define MSR_NEHALEM_S0_PMON_MATCH 0x00000E49\r
6997\r
6998\r
6999/**\r
7000 Package. Uncore S-box 0 perfmon local box mask MSR.\r
7001\r
7002 @param ECX MSR_NEHALEM_S0_PMON_MASK (0x00000E4A)\r
7003 @param EAX Lower 32-bits of MSR value.\r
7004 @param EDX Upper 32-bits of MSR value.\r
7005\r
7006 <b>Example usage</b>\r
7007 @code\r
7008 UINT64 Msr;\r
7009\r
7010 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK);\r
7011 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr);\r
7012 @endcode\r
7013**/\r
7014#define MSR_NEHALEM_S0_PMON_MASK 0x00000E4A\r
7015\r
7016\r
7017/**\r
7018 Package. Uncore B-box 1 perfmon local box match MSR.\r
7019\r
7020 @param ECX MSR_NEHALEM_B1_PMON_MATCH (0x00000E4D)\r
7021 @param EAX Lower 32-bits of MSR value.\r
7022 @param EDX Upper 32-bits of MSR value.\r
7023\r
7024 <b>Example usage</b>\r
7025 @code\r
7026 UINT64 Msr;\r
7027\r
7028 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH);\r
7029 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr);\r
7030 @endcode\r
7031**/\r
7032#define MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D\r
7033\r
7034\r
7035/**\r
7036 Package. Uncore B-box 1 perfmon local box mask MSR.\r
7037\r
7038 @param ECX MSR_NEHALEM_B1_PMON_MASK (0x00000E4E)\r
7039 @param EAX Lower 32-bits of MSR value.\r
7040 @param EDX Upper 32-bits of MSR value.\r
7041\r
7042 <b>Example usage</b>\r
7043 @code\r
7044 UINT64 Msr;\r
7045\r
7046 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK);\r
7047 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr);\r
7048 @endcode\r
7049**/\r
7050#define MSR_NEHALEM_B1_PMON_MASK 0x00000E4E\r
7051\r
7052\r
7053/**\r
7054 Package. Uncore M-box 0 perfmon local box address match/mask config MSR.\r
7055\r
7056 @param ECX MSR_NEHALEM_M0_PMON_MM_CONFIG (0x00000E54)\r
7057 @param EAX Lower 32-bits of MSR value.\r
7058 @param EDX Upper 32-bits of MSR value.\r
7059\r
7060 <b>Example usage</b>\r
7061 @code\r
7062 UINT64 Msr;\r
7063\r
7064 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG);\r
7065 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr);\r
7066 @endcode\r
7067**/\r
7068#define MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54\r
7069\r
7070\r
7071/**\r
7072 Package. Uncore M-box 0 perfmon local box address match MSR.\r
7073\r
7074 @param ECX MSR_NEHALEM_M0_PMON_ADDR_MATCH (0x00000E55)\r
7075 @param EAX Lower 32-bits of MSR value.\r
7076 @param EDX Upper 32-bits of MSR value.\r
7077\r
7078 <b>Example usage</b>\r
7079 @code\r
7080 UINT64 Msr;\r
7081\r
7082 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH);\r
7083 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr);\r
7084 @endcode\r
7085**/\r
7086#define MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55\r
7087\r
7088\r
7089/**\r
7090 Package. Uncore M-box 0 perfmon local box address mask MSR.\r
7091\r
7092 @param ECX MSR_NEHALEM_M0_PMON_ADDR_MASK (0x00000E56)\r
7093 @param EAX Lower 32-bits of MSR value.\r
7094 @param EDX Upper 32-bits of MSR value.\r
7095\r
7096 <b>Example usage</b>\r
7097 @code\r
7098 UINT64 Msr;\r
7099\r
7100 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK);\r
7101 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr);\r
7102 @endcode\r
7103**/\r
7104#define MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56\r
7105\r
7106\r
7107/**\r
7108 Package. Uncore S-box 1 perfmon local box match MSR.\r
7109\r
7110 @param ECX MSR_NEHALEM_S1_PMON_MATCH (0x00000E59)\r
7111 @param EAX Lower 32-bits of MSR value.\r
7112 @param EDX Upper 32-bits of MSR value.\r
7113\r
7114 <b>Example usage</b>\r
7115 @code\r
7116 UINT64 Msr;\r
7117\r
7118 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH);\r
7119 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr);\r
7120 @endcode\r
7121**/\r
7122#define MSR_NEHALEM_S1_PMON_MATCH 0x00000E59\r
7123\r
7124\r
7125/**\r
7126 Package. Uncore S-box 1 perfmon local box mask MSR.\r
7127\r
7128 @param ECX MSR_NEHALEM_S1_PMON_MASK (0x00000E5A)\r
7129 @param EAX Lower 32-bits of MSR value.\r
7130 @param EDX Upper 32-bits of MSR value.\r
7131\r
7132 <b>Example usage</b>\r
7133 @code\r
7134 UINT64 Msr;\r
7135\r
7136 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK);\r
7137 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr);\r
7138 @endcode\r
7139**/\r
7140#define MSR_NEHALEM_S1_PMON_MASK 0x00000E5A\r
7141\r
7142\r
7143/**\r
7144 Package. Uncore M-box 1 perfmon local box address match/mask config MSR.\r
7145\r
7146 @param ECX MSR_NEHALEM_M1_PMON_MM_CONFIG (0x00000E5C)\r
7147 @param EAX Lower 32-bits of MSR value.\r
7148 @param EDX Upper 32-bits of MSR value.\r
7149\r
7150 <b>Example usage</b>\r
7151 @code\r
7152 UINT64 Msr;\r
7153\r
7154 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG);\r
7155 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr);\r
7156 @endcode\r
7157**/\r
7158#define MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C\r
7159\r
7160\r
7161/**\r
7162 Package. Uncore M-box 1 perfmon local box address match MSR.\r
7163\r
7164 @param ECX MSR_NEHALEM_M1_PMON_ADDR_MATCH (0x00000E5D)\r
7165 @param EAX Lower 32-bits of MSR value.\r
7166 @param EDX Upper 32-bits of MSR value.\r
7167\r
7168 <b>Example usage</b>\r
7169 @code\r
7170 UINT64 Msr;\r
7171\r
7172 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH);\r
7173 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr);\r
7174 @endcode\r
7175**/\r
7176#define MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D\r
7177\r
7178\r
7179/**\r
7180 Package. Uncore M-box 1 perfmon local box address mask MSR.\r
7181\r
7182 @param ECX MSR_NEHALEM_M1_PMON_ADDR_MASK (0x00000E5E)\r
7183 @param EAX Lower 32-bits of MSR value.\r
7184 @param EDX Upper 32-bits of MSR value.\r
7185\r
7186 <b>Example usage</b>\r
7187 @code\r
7188 UINT64 Msr;\r
7189\r
7190 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK);\r
7191 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr);\r
7192 @endcode\r
7193**/\r
7194#define MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E\r
7195\r
7196#endif\r
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