]> git.proxmox.com Git - mirror_edk2.git/blame - UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
projects / mirror_edk2.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
UefiCpuPkg/PentiumMMsr.h: add MSR reference from SDM in comment
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / PentiumMMsr.h
CommitLineData
83d4e58c
MK		 1/** @file\r
2 MSR Definitions for Pentium M Processors.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
10 This program and the accompanying materials\r
11 are licensed and made available under the terms and conditions of the BSD License\r
12 which accompanies this distribution. The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-18.\r
21\r
22**/\r
23\r
24#ifndef __PENTIUM_M_MSR_H__\r
25#define __PENTIUM_M_MSR_H__\r
26\r
27#include <Register/ArchitecturalMsr.h>\r
28\r
29/**\r
30 See Section 35.20, "MSRs in Pentium Processors.".\r
31\r
32 @param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)\r
33 @param EAX Lower 32-bits of MSR value.\r
34 @param EDX Upper 32-bits of MSR value.\r
35\r
36 <b>Example usage</b>\r
37 @code\r
38 UINT64 Msr;\r
39\r
40 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);\r
41 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);\r
42 @endcode\r
65ee84bd 43 @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
83d4e58c
MK		 44**/\r
45#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000\r
46\r
47\r
48/**\r
49 See Section 35.20, "MSRs in Pentium Processors.".\r
50\r
51 @param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)\r
52 @param EAX Lower 32-bits of MSR value.\r
53 @param EDX Upper 32-bits of MSR value.\r
54\r
55 <b>Example usage</b>\r
56 @code\r
57 UINT64 Msr;\r
58\r
59 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);\r
60 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);\r
61 @endcode\r
65ee84bd 62 @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
83d4e58c
MK		 63**/\r
64#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001\r
65\r
66\r
67/**\r
68 Processor Hard Power-On Configuration (R/W) Enables and disables processor\r
69 features. (R) Indicates current processor configuration.\r
70\r
71 @param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)\r
72 @param EAX Lower 32-bits of MSR value.\r
73 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.\r
74 @param EDX Upper 32-bits of MSR value.\r
75 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.\r
76\r
77 <b>Example usage</b>\r
78 @code\r
79 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr;\r
80\r
81 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);\r
82 AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);\r
83 @endcode\r
65ee84bd 84 @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
83d4e58c
MK		 85**/\r
86#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A\r
87\r
88/**\r
89 MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON\r
90**/\r
91typedef union {\r
92 ///\r
93 /// Individual bit fields\r
94 ///\r
95 struct {\r
96 UINT32 Reserved1:1;\r
97 ///\r
98 /// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the\r
99 /// Pentium M processor.\r
100 ///\r
101 UINT32 DataErrorCheckingEnable:1;\r
102 ///\r
103 /// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on\r
104 /// the Pentium M processor.\r
105 ///\r
106 UINT32 ResponseErrorCheckingEnable:1;\r
107 ///\r
108 /// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium\r
109 /// M processor.\r
110 ///\r
111 UINT32 MCERR_DriveEnable:1;\r
112 ///\r
113 /// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium\r
114 /// M processor.\r
115 ///\r
116 UINT32 AddressParityEnable:1;\r
117 UINT32 Reserved2:2;\r
118 ///\r
119 /// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on\r
120 /// the Pentium M processor.\r
121 ///\r
122 UINT32 BINIT_DriverEnable:1;\r
123 ///\r
124 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
125 ///\r
126 UINT32 OutputTriStateEnable:1;\r
127 ///\r
128 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
129 ///\r
130 UINT32 ExecuteBIST:1;\r
131 ///\r
132 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
133 /// Always 0 on the Pentium M processor.\r
134 ///\r
135 UINT32 MCERR_ObservationEnabled:1;\r
136 UINT32 Reserved3:1;\r
137 ///\r
138 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
139 /// Always 0 on the Pentium M processor.\r
140 ///\r
141 UINT32 BINIT_ObservationEnabled:1;\r
142 UINT32 Reserved4:1;\r
143 ///\r
144 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes\r
145 /// Always 0 on the Pentium M processor.\r
146 ///\r
147 UINT32 ResetVector:1;\r
148 UINT32 Reserved5:1;\r
149 ///\r
150 /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M\r
151 /// processor.\r
152 ///\r
153 UINT32 APICClusterID:2;\r
154 ///\r
155 /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always\r
156 /// 0 on the Pentium M processor.\r
157 ///\r
158 UINT32 SystemBusFrequency:1;\r
159 UINT32 Reserved6:1;\r
160 ///\r
161 /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium\r
162 /// M processor.\r
163 ///\r
164 UINT32 SymmetricArbitrationID:2;\r
165 ///\r
166 /// [Bits 26:22] Clock Frequency Ratio (R/O).\r
167 ///\r
168 UINT32 ClockFrequencyRatio:5;\r
169 UINT32 Reserved7:5;\r
170 UINT32 Reserved8:32;\r
171 } Bits;\r
172 ///\r
173 /// All bit fields as a 32-bit value\r
174 ///\r
175 UINT32 Uint32;\r
176 ///\r
177 /// All bit fields as a 64-bit value\r
178 ///\r
179 UINT64 Uint64;\r
180} MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER;\r
181\r
182\r
183/**\r
184 Last Branch Record n (R/W) One of 8 last branch record registers on the last\r
185 branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold\r
186 the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section\r
187 17.12, "Last Branch, Interrupt, and Exception Recording (Pentium M\r
188 Processors)".\r
189\r
190 @param ECX MSR_PENTIUM_M_LASTBRANCH_n\r
191 @param EAX Lower 32-bits of MSR value.\r
192 @param EDX Upper 32-bits of MSR value.\r
193\r
194 <b>Example usage</b>\r
195 @code\r
196 UINT64 Msr;\r
197\r
198 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);\r
199 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);\r
200 @endcode\r
65ee84bd
JF		 201 @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.\r
202 MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.\r
203 MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.\r
204 MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r
205 MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.\r
206 MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.\r
207 MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.\r
208 MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.\r
83d4e58c
MK		 209 @{\r
210**/\r
211#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040\r
212#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041\r
213#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042\r
214#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043\r
215#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044\r
216#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045\r
217#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046\r
218#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047\r
219/// @}\r
220\r
221\r
222/**\r
223 Reserved.\r
224\r
225 @param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)\r
226 @param EAX Lower 32-bits of MSR value.\r
227 @param EDX Upper 32-bits of MSR value.\r
228\r
229 <b>Example usage</b>\r
230 @code\r
231 UINT64 Msr;\r
232\r
233 Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);\r
234 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);\r
235 @endcode\r
65ee84bd 236 @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.\r
83d4e58c
MK		 237**/\r
238#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119\r
239\r
240\r
241/**\r
242\r
243\r
244 @param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)\r
245 @param EAX Lower 32-bits of MSR value.\r
246 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.\r
247 @param EDX Upper 32-bits of MSR value.\r
248 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.\r
249\r
250 <b>Example usage</b>\r
251 @code\r
252 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr;\r
253\r
254 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);\r
255 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);\r
256 @endcode\r
65ee84bd 257 @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
83d4e58c
MK		 258**/\r
259#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E\r
260\r
261/**\r
262 MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3\r
263**/\r
264typedef union {\r
265 ///\r
266 /// Individual bit fields\r
267 ///\r
268 struct {\r
269 ///\r
270 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
271 /// Indicates if the L2 is hardware-disabled.\r
272 ///\r
273 UINT32 L2HardwareEnabled:1;\r
274 UINT32 Reserved1:4;\r
275 ///\r
276 /// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the\r
277 /// cache data bus. ECC is always generated on write cycles. 1. = Disabled\r
278 /// (default) 2. = Enabled For the Pentium M processor, ECC checking on\r
279 /// the cache data bus is always enabled.\r
280 ///\r
281 UINT32 ECCCheckEnable:1;\r
282 UINT32 Reserved2:2;\r
283 ///\r
284 /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =\r
285 /// Disabled (default) Until this bit is set the processor will not\r
286 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
287 ///\r
288 UINT32 L2Enabled:1;\r
289 UINT32 Reserved3:14;\r
290 ///\r
291 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
292 ///\r
293 UINT32 L2NotPresent:1;\r
294 UINT32 Reserved4:8;\r
295 UINT32 Reserved5:32;\r
296 } Bits;\r
297 ///\r
298 /// All bit fields as a 32-bit value\r
299 ///\r
300 UINT32 Uint32;\r
301 ///\r
302 /// All bit fields as a 64-bit value\r
303 ///\r
304 UINT64 Uint64;\r
305} MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER;\r
306\r
307\r
308/**\r
309\r
310\r
311 @param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D)\r
312 @param EAX Lower 32-bits of MSR value.\r
313 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.\r
314 @param EDX Upper 32-bits of MSR value.\r
315 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.\r
316\r
317 <b>Example usage</b>\r
318 @code\r
319 MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr;\r
320\r
321 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);\r
322 AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);\r
323 @endcode\r
65ee84bd 324 @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
83d4e58c
MK		 325**/\r
326#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D\r
327\r
328/**\r
329 MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL\r
330**/\r
331typedef union {\r
332 ///\r
333 /// Individual bit fields\r
334 ///\r
335 struct {\r
336 UINT32 Reserved1:16;\r
337 ///\r
338 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
339 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
340 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r
341 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
342 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.\r
343 ///\r
344 UINT32 TM_SELECT:1;\r
345 UINT32 Reserved2:15;\r
346 UINT32 Reserved3:32;\r
347 } Bits;\r
348 ///\r
349 /// All bit fields as a 32-bit value\r
350 ///\r
351 UINT32 Uint32;\r
352 ///\r
353 /// All bit fields as a 64-bit value\r
354 ///\r
355 UINT64 Uint64;\r
356} MSR_PENTIUM_M_THERM2_CTL_REGISTER;\r
357\r
358\r
359/**\r
360 Enable Miscellaneous Processor Features (R/W) Allows a variety of processor\r
361 functions to be enabled and disabled.\r
362\r
363 @param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)\r
364 @param EAX Lower 32-bits of MSR value.\r
365 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.\r
366 @param EDX Upper 32-bits of MSR value.\r
367 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.\r
368\r
369 <b>Example usage</b>\r
370 @code\r
371 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr;\r
372\r
373 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);\r
374 AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);\r
375 @endcode\r
65ee84bd 376 @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
83d4e58c
MK		 377**/\r
378#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0\r
379\r
380/**\r
381 MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE\r
382**/\r
383typedef union {\r
384 ///\r
385 /// Individual bit fields\r
386 ///\r
387 struct {\r
388 UINT32 Reserved1:3;\r
389 ///\r
390 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting\r
391 /// this bit enables the thermal control circuit (TCC) portion of the\r
392 /// Intel Thermal Monitor feature. This allows processor clocks to be\r
393 /// automatically modulated based on the processor's thermal sensor\r
394 /// operation. 0 = Disabled (default). The automatic thermal control\r
395 /// circuit enable bit determines if the thermal control circuit (TCC)\r
396 /// will be activated when the processor's internal thermal sensor\r
397 /// determines the processor is about to exceed its maximum operating\r
398 /// temperature. When the TCC is activated and TM1 is enabled, the\r
399 /// processors clocks will be forced to a 50% duty cycle. BIOS must enable\r
400 /// this feature. The bit should not be confused with the on-demand\r
401 /// thermal control circuit enable bit.\r
402 ///\r
403 UINT32 AutomaticThermalControlCircuit:1;\r
404 UINT32 Reserved2:3;\r
405 ///\r
406 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance\r
407 /// monitoring enabled 0 = Performance monitoring disabled.\r
408 ///\r
409 UINT32 PerformanceMonitoring:1;\r
410 UINT32 Reserved3:2;\r
411 ///\r
412 /// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the\r
413 /// processor to indicate a pending break event within the processor 0 =\r
414 /// Indicates compatible FERR# signaling behavior This bit must be set to\r
415 /// 1 to support XAPIC interrupt model usage.\r
416 /// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't\r
417 /// support branch trace storage (BTS) 0 = BTS is supported\r
418 ///\r
419 UINT32 FERR:1;\r
420 ///\r
421 /// [Bit 11] Branch Trace Storage Unavailable (RO)\r
422 /// 1 = Processor doesn't support branch trace storage (BTS)\r
423 /// 0 = BTS is supported\r
424 ///\r
425 UINT32 BTS:1;\r
426 ///\r
427 /// [Bit 12] Precise Event Based Sampling Unavailable (RO) 1 = Processor\r
428 /// does not support precise event-based sampling (PEBS); 0 = PEBS is\r
429 /// supported. The Pentium M processor does not support PEBS.\r
430 ///\r
431 UINT32 PEBS:1;\r
432 UINT32 Reserved5:3;\r
433 ///\r
434 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =\r
435 /// Enhanced Intel SpeedStep Technology enabled. On the Pentium M\r
436 /// processor, this bit may be configured to be read-only.\r
437 ///\r
438 UINT32 EIST:1;\r
439 UINT32 Reserved6:6;\r
440 ///\r
441 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r
442 /// disabled. xTPR messages are optional messages that allow the processor\r
443 /// to inform the chipset of its priority. The default is processor\r
444 /// specific.\r
445 ///\r
446 UINT32 xTPR_Message_Disable:1;\r
447 UINT32 Reserved7:8;\r
448 UINT32 Reserved8:32;\r
449 } Bits;\r
450 ///\r
451 /// All bit fields as a 32-bit value\r
452 ///\r
453 UINT32 Uint32;\r
454 ///\r
455 /// All bit fields as a 64-bit value\r
456 ///\r
457 UINT64 Uint64;\r
458} MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER;\r
459\r
460\r
461/**\r
462 Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points\r
463 to the MSR containing the most recent branch record. See also: -\r
464 MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.12, "Last Branch, Interrupt,\r
465 and Exception Recording (Pentium M Processors)".\r
466\r
467 @param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)\r
468 @param EAX Lower 32-bits of MSR value.\r
469 @param EDX Upper 32-bits of MSR value.\r
470\r
471 <b>Example usage</b>\r
472 @code\r
473 UINT64 Msr;\r
474\r
475 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);\r
476 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);\r
477 @endcode\r
65ee84bd 478 @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
83d4e58c
MK		 479**/\r
480#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9\r
481\r
482\r
483/**\r
484 Debug Control (R/W) Controls how several debug features are used. Bit\r
485 definitions are discussed in the referenced section. See Section 17.12,\r
486 "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".\r
487\r
488 @param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)\r
489 @param EAX Lower 32-bits of MSR value.\r
490 @param EDX Upper 32-bits of MSR value.\r
491\r
492 <b>Example usage</b>\r
493 @code\r
494 UINT64 Msr;\r
495\r
496 Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);\r
497 AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);\r
498 @endcode\r
65ee84bd 499 @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.\r
83d4e58c
MK		 500**/\r
501#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9\r
502\r
503\r
504/**\r
505 Last Exception Record To Linear IP (R) This area contains a pointer to the\r
506 target of the last branch instruction that the processor executed prior to\r
507 the last exception that was generated or the last interrupt that was\r
508 handled. See Section 17.12, "Last Branch, Interrupt, and Exception Recording\r
509 (Pentium M Processors)" and Section 17.13.2, "Last Branch and Last Exception\r
510 MSRs.".\r
511\r
512 @param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)\r
513 @param EAX Lower 32-bits of MSR value.\r
514 @param EDX Upper 32-bits of MSR value.\r
515\r
516 <b>Example usage</b>\r
517 @code\r
518 UINT64 Msr;\r
519\r
520 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);\r
521 @endcode\r
65ee84bd 522 @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
83d4e58c
MK		 523**/\r
524#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD\r
525\r
526\r
527/**\r
528 Last Exception Record From Linear IP (R) Contains a pointer to the last\r
529 branch instruction that the processor executed prior to the last exception\r
530 that was generated or the last interrupt that was handled. See Section\r
531 17.12, "Last Branch, Interrupt, and Exception Recording (Pentium M\r
532 Processors)" and Section 17.13.2, "Last Branch and Last Exception MSRs.".\r
533\r
534 @param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)\r
535 @param EAX Lower 32-bits of MSR value.\r
536 @param EDX Upper 32-bits of MSR value.\r
537\r
538 <b>Example usage</b>\r
539 @code\r
540 UINT64 Msr;\r
541\r
542 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);\r
543 @endcode\r
65ee84bd 544 @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
83d4e58c
MK		 545**/\r
546#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE\r
547\r
548\r
549/**\r
550 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
551\r
552 @param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C)\r
553 @param EAX Lower 32-bits of MSR value.\r
554 @param EDX Upper 32-bits of MSR value.\r
555\r
556 <b>Example usage</b>\r
557 @code\r
558 UINT64 Msr;\r
559\r
560 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);\r
561 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);\r
562 @endcode\r
65ee84bd 563 @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
83d4e58c
MK		 564**/\r
565#define MSR_PENTIUM_M_MC4_CTL 0x0000040C\r
566\r
567\r
568/**\r
569 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
570\r
571 @param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D)\r
572 @param EAX Lower 32-bits of MSR value.\r
573 @param EDX Upper 32-bits of MSR value.\r
574\r
575 <b>Example usage</b>\r
576 @code\r
577 UINT64 Msr;\r
578\r
579 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);\r
580 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);\r
581 @endcode\r
65ee84bd 582 @note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
83d4e58c
MK		 583**/\r
584#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D\r
585\r
586\r
587/**\r
588 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is\r
589 either not implemented or contains no address if the ADDRV flag in the\r
590 MSR_MC4_STATUS register is clear. When not implemented in the processor, all\r
591 reads and writes to this MSR will cause a general-protection exception.\r
592\r
593 @param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E)\r
594 @param EAX Lower 32-bits of MSR value.\r
595 @param EDX Upper 32-bits of MSR value.\r
596\r
597 <b>Example usage</b>\r
598 @code\r
599 UINT64 Msr;\r
600\r
601 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);\r
602 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);\r
603 @endcode\r
65ee84bd 604 @note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
83d4e58c
MK		 605**/\r
606#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E\r
607\r
608\r
609/**\r
610 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
611\r
612 @param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410)\r
613 @param EAX Lower 32-bits of MSR value.\r
614 @param EDX Upper 32-bits of MSR value.\r
615\r
616 <b>Example usage</b>\r
617 @code\r
618 UINT64 Msr;\r
619\r
620 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);\r
621 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);\r
622 @endcode\r
65ee84bd 623 @note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
83d4e58c
MK		 624**/\r
625#define MSR_PENTIUM_M_MC3_CTL 0x00000410\r
626\r
627\r
628/**\r
629 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
630\r
631 @param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411)\r
632 @param EAX Lower 32-bits of MSR value.\r
633 @param EDX Upper 32-bits of MSR value.\r
634\r
635 <b>Example usage</b>\r
636 @code\r
637 UINT64 Msr;\r
638\r
639 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);\r
640 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);\r
641 @endcode\r
65ee84bd 642 @note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
83d4e58c
MK		 643**/\r
644#define MSR_PENTIUM_M_MC3_STATUS 0x00000411\r
645\r
646\r
647/**\r
648 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is\r
649 either not implemented or contains no address if the ADDRV flag in the\r
650 MSR_MC3_STATUS register is clear. When not implemented in the processor, all\r
651 reads and writes to this MSR will cause a general-protection exception.\r
652\r
653 @param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412)\r
654 @param EAX Lower 32-bits of MSR value.\r
655 @param EDX Upper 32-bits of MSR value.\r
656\r
657 <b>Example usage</b>\r
658 @code\r
659 UINT64 Msr;\r
660\r
661 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);\r
662 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);\r
663 @endcode\r
65ee84bd 664 @note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
83d4e58c
MK		 665**/\r
666#define MSR_PENTIUM_M_MC3_ADDR 0x00000412\r
667\r
668#endif\r
EFI Development Kit II mirror for PVE