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1 | /** @file\r |
2 | MSR Definitions for Pentium Processors.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
9 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
10 | This program and the accompanying materials\r | |
11 | are licensed and made available under the terms and conditions of the BSD License\r | |
12 | which accompanies this distribution. The full text of the license may be found at\r | |
13 | http://opensource.org/licenses/bsd-license.php\r | |
14 | \r | |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | \r | |
18 | @par Specification Reference:\r | |
19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
20 | December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-20.\r | |
21 | \r | |
22 | **/\r | |
23 | \r | |
24 | #ifndef __PENTIUM_MSR_H__\r | |
25 | #define __PENTIUM_MSR_H__\r | |
26 | \r | |
27 | #include <Register/ArchitecturalMsr.h>\r | |
28 | \r | |
29 | /**\r | |
30 | See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".\r | |
31 | \r | |
32 | @param ECX MSR_PENTIUM_P5_MC_ADDR (0x00000000)\r | |
33 | @param EAX Lower 32-bits of MSR value.\r | |
34 | @param EDX Upper 32-bits of MSR value.\r | |
35 | \r | |
36 | <b>Example usage</b>\r | |
37 | @code\r | |
38 | UINT64 Msr;\r | |
39 | \r | |
40 | Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);\r | |
41 | AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);\r | |
42 | @endcode\r | |
634429c0 | 43 | @note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r |
a1e8e34d MK |
44 | **/\r |
45 | #define MSR_PENTIUM_P5_MC_ADDR 0x00000000\r | |
46 | \r | |
47 | \r | |
48 | /**\r | |
49 | See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".\r | |
50 | \r | |
51 | @param ECX MSR_PENTIUM_P5_MC_TYPE (0x00000001)\r | |
52 | @param EAX Lower 32-bits of MSR value.\r | |
53 | @param EDX Upper 32-bits of MSR value.\r | |
54 | \r | |
55 | <b>Example usage</b>\r | |
56 | @code\r | |
57 | UINT64 Msr;\r | |
58 | \r | |
59 | Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);\r | |
60 | AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);\r | |
61 | @endcode\r | |
634429c0 | 62 | @note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r |
a1e8e34d MK |
63 | **/\r |
64 | #define MSR_PENTIUM_P5_MC_TYPE 0x00000001\r | |
65 | \r | |
66 | \r | |
67 | /**\r | |
68 | See Section 17.14, "Time-Stamp Counter.".\r | |
69 | \r | |
70 | @param ECX MSR_PENTIUM_TSC (0x00000010)\r | |
71 | @param EAX Lower 32-bits of MSR value.\r | |
72 | @param EDX Upper 32-bits of MSR value.\r | |
73 | \r | |
74 | <b>Example usage</b>\r | |
75 | @code\r | |
76 | UINT64 Msr;\r | |
77 | \r | |
78 | Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);\r | |
79 | AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);\r | |
80 | @endcode\r | |
634429c0 | 81 | @note MSR_PENTIUM_TSC is defined as TSC in SDM.\r |
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82 | **/\r |
83 | #define MSR_PENTIUM_TSC 0x00000010\r | |
84 | \r | |
85 | \r | |
86 | /**\r | |
87 | See Section 18.20.1, "Control and Event Select Register (CESR).".\r | |
88 | \r | |
89 | @param ECX MSR_PENTIUM_CESR (0x00000011)\r | |
90 | @param EAX Lower 32-bits of MSR value.\r | |
91 | @param EDX Upper 32-bits of MSR value.\r | |
92 | \r | |
93 | <b>Example usage</b>\r | |
94 | @code\r | |
95 | UINT64 Msr;\r | |
96 | \r | |
97 | Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);\r | |
98 | AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);\r | |
99 | @endcode\r | |
634429c0 | 100 | @note MSR_PENTIUM_CESR is defined as CESR in SDM.\r |
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101 | **/\r |
102 | #define MSR_PENTIUM_CESR 0x00000011\r | |
103 | \r | |
104 | \r | |
105 | /**\r | |
106 | Section 18.20.3, "Events Counted.".\r | |
107 | \r | |
108 | @param ECX MSR_PENTIUM_CTRn\r | |
109 | @param EAX Lower 32-bits of MSR value.\r | |
110 | @param EDX Upper 32-bits of MSR value.\r | |
111 | \r | |
112 | <b>Example usage</b>\r | |
113 | @code\r | |
114 | UINT64 Msr;\r | |
115 | \r | |
116 | Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);\r | |
117 | AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);\r | |
118 | @endcode\r | |
634429c0 JF |
119 | @note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM.\r |
120 | MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.\r | |
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121 | @{\r |
122 | **/\r | |
123 | #define MSR_PENTIUM_CTR0 0x00000012\r | |
124 | #define MSR_PENTIUM_CTR1 0x00000013\r | |
125 | /// @}\r | |
126 | \r | |
127 | #endif\r |