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[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / SandyBridgeMsr.h
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dc5d621c
MK		 1/** @file\r
2 MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
f4c982bf 9 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
dc5d621c
MK		 10 This program and the accompanying materials\r
11 are licensed and made available under the terms and conditions of the BSD License\r
12 which accompanies this distribution. The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
0f16be6d 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.9.\r
dc5d621c
MK		 21\r
22**/\r
23\r
24#ifndef __SANDY_BRIDGE_MSR_H__\r
25#define __SANDY_BRIDGE_MSR_H__\r
26\r
27#include <Register/ArchitecturalMsr.h>\r
28\r
f4c982bf
JF		 29/**\r
30 Is Intel processors based on the Sandy Bridge microarchitecture?\r
31\r
32 @param DisplayFamily Display Family ID\r
33 @param DisplayModel Display Model ID\r
34\r
35 @retval TRUE Yes, it is.\r
36 @retval FALSE No, it isn't.\r
37**/\r
38#define IS_SANDY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \\r
39 (DisplayFamily == 0x06 && \\r
40 ( \\r
41 DisplayModel == 0x2A || \\r
42 DisplayModel == 0x2D \\r
43 ) \\r
44 )\r
45\r
dc5d621c
MK		 46/**\r
47 Thread. SMI Counter (R/O).\r
48\r
49 @param ECX MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034)\r
50 @param EAX Lower 32-bits of MSR value.\r
51 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.\r
52 @param EDX Upper 32-bits of MSR value.\r
53 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.\r
54\r
55 <b>Example usage</b>\r
56 @code\r
57 MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Msr;\r
58\r
59 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);\r
60 @endcode\r
367f5c9c 61 @note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
dc5d621c
MK		 62**/\r
63#define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034\r
64\r
65/**\r
66 MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT\r
67**/\r
68typedef union {\r
69 ///\r
70 /// Individual bit fields\r
71 ///\r
72 struct {\r
73 ///\r
74 /// [Bits 31:0] SMI Count (R/O) Count SMIs.\r
75 ///\r
76 UINT32 SMICount:32;\r
77 UINT32 Reserved:32;\r
78 } Bits;\r
79 ///\r
80 /// All bit fields as a 32-bit value\r
81 ///\r
82 UINT32 Uint32;\r
83 ///\r
84 /// All bit fields as a 64-bit value\r
85 ///\r
86 UINT64 Uint64;\r
87} MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER;\r
88\r
89\r
90/**\r
91 Package. See http://biosbits.org.\r
92\r
93 @param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE)\r
94 @param EAX Lower 32-bits of MSR value.\r
95 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.\r
96 @param EDX Upper 32-bits of MSR value.\r
97 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.\r
98\r
99 <b>Example usage</b>\r
100 @code\r
101 MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Msr;\r
102\r
103 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);\r
104 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);\r
105 @endcode\r
367f5c9c 106 @note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
dc5d621c
MK		 107**/\r
108#define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE\r
109\r
110/**\r
111 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO\r
112**/\r
113typedef union {\r
114 ///\r
115 /// Individual bit fields\r
116 ///\r
117 struct {\r
118 UINT32 Reserved1:8;\r
119 ///\r
120 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
121 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
122 /// MHz.\r
123 ///\r
124 UINT32 MaximumNonTurboRatio:8;\r
125 UINT32 Reserved2:12;\r
126 ///\r
127 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
128 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
129 /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
130 /// Turbo mode is disabled.\r
131 ///\r
132 UINT32 RatioLimit:1;\r
133 ///\r
134 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
135 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
136 /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
137 /// programmable.\r
138 ///\r
139 UINT32 TDPLimit:1;\r
140 UINT32 Reserved3:2;\r
141 UINT32 Reserved4:8;\r
142 ///\r
143 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
144 /// minimum ratio (maximum efficiency) that the processor can operates, in\r
145 /// units of 100MHz.\r
146 ///\r
147 UINT32 MaximumEfficiencyRatio:8;\r
148 UINT32 Reserved5:16;\r
149 } Bits;\r
150 ///\r
151 /// All bit fields as a 64-bit value\r
152 ///\r
153 UINT64 Uint64;\r
154} MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER;\r
155\r
156\r
157/**\r
158 Core. C-State Configuration Control (R/W) Note: C-state values are\r
159 processor specific C-state code names, unrelated to MWAIT extension C-state\r
160 parameters or ACPI CStates. See http://biosbits.org.\r
161\r
162 @param ECX MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
163 @param EAX Lower 32-bits of MSR value.\r
164 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
165 @param EDX Upper 32-bits of MSR value.\r
166 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
167\r
168 <b>Example usage</b>\r
169 @code\r
170 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
171\r
172 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL);\r
173 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
174 @endcode\r
367f5c9c 175 @note MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
dc5d621c
MK		 176**/\r
177#define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
178\r
179/**\r
180 MSR information returned for MSR index\r
181 #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL\r
182**/\r
183typedef union {\r
184 ///\r
185 /// Individual bit fields\r
186 ///\r
187 struct {\r
188 ///\r
189 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
190 /// processor-specific C-state code name (consuming the least power). for\r
191 /// the package. The default is set as factory-configured package C-state\r
192 /// limit. The following C-state code name encodings are supported: 000b:\r
193 /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:\r
194 /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:\r
195 /// This field cannot be used to limit package C-state to C3.\r
196 ///\r
197 UINT32 Limit:3;\r
198 UINT32 Reserved1:7;\r
199 ///\r
200 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
201 /// IO_read instructions sent to IO register specified by\r
202 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
203 ///\r
204 UINT32 IO_MWAIT:1;\r
205 UINT32 Reserved2:4;\r
206 ///\r
207 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
208 /// until next reset.\r
209 ///\r
210 UINT32 CFGLock:1;\r
211 UINT32 Reserved3:9;\r
212 ///\r
213 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r
214 /// will conditionally demote C6/C7 requests to C3 based on uncore\r
215 /// auto-demote information.\r
216 ///\r
217 UINT32 C3AutoDemotion:1;\r
218 ///\r
219 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r
220 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
221 /// auto-demote information.\r
222 ///\r
223 UINT32 C1AutoDemotion:1;\r
224 ///\r
225 /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from\r
226 /// demoted C3.\r
227 ///\r
228 UINT32 C3Undemotion:1;\r
229 ///\r
230 /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from\r
231 /// demoted C1.\r
232 ///\r
233 UINT32 C1Undemotion:1;\r
234 UINT32 Reserved4:3;\r
235 UINT32 Reserved5:32;\r
236 } Bits;\r
237 ///\r
238 /// All bit fields as a 32-bit value\r
239 ///\r
240 UINT32 Uint32;\r
241 ///\r
242 /// All bit fields as a 64-bit value\r
243 ///\r
244 UINT64 Uint64;\r
245} MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
246\r
247\r
248/**\r
249 Core. Power Management IO Redirection in C-state (R/W) See\r
250 http://biosbits.org.\r
251\r
252 @param ECX MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE (0x000000E4)\r
253 @param EAX Lower 32-bits of MSR value.\r
254 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.\r
255 @param EDX Upper 32-bits of MSR value.\r
256 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.\r
257\r
258 <b>Example usage</b>\r
259 @code\r
260 MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r
261\r
262 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE);\r
263 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
264 @endcode\r
367f5c9c 265 @note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
dc5d621c
MK		 266**/\r
267#define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4\r
268\r
269/**\r
270 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE\r
271**/\r
272typedef union {\r
273 ///\r
274 /// Individual bit fields\r
275 ///\r
276 struct {\r
277 ///\r
278 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address\r
279 /// visible to software for IO redirection. If IO MWAIT Redirection is\r
280 /// enabled, reads to this address will be consumed by the power\r
281 /// management logic and decoded to MWAIT instructions. When IO port\r
282 /// address redirection is enabled, this is the IO port address reported\r
283 /// to the OS/software.\r
284 ///\r
285 UINT32 Lvl2Base:16;\r
286 ///\r
287 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
288 /// maximum C-State code name to be included when IO read to MWAIT\r
289 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3\r
290 /// is the max C-State to include 001b - C6 is the max C-State to include\r
291 /// 010b - C7 is the max C-State to include.\r
292 ///\r
293 UINT32 CStateRange:3;\r
294 UINT32 Reserved1:13;\r
295 UINT32 Reserved2:32;\r
296 } Bits;\r
297 ///\r
298 /// All bit fields as a 32-bit value\r
299 ///\r
300 UINT32 Uint32;\r
301 ///\r
302 /// All bit fields as a 64-bit value\r
303 ///\r
304 UINT64 Uint64;\r
305} MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER;\r
306\r
307\r
308/**\r
309 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
310 handler to handle unsuccessful read of this MSR.\r
311\r
312 @param ECX MSR_SANDY_BRIDGE_FEATURE_CONFIG (0x0000013C)\r
313 @param EAX Lower 32-bits of MSR value.\r
314 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.\r
315 @param EDX Upper 32-bits of MSR value.\r
316 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.\r
317\r
318 <b>Example usage</b>\r
319 @code\r
320 MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Msr;\r
321\r
322 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);\r
323 AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64);\r
324 @endcode\r
367f5c9c 325 @note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
dc5d621c
MK		 326**/\r
327#define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C\r
328\r
329/**\r
330 MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG\r
331**/\r
332typedef union {\r
333 ///\r
334 /// Individual bit fields\r
335 ///\r
336 struct {\r
337 ///\r
338 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
339 /// MSR, the configuration of AES instruction set availability is as\r
340 /// follows: 11b: AES instructions are not available until next RESET.\r
341 /// otherwise, AES instructions are available. Note, AES instruction set\r
342 /// is not available if read is unsuccessful. If the configuration is not\r
343 /// 01b, AES instruction can be mis-configured if a privileged agent\r
344 /// unintentionally writes 11b.\r
345 ///\r
346 UINT32 AESConfiguration:2;\r
347 UINT32 Reserved1:30;\r
348 UINT32 Reserved2:32;\r
349 } Bits;\r
350 ///\r
351 /// All bit fields as a 32-bit value\r
352 ///\r
353 UINT32 Uint32;\r
354 ///\r
355 /// All bit fields as a 64-bit value\r
356 ///\r
357 UINT64 Uint64;\r
358} MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER;\r
359\r
360\r
361/**\r
362 Core. See Table 35-2; If CPUID.0AH:EAX[15:8] = 8.\r
363\r
364 @param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn\r
365 @param EAX Lower 32-bits of MSR value.\r
366 @param EDX Upper 32-bits of MSR value.\r
367\r
368 <b>Example usage</b>\r
369 @code\r
370 UINT64 Msr;\r
371\r
372 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4);\r
373 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr);\r
374 @endcode\r
367f5c9c
JF		 375 @note MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 is defined as IA32_PERFEVTSEL4 in SDM.\r
376 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 is defined as IA32_PERFEVTSEL5 in SDM.\r
377 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 is defined as IA32_PERFEVTSEL6 in SDM.\r
378 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in SDM.\r
dc5d621c
MK		 379 @{\r
380**/\r
381#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A\r
382#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B\r
383#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C\r
384#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D\r
385/// @}\r
386\r
387\r
388/**\r
389 Package.\r
390\r
391 @param ECX MSR_SANDY_BRIDGE_PERF_STATUS (0x00000198)\r
392 @param EAX Lower 32-bits of MSR value.\r
393 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.\r
394 @param EDX Upper 32-bits of MSR value.\r
395 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.\r
396\r
397 <b>Example usage</b>\r
398 @code\r
399 MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Msr;\r
400\r
401 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS);\r
402 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64);\r
403 @endcode\r
367f5c9c 404 @note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r
dc5d621c
MK		 405**/\r
406#define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198\r
407\r
408/**\r
409 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS\r
410**/\r
411typedef union {\r
412 ///\r
413 /// Individual bit fields\r
414 ///\r
415 struct {\r
416 UINT32 Reserved1:32;\r
417 ///\r
418 /// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed\r
419 /// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13).\r
420 ///\r
421 UINT32 CoreVoltage:16;\r
422 UINT32 Reserved2:16;\r
423 } Bits;\r
424 ///\r
425 /// All bit fields as a 64-bit value\r
426 ///\r
427 UINT64 Uint64;\r
428} MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER;\r
429\r
430\r
431/**\r
432 Thread. Clock Modulation (R/W) See Table 35-2 IA32_CLOCK_MODULATION MSR was\r
433 originally named IA32_THERM_CONTROL MSR.\r
434\r
435 @param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A)\r
436 @param EAX Lower 32-bits of MSR value.\r
437 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.\r
438 @param EDX Upper 32-bits of MSR value.\r
439 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.\r
440\r
441 <b>Example usage</b>\r
442 @code\r
443 MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Msr;\r
444\r
445 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION);\r
446 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64);\r
447 @endcode\r
367f5c9c 448 @note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.\r
dc5d621c
MK		 449**/\r
450#define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A\r
451\r
452/**\r
453 MSR information returned for MSR index\r
454 #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION\r
455**/\r
456typedef union {\r
457 ///\r
458 /// Individual bit fields\r
459 ///\r
460 struct {\r
461 ///\r
462 /// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25%\r
463 /// increment.\r
464 ///\r
465 UINT32 OnDemandClockModulationDutyCycle:4;\r
466 ///\r
467 /// [Bit 4] On demand Clock Modulation Enable (R/W).\r
468 ///\r
469 UINT32 OnDemandClockModulationEnable:1;\r
470 UINT32 Reserved1:27;\r
471 UINT32 Reserved2:32;\r
472 } Bits;\r
473 ///\r
474 /// All bit fields as a 32-bit value\r
475 ///\r
476 UINT32 Uint32;\r
477 ///\r
478 /// All bit fields as a 64-bit value\r
479 ///\r
480 UINT64 Uint64;\r
481} MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER;\r
482\r
483\r
484/**\r
485 Enable Misc. Processor Features (R/W) Allows a variety of processor\r
486 functions to be enabled and disabled.\r
487\r
488 @param ECX MSR_SANDY_BRIDGE_IA32_MISC_ENABLE (0x000001A0)\r
489 @param EAX Lower 32-bits of MSR value.\r
490 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.\r
491 @param EDX Upper 32-bits of MSR value.\r
492 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.\r
493\r
494 <b>Example usage</b>\r
495 @code\r
496 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Msr;\r
497\r
498 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE);\r
499 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64);\r
500 @endcode\r
367f5c9c 501 @note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
dc5d621c
MK		 502**/\r
503#define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0\r
504\r
505/**\r
506 MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE\r
507**/\r
508typedef union {\r
509 ///\r
510 /// Individual bit fields\r
511 ///\r
512 struct {\r
513 ///\r
514 /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.\r
515 ///\r
516 UINT32 FastStrings:1;\r
517 UINT32 Reserved1:6;\r
518 ///\r
519 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.\r
520 ///\r
521 UINT32 PerformanceMonitoring:1;\r
522 UINT32 Reserved2:3;\r
523 ///\r
524 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.\r
525 ///\r
526 UINT32 BTS:1;\r
527 ///\r
0f16be6d 528 /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See\r
dc5d621c
MK		 529 /// Table 35-2.\r
530 ///\r
531 UINT32 PEBS:1;\r
532 UINT32 Reserved3:3;\r
533 ///\r
534 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
535 /// Table 35-2.\r
536 ///\r
537 UINT32 EIST:1;\r
538 UINT32 Reserved4:1;\r
539 ///\r
540 /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.\r
541 ///\r
542 UINT32 MONITOR:1;\r
543 UINT32 Reserved5:3;\r
544 ///\r
545 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.\r
546 ///\r
547 UINT32 LimitCpuidMaxval:1;\r
548 ///\r
549 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.\r
550 ///\r
551 UINT32 xTPR_Message_Disable:1;\r
552 UINT32 Reserved6:8;\r
553 UINT32 Reserved7:2;\r
554 ///\r
555 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.\r
556 ///\r
557 UINT32 XD:1;\r
558 UINT32 Reserved8:3;\r
559 ///\r
560 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r
561 /// that support Intel Turbo Boost Technology, the turbo mode feature is\r
562 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r
563 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r
564 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r
565 /// the power-on default value is used by BIOS to detect hardware support\r
566 /// of turbo mode. If power-on default value is 1, turbo mode is available\r
567 /// in the processor. If power-on default value is 0, turbo mode is not\r
568 /// available.\r
569 ///\r
570 UINT32 TurboModeDisable:1;\r
571 UINT32 Reserved9:25;\r
572 } Bits;\r
573 ///\r
574 /// All bit fields as a 64-bit value\r
575 ///\r
576 UINT64 Uint64;\r
577} MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER;\r
578\r
579\r
580/**\r
581 Unique.\r
582\r
583 @param ECX MSR_SANDY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)\r
584 @param EAX Lower 32-bits of MSR value.\r
585 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r
586 @param EDX Upper 32-bits of MSR value.\r
587 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r
588\r
589 <b>Example usage</b>\r
590 @code\r
591 MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;\r
592\r
593 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET);\r
594 AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);\r
595 @endcode\r
367f5c9c 596 @note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
dc5d621c
MK		 597**/\r
598#define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r
599\r
600/**\r
601 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET\r
602**/\r
603typedef union {\r
604 ///\r
605 /// Individual bit fields\r
606 ///\r
607 struct {\r
608 UINT32 Reserved1:16;\r
609 ///\r
610 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which\r
611 /// PROCHOT# will be asserted. The value is degree C.\r
612 ///\r
613 UINT32 TemperatureTarget:8;\r
614 UINT32 Reserved2:8;\r
615 UINT32 Reserved3:32;\r
616 } Bits;\r
617 ///\r
618 /// All bit fields as a 32-bit value\r
619 ///\r
620 UINT32 Uint32;\r
621 ///\r
622 /// All bit fields as a 64-bit value\r
623 ///\r
624 UINT64 Uint64;\r
625} MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER;\r
626\r
627\r
628/**\r
629 Miscellaneous Feature Control (R/W).\r
630\r
631 @param ECX MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL (0x000001A4)\r
632 @param EAX Lower 32-bits of MSR value.\r
633 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.\r
634 @param EDX Upper 32-bits of MSR value.\r
635 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.\r
636\r
637 <b>Example usage</b>\r
638 @code\r
639 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Msr;\r
640\r
641 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL);\r
642 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64);\r
643 @endcode\r
367f5c9c 644 @note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
dc5d621c
MK		 645**/\r
646#define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4\r
647\r
648/**\r
649 MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL\r
650**/\r
651typedef union {\r
652 ///\r
653 /// Individual bit fields\r
654 ///\r
655 struct {\r
656 ///\r
657 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
658 /// L2 hardware prefetcher, which fetches additional lines of code or data\r
659 /// into the L2 cache.\r
660 ///\r
661 UINT32 L2HardwarePrefetcherDisable:1;\r
662 ///\r
663 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,\r
664 /// disables the adjacent cache line prefetcher, which fetches the cache\r
665 /// line that comprises a cache line pair (128 bytes).\r
666 ///\r
667 UINT32 L2AdjacentCacheLinePrefetcherDisable:1;\r
668 ///\r
669 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
670 /// the L1 data cache prefetcher, which fetches the next cache line into\r
671 /// L1 data cache.\r
672 ///\r
673 UINT32 DCUHardwarePrefetcherDisable:1;\r
674 ///\r
675 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1\r
676 /// data cache IP prefetcher, which uses sequential load history (based on\r
677 /// instruction Pointer of previous loads) to determine whether to\r
678 /// prefetch additional lines.\r
679 ///\r
680 UINT32 DCUIPPrefetcherDisable:1;\r
681 UINT32 Reserved1:28;\r
682 UINT32 Reserved2:32;\r
683 } Bits;\r
684 ///\r
685 /// All bit fields as a 32-bit value\r
686 ///\r
687 UINT32 Uint32;\r
688 ///\r
689 /// All bit fields as a 64-bit value\r
690 ///\r
691 UINT64 Uint64;\r
692} MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER;\r
693\r
694\r
695/**\r
696 Thread. Offcore Response Event Select Register (R/W).\r
697\r
698 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_0 (0x000001A6)\r
699 @param EAX Lower 32-bits of MSR value.\r
700 @param EDX Upper 32-bits of MSR value.\r
701\r
702 <b>Example usage</b>\r
703 @code\r
704 UINT64 Msr;\r
705\r
706 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0);\r
707 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr);\r
708 @endcode\r
367f5c9c 709 @note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
dc5d621c
MK		 710**/\r
711#define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6\r
712\r
713\r
714/**\r
715 Thread. Offcore Response Event Select Register (R/W).\r
716\r
717 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_1 (0x000001A7)\r
718 @param EAX Lower 32-bits of MSR value.\r
719 @param EDX Upper 32-bits of MSR value.\r
720\r
721 <b>Example usage</b>\r
722 @code\r
723 UINT64 Msr;\r
724\r
725 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1);\r
726 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr);\r
727 @endcode\r
367f5c9c 728 @note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
dc5d621c
MK		 729**/\r
730#define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7\r
731\r
732\r
733/**\r
734 See http://biosbits.org.\r
735\r
736 @param ECX MSR_SANDY_BRIDGE_MISC_PWR_MGMT (0x000001AA)\r
737 @param EAX Lower 32-bits of MSR value.\r
738 @param EDX Upper 32-bits of MSR value.\r
739\r
740 <b>Example usage</b>\r
741 @code\r
742 UINT64 Msr;\r
743\r
744 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT);\r
745 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr);\r
746 @endcode\r
367f5c9c 747 @note MSR_SANDY_BRIDGE_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r
dc5d621c
MK		 748**/\r
749#define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA\r
750\r
751\r
752/**\r
753 Thread. Last Branch Record Filtering Select Register (R/W) See Section\r
0f16be6d 754 17.7.2, "Filtering of Last Branch Records.".\r
dc5d621c
MK		 755\r
756 @param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)\r
757 @param EAX Lower 32-bits of MSR value.\r
758 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.\r
759 @param EDX Upper 32-bits of MSR value.\r
760 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.\r
761\r
762 <b>Example usage</b>\r
763 @code\r
764 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Msr;\r
765\r
766 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT);\r
767 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64);\r
768 @endcode\r
367f5c9c 769 @note MSR_SANDY_BRIDGE_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
dc5d621c
MK		 770**/\r
771#define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8\r
772\r
773/**\r
774 MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT\r
775**/\r
776typedef union {\r
777 ///\r
778 /// Individual bit fields\r
779 ///\r
780 struct {\r
781 ///\r
782 /// [Bit 0] CPL_EQ_0.\r
783 ///\r
784 UINT32 CPL_EQ_0:1;\r
785 ///\r
786 /// [Bit 1] CPL_NEQ_0.\r
787 ///\r
788 UINT32 CPL_NEQ_0:1;\r
789 ///\r
790 /// [Bit 2] JCC.\r
791 ///\r
792 UINT32 JCC:1;\r
793 ///\r
794 /// [Bit 3] NEAR_REL_CALL.\r
795 ///\r
796 UINT32 NEAR_REL_CALL:1;\r
797 ///\r
798 /// [Bit 4] NEAR_IND_CALL.\r
799 ///\r
800 UINT32 NEAR_IND_CALL:1;\r
801 ///\r
802 /// [Bit 5] NEAR_RET.\r
803 ///\r
804 UINT32 NEAR_RET:1;\r
805 ///\r
806 /// [Bit 6] NEAR_IND_JMP.\r
807 ///\r
808 UINT32 NEAR_IND_JMP:1;\r
809 ///\r
810 /// [Bit 7] NEAR_REL_JMP.\r
811 ///\r
812 UINT32 NEAR_REL_JMP:1;\r
813 ///\r
814 /// [Bit 8] FAR_BRANCH.\r
815 ///\r
816 UINT32 FAR_BRANCH:1;\r
817 UINT32 Reserved1:23;\r
818 UINT32 Reserved2:32;\r
819 } Bits;\r
820 ///\r
821 /// All bit fields as a 32-bit value\r
822 ///\r
823 UINT32 Uint32;\r
824 ///\r
825 /// All bit fields as a 64-bit value\r
826 ///\r
827 UINT64 Uint64;\r
828} MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER;\r
829\r
830\r
831/**\r
832 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
833 that points to the MSR containing the most recent branch record. See\r
834 MSR_LASTBRANCH_0_FROM_IP (at 680H).\r
835\r
836 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_TOS (0x000001C9)\r
837 @param EAX Lower 32-bits of MSR value.\r
838 @param EDX Upper 32-bits of MSR value.\r
839\r
840 <b>Example usage</b>\r
841 @code\r
842 UINT64 Msr;\r
843\r
844 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS);\r
845 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr);\r
846 @endcode\r
367f5c9c 847 @note MSR_SANDY_BRIDGE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
dc5d621c
MK		 848**/\r
849#define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9\r
850\r
851\r
852/**\r
853 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the\r
854 last branch instruction that the processor executed prior to the last\r
855 exception that was generated or the last interrupt that was handled.\r
856\r
857 @param ECX MSR_SANDY_BRIDGE_LER_FROM_LIP (0x000001DD)\r
858 @param EAX Lower 32-bits of MSR value.\r
859 @param EDX Upper 32-bits of MSR value.\r
860\r
861 <b>Example usage</b>\r
862 @code\r
863 UINT64 Msr;\r
864\r
865 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP);\r
866 @endcode\r
367f5c9c 867 @note MSR_SANDY_BRIDGE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
dc5d621c
MK		 868**/\r
869#define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD\r
870\r
871\r
872/**\r
873 Thread. Last Exception Record To Linear IP (R) This area contains a pointer\r
874 to the target of the last branch instruction that the processor executed\r
875 prior to the last exception that was generated or the last interrupt that\r
876 was handled.\r
877\r
878 @param ECX MSR_SANDY_BRIDGE_LER_TO_LIP (0x000001DE)\r
879 @param EAX Lower 32-bits of MSR value.\r
880 @param EDX Upper 32-bits of MSR value.\r
881\r
882 <b>Example usage</b>\r
883 @code\r
884 UINT64 Msr;\r
885\r
886 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP);\r
887 @endcode\r
367f5c9c 888 @note MSR_SANDY_BRIDGE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
dc5d621c
MK		 889**/\r
890#define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE\r
891\r
892\r
893/**\r
894 Core. See http://biosbits.org.\r
895\r
896 @param ECX MSR_SANDY_BRIDGE_POWER_CTL (0x000001FC)\r
897 @param EAX Lower 32-bits of MSR value.\r
898 @param EDX Upper 32-bits of MSR value.\r
899\r
900 <b>Example usage</b>\r
901 @code\r
902 UINT64 Msr;\r
903\r
904 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL);\r
905 AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr);\r
906 @endcode\r
367f5c9c 907 @note MSR_SANDY_BRIDGE_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r
dc5d621c
MK		 908**/\r
909#define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC\r
910\r
911\r
912/**\r
913 Package. Always 0 (CMCI not supported).\r
914\r
0f16be6d 915 @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL2 (0x00000284)\r
dc5d621c
MK		 916 @param EAX Lower 32-bits of MSR value.\r
917 @param EDX Upper 32-bits of MSR value.\r
918\r
919 <b>Example usage</b>\r
920 @code\r
921 UINT64 Msr;\r
922\r
0f16be6d
HW		 923 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2);\r
924 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2, Msr);\r
dc5d621c 925 @endcode\r
0f16be6d 926 @note MSR_SANDY_BRIDGE_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.\r
dc5d621c 927**/\r
0f16be6d 928#define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284\r
dc5d621c
MK		 929\r
930\r
931/**\r
932 See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".\r
933\r
0f16be6d 934 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
dc5d621c 935 @param EAX Lower 32-bits of MSR value.\r
0f16be6d 936 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
dc5d621c 937 @param EDX Upper 32-bits of MSR value.\r
0f16be6d 938 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
dc5d621c
MK		 939\r
940 <b>Example usage</b>\r
941 @code\r
0f16be6d 942 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
dc5d621c 943\r
0f16be6d
HW		 944 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS);\r
945 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
dc5d621c 946 @endcode\r
0f16be6d 947 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
dc5d621c 948**/\r
0f16be6d 949#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
dc5d621c
MK		 950\r
951/**\r
952 MSR information returned for MSR index\r
0f16be6d 953 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS\r
dc5d621c
MK		 954**/\r
955typedef union {\r
956 ///\r
957 /// Individual bit fields\r
958 ///\r
959 struct {\r
960 ///\r
961 /// [Bit 0] Thread. Ovf_PMC0.\r
962 ///\r
963 UINT32 Ovf_PMC0:1;\r
964 ///\r
965 /// [Bit 1] Thread. Ovf_PMC1.\r
966 ///\r
967 UINT32 Ovf_PMC1:1;\r
968 ///\r
969 /// [Bit 2] Thread. Ovf_PMC2.\r
970 ///\r
971 UINT32 Ovf_PMC2:1;\r
972 ///\r
973 /// [Bit 3] Thread. Ovf_PMC3.\r
974 ///\r
975 UINT32 Ovf_PMC3:1;\r
976 ///\r
977 /// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
978 ///\r
979 UINT32 Ovf_PMC4:1;\r
980 ///\r
981 /// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
982 ///\r
983 UINT32 Ovf_PMC5:1;\r
984 ///\r
985 /// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
986 ///\r
987 UINT32 Ovf_PMC6:1;\r
988 ///\r
989 /// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
990 ///\r
991 UINT32 Ovf_PMC7:1;\r
992 UINT32 Reserved1:24;\r
993 ///\r
994 /// [Bit 32] Thread. Ovf_FixedCtr0.\r
995 ///\r
996 UINT32 Ovf_FixedCtr0:1;\r
997 ///\r
998 /// [Bit 33] Thread. Ovf_FixedCtr1.\r
999 ///\r
1000 UINT32 Ovf_FixedCtr1:1;\r
1001 ///\r
1002 /// [Bit 34] Thread. Ovf_FixedCtr2.\r
1003 ///\r
1004 UINT32 Ovf_FixedCtr2:1;\r
1005 UINT32 Reserved2:26;\r
1006 ///\r
1007 /// [Bit 61] Thread. Ovf_Uncore.\r
1008 ///\r
1009 UINT32 Ovf_Uncore:1;\r
1010 ///\r
1011 /// [Bit 62] Thread. Ovf_BufDSSAVE.\r
1012 ///\r
1013 UINT32 Ovf_BufDSSAVE:1;\r
1014 ///\r
1015 /// [Bit 63] Thread. CondChgd.\r
1016 ///\r
1017 UINT32 CondChgd:1;\r
1018 } Bits;\r
1019 ///\r
1020 /// All bit fields as a 64-bit value\r
1021 ///\r
1022 UINT64 Uint64;\r
0f16be6d 1023} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
dc5d621c
MK		 1024\r
1025\r
1026/**\r
1027 Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
1028 Facilities.".\r
1029\r
1030 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F)\r
1031 @param EAX Lower 32-bits of MSR value.\r
1032 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.\r
1033 @param EDX Upper 32-bits of MSR value.\r
1034 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.\r
1035\r
1036 <b>Example usage</b>\r
1037 @code\r
1038 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;\r
1039\r
1040 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL);\r
1041 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);\r
1042 @endcode\r
367f5c9c 1043 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.\r
dc5d621c
MK		 1044**/\r
1045#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F\r
1046\r
1047/**\r
1048 MSR information returned for MSR index\r
1049 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL\r
1050**/\r
1051typedef union {\r
1052 ///\r
1053 /// Individual bit fields\r
1054 ///\r
1055 struct {\r
1056 ///\r
1057 /// [Bit 0] Thread. Set 1 to enable PMC0 to count.\r
1058 ///\r
1059 UINT32 PCM0_EN:1;\r
1060 ///\r
1061 /// [Bit 1] Thread. Set 1 to enable PMC1 to count.\r
1062 ///\r
1063 UINT32 PCM1_EN:1;\r
1064 ///\r
1065 /// [Bit 2] Thread. Set 1 to enable PMC2 to count.\r
1066 ///\r
1067 UINT32 PCM2_EN:1;\r
1068 ///\r
1069 /// [Bit 3] Thread. Set 1 to enable PMC3 to count.\r
1070 ///\r
1071 UINT32 PCM3_EN:1;\r
1072 ///\r
1073 /// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] >\r
1074 /// 4).\r
1075 ///\r
1076 UINT32 PCM4_EN:1;\r
1077 ///\r
1078 /// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] >\r
1079 /// 5).\r
1080 ///\r
1081 UINT32 PCM5_EN:1;\r
1082 ///\r
1083 /// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] >\r
1084 /// 6).\r
1085 ///\r
1086 UINT32 PCM6_EN:1;\r
1087 ///\r
1088 /// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] >\r
1089 /// 7).\r
1090 ///\r
1091 UINT32 PCM7_EN:1;\r
1092 UINT32 Reserved1:24;\r
1093 ///\r
1094 /// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count.\r
1095 ///\r
1096 UINT32 FIXED_CTR0:1;\r
1097 ///\r
1098 /// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count.\r
1099 ///\r
1100 UINT32 FIXED_CTR1:1;\r
1101 ///\r
1102 /// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count.\r
1103 ///\r
1104 UINT32 FIXED_CTR2:1;\r
1105 UINT32 Reserved2:29;\r
1106 } Bits;\r
1107 ///\r
1108 /// All bit fields as a 64-bit value\r
1109 ///\r
1110 UINT64 Uint64;\r
1111} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER;\r
1112\r
1113\r
1114/**\r
1115 See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".\r
1116\r
1117 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
1118 @param EAX Lower 32-bits of MSR value.\r
1119 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
1120 @param EDX Upper 32-bits of MSR value.\r
1121 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
1122\r
1123 <b>Example usage</b>\r
1124 @code\r
1125 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r
1126\r
1127 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL);\r
1128 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r
1129 @endcode\r
367f5c9c 1130 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.\r
dc5d621c
MK		 1131**/\r
1132#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r
1133\r
1134/**\r
1135 MSR information returned for MSR index\r
1136 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL\r
1137**/\r
1138typedef union {\r
1139 ///\r
1140 /// Individual bit fields\r
1141 ///\r
1142 struct {\r
1143 ///\r
1144 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.\r
1145 ///\r
1146 UINT32 Ovf_PMC0:1;\r
1147 ///\r
1148 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.\r
1149 ///\r
1150 UINT32 Ovf_PMC1:1;\r
1151 ///\r
1152 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.\r
1153 ///\r
1154 UINT32 Ovf_PMC2:1;\r
1155 ///\r
1156 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.\r
1157 ///\r
1158 UINT32 Ovf_PMC3:1;\r
1159 ///\r
1160 /// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
1161 ///\r
1162 UINT32 Ovf_PMC4:1;\r
1163 ///\r
1164 /// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
1165 ///\r
1166 UINT32 Ovf_PMC5:1;\r
1167 ///\r
1168 /// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
1169 ///\r
1170 UINT32 Ovf_PMC6:1;\r
1171 ///\r
1172 /// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
1173 ///\r
1174 UINT32 Ovf_PMC7:1;\r
1175 UINT32 Reserved1:24;\r
1176 ///\r
1177 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.\r
1178 ///\r
1179 UINT32 Ovf_FixedCtr0:1;\r
1180 ///\r
1181 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.\r
1182 ///\r
1183 UINT32 Ovf_FixedCtr1:1;\r
1184 ///\r
1185 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.\r
1186 ///\r
1187 UINT32 Ovf_FixedCtr2:1;\r
1188 UINT32 Reserved2:26;\r
1189 ///\r
1190 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.\r
1191 ///\r
1192 UINT32 Ovf_Uncore:1;\r
1193 ///\r
1194 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.\r
1195 ///\r
1196 UINT32 Ovf_BufDSSAVE:1;\r
1197 ///\r
1198 /// [Bit 63] Thread. Set 1 to clear CondChgd.\r
1199 ///\r
1200 UINT32 CondChgd:1;\r
1201 } Bits;\r
1202 ///\r
1203 /// All bit fields as a 64-bit value\r
1204 ///\r
1205 UINT64 Uint64;\r
1206} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
1207\r
1208\r
1209/**\r
0f16be6d 1210 Thread. See Section 18.8.1.1, "Processor Event Based Sampling (PEBS).".\r
dc5d621c
MK		 1211\r
1212 @param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)\r
1213 @param EAX Lower 32-bits of MSR value.\r
1214 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.\r
1215 @param EDX Upper 32-bits of MSR value.\r
1216 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.\r
1217\r
1218 <b>Example usage</b>\r
1219 @code\r
1220 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Msr;\r
1221\r
1222 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE);\r
1223 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64);\r
1224 @endcode\r
367f5c9c 1225 @note MSR_SANDY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
dc5d621c
MK		 1226**/\r
1227#define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1\r
1228\r
1229/**\r
1230 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE\r
1231**/\r
1232typedef union {\r
1233 ///\r
1234 /// Individual bit fields\r
1235 ///\r
1236 struct {\r
1237 ///\r
1238 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
1239 ///\r
1240 UINT32 PEBS_EN_PMC0:1;\r
1241 ///\r
1242 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
1243 ///\r
1244 UINT32 PEBS_EN_PMC1:1;\r
1245 ///\r
1246 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
1247 ///\r
1248 UINT32 PEBS_EN_PMC2:1;\r
1249 ///\r
1250 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
1251 ///\r
1252 UINT32 PEBS_EN_PMC3:1;\r
1253 UINT32 Reserved1:28;\r
1254 ///\r
1255 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
1256 ///\r
1257 UINT32 LL_EN_PMC0:1;\r
1258 ///\r
1259 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
1260 ///\r
1261 UINT32 LL_EN_PMC1:1;\r
1262 ///\r
1263 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
1264 ///\r
1265 UINT32 LL_EN_PMC2:1;\r
1266 ///\r
1267 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
1268 ///\r
1269 UINT32 LL_EN_PMC3:1;\r
1270 UINT32 Reserved2:27;\r
1271 ///\r
1272 /// [Bit 63] Enable Precise Store. (R/W).\r
1273 ///\r
1274 UINT32 PS_EN:1;\r
1275 } Bits;\r
1276 ///\r
1277 /// All bit fields as a 64-bit value\r
1278 ///\r
1279 UINT64 Uint64;\r
1280} MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER;\r
1281\r
1282\r
1283/**\r
0f16be6d 1284 Thread. see See Section 18.8.1.2, "Load Latency Performance Monitoring\r
dc5d621c
MK		 1285 Facility.".\r
1286\r
1287 @param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)\r
1288 @param EAX Lower 32-bits of MSR value.\r
1289 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.\r
1290 @param EDX Upper 32-bits of MSR value.\r
1291 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.\r
1292\r
1293 <b>Example usage</b>\r
1294 @code\r
1295 MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Msr;\r
1296\r
1297 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT);\r
1298 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64);\r
1299 @endcode\r
367f5c9c 1300 @note MSR_SANDY_BRIDGE_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.\r
dc5d621c
MK		 1301**/\r
1302#define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6\r
1303\r
1304/**\r
1305 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT\r
1306**/\r
1307typedef union {\r
1308 ///\r
1309 /// Individual bit fields\r
1310 ///\r
1311 struct {\r
1312 ///\r
1313 /// [Bits 15:0] Minimum threshold latency value of tagged load operation\r
1314 /// that will be counted. (R/W).\r
1315 ///\r
1316 UINT32 MinimumThreshold:16;\r
1317 UINT32 Reserved1:16;\r
1318 UINT32 Reserved2:32;\r
1319 } Bits;\r
1320 ///\r
1321 /// All bit fields as a 32-bit value\r
1322 ///\r
1323 UINT32 Uint32;\r
1324 ///\r
1325 /// All bit fields as a 64-bit value\r
1326 ///\r
1327 UINT64 Uint64;\r
1328} MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER;\r
1329\r
1330\r
1331/**\r
1332 Package. Note: C-state values are processor specific C-state code names,\r
1333 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r
1334 Residency Counter. (R/O) Value since last reset that this package is in\r
1335 processor-specific C3 states. Count at the same frequency as the TSC.\r
1336\r
1337 @param ECX MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY (0x000003F8)\r
1338 @param EAX Lower 32-bits of MSR value.\r
1339 @param EDX Upper 32-bits of MSR value.\r
1340\r
1341 <b>Example usage</b>\r
1342 @code\r
1343 UINT64 Msr;\r
1344\r
1345 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY);\r
1346 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr);\r
1347 @endcode\r
367f5c9c 1348 @note MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
dc5d621c
MK		 1349**/\r
1350#define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8\r
1351\r
1352\r
1353/**\r
1354 Package. Note: C-state values are processor specific C-state code names,\r
1355 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r
1356 Residency Counter. (R/O) Value since last reset that this package is in\r
1357 processor-specific C6 states. Count at the same frequency as the TSC.\r
1358\r
1359 @param ECX MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY (0x000003F9)\r
1360 @param EAX Lower 32-bits of MSR value.\r
1361 @param EDX Upper 32-bits of MSR value.\r
1362\r
1363 <b>Example usage</b>\r
1364 @code\r
1365 UINT64 Msr;\r
1366\r
1367 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY);\r
1368 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr);\r
1369 @endcode\r
367f5c9c 1370 @note MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
dc5d621c
MK		 1371**/\r
1372#define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9\r
1373\r
1374\r
1375/**\r
1376 Package. Note: C-state values are processor specific C-state code names,\r
1377 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7\r
1378 Residency Counter. (R/O) Value since last reset that this package is in\r
1379 processor-specific C7 states. Count at the same frequency as the TSC.\r
1380\r
1381 @param ECX MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY (0x000003FA)\r
1382 @param EAX Lower 32-bits of MSR value.\r
1383 @param EDX Upper 32-bits of MSR value.\r
1384\r
1385 <b>Example usage</b>\r
1386 @code\r
1387 UINT64 Msr;\r
1388\r
1389 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY);\r
1390 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr);\r
1391 @endcode\r
367f5c9c 1392 @note MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r
dc5d621c
MK		 1393**/\r
1394#define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA\r
1395\r
1396\r
1397/**\r
1398 Core. Note: C-state values are processor specific C-state code names,\r
1399 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3\r
1400 Residency Counter. (R/O) Value since last reset that this core is in\r
1401 processor-specific C3 states. Count at the same frequency as the TSC.\r
1402\r
1403 @param ECX MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY (0x000003FC)\r
1404 @param EAX Lower 32-bits of MSR value.\r
1405 @param EDX Upper 32-bits of MSR value.\r
1406\r
1407 <b>Example usage</b>\r
1408 @code\r
1409 UINT64 Msr;\r
1410\r
1411 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY);\r
1412 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr);\r
1413 @endcode\r
367f5c9c 1414 @note MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r
dc5d621c
MK		 1415**/\r
1416#define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC\r
1417\r
1418\r
1419/**\r
1420 Core. Note: C-state values are processor specific C-state code names,\r
1421 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6\r
1422 Residency Counter. (R/O) Value since last reset that this core is in\r
1423 processor-specific C6 states. Count at the same frequency as the TSC.\r
1424\r
1425 @param ECX MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY (0x000003FD)\r
1426 @param EAX Lower 32-bits of MSR value.\r
1427 @param EDX Upper 32-bits of MSR value.\r
1428\r
1429 <b>Example usage</b>\r
1430 @code\r
1431 UINT64 Msr;\r
1432\r
1433 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY);\r
1434 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr);\r
1435 @endcode\r
367f5c9c 1436 @note MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
dc5d621c
MK		 1437**/\r
1438#define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD\r
1439\r
1440\r
1441/**\r
1442 Core. Note: C-state values are processor specific C-state code names,\r
1443 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C7\r
1444 Residency Counter. (R/O) Value since last reset that this core is in\r
1445 processor-specific C7 states. Count at the same frequency as the TSC.\r
1446\r
1447 @param ECX MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY (0x000003FE)\r
1448 @param EAX Lower 32-bits of MSR value.\r
1449 @param EDX Upper 32-bits of MSR value.\r
1450\r
1451 <b>Example usage</b>\r
1452 @code\r
1453 UINT64 Msr;\r
1454\r
1455 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY);\r
1456 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr);\r
1457 @endcode\r
367f5c9c 1458 @note MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY is defined as MSR_CORE_C7_RESIDENCY in SDM.\r
dc5d621c
MK		 1459**/\r
1460#define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE\r
1461\r
1462\r
1463/**\r
1464 Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
1465\r
0f16be6d 1466 @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL (0x00000410)\r
dc5d621c 1467 @param EAX Lower 32-bits of MSR value.\r
0f16be6d 1468 Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.\r
dc5d621c 1469 @param EDX Upper 32-bits of MSR value.\r
0f16be6d 1470 Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.\r
dc5d621c
MK		 1471\r
1472 <b>Example usage</b>\r
1473 @code\r
0f16be6d 1474 MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER Msr;\r
dc5d621c 1475\r
0f16be6d
HW		 1476 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL);\r
1477 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL, Msr.Uint64);\r
dc5d621c 1478 @endcode\r
0f16be6d 1479 @note MSR_SANDY_BRIDGE_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.\r
dc5d621c 1480**/\r
0f16be6d 1481#define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410\r
dc5d621c
MK		 1482\r
1483/**\r
0f16be6d 1484 MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL\r
dc5d621c
MK		 1485**/\r
1486typedef union {\r
1487 ///\r
1488 /// Individual bit fields\r
1489 ///\r
1490 struct {\r
1491 ///\r
1492 /// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU\r
1493 /// hardware detected errors.\r
1494 ///\r
1495 UINT32 PCUHardwareError:1;\r
1496 ///\r
1497 /// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU\r
1498 /// controller detected errors.\r
1499 ///\r
1500 UINT32 PCUControllerError:1;\r
1501 ///\r
1502 /// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU\r
1503 /// firmware detected errors.\r
1504 ///\r
1505 UINT32 PCUFirmwareError:1;\r
1506 UINT32 Reserved1:29;\r
1507 UINT32 Reserved2:32;\r
1508 } Bits;\r
1509 ///\r
1510 /// All bit fields as a 32-bit value\r
1511 ///\r
1512 UINT32 Uint32;\r
1513 ///\r
1514 /// All bit fields as a 64-bit value\r
1515 ///\r
1516 UINT64 Uint64;\r
0f16be6d 1517} MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER;\r
dc5d621c
MK		 1518\r
1519\r
1520/**\r
1521 Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.\r
1522\r
1523 @param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r
1524 @param EAX Lower 32-bits of MSR value.\r
1525 @param EDX Upper 32-bits of MSR value.\r
1526\r
1527 <b>Example usage</b>\r
1528 @code\r
1529 UINT64 Msr;\r
1530\r
1531 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM);\r
1532 @endcode\r
367f5c9c 1533 @note MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r
dc5d621c
MK		 1534**/\r
1535#define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
1536\r
1537\r
1538/**\r
1539 Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r
1540 "RAPL Interfaces.".\r
1541\r
1542 @param ECX MSR_SANDY_BRIDGE_RAPL_POWER_UNIT (0x00000606)\r
1543 @param EAX Lower 32-bits of MSR value.\r
1544 @param EDX Upper 32-bits of MSR value.\r
1545\r
1546 <b>Example usage</b>\r
1547 @code\r
1548 UINT64 Msr;\r
1549\r
1550 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT);\r
1551 @endcode\r
367f5c9c 1552 @note MSR_SANDY_BRIDGE_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
dc5d621c
MK		 1553**/\r
1554#define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606\r
1555\r
1556\r
1557/**\r
1558 Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are\r
1559 processor specific C-state code names, unrelated to MWAIT extension C-state\r
1560 parameters or ACPI CStates.\r
1561\r
1562 @param ECX MSR_SANDY_BRIDGE_PKGC3_IRTL (0x0000060A)\r
1563 @param EAX Lower 32-bits of MSR value.\r
1564 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.\r
1565 @param EDX Upper 32-bits of MSR value.\r
1566 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.\r
1567\r
1568 <b>Example usage</b>\r
1569 @code\r
1570 MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Msr;\r
1571\r
1572 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL);\r
1573 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64);\r
1574 @endcode\r
367f5c9c 1575 @note MSR_SANDY_BRIDGE_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.\r
dc5d621c
MK		 1576**/\r
1577#define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A\r
1578\r
1579/**\r
1580 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL\r
1581**/\r
1582typedef union {\r
1583 ///\r
1584 /// Individual bit fields\r
1585 ///\r
1586 struct {\r
1587 ///\r
1588 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
1589 /// that should be used to decide if the package should be put into a\r
1590 /// package C3 state.\r
1591 ///\r
1592 UINT32 TimeLimit:10;\r
1593 ///\r
1594 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
1595 /// unit of the interrupt response time limit. The following time unit\r
1596 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
1597 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
1598 ///\r
1599 UINT32 TimeUnit:3;\r
1600 UINT32 Reserved1:2;\r
1601 ///\r
1602 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
1603 /// valid and can be used by the processor for package C-sate management.\r
1604 ///\r
1605 UINT32 Valid:1;\r
1606 UINT32 Reserved2:16;\r
1607 UINT32 Reserved3:32;\r
1608 } Bits;\r
1609 ///\r
1610 /// All bit fields as a 32-bit value\r
1611 ///\r
1612 UINT32 Uint32;\r
1613 ///\r
1614 /// All bit fields as a 64-bit value\r
1615 ///\r
1616 UINT64 Uint64;\r
1617} MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER;\r
1618\r
1619\r
1620/**\r
1621 Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the\r
1622 budget allocated for the package to exit from C6 to a C0 state, where\r
1623 interrupt request can be delivered to the core and serviced. Additional\r
1624 core-exit latency amy be applicable depending on the actual C-state the core\r
1625 is in. Note: C-state values are processor specific C-state code names,\r
1626 unrelated to MWAIT extension C-state parameters or ACPI CStates.\r
1627\r
1628 @param ECX MSR_SANDY_BRIDGE_PKGC6_IRTL (0x0000060B)\r
1629 @param EAX Lower 32-bits of MSR value.\r
1630 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.\r
1631 @param EDX Upper 32-bits of MSR value.\r
1632 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.\r
1633\r
1634 <b>Example usage</b>\r
1635 @code\r
1636 MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Msr;\r
1637\r
1638 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL);\r
1639 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64);\r
1640 @endcode\r
367f5c9c 1641 @note MSR_SANDY_BRIDGE_PKGC6_IRTL is defined as MSR_PKGC6_IRTL in SDM.\r
dc5d621c
MK		 1642**/\r
1643#define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B\r
1644\r
1645/**\r
1646 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL\r
1647**/\r
1648typedef union {\r
1649 ///\r
1650 /// Individual bit fields\r
1651 ///\r
1652 struct {\r
1653 ///\r
1654 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
1655 /// that should be used to decide if the package should be put into a\r
1656 /// package C6 state.\r
1657 ///\r
1658 UINT32 TimeLimit:10;\r
1659 ///\r
1660 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
1661 /// unit of the interrupt response time limit. The following time unit\r
1662 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
1663 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
1664 ///\r
1665 UINT32 TimeUnit:3;\r
1666 UINT32 Reserved1:2;\r
1667 ///\r
1668 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
1669 /// valid and can be used by the processor for package C-sate management.\r
1670 ///\r
1671 UINT32 Valid:1;\r
1672 UINT32 Reserved2:16;\r
1673 UINT32 Reserved3:32;\r
1674 } Bits;\r
1675 ///\r
1676 /// All bit fields as a 32-bit value\r
1677 ///\r
1678 UINT32 Uint32;\r
1679 ///\r
1680 /// All bit fields as a 64-bit value\r
1681 ///\r
1682 UINT64 Uint64;\r
1683} MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER;\r
1684\r
1685\r
1686/**\r
1687 Package. Note: C-state values are processor specific C-state code names,\r
1688 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2\r
1689 Residency Counter. (R/O) Value since last reset that this package is in\r
1690 processor-specific C2 states. Count at the same frequency as the TSC.\r
1691\r
1692 @param ECX MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY (0x0000060D)\r
1693 @param EAX Lower 32-bits of MSR value.\r
1694 @param EDX Upper 32-bits of MSR value.\r
1695\r
1696 <b>Example usage</b>\r
1697 @code\r
1698 UINT64 Msr;\r
1699\r
1700 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY);\r
1701 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr);\r
1702 @endcode\r
367f5c9c 1703 @note MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
dc5d621c
MK		 1704**/\r
1705#define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D\r
1706\r
1707\r
1708/**\r
1709 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r
1710 RAPL Domain.".\r
1711\r
1712 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_LIMIT (0x00000610)\r
1713 @param EAX Lower 32-bits of MSR value.\r
1714 @param EDX Upper 32-bits of MSR value.\r
1715\r
1716 <b>Example usage</b>\r
1717 @code\r
1718 UINT64 Msr;\r
1719\r
1720 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT);\r
1721 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr);\r
1722 @endcode\r
367f5c9c 1723 @note MSR_SANDY_BRIDGE_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
dc5d621c
MK		 1724**/\r
1725#define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610\r
1726\r
1727\r
1728/**\r
1729 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
1730\r
1731 @param ECX MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS (0x00000611)\r
1732 @param EAX Lower 32-bits of MSR value.\r
1733 @param EDX Upper 32-bits of MSR value.\r
1734\r
1735 <b>Example usage</b>\r
1736 @code\r
1737 UINT64 Msr;\r
1738\r
1739 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS);\r
1740 @endcode\r
367f5c9c 1741 @note MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
dc5d621c
MK		 1742**/\r
1743#define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611\r
1744\r
1745\r
1746/**\r
1747 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL\r
1748 Domain.".\r
1749\r
1750 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_INFO (0x00000614)\r
1751 @param EAX Lower 32-bits of MSR value.\r
1752 @param EDX Upper 32-bits of MSR value.\r
1753\r
1754 <b>Example usage</b>\r
1755 @code\r
1756 UINT64 Msr;\r
1757\r
1758 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO);\r
1759 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr);\r
1760 @endcode\r
367f5c9c 1761 @note MSR_SANDY_BRIDGE_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
dc5d621c
MK		 1762**/\r
1763#define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614\r
1764\r
1765\r
1766/**\r
1767 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
1768 RAPL Domains.".\r
1769\r
1770 @param ECX MSR_SANDY_BRIDGE_PP0_POWER_LIMIT (0x00000638)\r
1771 @param EAX Lower 32-bits of MSR value.\r
1772 @param EDX Upper 32-bits of MSR value.\r
1773\r
1774 <b>Example usage</b>\r
1775 @code\r
1776 UINT64 Msr;\r
1777\r
1778 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT);\r
1779 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr);\r
1780 @endcode\r
367f5c9c 1781 @note MSR_SANDY_BRIDGE_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r
dc5d621c
MK		 1782**/\r
1783#define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638\r
1784\r
1785\r
1786/**\r
1787 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
1788 Domains.".\r
1789\r
1790 @param ECX MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)\r
1791 @param EAX Lower 32-bits of MSR value.\r
1792 @param EDX Upper 32-bits of MSR value.\r
1793\r
1794 <b>Example usage</b>\r
1795 @code\r
1796 UINT64 Msr;\r
1797\r
1798 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS);\r
1799 @endcode\r
367f5c9c 1800 @note MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
dc5d621c
MK		 1801**/\r
1802#define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r
1803\r
1804\r
1805/**\r
1806 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r
1807 branch record registers on the last branch record stack. This part of the\r
1808 stack contains pointers to the source instruction. See also: - Last Branch\r
0f16be6d
HW		 1809 Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section\r
1810 17.4.8.1.\r
dc5d621c
MK		 1811\r
1812 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP\r
1813 @param EAX Lower 32-bits of MSR value.\r
1814 @param EDX Upper 32-bits of MSR value.\r
1815\r
1816 <b>Example usage</b>\r
1817 @code\r
1818 UINT64 Msr;\r
1819\r
1820 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP);\r
1821 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr);\r
1822 @endcode\r
367f5c9c
JF		 1823 @note MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
1824 MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
1825 MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
1826 MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
1827 MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r
1828 MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r
1829 MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r
1830 MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
1831 MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.\r
1832 MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.\r
1833 MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r
1834 MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r
1835 MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r
1836 MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r
1837 MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r
1838 MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
dc5d621c
MK		 1839 @{\r
1840**/\r
1841#define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680\r
1842#define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681\r
1843#define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682\r
1844#define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683\r
1845#define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684\r
1846#define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685\r
1847#define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686\r
1848#define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687\r
1849#define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688\r
1850#define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689\r
1851#define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A\r
1852#define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B\r
1853#define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C\r
1854#define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D\r
1855#define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E\r
1856#define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F\r
1857/// @}\r
1858\r
1859\r
1860/**\r
1861 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch\r
1862 record registers on the last branch record stack. This part of the stack\r
1863 contains pointers to the destination instruction.\r
1864\r
1865 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_TO_IP\r
1866 @param EAX Lower 32-bits of MSR value.\r
1867 @param EDX Upper 32-bits of MSR value.\r
1868\r
1869 <b>Example usage</b>\r
1870 @code\r
1871 UINT64 Msr;\r
1872\r
1873 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP);\r
1874 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr);\r
1875 @endcode\r
367f5c9c
JF		 1876 @note MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
1877 MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
1878 MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
1879 MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
1880 MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r
1881 MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r
1882 MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r
1883 MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
1884 MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.\r
1885 MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.\r
1886 MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r
1887 MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r
1888 MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r
1889 MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r
1890 MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r
1891 MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
dc5d621c
MK		 1892 @{\r
1893**/\r
1894#define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0\r
1895#define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1\r
1896#define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2\r
1897#define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3\r
1898#define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4\r
1899#define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5\r
1900#define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6\r
1901#define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7\r
1902#define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8\r
1903#define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9\r
1904#define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA\r
1905#define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB\r
1906#define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC\r
1907#define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD\r
1908#define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE\r
1909#define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF\r
1910/// @}\r
1911\r
1912\r
1913/**\r
1914 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
1915 RW if MSR_PLATFORM_INFO.[28] = 1.\r
1916\r
1917 @param ECX MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT (0x000001AD)\r
1918 @param EAX Lower 32-bits of MSR value.\r
1919 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.\r
1920 @param EDX Upper 32-bits of MSR value.\r
1921 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.\r
1922\r
1923 <b>Example usage</b>\r
1924 @code\r
1925 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Msr;\r
1926\r
1927 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT);\r
1928 @endcode\r
367f5c9c 1929 @note MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
dc5d621c
MK		 1930**/\r
1931#define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD\r
1932\r
1933/**\r
1934 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT\r
1935**/\r
1936typedef union {\r
1937 ///\r
1938 /// Individual bit fields\r
1939 ///\r
1940 struct {\r
1941 ///\r
1942 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
1943 /// limit of 1 core active.\r
1944 ///\r
1945 UINT32 Maximum1C:8;\r
1946 ///\r
1947 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
1948 /// limit of 2 core active.\r
1949 ///\r
1950 UINT32 Maximum2C:8;\r
1951 ///\r
1952 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
1953 /// limit of 3 core active.\r
1954 ///\r
1955 UINT32 Maximum3C:8;\r
1956 ///\r
1957 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
1958 /// limit of 4 core active.\r
1959 ///\r
1960 UINT32 Maximum4C:8;\r
1961 ///\r
1962 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
1963 /// limit of 5 core active.\r
1964 ///\r
1965 UINT32 Maximum5C:8;\r
1966 ///\r
1967 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
1968 /// limit of 6 core active.\r
1969 ///\r
1970 UINT32 Maximum6C:8;\r
1971 ///\r
1972 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
1973 /// limit of 7 core active.\r
1974 ///\r
1975 UINT32 Maximum7C:8;\r
1976 ///\r
1977 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
1978 /// limit of 8 core active.\r
1979 ///\r
1980 UINT32 Maximum8C:8;\r
1981 } Bits;\r
1982 ///\r
1983 /// All bit fields as a 64-bit value\r
1984 ///\r
1985 UINT64 Uint64;\r
1986} MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER;\r
1987\r
1988\r
1989/**\r
1990 Package. Uncore PMU global control.\r
1991\r
1992 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL (0x00000391)\r
1993 @param EAX Lower 32-bits of MSR value.\r
1994 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
1995 @param EDX Upper 32-bits of MSR value.\r
1996 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
1997\r
1998 <b>Example usage</b>\r
1999 @code\r
2000 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;\r
2001\r
2002 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL);\r
2003 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r
2004 @endcode\r
367f5c9c 2005 @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
dc5d621c
MK		 2006**/\r
2007#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391\r
2008\r
2009/**\r
2010 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL\r
2011**/\r
2012typedef union {\r
2013 ///\r
2014 /// Individual bit fields\r
2015 ///\r
2016 struct {\r
2017 ///\r
0f16be6d 2018 /// [Bit 0] Slice 0 select.\r
dc5d621c 2019 ///\r
0f16be6d 2020 UINT32 PMI_Sel_Slice0:1;\r
dc5d621c 2021 ///\r
0f16be6d 2022 /// [Bit 1] Slice 1 select.\r
dc5d621c 2023 ///\r
0f16be6d 2024 UINT32 PMI_Sel_Slice1:1;\r
dc5d621c 2025 ///\r
0f16be6d 2026 /// [Bit 2] Slice 2 select.\r
dc5d621c 2027 ///\r
0f16be6d 2028 UINT32 PMI_Sel_Slice2:1;\r
dc5d621c 2029 ///\r
0f16be6d 2030 /// [Bit 3] Slice 3 select.\r
dc5d621c 2031 ///\r
0f16be6d
HW		 2032 UINT32 PMI_Sel_Slice3:1;\r
2033 ///\r
2034 /// [Bit 4] Slice 4 select.\r
2035 ///\r
2036 UINT32 PMI_Sel_Slice4:1;\r
2037 UINT32 Reserved1:14;\r
dc5d621c
MK		 2038 UINT32 Reserved2:10;\r
2039 ///\r
2040 /// [Bit 29] Enable all uncore counters.\r
2041 ///\r
2042 UINT32 EN:1;\r
2043 ///\r
2044 /// [Bit 30] Enable wake on PMI.\r
2045 ///\r
2046 UINT32 WakePMI:1;\r
2047 ///\r
2048 /// [Bit 31] Enable Freezing counter when overflow.\r
2049 ///\r
2050 UINT32 FREEZE:1;\r
2051 UINT32 Reserved3:32;\r
2052 } Bits;\r
2053 ///\r
2054 /// All bit fields as a 32-bit value\r
2055 ///\r
2056 UINT32 Uint32;\r
2057 ///\r
2058 /// All bit fields as a 64-bit value\r
2059 ///\r
2060 UINT64 Uint64;\r
2061} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
2062\r
2063\r
2064/**\r
2065 Package. Uncore PMU main status.\r
2066\r
2067 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS (0x00000392)\r
2068 @param EAX Lower 32-bits of MSR value.\r
2069 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
2070 @param EDX Upper 32-bits of MSR value.\r
2071 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
2072\r
2073 <b>Example usage</b>\r
2074 @code\r
2075 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;\r
2076\r
2077 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS);\r
2078 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r
2079 @endcode\r
367f5c9c 2080 @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r
dc5d621c
MK		 2081**/\r
2082#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS 0x00000392\r
2083\r
2084/**\r
2085 MSR information returned for MSR index\r
2086 #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS\r
2087**/\r
2088typedef union {\r
2089 ///\r
2090 /// Individual bit fields\r
2091 ///\r
2092 struct {\r
2093 ///\r
2094 /// [Bit 0] Fixed counter overflowed.\r
2095 ///\r
2096 UINT32 Fixed:1;\r
2097 ///\r
2098 /// [Bit 1] An ARB counter overflowed.\r
2099 ///\r
2100 UINT32 ARB:1;\r
2101 UINT32 Reserved1:1;\r
2102 ///\r
2103 /// [Bit 3] A CBox counter overflowed (on any slice).\r
2104 ///\r
2105 UINT32 CBox:1;\r
2106 UINT32 Reserved2:28;\r
2107 UINT32 Reserved3:32;\r
2108 } Bits;\r
2109 ///\r
2110 /// All bit fields as a 32-bit value\r
2111 ///\r
2112 UINT32 Uint32;\r
2113 ///\r
2114 /// All bit fields as a 64-bit value\r
2115 ///\r
2116 UINT64 Uint64;\r
2117} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
2118\r
2119\r
2120/**\r
2121 Package. Uncore fixed counter control (R/W).\r
2122\r
2123 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL (0x00000394)\r
2124 @param EAX Lower 32-bits of MSR value.\r
2125 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.\r
2126 @param EDX Upper 32-bits of MSR value.\r
2127 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.\r
2128\r
2129 <b>Example usage</b>\r
2130 @code\r
2131 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Msr;\r
2132\r
2133 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL);\r
2134 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r
2135 @endcode\r
367f5c9c 2136 @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
dc5d621c
MK		 2137**/\r
2138#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394\r
2139\r
2140/**\r
2141 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL\r
2142**/\r
2143typedef union {\r
2144 ///\r
2145 /// Individual bit fields\r
2146 ///\r
2147 struct {\r
2148 UINT32 Reserved1:20;\r
2149 ///\r
2150 /// [Bit 20] Enable overflow propagation.\r
2151 ///\r
2152 UINT32 EnableOverflow:1;\r
2153 UINT32 Reserved2:1;\r
2154 ///\r
2155 /// [Bit 22] Enable counting.\r
2156 ///\r
2157 UINT32 EnableCounting:1;\r
2158 UINT32 Reserved3:9;\r
2159 UINT32 Reserved4:32;\r
2160 } Bits;\r
2161 ///\r
2162 /// All bit fields as a 32-bit value\r
2163 ///\r
2164 UINT32 Uint32;\r
2165 ///\r
2166 /// All bit fields as a 64-bit value\r
2167 ///\r
2168 UINT64 Uint64;\r
2169} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER;\r
2170\r
2171\r
2172/**\r
2173 Package. Uncore fixed counter.\r
2174\r
2175 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR (0x00000395)\r
2176 @param EAX Lower 32-bits of MSR value.\r
2177 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.\r
2178 @param EDX Upper 32-bits of MSR value.\r
2179 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.\r
2180\r
2181 <b>Example usage</b>\r
2182 @code\r
2183 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Msr;\r
2184\r
2185 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR);\r
2186 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64);\r
2187 @endcode\r
367f5c9c 2188 @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
dc5d621c
MK		 2189**/\r
2190#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395\r
2191\r
2192/**\r
2193 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR\r
2194**/\r
2195typedef union {\r
2196 ///\r
2197 /// Individual bit fields\r
2198 ///\r
2199 struct {\r
2200 ///\r
2201 /// [Bits 31:0] Current count.\r
2202 ///\r
2203 UINT32 CurrentCount:32;\r
2204 ///\r
2205 /// [Bits 47:32] Current count.\r
2206 ///\r
2207 UINT32 CurrentCountHi:16;\r
2208 UINT32 Reserved:16;\r
2209 } Bits;\r
2210 ///\r
2211 /// All bit fields as a 64-bit value\r
2212 ///\r
2213 UINT64 Uint64;\r
2214} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER;\r
2215\r
2216\r
2217/**\r
2218 Package. Uncore C-Box configuration information (R/O).\r
2219\r
2220 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_CONFIG (0x00000396)\r
2221 @param EAX Lower 32-bits of MSR value.\r
2222 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.\r
2223 @param EDX Upper 32-bits of MSR value.\r
2224 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.\r
2225\r
2226 <b>Example usage</b>\r
2227 @code\r
2228 MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Msr;\r
2229\r
2230 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG);\r
2231 @endcode\r
367f5c9c 2232 @note MSR_SANDY_BRIDGE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
dc5d621c
MK		 2233**/\r
2234#define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396\r
2235\r
2236/**\r
2237 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG\r
2238**/\r
2239typedef union {\r
2240 ///\r
2241 /// Individual bit fields\r
2242 ///\r
2243 struct {\r
2244 ///\r
0f16be6d
HW		 2245 /// [Bits 3:0] Report the number of C-Box units with performance counters,\r
2246 /// including processor cores and processor graphics".\r
dc5d621c
MK		 2247 ///\r
2248 UINT32 CBox:4;\r
2249 UINT32 Reserved1:28;\r
2250 UINT32 Reserved2:32;\r
2251 } Bits;\r
2252 ///\r
2253 /// All bit fields as a 32-bit value\r
2254 ///\r
2255 UINT32 Uint32;\r
2256 ///\r
2257 /// All bit fields as a 64-bit value\r
2258 ///\r
2259 UINT64 Uint64;\r
2260} MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER;\r
2261\r
2262\r
2263/**\r
2264 Package. Uncore Arb unit, performance counter 0.\r
2265\r
2266 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 (0x000003B0)\r
2267 @param EAX Lower 32-bits of MSR value.\r
2268 @param EDX Upper 32-bits of MSR value.\r
2269\r
2270 <b>Example usage</b>\r
2271 @code\r
2272 UINT64 Msr;\r
2273\r
2274 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0);\r
2275 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr);\r
2276 @endcode\r
367f5c9c 2277 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
dc5d621c
MK		 2278**/\r
2279#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0\r
2280\r
2281\r
2282/**\r
2283 Package. Uncore Arb unit, performance counter 1.\r
2284\r
2285 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 (0x000003B1)\r
2286 @param EAX Lower 32-bits of MSR value.\r
2287 @param EDX Upper 32-bits of MSR value.\r
2288\r
2289 <b>Example usage</b>\r
2290 @code\r
2291 UINT64 Msr;\r
2292\r
2293 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1);\r
2294 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr);\r
2295 @endcode\r
367f5c9c 2296 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
dc5d621c
MK		 2297**/\r
2298#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1\r
2299\r
2300\r
2301/**\r
2302 Package. Uncore Arb unit, counter 0 event select MSR.\r
2303\r
2304 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 (0x000003B2)\r
2305 @param EAX Lower 32-bits of MSR value.\r
2306 @param EDX Upper 32-bits of MSR value.\r
2307\r
2308 <b>Example usage</b>\r
2309 @code\r
2310 UINT64 Msr;\r
2311\r
2312 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0);\r
2313 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr);\r
2314 @endcode\r
367f5c9c 2315 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
dc5d621c
MK		 2316**/\r
2317#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2\r
2318\r
2319\r
2320/**\r
2321 Package. Uncore Arb unit, counter 1 event select MSR.\r
2322\r
2323 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 (0x000003B3)\r
2324 @param EAX Lower 32-bits of MSR value.\r
2325 @param EDX Upper 32-bits of MSR value.\r
2326\r
2327 <b>Example usage</b>\r
2328 @code\r
2329 UINT64 Msr;\r
2330\r
2331 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1);\r
2332 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr);\r
2333 @endcode\r
367f5c9c 2334 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.\r
dc5d621c
MK		 2335**/\r
2336#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3\r
2337\r
2338\r
2339/**\r
2340 Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the\r
2341 budget allocated for the package to exit from C7 to a C0 state, where\r
2342 interrupt request can be delivered to the core and serviced. Additional\r
2343 core-exit latency amy be applicable depending on the actual C-state the core\r
2344 is in. Note: C-state values are processor specific C-state code names,\r
2345 unrelated to MWAIT extension C-state parameters or ACPI CStates.\r
2346\r
2347 @param ECX MSR_SANDY_BRIDGE_PKGC7_IRTL (0x0000060C)\r
2348 @param EAX Lower 32-bits of MSR value.\r
2349 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.\r
2350 @param EDX Upper 32-bits of MSR value.\r
2351 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.\r
2352\r
2353 <b>Example usage</b>\r
2354 @code\r
2355 MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Msr;\r
2356\r
2357 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL);\r
2358 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64);\r
2359 @endcode\r
367f5c9c 2360 @note MSR_SANDY_BRIDGE_PKGC7_IRTL is defined as MSR_PKGC7_IRTL in SDM.\r
dc5d621c
MK		 2361**/\r
2362#define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C\r
2363\r
2364/**\r
2365 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL\r
2366**/\r
2367typedef union {\r
2368 ///\r
2369 /// Individual bit fields\r
2370 ///\r
2371 struct {\r
2372 ///\r
2373 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
2374 /// that should be used to decide if the package should be put into a\r
2375 /// package C7 state.\r
2376 ///\r
2377 UINT32 TimeLimit:10;\r
2378 ///\r
2379 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
2380 /// unit of the interrupt response time limit. The following time unit\r
2381 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
2382 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
2383 ///\r
2384 UINT32 TimeUnit:3;\r
2385 UINT32 Reserved1:2;\r
2386 ///\r
2387 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
2388 /// valid and can be used by the processor for package C-sate management.\r
2389 ///\r
2390 UINT32 Valid:1;\r
2391 UINT32 Reserved2:16;\r
2392 UINT32 Reserved3:32;\r
2393 } Bits;\r
2394 ///\r
2395 /// All bit fields as a 32-bit value\r
2396 ///\r
2397 UINT32 Uint32;\r
2398 ///\r
2399 /// All bit fields as a 64-bit value\r
2400 ///\r
2401 UINT64 Uint64;\r
2402} MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER;\r
2403\r
2404\r
2405/**\r
2406 Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
2407 Domains.".\r
2408\r
2409 @param ECX MSR_SANDY_BRIDGE_PP0_POLICY (0x0000063A)\r
2410 @param EAX Lower 32-bits of MSR value.\r
2411 @param EDX Upper 32-bits of MSR value.\r
2412\r
2413 <b>Example usage</b>\r
2414 @code\r
2415 UINT64 Msr;\r
2416\r
2417 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY);\r
2418 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr);\r
2419 @endcode\r
367f5c9c 2420 @note MSR_SANDY_BRIDGE_PP0_POLICY is defined as MSR_PP0_POLICY in SDM.\r
dc5d621c
MK		 2421**/\r
2422#define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A\r
2423\r
2424\r
2425/**\r
2426 Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
2427 RAPL Domains.".\r
2428\r
2429 @param ECX MSR_SANDY_BRIDGE_PP1_POWER_LIMIT (0x00000640)\r
2430 @param EAX Lower 32-bits of MSR value.\r
2431 @param EDX Upper 32-bits of MSR value.\r
2432\r
2433 <b>Example usage</b>\r
2434 @code\r
2435 UINT64 Msr;\r
2436\r
2437 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT);\r
2438 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr);\r
2439 @endcode\r
367f5c9c 2440 @note MSR_SANDY_BRIDGE_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.\r
dc5d621c
MK		 2441**/\r
2442#define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640\r
2443\r
2444\r
2445/**\r
2446 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
2447 Domains.".\r
2448\r
2449 @param ECX MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS (0x00000641)\r
2450 @param EAX Lower 32-bits of MSR value.\r
2451 @param EDX Upper 32-bits of MSR value.\r
2452\r
2453 <b>Example usage</b>\r
2454 @code\r
2455 UINT64 Msr;\r
2456\r
2457 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS);\r
2458 @endcode\r
367f5c9c 2459 @note MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r
dc5d621c
MK		 2460**/\r
2461#define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641\r
2462\r
2463\r
2464/**\r
2465 Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
2466 Domains.".\r
2467\r
2468 @param ECX MSR_SANDY_BRIDGE_PP1_POLICY (0x00000642)\r
2469 @param EAX Lower 32-bits of MSR value.\r
2470 @param EDX Upper 32-bits of MSR value.\r
2471\r
2472 <b>Example usage</b>\r
2473 @code\r
2474 UINT64 Msr;\r
2475\r
2476 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY);\r
2477 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr);\r
2478 @endcode\r
367f5c9c 2479 @note MSR_SANDY_BRIDGE_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.\r
dc5d621c
MK		 2480**/\r
2481#define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642\r
2482\r
2483\r
2484/**\r
0f16be6d 2485 Package. Uncore C-Box 0, counter n event select MSR.\r
dc5d621c 2486\r
0f16be6d 2487 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSELn\r
dc5d621c
MK		 2488 @param EAX Lower 32-bits of MSR value.\r
2489 @param EDX Upper 32-bits of MSR value.\r
2490\r
2491 <b>Example usage</b>\r
2492 @code\r
2493 UINT64 Msr;\r
2494\r
2495 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0);\r
2496 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr);\r
2497 @endcode\r
367f5c9c 2498 @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r
0f16be6d
HW		 2499 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
2500 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 is defined as MSR_UNC_CBO_0_PERFEVTSEL2 in SDM.\r
2501 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 is defined as MSR_UNC_CBO_0_PERFEVTSEL3 in SDM.\r
2502 @{\r
dc5d621c
MK		 2503**/\r
2504#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
0f16be6d
HW		 2505#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
2506#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702\r
2507#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703\r
2508/// @}\r
dc5d621c
MK		 2509\r
2510\r
2511/**\r
0f16be6d 2512 Package. Uncore C-Box n, unit status for counter 0-3.\r
dc5d621c 2513\r
0f16be6d 2514 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_n_UNIT_STATUS\r
dc5d621c
MK		 2515 @param EAX Lower 32-bits of MSR value.\r
2516 @param EDX Upper 32-bits of MSR value.\r
2517\r
2518 <b>Example usage</b>\r
2519 @code\r
2520 UINT64 Msr;\r
2521\r
0f16be6d
HW		 2522 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS);\r
2523 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS, Msr);\r
dc5d621c 2524 @endcode\r
0f16be6d
HW		 2525 @note MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS is defined as MSR_UNC_CBO_0_UNIT_STATUS in SDM.\r
2526 MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS is defined as MSR_UNC_CBO_1_UNIT_STATUS in SDM.\r
2527 MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS is defined as MSR_UNC_CBO_2_UNIT_STATUS in SDM.\r
2528 MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS is defined as MSR_UNC_CBO_3_UNIT_STATUS in SDM.\r
2529 MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS is defined as MSR_UNC_CBO_4_UNIT_STATUS in SDM.\r
2530 @{\r
dc5d621c 2531**/\r
0f16be6d
HW		 2532#define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705\r
2533#define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715\r
2534#define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725\r
2535#define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735\r
2536#define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745\r
2537/// @}\r
dc5d621c
MK		 2538\r
2539\r
2540/**\r
0f16be6d 2541 Package. Uncore C-Box 0, performance counter n.\r
dc5d621c 2542\r
0f16be6d 2543 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTRn\r
dc5d621c
MK		 2544 @param EAX Lower 32-bits of MSR value.\r
2545 @param EDX Upper 32-bits of MSR value.\r
2546\r
2547 <b>Example usage</b>\r
2548 @code\r
2549 UINT64 Msr;\r
2550\r
2551 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0);\r
2552 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr);\r
2553 @endcode\r
367f5c9c 2554 @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r
0f16be6d
HW		 2555 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
2556 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 is defined as MSR_UNC_CBO_0_PERFCTR2 in SDM.\r
2557 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 is defined as MSR_UNC_CBO_0_PERFCTR3 in SDM.\r
2558 @{\r
dc5d621c
MK		 2559**/\r
2560#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706\r
dc5d621c 2561#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707\r
0f16be6d
HW		 2562#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708\r
2563#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709\r
2564/// @}\r
dc5d621c
MK		 2565\r
2566\r
2567/**\r
0f16be6d 2568 Package. Uncore C-Box 1, counter n event select MSR.\r
dc5d621c 2569\r
0f16be6d 2570 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSELn\r
dc5d621c
MK		 2571 @param EAX Lower 32-bits of MSR value.\r
2572 @param EDX Upper 32-bits of MSR value.\r
2573\r
2574 <b>Example usage</b>\r
2575 @code\r
2576 UINT64 Msr;\r
2577\r
2578 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0);\r
2579 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr);\r
2580 @endcode\r
367f5c9c 2581 @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r
0f16be6d
HW		 2582 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
2583 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 is defined as MSR_UNC_CBO_1_PERFEVTSEL2 in SDM.\r
2584 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 is defined as MSR_UNC_CBO_1_PERFEVTSEL3 in SDM.\r
2585 @{\r
dc5d621c
MK		 2586**/\r
2587#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
dc5d621c 2588#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
0f16be6d
HW		 2589#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712\r
2590#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713\r
2591/// @}\r
dc5d621c
MK		 2592\r
2593\r
2594/**\r
0f16be6d 2595 Package. Uncore C-Box 1, performance counter n.\r
dc5d621c 2596\r
0f16be6d 2597 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTRn\r
dc5d621c
MK		 2598 @param EAX Lower 32-bits of MSR value.\r
2599 @param EDX Upper 32-bits of MSR value.\r
2600\r
2601 <b>Example usage</b>\r
2602 @code\r
2603 UINT64 Msr;\r
2604\r
2605 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0);\r
2606 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr);\r
2607 @endcode\r
367f5c9c 2608 @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r
0f16be6d
HW		 2609 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
2610 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 is defined as MSR_UNC_CBO_1_PERFCTR2 in SDM.\r
2611 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 is defined as MSR_UNC_CBO_1_PERFCTR3 in SDM.\r
2612 @{\r
dc5d621c
MK		 2613**/\r
2614#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716\r
dc5d621c 2615#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717\r
0f16be6d
HW		 2616#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718\r
2617#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719\r
2618/// @}\r
dc5d621c
MK		 2619\r
2620\r
2621/**\r
0f16be6d 2622 Package. Uncore C-Box 2, counter n event select MSR.\r
dc5d621c 2623\r
0f16be6d 2624 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSELn\r
dc5d621c
MK		 2625 @param EAX Lower 32-bits of MSR value.\r
2626 @param EDX Upper 32-bits of MSR value.\r
2627\r
2628 <b>Example usage</b>\r
2629 @code\r
2630 UINT64 Msr;\r
2631\r
2632 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0);\r
2633 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr);\r
2634 @endcode\r
367f5c9c 2635 @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r
0f16be6d
HW		 2636 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
2637 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 is defined as MSR_UNC_CBO_2_PERFEVTSEL2 in SDM.\r
2638 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 is defined as MSR_UNC_CBO_2_PERFEVTSEL3 in SDM.\r
2639 @{\r
dc5d621c
MK		 2640**/\r
2641#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
dc5d621c 2642#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
0f16be6d
HW		 2643#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722\r
2644#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723\r
2645/// @}\r
dc5d621c
MK		 2646\r
2647\r
2648/**\r
0f16be6d 2649 Package. Uncore C-Box 2, performance counter n.\r
dc5d621c 2650\r
0f16be6d 2651 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTRn\r
dc5d621c
MK		 2652 @param EAX Lower 32-bits of MSR value.\r
2653 @param EDX Upper 32-bits of MSR value.\r
2654\r
2655 <b>Example usage</b>\r
2656 @code\r
2657 UINT64 Msr;\r
2658\r
2659 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0);\r
2660 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr);\r
2661 @endcode\r
367f5c9c 2662 @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r
0f16be6d
HW		 2663 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
2664 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 is defined as MSR_UNC_CBO_2_PERFCTR2 in SDM.\r
2665 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 is defined as MSR_UNC_CBO_2_PERFCTR3 in SDM.\r
2666 @{\r
dc5d621c
MK		 2667**/\r
2668#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726\r
dc5d621c 2669#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727\r
0f16be6d
HW		 2670#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728\r
2671#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729\r
2672/// @}\r
dc5d621c
MK		 2673\r
2674\r
2675/**\r
0f16be6d 2676 Package. Uncore C-Box 3, counter n event select MSR.\r
dc5d621c 2677\r
0f16be6d 2678 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSELn\r
dc5d621c
MK		 2679 @param EAX Lower 32-bits of MSR value.\r
2680 @param EDX Upper 32-bits of MSR value.\r
2681\r
2682 <b>Example usage</b>\r
2683 @code\r
2684 UINT64 Msr;\r
2685\r
2686 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0);\r
2687 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr);\r
2688 @endcode\r
367f5c9c 2689 @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r
0f16be6d
HW		 2690 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
2691 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 is defined as MSR_UNC_CBO_3_PERFEVTSEL2 in SDM.\r
2692 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 is defined as MSR_UNC_CBO_3_PERFEVTSEL3 in SDM.\r
2693 @{\r
dc5d621c
MK		 2694**/\r
2695#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
0f16be6d
HW		 2696#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
2697#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732\r
2698#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733\r
2699/// @}\r
dc5d621c
MK		 2700\r
2701\r
2702/**\r
0f16be6d 2703 Package. Uncore C-Box 3, performance counter n.\r
dc5d621c 2704\r
0f16be6d 2705 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTRn\r
dc5d621c
MK		 2706 @param EAX Lower 32-bits of MSR value.\r
2707 @param EDX Upper 32-bits of MSR value.\r
2708\r
2709 <b>Example usage</b>\r
2710 @code\r
2711 UINT64 Msr;\r
2712\r
0f16be6d
HW		 2713 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);\r
2714 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);\r
dc5d621c 2715 @endcode\r
0f16be6d
HW		 2716 @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
2717 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
2718 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 is defined as MSR_UNC_CBO_3_PERFCTR2 in SDM.\r
2719 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 is defined as MSR_UNC_CBO_3_PERFCTR3 in SDM.\r
2720 @{\r
dc5d621c 2721**/\r
0f16be6d
HW		 2722#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736\r
2723#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737\r
2724#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738\r
2725#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739\r
2726/// @}\r
dc5d621c
MK		 2727\r
2728\r
2729/**\r
0f16be6d 2730 Package. Uncore C-Box 4, counter n event select MSR.\r
dc5d621c 2731\r
0f16be6d 2732 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSELn\r
dc5d621c
MK		 2733 @param EAX Lower 32-bits of MSR value.\r
2734 @param EDX Upper 32-bits of MSR value.\r
2735\r
2736 <b>Example usage</b>\r
2737 @code\r
2738 UINT64 Msr;\r
2739\r
0f16be6d
HW		 2740 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0);\r
2741 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0, Msr);\r
dc5d621c 2742 @endcode\r
0f16be6d
HW		 2743 @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 is defined as MSR_UNC_CBO_4_PERFEVTSEL0 in SDM.\r
2744 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 is defined as MSR_UNC_CBO_4_PERFEVTSEL1 in SDM.\r
2745 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 is defined as MSR_UNC_CBO_4_PERFEVTSEL2 in SDM.\r
2746 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 is defined as MSR_UNC_CBO_4_PERFEVTSEL3 in SDM.\r
2747 @{\r
dc5d621c 2748**/\r
0f16be6d
HW		 2749#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740\r
2750#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741\r
2751#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742\r
2752#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743\r
2753/// @}\r
dc5d621c
MK		 2754\r
2755\r
2756/**\r
0f16be6d 2757 Package. Uncore C-Box 4, performance counter n.\r
dc5d621c 2758\r
0f16be6d 2759 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTRn\r
dc5d621c
MK		 2760 @param EAX Lower 32-bits of MSR value.\r
2761 @param EDX Upper 32-bits of MSR value.\r
2762\r
2763 <b>Example usage</b>\r
2764 @code\r
2765 UINT64 Msr;\r
2766\r
0f16be6d
HW		 2767 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0);\r
2768 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0, Msr);\r
dc5d621c 2769 @endcode\r
0f16be6d
HW		 2770 @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 is defined as MSR_UNC_CBO_4_PERFCTR0 in SDM.\r
2771 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 is defined as MSR_UNC_CBO_4_PERFCTR1 in SDM.\r
2772 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 is defined as MSR_UNC_CBO_4_PERFCTR2 in SDM.\r
2773 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 is defined as MSR_UNC_CBO_4_PERFCTR3 in SDM.\r
2774 @{\r
dc5d621c 2775**/\r
0f16be6d
HW		 2776#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746\r
2777#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747\r
2778#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748\r
2779#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749\r
2780/// @}\r
dc5d621c
MK		 2781\r
2782\r
2783/**\r
2784 Package. MC Bank Error Configuration (R/W).\r
2785\r
2786 @param ECX MSR_SANDY_BRIDGE_ERROR_CONTROL (0x0000017F)\r
2787 @param EAX Lower 32-bits of MSR value.\r
2788 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.\r
2789 @param EDX Upper 32-bits of MSR value.\r
2790 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.\r
2791\r
2792 <b>Example usage</b>\r
2793 @code\r
2794 MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Msr;\r
2795\r
2796 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL);\r
2797 AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64);\r
2798 @endcode\r
367f5c9c 2799 @note MSR_SANDY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r
dc5d621c
MK		 2800**/\r
2801#define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F\r
2802\r
2803/**\r
2804 MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL\r
2805**/\r
2806typedef union {\r
2807 ///\r
2808 /// Individual bit fields\r
2809 ///\r
2810 struct {\r
2811 UINT32 Reserved1:1;\r
2812 ///\r
2813 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r
2814 /// to log additional info in bits 36:32.\r
2815 ///\r
2816 UINT32 MemErrorLogEnable:1;\r
2817 UINT32 Reserved2:30;\r
2818 UINT32 Reserved3:32;\r
2819 } Bits;\r
2820 ///\r
2821 /// All bit fields as a 32-bit value\r
2822 ///\r
2823 UINT32 Uint32;\r
2824 ///\r
2825 /// All bit fields as a 64-bit value\r
2826 ///\r
2827 UINT64 Uint64;\r
2828} MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER;\r
2829\r
2830\r
2831/**\r
2832 Package.\r
2833\r
2834 @param ECX MSR_SANDY_BRIDGE_PEBS_NUM_ALT (0x0000039C)\r
2835 @param EAX Lower 32-bits of MSR value.\r
2836 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.\r
2837 @param EDX Upper 32-bits of MSR value.\r
2838 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.\r
2839\r
2840 <b>Example usage</b>\r
2841 @code\r
2842 MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Msr;\r
2843\r
2844 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT);\r
2845 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64);\r
2846 @endcode\r
367f5c9c 2847 @note MSR_SANDY_BRIDGE_PEBS_NUM_ALT is defined as MSR_PEBS_NUM_ALT in SDM.\r
dc5d621c
MK		 2848**/\r
2849#define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C\r
2850\r
2851/**\r
2852 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT\r
2853**/\r
2854typedef union {\r
2855 ///\r
2856 /// Individual bit fields\r
2857 ///\r
2858 struct {\r
2859 ///\r
2860 /// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS\r
2861 /// counting logic for specific events requiring additional configuration,\r
0f16be6d 2862 /// see Table 19-15.\r
dc5d621c
MK		 2863 ///\r
2864 UINT32 ENABLE_PEBS_NUM_ALT:1;\r
2865 UINT32 Reserved1:31;\r
2866 UINT32 Reserved2:32;\r
2867 } Bits;\r
2868 ///\r
2869 /// All bit fields as a 32-bit value\r
2870 ///\r
2871 UINT32 Uint32;\r
2872 ///\r
2873 /// All bit fields as a 64-bit value\r
2874 ///\r
2875 UINT64 Uint64;\r
2876} MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER;\r
2877\r
2878\r
dc5d621c
MK		 2879/**\r
2880 Package. Package RAPL Perf Status (R/O).\r
2881\r
2882 @param ECX MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613)\r
2883 @param EAX Lower 32-bits of MSR value.\r
2884 @param EDX Upper 32-bits of MSR value.\r
2885\r
2886 <b>Example usage</b>\r
2887 @code\r
2888 UINT64 Msr;\r
2889\r
2890 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS);\r
2891 @endcode\r
367f5c9c 2892 @note MSR_SANDY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
dc5d621c
MK		 2893**/\r
2894#define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613\r
2895\r
2896\r
2897/**\r
2898 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
2899 Domain.".\r
2900\r
2901 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)\r
2902 @param EAX Lower 32-bits of MSR value.\r
2903 @param EDX Upper 32-bits of MSR value.\r
2904\r
2905 <b>Example usage</b>\r
2906 @code\r
2907 UINT64 Msr;\r
2908\r
2909 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT);\r
2910 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr);\r
2911 @endcode\r
367f5c9c 2912 @note MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
dc5d621c
MK		 2913**/\r
2914#define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r
2915\r
2916\r
2917/**\r
2918 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
2919\r
2920 @param ECX MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)\r
2921 @param EAX Lower 32-bits of MSR value.\r
2922 @param EDX Upper 32-bits of MSR value.\r
2923\r
2924 <b>Example usage</b>\r
2925 @code\r
2926 UINT64 Msr;\r
2927\r
2928 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS);\r
2929 @endcode\r
367f5c9c 2930 @note MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
dc5d621c
MK		 2931**/\r
2932#define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r
2933\r
2934\r
2935/**\r
2936 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
2937 RAPL Domain.".\r
2938\r
2939 @param ECX MSR_SANDY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)\r
2940 @param EAX Lower 32-bits of MSR value.\r
2941 @param EDX Upper 32-bits of MSR value.\r
2942\r
2943 <b>Example usage</b>\r
2944 @code\r
2945 UINT64 Msr;\r
2946\r
2947 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS);\r
2948 @endcode\r
367f5c9c 2949 @note MSR_SANDY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
dc5d621c
MK		 2950**/\r
2951#define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r
2952\r
2953\r
2954/**\r
2955 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
2956\r
2957 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_INFO (0x0000061C)\r
2958 @param EAX Lower 32-bits of MSR value.\r
2959 @param EDX Upper 32-bits of MSR value.\r
2960\r
2961 <b>Example usage</b>\r
2962 @code\r
2963 UINT64 Msr;\r
2964\r
2965 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO);\r
2966 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr);\r
2967 @endcode\r
367f5c9c 2968 @note MSR_SANDY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
dc5d621c
MK		 2969**/\r
2970#define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r
2971\r
2972\r
2973/**\r
2974 Package. Uncore U-box UCLK fixed counter control.\r
2975\r
2976 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL (0x00000C08)\r
2977 @param EAX Lower 32-bits of MSR value.\r
2978 @param EDX Upper 32-bits of MSR value.\r
2979\r
2980 <b>Example usage</b>\r
2981 @code\r
2982 UINT64 Msr;\r
2983\r
2984 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL);\r
2985 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr);\r
2986 @endcode\r
367f5c9c 2987 @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.\r
dc5d621c
MK		 2988**/\r
2989#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08\r
2990\r
2991\r
2992/**\r
2993 Package. Uncore U-box UCLK fixed counter.\r
2994\r
2995 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR (0x00000C09)\r
2996 @param EAX Lower 32-bits of MSR value.\r
2997 @param EDX Upper 32-bits of MSR value.\r
2998\r
2999 <b>Example usage</b>\r
3000 @code\r
3001 UINT64 Msr;\r
3002\r
3003 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR);\r
3004 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr);\r
3005 @endcode\r
367f5c9c 3006 @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.\r
dc5d621c
MK		 3007**/\r
3008#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09\r
3009\r
3010\r
3011/**\r
3012 Package. Uncore U-box perfmon event select for U-box counter 0.\r
3013\r
3014 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 (0x00000C10)\r
3015 @param EAX Lower 32-bits of MSR value.\r
3016 @param EDX Upper 32-bits of MSR value.\r
3017\r
3018 <b>Example usage</b>\r
3019 @code\r
3020 UINT64 Msr;\r
3021\r
3022 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0);\r
3023 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr);\r
3024 @endcode\r
367f5c9c 3025 @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.\r
dc5d621c
MK		 3026**/\r
3027#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10\r
3028\r
3029\r
3030/**\r
3031 Package. Uncore U-box perfmon event select for U-box counter 1.\r
3032\r
3033 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 (0x00000C11)\r
3034 @param EAX Lower 32-bits of MSR value.\r
3035 @param EDX Upper 32-bits of MSR value.\r
3036\r
3037 <b>Example usage</b>\r
3038 @code\r
3039 UINT64 Msr;\r
3040\r
3041 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1);\r
3042 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr);\r
3043 @endcode\r
367f5c9c 3044 @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.\r
dc5d621c
MK		 3045**/\r
3046#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11\r
3047\r
3048\r
3049/**\r
3050 Package. Uncore U-box perfmon counter 0.\r
3051\r
3052 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR0 (0x00000C16)\r
3053 @param EAX Lower 32-bits of MSR value.\r
3054 @param EDX Upper 32-bits of MSR value.\r
3055\r
3056 <b>Example usage</b>\r
3057 @code\r
3058 UINT64 Msr;\r
3059\r
3060 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0);\r
3061 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr);\r
3062 @endcode\r
367f5c9c 3063 @note MSR_SANDY_BRIDGE_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.\r
dc5d621c
MK		 3064**/\r
3065#define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16\r
3066\r
3067\r
3068/**\r
3069 Package. Uncore U-box perfmon counter 1.\r
3070\r
3071 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR1 (0x00000C17)\r
3072 @param EAX Lower 32-bits of MSR value.\r
3073 @param EDX Upper 32-bits of MSR value.\r
3074\r
3075 <b>Example usage</b>\r
3076 @code\r
3077 UINT64 Msr;\r
3078\r
3079 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1);\r
3080 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr);\r
3081 @endcode\r
367f5c9c 3082 @note MSR_SANDY_BRIDGE_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.\r
dc5d621c
MK		 3083**/\r
3084#define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17\r
3085\r
3086\r
3087/**\r
3088 Package. Uncore PCU perfmon for PCU-box-wide control.\r
3089\r
3090 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL (0x00000C24)\r
3091 @param EAX Lower 32-bits of MSR value.\r
3092 @param EDX Upper 32-bits of MSR value.\r
3093\r
3094 <b>Example usage</b>\r
3095 @code\r
3096 UINT64 Msr;\r
3097\r
3098 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL);\r
3099 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr);\r
3100 @endcode\r
367f5c9c 3101 @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.\r
dc5d621c
MK		 3102**/\r
3103#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24\r
3104\r
3105\r
3106/**\r
3107 Package. Uncore PCU perfmon event select for PCU counter 0.\r
3108\r
3109 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 (0x00000C30)\r
3110 @param EAX Lower 32-bits of MSR value.\r
3111 @param EDX Upper 32-bits of MSR value.\r
3112\r
3113 <b>Example usage</b>\r
3114 @code\r
3115 UINT64 Msr;\r
3116\r
3117 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0);\r
3118 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr);\r
3119 @endcode\r
367f5c9c 3120 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.\r
dc5d621c
MK		 3121**/\r
3122#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30\r
3123\r
3124\r
3125/**\r
3126 Package. Uncore PCU perfmon event select for PCU counter 1.\r
3127\r
3128 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 (0x00000C31)\r
3129 @param EAX Lower 32-bits of MSR value.\r
3130 @param EDX Upper 32-bits of MSR value.\r
3131\r
3132 <b>Example usage</b>\r
3133 @code\r
3134 UINT64 Msr;\r
3135\r
3136 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1);\r
3137 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr);\r
3138 @endcode\r
367f5c9c 3139 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.\r
dc5d621c
MK		 3140**/\r
3141#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31\r
3142\r
3143\r
3144/**\r
3145 Package. Uncore PCU perfmon event select for PCU counter 2.\r
3146\r
3147 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 (0x00000C32)\r
3148 @param EAX Lower 32-bits of MSR value.\r
3149 @param EDX Upper 32-bits of MSR value.\r
3150\r
3151 <b>Example usage</b>\r
3152 @code\r
3153 UINT64 Msr;\r
3154\r
3155 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2);\r
3156 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr);\r
3157 @endcode\r
367f5c9c 3158 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.\r
dc5d621c
MK		 3159**/\r
3160#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32\r
3161\r
3162\r
3163/**\r
3164 Package. Uncore PCU perfmon event select for PCU counter 3.\r
3165\r
3166 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 (0x00000C33)\r
3167 @param EAX Lower 32-bits of MSR value.\r
3168 @param EDX Upper 32-bits of MSR value.\r
3169\r
3170 <b>Example usage</b>\r
3171 @code\r
3172 UINT64 Msr;\r
3173\r
3174 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3);\r
3175 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr);\r
3176 @endcode\r
367f5c9c 3177 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.\r
dc5d621c
MK		 3178**/\r
3179#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33\r
3180\r
3181\r
3182/**\r
3183 Package. Uncore PCU perfmon box-wide filter.\r
3184\r
3185 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER (0x00000C34)\r
3186 @param EAX Lower 32-bits of MSR value.\r
3187 @param EDX Upper 32-bits of MSR value.\r
3188\r
3189 <b>Example usage</b>\r
3190 @code\r
3191 UINT64 Msr;\r
3192\r
3193 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER);\r
3194 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr);\r
3195 @endcode\r
367f5c9c 3196 @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.\r
dc5d621c
MK		 3197**/\r
3198#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34\r
3199\r
3200\r
3201/**\r
3202 Package. Uncore PCU perfmon counter 0.\r
3203\r
3204 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR0 (0x00000C36)\r
3205 @param EAX Lower 32-bits of MSR value.\r
3206 @param EDX Upper 32-bits of MSR value.\r
3207\r
3208 <b>Example usage</b>\r
3209 @code\r
3210 UINT64 Msr;\r
3211\r
3212 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0);\r
3213 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr);\r
3214 @endcode\r
367f5c9c 3215 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.\r
dc5d621c
MK		 3216**/\r
3217#define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36\r
3218\r
3219\r
3220/**\r
3221 Package. Uncore PCU perfmon counter 1.\r
3222\r
3223 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR1 (0x00000C37)\r
3224 @param EAX Lower 32-bits of MSR value.\r
3225 @param EDX Upper 32-bits of MSR value.\r
3226\r
3227 <b>Example usage</b>\r
3228 @code\r
3229 UINT64 Msr;\r
3230\r
3231 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1);\r
3232 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr);\r
3233 @endcode\r
367f5c9c 3234 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.\r
dc5d621c
MK		 3235**/\r
3236#define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37\r
3237\r
3238\r
3239/**\r
3240 Package. Uncore PCU perfmon counter 2.\r
3241\r
3242 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR2 (0x00000C38)\r
3243 @param EAX Lower 32-bits of MSR value.\r
3244 @param EDX Upper 32-bits of MSR value.\r
3245\r
3246 <b>Example usage</b>\r
3247 @code\r
3248 UINT64 Msr;\r
3249\r
3250 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2);\r
3251 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr);\r
3252 @endcode\r
367f5c9c 3253 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.\r
dc5d621c
MK		 3254**/\r
3255#define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38\r
3256\r
3257\r
3258/**\r
3259 Package. Uncore PCU perfmon counter 3.\r
3260\r
3261 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR3 (0x00000C39)\r
3262 @param EAX Lower 32-bits of MSR value.\r
3263 @param EDX Upper 32-bits of MSR value.\r
3264\r
3265 <b>Example usage</b>\r
3266 @code\r
3267 UINT64 Msr;\r
3268\r
3269 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3);\r
3270 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr);\r
3271 @endcode\r
367f5c9c 3272 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.\r
dc5d621c
MK		 3273**/\r
3274#define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39\r
3275\r
3276\r
3277/**\r
3278 Package. Uncore C-box 0 perfmon local box wide control.\r
3279\r
3280 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL (0x00000D04)\r
3281 @param EAX Lower 32-bits of MSR value.\r
3282 @param EDX Upper 32-bits of MSR value.\r
3283\r
3284 <b>Example usage</b>\r
3285 @code\r
3286 UINT64 Msr;\r
3287\r
3288 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL);\r
3289 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr);\r
3290 @endcode\r
367f5c9c 3291 @note MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.\r
dc5d621c
MK		 3292**/\r
3293#define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04\r
3294\r
3295\r
3296/**\r
3297 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.\r
3298\r
3299 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 (0x00000D10)\r
3300 @param EAX Lower 32-bits of MSR value.\r
3301 @param EDX Upper 32-bits of MSR value.\r
3302\r
3303 <b>Example usage</b>\r
3304 @code\r
3305 UINT64 Msr;\r
3306\r
3307 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0);\r
3308 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr);\r
3309 @endcode\r
367f5c9c 3310 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.\r
dc5d621c
MK		 3311**/\r
3312#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10\r
3313\r
3314\r
3315/**\r
3316 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.\r
3317\r
3318 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 (0x00000D11)\r
3319 @param EAX Lower 32-bits of MSR value.\r
3320 @param EDX Upper 32-bits of MSR value.\r
3321\r
3322 <b>Example usage</b>\r
3323 @code\r
3324 UINT64 Msr;\r
3325\r
3326 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1);\r
3327 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr);\r
3328 @endcode\r
367f5c9c 3329 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.\r
dc5d621c
MK		 3330**/\r
3331#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11\r
3332\r
3333\r
3334/**\r
3335 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.\r
3336\r
3337 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 (0x00000D12)\r
3338 @param EAX Lower 32-bits of MSR value.\r
3339 @param EDX Upper 32-bits of MSR value.\r
3340\r
3341 <b>Example usage</b>\r
3342 @code\r
3343 UINT64 Msr;\r
3344\r
3345 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2);\r
3346 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr);\r
3347 @endcode\r
367f5c9c 3348 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.\r
dc5d621c
MK		 3349**/\r
3350#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12\r
3351\r
3352\r
3353/**\r
3354 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.\r
3355\r
3356 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 (0x00000D13)\r
3357 @param EAX Lower 32-bits of MSR value.\r
3358 @param EDX Upper 32-bits of MSR value.\r
3359\r
3360 <b>Example usage</b>\r
3361 @code\r
3362 UINT64 Msr;\r
3363\r
3364 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3);\r
3365 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr);\r
3366 @endcode\r
367f5c9c 3367 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.\r
dc5d621c
MK		 3368**/\r
3369#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13\r
3370\r
3371\r
3372/**\r
3373 Package. Uncore C-box 0 perfmon box wide filter.\r
3374\r
3375 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER (0x00000D14)\r
3376 @param EAX Lower 32-bits of MSR value.\r
3377 @param EDX Upper 32-bits of MSR value.\r
3378\r
3379 <b>Example usage</b>\r
3380 @code\r
3381 UINT64 Msr;\r
3382\r
3383 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER);\r
3384 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr);\r
3385 @endcode\r
367f5c9c 3386 @note MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER is defined as MSR_C0_PMON_BOX_FILTER in SDM.\r
dc5d621c
MK		 3387**/\r
3388#define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14\r
3389\r
3390\r
3391/**\r
3392 Package. Uncore C-box 0 perfmon counter 0.\r
3393\r
3394 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR0 (0x00000D16)\r
3395 @param EAX Lower 32-bits of MSR value.\r
3396 @param EDX Upper 32-bits of MSR value.\r
3397\r
3398 <b>Example usage</b>\r
3399 @code\r
3400 UINT64 Msr;\r
3401\r
3402 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0);\r
3403 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr);\r
3404 @endcode\r
367f5c9c 3405 @note MSR_SANDY_BRIDGE_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r
dc5d621c
MK		 3406**/\r
3407#define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16\r
3408\r
3409\r
3410/**\r
3411 Package. Uncore C-box 0 perfmon counter 1.\r
3412\r
3413 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR1 (0x00000D17)\r
3414 @param EAX Lower 32-bits of MSR value.\r
3415 @param EDX Upper 32-bits of MSR value.\r
3416\r
3417 <b>Example usage</b>\r
3418 @code\r
3419 UINT64 Msr;\r
3420\r
3421 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1);\r
3422 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr);\r
3423 @endcode\r
367f5c9c 3424 @note MSR_SANDY_BRIDGE_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r
dc5d621c
MK		 3425**/\r
3426#define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17\r
3427\r
3428\r
3429/**\r
3430 Package. Uncore C-box 0 perfmon counter 2.\r
3431\r
3432 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR2 (0x00000D18)\r
3433 @param EAX Lower 32-bits of MSR value.\r
3434 @param EDX Upper 32-bits of MSR value.\r
3435\r
3436 <b>Example usage</b>\r
3437 @code\r
3438 UINT64 Msr;\r
3439\r
3440 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2);\r
3441 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr);\r
3442 @endcode\r
367f5c9c 3443 @note MSR_SANDY_BRIDGE_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r
dc5d621c
MK		 3444**/\r
3445#define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18\r
3446\r
3447\r
3448/**\r
3449 Package. Uncore C-box 0 perfmon counter 3.\r
3450\r
3451 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR3 (0x00000D19)\r
3452 @param EAX Lower 32-bits of MSR value.\r
3453 @param EDX Upper 32-bits of MSR value.\r
3454\r
3455 <b>Example usage</b>\r
3456 @code\r
3457 UINT64 Msr;\r
3458\r
3459 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3);\r
3460 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr);\r
3461 @endcode\r
367f5c9c 3462 @note MSR_SANDY_BRIDGE_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r
dc5d621c
MK		 3463**/\r
3464#define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19\r
3465\r
3466\r
3467/**\r
3468 Package. Uncore C-box 1 perfmon local box wide control.\r
3469\r
3470 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL (0x00000D24)\r
3471 @param EAX Lower 32-bits of MSR value.\r
3472 @param EDX Upper 32-bits of MSR value.\r
3473\r
3474 <b>Example usage</b>\r
3475 @code\r
3476 UINT64 Msr;\r
3477\r
3478 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL);\r
3479 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr);\r
3480 @endcode\r
367f5c9c 3481 @note MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.\r
dc5d621c
MK		 3482**/\r
3483#define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24\r
3484\r
3485\r
3486/**\r
3487 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.\r
3488\r
3489 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 (0x00000D30)\r
3490 @param EAX Lower 32-bits of MSR value.\r
3491 @param EDX Upper 32-bits of MSR value.\r
3492\r
3493 <b>Example usage</b>\r
3494 @code\r
3495 UINT64 Msr;\r
3496\r
3497 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0);\r
3498 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr);\r
3499 @endcode\r
367f5c9c 3500 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.\r
dc5d621c
MK		 3501**/\r
3502#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30\r
3503\r
3504\r
3505/**\r
3506 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.\r
3507\r
3508 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 (0x00000D31)\r
3509 @param EAX Lower 32-bits of MSR value.\r
3510 @param EDX Upper 32-bits of MSR value.\r
3511\r
3512 <b>Example usage</b>\r
3513 @code\r
3514 UINT64 Msr;\r
3515\r
3516 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1);\r
3517 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr);\r
3518 @endcode\r
367f5c9c 3519 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.\r
dc5d621c
MK		 3520**/\r
3521#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31\r
3522\r
3523\r
3524/**\r
3525 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.\r
3526\r
3527 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 (0x00000D32)\r
3528 @param EAX Lower 32-bits of MSR value.\r
3529 @param EDX Upper 32-bits of MSR value.\r
3530\r
3531 <b>Example usage</b>\r
3532 @code\r
3533 UINT64 Msr;\r
3534\r
3535 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2);\r
3536 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr);\r
3537 @endcode\r
367f5c9c 3538 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.\r
dc5d621c
MK		 3539**/\r
3540#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32\r
3541\r
3542\r
3543/**\r
3544 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.\r
3545\r
3546 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 (0x00000D33)\r
3547 @param EAX Lower 32-bits of MSR value.\r
3548 @param EDX Upper 32-bits of MSR value.\r
3549\r
3550 <b>Example usage</b>\r
3551 @code\r
3552 UINT64 Msr;\r
3553\r
3554 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3);\r
3555 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr);\r
3556 @endcode\r
367f5c9c 3557 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.\r
dc5d621c
MK		 3558**/\r
3559#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33\r
3560\r
3561\r
3562/**\r
3563 Package. Uncore C-box 1 perfmon box wide filter.\r
3564\r
3565 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER (0x00000D34)\r
3566 @param EAX Lower 32-bits of MSR value.\r
3567 @param EDX Upper 32-bits of MSR value.\r
3568\r
3569 <b>Example usage</b>\r
3570 @code\r
3571 UINT64 Msr;\r
3572\r
3573 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER);\r
3574 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr);\r
3575 @endcode\r
367f5c9c 3576 @note MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER is defined as MSR_C1_PMON_BOX_FILTER in SDM.\r
dc5d621c
MK		 3577**/\r
3578#define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34\r
3579\r
3580\r
3581/**\r
3582 Package. Uncore C-box 1 perfmon counter 0.\r
3583\r
3584 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR0 (0x00000D36)\r
3585 @param EAX Lower 32-bits of MSR value.\r
3586 @param EDX Upper 32-bits of MSR value.\r
3587\r
3588 <b>Example usage</b>\r
3589 @code\r
3590 UINT64 Msr;\r
3591\r
3592 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0);\r
3593 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr);\r
3594 @endcode\r
367f5c9c 3595 @note MSR_SANDY_BRIDGE_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r
dc5d621c
MK		 3596**/\r
3597#define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36\r
3598\r
3599\r
3600/**\r
3601 Package. Uncore C-box 1 perfmon counter 1.\r
3602\r
3603 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR1 (0x00000D37)\r
3604 @param EAX Lower 32-bits of MSR value.\r
3605 @param EDX Upper 32-bits of MSR value.\r
3606\r
3607 <b>Example usage</b>\r
3608 @code\r
3609 UINT64 Msr;\r
3610\r
3611 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1);\r
3612 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr);\r
3613 @endcode\r
367f5c9c 3614 @note MSR_SANDY_BRIDGE_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r
dc5d621c
MK		 3615**/\r
3616#define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37\r
3617\r
3618\r
3619/**\r
3620 Package. Uncore C-box 1 perfmon counter 2.\r
3621\r
3622 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR2 (0x00000D38)\r
3623 @param EAX Lower 32-bits of MSR value.\r
3624 @param EDX Upper 32-bits of MSR value.\r
3625\r
3626 <b>Example usage</b>\r
3627 @code\r
3628 UINT64 Msr;\r
3629\r
3630 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2);\r
3631 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr);\r
3632 @endcode\r
367f5c9c 3633 @note MSR_SANDY_BRIDGE_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r
dc5d621c
MK		 3634**/\r
3635#define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38\r
3636\r
3637\r
3638/**\r
3639 Package. Uncore C-box 1 perfmon counter 3.\r
3640\r
3641 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR3 (0x00000D39)\r
3642 @param EAX Lower 32-bits of MSR value.\r
3643 @param EDX Upper 32-bits of MSR value.\r
3644\r
3645 <b>Example usage</b>\r
3646 @code\r
3647 UINT64 Msr;\r
3648\r
3649 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3);\r
3650 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr);\r
3651 @endcode\r
367f5c9c 3652 @note MSR_SANDY_BRIDGE_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r
dc5d621c
MK		 3653**/\r
3654#define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39\r
3655\r
3656\r
3657/**\r
3658 Package. Uncore C-box 2 perfmon local box wide control.\r
3659\r
3660 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL (0x00000D44)\r
3661 @param EAX Lower 32-bits of MSR value.\r
3662 @param EDX Upper 32-bits of MSR value.\r
3663\r
3664 <b>Example usage</b>\r
3665 @code\r
3666 UINT64 Msr;\r
3667\r
3668 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL);\r
3669 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr);\r
3670 @endcode\r
367f5c9c 3671 @note MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.\r
dc5d621c
MK		 3672**/\r
3673#define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44\r
3674\r
3675\r
3676/**\r
3677 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.\r
3678\r
3679 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 (0x00000D50)\r
3680 @param EAX Lower 32-bits of MSR value.\r
3681 @param EDX Upper 32-bits of MSR value.\r
3682\r
3683 <b>Example usage</b>\r
3684 @code\r
3685 UINT64 Msr;\r
3686\r
3687 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0);\r
3688 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr);\r
3689 @endcode\r
367f5c9c 3690 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.\r
dc5d621c
MK		 3691**/\r
3692#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50\r
3693\r
3694\r
3695/**\r
3696 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.\r
3697\r
3698 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 (0x00000D51)\r
3699 @param EAX Lower 32-bits of MSR value.\r
3700 @param EDX Upper 32-bits of MSR value.\r
3701\r
3702 <b>Example usage</b>\r
3703 @code\r
3704 UINT64 Msr;\r
3705\r
3706 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1);\r
3707 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr);\r
3708 @endcode\r
367f5c9c 3709 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.\r
dc5d621c
MK		 3710**/\r
3711#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51\r
3712\r
3713\r
3714/**\r
3715 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.\r
3716\r
3717 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 (0x00000D52)\r
3718 @param EAX Lower 32-bits of MSR value.\r
3719 @param EDX Upper 32-bits of MSR value.\r
3720\r
3721 <b>Example usage</b>\r
3722 @code\r
3723 UINT64 Msr;\r
3724\r
3725 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2);\r
3726 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr);\r
3727 @endcode\r
367f5c9c 3728 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.\r
dc5d621c
MK		 3729**/\r
3730#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52\r
3731\r
3732\r
3733/**\r
3734 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.\r
3735\r
3736 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 (0x00000D53)\r
3737 @param EAX Lower 32-bits of MSR value.\r
3738 @param EDX Upper 32-bits of MSR value.\r
3739\r
3740 <b>Example usage</b>\r
3741 @code\r
3742 UINT64 Msr;\r
3743\r
3744 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3);\r
3745 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr);\r
3746 @endcode\r
367f5c9c 3747 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.\r
dc5d621c
MK		 3748**/\r
3749#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53\r
3750\r
3751\r
3752/**\r
3753 Package. Uncore C-box 2 perfmon box wide filter.\r
3754\r
3755 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER (0x00000D54)\r
3756 @param EAX Lower 32-bits of MSR value.\r
3757 @param EDX Upper 32-bits of MSR value.\r
3758\r
3759 <b>Example usage</b>\r
3760 @code\r
3761 UINT64 Msr;\r
3762\r
3763 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER);\r
3764 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr);\r
3765 @endcode\r
367f5c9c 3766 @note MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER is defined as MSR_C2_PMON_BOX_FILTER in SDM.\r
dc5d621c
MK		 3767**/\r
3768#define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54\r
3769\r
3770\r
3771/**\r
3772 Package. Uncore C-box 2 perfmon counter 0.\r
3773\r
3774 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR0 (0x00000D56)\r
3775 @param EAX Lower 32-bits of MSR value.\r
3776 @param EDX Upper 32-bits of MSR value.\r
3777\r
3778 <b>Example usage</b>\r
3779 @code\r
3780 UINT64 Msr;\r
3781\r
3782 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0);\r
3783 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr);\r
3784 @endcode\r
367f5c9c 3785 @note MSR_SANDY_BRIDGE_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r
dc5d621c
MK		 3786**/\r
3787#define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56\r
3788\r
3789\r
3790/**\r
3791 Package. Uncore C-box 2 perfmon counter 1.\r
3792\r
3793 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR1 (0x00000D57)\r
3794 @param EAX Lower 32-bits of MSR value.\r
3795 @param EDX Upper 32-bits of MSR value.\r
3796\r
3797 <b>Example usage</b>\r
3798 @code\r
3799 UINT64 Msr;\r
3800\r
3801 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1);\r
3802 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr);\r
3803 @endcode\r
367f5c9c 3804 @note MSR_SANDY_BRIDGE_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r
dc5d621c
MK		 3805**/\r
3806#define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57\r
3807\r
3808\r
3809/**\r
3810 Package. Uncore C-box 2 perfmon counter 2.\r
3811\r
3812 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR2 (0x00000D58)\r
3813 @param EAX Lower 32-bits of MSR value.\r
3814 @param EDX Upper 32-bits of MSR value.\r
3815\r
3816 <b>Example usage</b>\r
3817 @code\r
3818 UINT64 Msr;\r
3819\r
3820 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2);\r
3821 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr);\r
3822 @endcode\r
367f5c9c 3823 @note MSR_SANDY_BRIDGE_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r
dc5d621c
MK		 3824**/\r
3825#define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58\r
3826\r
3827\r
3828/**\r
3829 Package. Uncore C-box 2 perfmon counter 3.\r
3830\r
3831 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR3 (0x00000D59)\r
3832 @param EAX Lower 32-bits of MSR value.\r
3833 @param EDX Upper 32-bits of MSR value.\r
3834\r
3835 <b>Example usage</b>\r
3836 @code\r
3837 UINT64 Msr;\r
3838\r
3839 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3);\r
3840 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr);\r
3841 @endcode\r
367f5c9c 3842 @note MSR_SANDY_BRIDGE_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r
dc5d621c
MK		 3843**/\r
3844#define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59\r
3845\r
3846\r
3847/**\r
3848 Package. Uncore C-box 3 perfmon local box wide control.\r
3849\r
3850 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL (0x00000D64)\r
3851 @param EAX Lower 32-bits of MSR value.\r
3852 @param EDX Upper 32-bits of MSR value.\r
3853\r
3854 <b>Example usage</b>\r
3855 @code\r
3856 UINT64 Msr;\r
3857\r
3858 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL);\r
3859 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr);\r
3860 @endcode\r
367f5c9c 3861 @note MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.\r
dc5d621c
MK		 3862**/\r
3863#define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64\r
3864\r
3865\r
3866/**\r
3867 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.\r
3868\r
3869 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 (0x00000D70)\r
3870 @param EAX Lower 32-bits of MSR value.\r
3871 @param EDX Upper 32-bits of MSR value.\r
3872\r
3873 <b>Example usage</b>\r
3874 @code\r
3875 UINT64 Msr;\r
3876\r
3877 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0);\r
3878 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr);\r
3879 @endcode\r
367f5c9c 3880 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.\r
dc5d621c
MK		 3881**/\r
3882#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70\r
3883\r
3884\r
3885/**\r
3886 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.\r
3887\r
3888 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 (0x00000D71)\r
3889 @param EAX Lower 32-bits of MSR value.\r
3890 @param EDX Upper 32-bits of MSR value.\r
3891\r
3892 <b>Example usage</b>\r
3893 @code\r
3894 UINT64 Msr;\r
3895\r
3896 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1);\r
3897 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr);\r
3898 @endcode\r
367f5c9c 3899 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.\r
dc5d621c
MK		 3900**/\r
3901#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71\r
3902\r
3903\r
3904/**\r
3905 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.\r
3906\r
3907 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 (0x00000D72)\r
3908 @param EAX Lower 32-bits of MSR value.\r
3909 @param EDX Upper 32-bits of MSR value.\r
3910\r
3911 <b>Example usage</b>\r
3912 @code\r
3913 UINT64 Msr;\r
3914\r
3915 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2);\r
3916 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr);\r
3917 @endcode\r
367f5c9c 3918 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.\r
dc5d621c
MK		 3919**/\r
3920#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72\r
3921\r
3922\r
3923/**\r
3924 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.\r
3925\r
3926 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 (0x00000D73)\r
3927 @param EAX Lower 32-bits of MSR value.\r
3928 @param EDX Upper 32-bits of MSR value.\r
3929\r
3930 <b>Example usage</b>\r
3931 @code\r
3932 UINT64 Msr;\r
3933\r
3934 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3);\r
3935 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr);\r
3936 @endcode\r
367f5c9c 3937 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.\r
dc5d621c
MK		 3938**/\r
3939#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73\r
3940\r
3941\r
3942/**\r
3943 Package. Uncore C-box 3 perfmon box wide filter.\r
3944\r
3945 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER (0x00000D74)\r
3946 @param EAX Lower 32-bits of MSR value.\r
3947 @param EDX Upper 32-bits of MSR value.\r
3948\r
3949 <b>Example usage</b>\r
3950 @code\r
3951 UINT64 Msr;\r
3952\r
3953 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER);\r
3954 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr);\r
3955 @endcode\r
367f5c9c 3956 @note MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER is defined as MSR_C3_PMON_BOX_FILTER in SDM.\r
dc5d621c
MK		 3957**/\r
3958#define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74\r
3959\r
3960\r
3961/**\r
3962 Package. Uncore C-box 3 perfmon counter 0.\r
3963\r
3964 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR0 (0x00000D76)\r
3965 @param EAX Lower 32-bits of MSR value.\r
3966 @param EDX Upper 32-bits of MSR value.\r
3967\r
3968 <b>Example usage</b>\r
3969 @code\r
3970 UINT64 Msr;\r
3971\r
3972 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0);\r
3973 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr);\r
3974 @endcode\r
367f5c9c 3975 @note MSR_SANDY_BRIDGE_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r
dc5d621c
MK		 3976**/\r
3977#define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76\r
3978\r
3979\r
3980/**\r
3981 Package. Uncore C-box 3 perfmon counter 1.\r
3982\r
3983 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR1 (0x00000D77)\r
3984 @param EAX Lower 32-bits of MSR value.\r
3985 @param EDX Upper 32-bits of MSR value.\r
3986\r
3987 <b>Example usage</b>\r
3988 @code\r
3989 UINT64 Msr;\r
3990\r
3991 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1);\r
3992 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr);\r
3993 @endcode\r
367f5c9c 3994 @note MSR_SANDY_BRIDGE_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r
dc5d621c
MK		 3995**/\r
3996#define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77\r
3997\r
3998\r
3999/**\r
4000 Package. Uncore C-box 3 perfmon counter 2.\r
4001\r
4002 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR2 (0x00000D78)\r
4003 @param EAX Lower 32-bits of MSR value.\r
4004 @param EDX Upper 32-bits of MSR value.\r
4005\r
4006 <b>Example usage</b>\r
4007 @code\r
4008 UINT64 Msr;\r
4009\r
4010 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2);\r
4011 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr);\r
4012 @endcode\r
367f5c9c 4013 @note MSR_SANDY_BRIDGE_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r
dc5d621c
MK		 4014**/\r
4015#define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78\r
4016\r
4017\r
4018/**\r
4019 Package. Uncore C-box 3 perfmon counter 3.\r
4020\r
4021 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR3 (0x00000D79)\r
4022 @param EAX Lower 32-bits of MSR value.\r
4023 @param EDX Upper 32-bits of MSR value.\r
4024\r
4025 <b>Example usage</b>\r
4026 @code\r
4027 UINT64 Msr;\r
4028\r
4029 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3);\r
4030 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr);\r
4031 @endcode\r
367f5c9c 4032 @note MSR_SANDY_BRIDGE_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r
dc5d621c
MK		 4033**/\r
4034#define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79\r
4035\r
4036\r
4037/**\r
4038 Package. Uncore C-box 4 perfmon local box wide control.\r
4039\r
4040 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL (0x00000D84)\r
4041 @param EAX Lower 32-bits of MSR value.\r
4042 @param EDX Upper 32-bits of MSR value.\r
4043\r
4044 <b>Example usage</b>\r
4045 @code\r
4046 UINT64 Msr;\r
4047\r
4048 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL);\r
4049 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr);\r
4050 @endcode\r
367f5c9c 4051 @note MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.\r
dc5d621c
MK		 4052**/\r
4053#define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84\r
4054\r
4055\r
4056/**\r
4057 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.\r
4058\r
4059 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 (0x00000D90)\r
4060 @param EAX Lower 32-bits of MSR value.\r
4061 @param EDX Upper 32-bits of MSR value.\r
4062\r
4063 <b>Example usage</b>\r
4064 @code\r
4065 UINT64 Msr;\r
4066\r
4067 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0);\r
4068 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr);\r
4069 @endcode\r
367f5c9c 4070 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.\r
dc5d621c
MK		 4071**/\r
4072#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90\r
4073\r
4074\r
4075/**\r
4076 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.\r
4077\r
4078 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 (0x00000D91)\r
4079 @param EAX Lower 32-bits of MSR value.\r
4080 @param EDX Upper 32-bits of MSR value.\r
4081\r
4082 <b>Example usage</b>\r
4083 @code\r
4084 UINT64 Msr;\r
4085\r
4086 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1);\r
4087 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr);\r
4088 @endcode\r
367f5c9c 4089 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.\r
dc5d621c
MK		 4090**/\r
4091#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91\r
4092\r
4093\r
4094/**\r
4095 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.\r
4096\r
4097 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 (0x00000D92)\r
4098 @param EAX Lower 32-bits of MSR value.\r
4099 @param EDX Upper 32-bits of MSR value.\r
4100\r
4101 <b>Example usage</b>\r
4102 @code\r
4103 UINT64 Msr;\r
4104\r
4105 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2);\r
4106 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr);\r
4107 @endcode\r
367f5c9c 4108 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.\r
dc5d621c
MK		 4109**/\r
4110#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92\r
4111\r
4112\r
4113/**\r
4114 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.\r
4115\r
4116 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 (0x00000D93)\r
4117 @param EAX Lower 32-bits of MSR value.\r
4118 @param EDX Upper 32-bits of MSR value.\r
4119\r
4120 <b>Example usage</b>\r
4121 @code\r
4122 UINT64 Msr;\r
4123\r
4124 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3);\r
4125 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr);\r
4126 @endcode\r
367f5c9c 4127 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.\r
dc5d621c
MK		 4128**/\r
4129#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93\r
4130\r
4131\r
4132/**\r
4133 Package. Uncore C-box 4 perfmon box wide filter.\r
4134\r
4135 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER (0x00000D94)\r
4136 @param EAX Lower 32-bits of MSR value.\r
4137 @param EDX Upper 32-bits of MSR value.\r
4138\r
4139 <b>Example usage</b>\r
4140 @code\r
4141 UINT64 Msr;\r
4142\r
4143 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER);\r
4144 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr);\r
4145 @endcode\r
367f5c9c 4146 @note MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER is defined as MSR_C4_PMON_BOX_FILTER in SDM.\r
dc5d621c
MK		 4147**/\r
4148#define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94\r
4149\r
4150\r
4151/**\r
4152 Package. Uncore C-box 4 perfmon counter 0.\r
4153\r
4154 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR0 (0x00000D96)\r
4155 @param EAX Lower 32-bits of MSR value.\r
4156 @param EDX Upper 32-bits of MSR value.\r
4157\r
4158 <b>Example usage</b>\r
4159 @code\r
4160 UINT64 Msr;\r
4161\r
4162 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0);\r
4163 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr);\r
4164 @endcode\r
367f5c9c 4165 @note MSR_SANDY_BRIDGE_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r
dc5d621c
MK		 4166**/\r
4167#define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96\r
4168\r
4169\r
4170/**\r
4171 Package. Uncore C-box 4 perfmon counter 1.\r
4172\r
4173 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR1 (0x00000D97)\r
4174 @param EAX Lower 32-bits of MSR value.\r
4175 @param EDX Upper 32-bits of MSR value.\r
4176\r
4177 <b>Example usage</b>\r
4178 @code\r
4179 UINT64 Msr;\r
4180\r
4181 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1);\r
4182 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr);\r
4183 @endcode\r
367f5c9c 4184 @note MSR_SANDY_BRIDGE_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r
dc5d621c
MK		 4185**/\r
4186#define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97\r
4187\r
4188\r
4189/**\r
4190 Package. Uncore C-box 4 perfmon counter 2.\r
4191\r
4192 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR2 (0x00000D98)\r
4193 @param EAX Lower 32-bits of MSR value.\r
4194 @param EDX Upper 32-bits of MSR value.\r
4195\r
4196 <b>Example usage</b>\r
4197 @code\r
4198 UINT64 Msr;\r
4199\r
4200 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2);\r
4201 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr);\r
4202 @endcode\r
367f5c9c 4203 @note MSR_SANDY_BRIDGE_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r
dc5d621c
MK		 4204**/\r
4205#define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98\r
4206\r
4207\r
4208/**\r
4209 Package. Uncore C-box 4 perfmon counter 3.\r
4210\r
4211 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR3 (0x00000D99)\r
4212 @param EAX Lower 32-bits of MSR value.\r
4213 @param EDX Upper 32-bits of MSR value.\r
4214\r
4215 <b>Example usage</b>\r
4216 @code\r
4217 UINT64 Msr;\r
4218\r
4219 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3);\r
4220 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr);\r
4221 @endcode\r
367f5c9c 4222 @note MSR_SANDY_BRIDGE_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r
dc5d621c
MK		 4223**/\r
4224#define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99\r
4225\r
4226\r
4227/**\r
4228 Package. Uncore C-box 5 perfmon local box wide control.\r
4229\r
4230 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL (0x00000DA4)\r
4231 @param EAX Lower 32-bits of MSR value.\r
4232 @param EDX Upper 32-bits of MSR value.\r
4233\r
4234 <b>Example usage</b>\r
4235 @code\r
4236 UINT64 Msr;\r
4237\r
4238 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL);\r
4239 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr);\r
4240 @endcode\r
367f5c9c 4241 @note MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.\r
dc5d621c
MK		 4242**/\r
4243#define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4\r
4244\r
4245\r
4246/**\r
4247 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.\r
4248\r
4249 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 (0x00000DB0)\r
4250 @param EAX Lower 32-bits of MSR value.\r
4251 @param EDX Upper 32-bits of MSR value.\r
4252\r
4253 <b>Example usage</b>\r
4254 @code\r
4255 UINT64 Msr;\r
4256\r
4257 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0);\r
4258 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr);\r
4259 @endcode\r
367f5c9c 4260 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.\r
dc5d621c
MK		 4261**/\r
4262#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0\r
4263\r
4264\r
4265/**\r
4266 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.\r
4267\r
4268 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 (0x00000DB1)\r
4269 @param EAX Lower 32-bits of MSR value.\r
4270 @param EDX Upper 32-bits of MSR value.\r
4271\r
4272 <b>Example usage</b>\r
4273 @code\r
4274 UINT64 Msr;\r
4275\r
4276 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1);\r
4277 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr);\r
4278 @endcode\r
367f5c9c 4279 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.\r
dc5d621c
MK		 4280**/\r
4281#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1\r
4282\r
4283\r
4284/**\r
4285 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.\r
4286\r
4287 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 (0x00000DB2)\r
4288 @param EAX Lower 32-bits of MSR value.\r
4289 @param EDX Upper 32-bits of MSR value.\r
4290\r
4291 <b>Example usage</b>\r
4292 @code\r
4293 UINT64 Msr;\r
4294\r
4295 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2);\r
4296 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr);\r
4297 @endcode\r
367f5c9c 4298 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.\r
dc5d621c
MK		 4299**/\r
4300#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2\r
4301\r
4302\r
4303/**\r
4304 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.\r
4305\r
4306 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 (0x00000DB3)\r
4307 @param EAX Lower 32-bits of MSR value.\r
4308 @param EDX Upper 32-bits of MSR value.\r
4309\r
4310 <b>Example usage</b>\r
4311 @code\r
4312 UINT64 Msr;\r
4313\r
4314 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3);\r
4315 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr);\r
4316 @endcode\r
367f5c9c 4317 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.\r
dc5d621c
MK		 4318**/\r
4319#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3\r
4320\r
4321\r
4322/**\r
4323 Package. Uncore C-box 5 perfmon box wide filter.\r
4324\r
4325 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER (0x00000DB4)\r
4326 @param EAX Lower 32-bits of MSR value.\r
4327 @param EDX Upper 32-bits of MSR value.\r
4328\r
4329 <b>Example usage</b>\r
4330 @code\r
4331 UINT64 Msr;\r
4332\r
4333 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER);\r
4334 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr);\r
4335 @endcode\r
367f5c9c 4336 @note MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER is defined as MSR_C5_PMON_BOX_FILTER in SDM.\r
dc5d621c
MK		 4337**/\r
4338#define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4\r
4339\r
4340\r
4341/**\r
4342 Package. Uncore C-box 5 perfmon counter 0.\r
4343\r
4344 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR0 (0x00000DB6)\r
4345 @param EAX Lower 32-bits of MSR value.\r
4346 @param EDX Upper 32-bits of MSR value.\r
4347\r
4348 <b>Example usage</b>\r
4349 @code\r
4350 UINT64 Msr;\r
4351\r
4352 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0);\r
4353 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr);\r
4354 @endcode\r
367f5c9c 4355 @note MSR_SANDY_BRIDGE_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r
dc5d621c
MK		 4356**/\r
4357#define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6\r
4358\r
4359\r
4360/**\r
4361 Package. Uncore C-box 5 perfmon counter 1.\r
4362\r
4363 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR1 (0x00000DB7)\r
4364 @param EAX Lower 32-bits of MSR value.\r
4365 @param EDX Upper 32-bits of MSR value.\r
4366\r
4367 <b>Example usage</b>\r
4368 @code\r
4369 UINT64 Msr;\r
4370\r
4371 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1);\r
4372 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr);\r
4373 @endcode\r
367f5c9c 4374 @note MSR_SANDY_BRIDGE_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r
dc5d621c
MK		 4375**/\r
4376#define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7\r
4377\r
4378\r
4379/**\r
4380 Package. Uncore C-box 5 perfmon counter 2.\r
4381\r
4382 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR2 (0x00000DB8)\r
4383 @param EAX Lower 32-bits of MSR value.\r
4384 @param EDX Upper 32-bits of MSR value.\r
4385\r
4386 <b>Example usage</b>\r
4387 @code\r
4388 UINT64 Msr;\r
4389\r
4390 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2);\r
4391 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr);\r
4392 @endcode\r
367f5c9c 4393 @note MSR_SANDY_BRIDGE_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r
dc5d621c
MK		 4394**/\r
4395#define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8\r
4396\r
4397\r
4398/**\r
4399 Package. Uncore C-box 5 perfmon counter 3.\r
4400\r
4401 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR3 (0x00000DB9)\r
4402 @param EAX Lower 32-bits of MSR value.\r
4403 @param EDX Upper 32-bits of MSR value.\r
4404\r
4405 <b>Example usage</b>\r
4406 @code\r
4407 UINT64 Msr;\r
4408\r
4409 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3);\r
4410 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr);\r
4411 @endcode\r
367f5c9c 4412 @note MSR_SANDY_BRIDGE_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r
dc5d621c
MK		 4413**/\r
4414#define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9\r
4415\r
4416\r
4417/**\r
4418 Package. Uncore C-box 6 perfmon local box wide control.\r
4419\r
4420 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL (0x00000DC4)\r
4421 @param EAX Lower 32-bits of MSR value.\r
4422 @param EDX Upper 32-bits of MSR value.\r
4423\r
4424 <b>Example usage</b>\r
4425 @code\r
4426 UINT64 Msr;\r
4427\r
4428 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL);\r
4429 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr);\r
4430 @endcode\r
367f5c9c 4431 @note MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.\r
dc5d621c
MK		 4432**/\r
4433#define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4\r
4434\r
4435\r
4436/**\r
4437 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.\r
4438\r
4439 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 (0x00000DD0)\r
4440 @param EAX Lower 32-bits of MSR value.\r
4441 @param EDX Upper 32-bits of MSR value.\r
4442\r
4443 <b>Example usage</b>\r
4444 @code\r
4445 UINT64 Msr;\r
4446\r
4447 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0);\r
4448 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr);\r
4449 @endcode\r
367f5c9c 4450 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.\r
dc5d621c
MK		 4451**/\r
4452#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0\r
4453\r
4454\r
4455/**\r
4456 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.\r
4457\r
4458 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 (0x00000DD1)\r
4459 @param EAX Lower 32-bits of MSR value.\r
4460 @param EDX Upper 32-bits of MSR value.\r
4461\r
4462 <b>Example usage</b>\r
4463 @code\r
4464 UINT64 Msr;\r
4465\r
4466 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1);\r
4467 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr);\r
4468 @endcode\r
367f5c9c 4469 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.\r
dc5d621c
MK		 4470**/\r
4471#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1\r
4472\r
4473\r
4474/**\r
4475 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.\r
4476\r
4477 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 (0x00000DD2)\r
4478 @param EAX Lower 32-bits of MSR value.\r
4479 @param EDX Upper 32-bits of MSR value.\r
4480\r
4481 <b>Example usage</b>\r
4482 @code\r
4483 UINT64 Msr;\r
4484\r
4485 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2);\r
4486 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr);\r
4487 @endcode\r
367f5c9c 4488 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.\r
dc5d621c
MK		 4489**/\r
4490#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2\r
4491\r
4492\r
4493/**\r
4494 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.\r
4495\r
4496 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 (0x00000DD3)\r
4497 @param EAX Lower 32-bits of MSR value.\r
4498 @param EDX Upper 32-bits of MSR value.\r
4499\r
4500 <b>Example usage</b>\r
4501 @code\r
4502 UINT64 Msr;\r
4503\r
4504 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3);\r
4505 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr);\r
4506 @endcode\r
367f5c9c 4507 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.\r
dc5d621c
MK		 4508**/\r
4509#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3\r
4510\r
4511\r
4512/**\r
4513 Package. Uncore C-box 6 perfmon box wide filter.\r
4514\r
4515 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER (0x00000DD4)\r
4516 @param EAX Lower 32-bits of MSR value.\r
4517 @param EDX Upper 32-bits of MSR value.\r
4518\r
4519 <b>Example usage</b>\r
4520 @code\r
4521 UINT64 Msr;\r
4522\r
4523 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER);\r
4524 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr);\r
4525 @endcode\r
367f5c9c 4526 @note MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER is defined as MSR_C6_PMON_BOX_FILTER in SDM.\r
dc5d621c
MK		 4527**/\r
4528#define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4\r
4529\r
4530\r
4531/**\r
4532 Package. Uncore C-box 6 perfmon counter 0.\r
4533\r
4534 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR0 (0x00000DD6)\r
4535 @param EAX Lower 32-bits of MSR value.\r
4536 @param EDX Upper 32-bits of MSR value.\r
4537\r
4538 <b>Example usage</b>\r
4539 @code\r
4540 UINT64 Msr;\r
4541\r
4542 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0);\r
4543 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr);\r
4544 @endcode\r
367f5c9c 4545 @note MSR_SANDY_BRIDGE_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r
dc5d621c
MK		 4546**/\r
4547#define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6\r
4548\r
4549\r
4550/**\r
4551 Package. Uncore C-box 6 perfmon counter 1.\r
4552\r
4553 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR1 (0x00000DD7)\r
4554 @param EAX Lower 32-bits of MSR value.\r
4555 @param EDX Upper 32-bits of MSR value.\r
4556\r
4557 <b>Example usage</b>\r
4558 @code\r
4559 UINT64 Msr;\r
4560\r
4561 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1);\r
4562 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr);\r
4563 @endcode\r
367f5c9c 4564 @note MSR_SANDY_BRIDGE_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r
dc5d621c
MK		 4565**/\r
4566#define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7\r
4567\r
4568\r
4569/**\r
4570 Package. Uncore C-box 6 perfmon counter 2.\r
4571\r
4572 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR2 (0x00000DD8)\r
4573 @param EAX Lower 32-bits of MSR value.\r
4574 @param EDX Upper 32-bits of MSR value.\r
4575\r
4576 <b>Example usage</b>\r
4577 @code\r
4578 UINT64 Msr;\r
4579\r
4580 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2);\r
4581 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr);\r
4582 @endcode\r
367f5c9c 4583 @note MSR_SANDY_BRIDGE_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r
dc5d621c
MK		 4584**/\r
4585#define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8\r
4586\r
4587\r
4588/**\r
4589 Package. Uncore C-box 6 perfmon counter 3.\r
4590\r
4591 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR3 (0x00000DD9)\r
4592 @param EAX Lower 32-bits of MSR value.\r
4593 @param EDX Upper 32-bits of MSR value.\r
4594\r
4595 <b>Example usage</b>\r
4596 @code\r
4597 UINT64 Msr;\r
4598\r
4599 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3);\r
4600 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr);\r
4601 @endcode\r
367f5c9c 4602 @note MSR_SANDY_BRIDGE_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r
dc5d621c
MK		 4603**/\r
4604#define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9\r
4605\r
4606\r
4607/**\r
4608 Package. Uncore C-box 7 perfmon local box wide control.\r
4609\r
4610 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL (0x00000DE4)\r
4611 @param EAX Lower 32-bits of MSR value.\r
4612 @param EDX Upper 32-bits of MSR value.\r
4613\r
4614 <b>Example usage</b>\r
4615 @code\r
4616 UINT64 Msr;\r
4617\r
4618 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL);\r
4619 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr);\r
4620 @endcode\r
367f5c9c 4621 @note MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.\r
dc5d621c
MK		 4622**/\r
4623#define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4\r
4624\r
4625\r
4626/**\r
4627 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.\r
4628\r
4629 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 (0x00000DF0)\r
4630 @param EAX Lower 32-bits of MSR value.\r
4631 @param EDX Upper 32-bits of MSR value.\r
4632\r
4633 <b>Example usage</b>\r
4634 @code\r
4635 UINT64 Msr;\r
4636\r
4637 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0);\r
4638 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr);\r
4639 @endcode\r
367f5c9c 4640 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.\r
dc5d621c
MK		 4641**/\r
4642#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0\r
4643\r
4644\r
4645/**\r
4646 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.\r
4647\r
4648 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 (0x00000DF1)\r
4649 @param EAX Lower 32-bits of MSR value.\r
4650 @param EDX Upper 32-bits of MSR value.\r
4651\r
4652 <b>Example usage</b>\r
4653 @code\r
4654 UINT64 Msr;\r
4655\r
4656 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1);\r
4657 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr);\r
4658 @endcode\r
367f5c9c 4659 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.\r
dc5d621c
MK		 4660**/\r
4661#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1\r
4662\r
4663\r
4664/**\r
4665 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.\r
4666\r
4667 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 (0x00000DF2)\r
4668 @param EAX Lower 32-bits of MSR value.\r
4669 @param EDX Upper 32-bits of MSR value.\r
4670\r
4671 <b>Example usage</b>\r
4672 @code\r
4673 UINT64 Msr;\r
4674\r
4675 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2);\r
4676 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr);\r
4677 @endcode\r
367f5c9c 4678 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.\r
dc5d621c
MK		 4679**/\r
4680#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2\r
4681\r
4682\r
4683/**\r
4684 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.\r
4685\r
4686 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 (0x00000DF3)\r
4687 @param EAX Lower 32-bits of MSR value.\r
4688 @param EDX Upper 32-bits of MSR value.\r
4689\r
4690 <b>Example usage</b>\r
4691 @code\r
4692 UINT64 Msr;\r
4693\r
4694 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3);\r
4695 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr);\r
4696 @endcode\r
367f5c9c 4697 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.\r
dc5d621c
MK		 4698**/\r
4699#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3\r
4700\r
4701\r
4702/**\r
4703 Package. Uncore C-box 7 perfmon box wide filter.\r
4704\r
4705 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER (0x00000DF4)\r
4706 @param EAX Lower 32-bits of MSR value.\r
4707 @param EDX Upper 32-bits of MSR value.\r
4708\r
4709 <b>Example usage</b>\r
4710 @code\r
4711 UINT64 Msr;\r
4712\r
4713 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER);\r
4714 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr);\r
4715 @endcode\r
367f5c9c 4716 @note MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER is defined as MSR_C7_PMON_BOX_FILTER in SDM.\r
dc5d621c
MK		 4717**/\r
4718#define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4\r
4719\r
4720\r
4721/**\r
4722 Package. Uncore C-box 7 perfmon counter 0.\r
4723\r
4724 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR0 (0x00000DF6)\r
4725 @param EAX Lower 32-bits of MSR value.\r
4726 @param EDX Upper 32-bits of MSR value.\r
4727\r
4728 <b>Example usage</b>\r
4729 @code\r
4730 UINT64 Msr;\r
4731\r
4732 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0);\r
4733 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr);\r
4734 @endcode\r
367f5c9c 4735 @note MSR_SANDY_BRIDGE_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r
dc5d621c
MK		 4736**/\r
4737#define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6\r
4738\r
4739\r
4740/**\r
4741 Package. Uncore C-box 7 perfmon counter 1.\r
4742\r
4743 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR1 (0x00000DF7)\r
4744 @param EAX Lower 32-bits of MSR value.\r
4745 @param EDX Upper 32-bits of MSR value.\r
4746\r
4747 <b>Example usage</b>\r
4748 @code\r
4749 UINT64 Msr;\r
4750\r
4751 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1);\r
4752 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr);\r
4753 @endcode\r
367f5c9c 4754 @note MSR_SANDY_BRIDGE_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r
dc5d621c
MK		 4755**/\r
4756#define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7\r
4757\r
4758\r
4759/**\r
4760 Package. Uncore C-box 7 perfmon counter 2.\r
4761\r
4762 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR2 (0x00000DF8)\r
4763 @param EAX Lower 32-bits of MSR value.\r
4764 @param EDX Upper 32-bits of MSR value.\r
4765\r
4766 <b>Example usage</b>\r
4767 @code\r
4768 UINT64 Msr;\r
4769\r
4770 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2);\r
4771 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr);\r
4772 @endcode\r
367f5c9c 4773 @note MSR_SANDY_BRIDGE_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r
dc5d621c
MK		 4774**/\r
4775#define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8\r
4776\r
4777\r
4778/**\r
4779 Package. Uncore C-box 7 perfmon counter 3.\r
4780\r
4781 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR3 (0x00000DF9)\r
4782 @param EAX Lower 32-bits of MSR value.\r
4783 @param EDX Upper 32-bits of MSR value.\r
4784\r
4785 <b>Example usage</b>\r
4786 @code\r
4787 UINT64 Msr;\r
4788\r
4789 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3);\r
4790 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr);\r
4791 @endcode\r
367f5c9c 4792 @note MSR_SANDY_BRIDGE_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r
dc5d621c
MK		 4793**/\r
4794#define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9\r
4795\r
4796#endif\r
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