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1 | /** @file\r |
2 | MSR Definitions for Intel processors based on the Silvermont microarchitecture.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
f4c982bf | 9 | Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r |
053a6ae9 MK |
10 | This program and the accompanying materials\r |
11 | are licensed and made available under the terms and conditions of the BSD License\r | |
12 | which accompanies this distribution. The full text of the license may be found at\r | |
13 | http://opensource.org/licenses/bsd-license.php\r | |
14 | \r | |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | \r | |
18 | @par Specification Reference:\r | |
19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
0f16be6d | 20 | September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.4.\r |
053a6ae9 MK |
21 | \r |
22 | **/\r | |
23 | \r | |
24 | #ifndef __SILVERMONT_MSR_H__\r | |
25 | #define __SILVERMONT_MSR_H__\r | |
26 | \r | |
27 | #include <Register/ArchitecturalMsr.h>\r | |
28 | \r | |
f4c982bf JF |
29 | /**\r |
30 | Is Intel processors based on the Silvermont microarchitecture?\r | |
31 | \r | |
32 | @param DisplayFamily Display Family ID\r | |
33 | @param DisplayModel Display Model ID\r | |
34 | \r | |
35 | @retval TRUE Yes, it is.\r | |
36 | @retval FALSE No, it isn't.\r | |
37 | **/\r | |
38 | #define IS_SILVERMONT_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
39 | (DisplayFamily == 0x06 && \\r | |
40 | ( \\r | |
41 | DisplayModel == 0x37 || \\r | |
42 | DisplayModel == 0x4A || \\r | |
43 | DisplayModel == 0x4D || \\r | |
44 | DisplayModel == 0x5A || \\r | |
45 | DisplayModel == 0x5D \\r | |
46 | ) \\r | |
47 | )\r | |
48 | \r | |
053a6ae9 | 49 | /**\r |
0f16be6d | 50 | Module. Model Specific Platform ID (R).\r |
053a6ae9 MK |
51 | \r |
52 | @param ECX MSR_SILVERMONT_PLATFORM_ID (0x00000017)\r | |
53 | @param EAX Lower 32-bits of MSR value.\r | |
54 | Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.\r | |
55 | @param EDX Upper 32-bits of MSR value.\r | |
56 | Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.\r | |
57 | \r | |
58 | <b>Example usage</b>\r | |
59 | @code\r | |
60 | MSR_SILVERMONT_PLATFORM_ID_REGISTER Msr;\r | |
61 | \r | |
62 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);\r | |
63 | @endcode\r | |
94fe1b5f | 64 | @note MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r |
053a6ae9 MK |
65 | **/\r |
66 | #define MSR_SILVERMONT_PLATFORM_ID 0x00000017\r | |
67 | \r | |
68 | /**\r | |
69 | MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID\r | |
70 | **/\r | |
71 | typedef union {\r | |
72 | ///\r | |
73 | /// Individual bit fields\r | |
74 | ///\r | |
75 | struct {\r | |
76 | UINT32 Reserved1:8;\r | |
77 | ///\r | |
78 | /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r | |
79 | ///\r | |
80 | UINT32 MaximumQualifiedRatio:5;\r | |
81 | UINT32 Reserved2:19;\r | |
82 | UINT32 Reserved3:18;\r | |
83 | ///\r | |
84 | /// [Bits 52:50] See Table 35-2.\r | |
85 | ///\r | |
86 | UINT32 PlatformId:3;\r | |
87 | UINT32 Reserved4:11;\r | |
88 | } Bits;\r | |
89 | ///\r | |
90 | /// All bit fields as a 64-bit value\r | |
91 | ///\r | |
92 | UINT64 Uint64;\r | |
93 | } MSR_SILVERMONT_PLATFORM_ID_REGISTER;\r | |
94 | \r | |
95 | \r | |
96 | /**\r | |
0f16be6d | 97 | Module. Processor Hard Power-On Configuration (R/W) Writes ignored.\r |
053a6ae9 MK |
98 | \r |
99 | @param ECX MSR_SILVERMONT_EBL_CR_POWERON (0x0000002A)\r | |
100 | @param EAX Lower 32-bits of MSR value.\r | |
101 | Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.\r | |
102 | @param EDX Upper 32-bits of MSR value.\r | |
103 | Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.\r | |
104 | \r | |
105 | <b>Example usage</b>\r | |
106 | @code\r | |
107 | MSR_SILVERMONT_EBL_CR_POWERON_REGISTER Msr;\r | |
108 | \r | |
109 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);\r | |
110 | AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);\r | |
111 | @endcode\r | |
94fe1b5f | 112 | @note MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r |
053a6ae9 MK |
113 | **/\r |
114 | #define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A\r | |
115 | \r | |
116 | /**\r | |
117 | MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON\r | |
118 | **/\r | |
119 | typedef union {\r | |
120 | ///\r | |
121 | /// Individual bit fields\r | |
122 | ///\r | |
123 | struct {\r | |
0f16be6d HW |
124 | UINT32 Reserved1:32;\r |
125 | UINT32 Reserved2:32;\r | |
053a6ae9 MK |
126 | } Bits;\r |
127 | ///\r | |
128 | /// All bit fields as a 32-bit value\r | |
129 | ///\r | |
130 | UINT32 Uint32;\r | |
131 | ///\r | |
132 | /// All bit fields as a 64-bit value\r | |
133 | ///\r | |
134 | UINT64 Uint64;\r | |
135 | } MSR_SILVERMONT_EBL_CR_POWERON_REGISTER;\r | |
136 | \r | |
137 | \r | |
138 | /**\r | |
139 | Core. SMI Counter (R/O).\r | |
140 | \r | |
141 | @param ECX MSR_SILVERMONT_SMI_COUNT (0x00000034)\r | |
142 | @param EAX Lower 32-bits of MSR value.\r | |
143 | Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.\r | |
144 | @param EDX Upper 32-bits of MSR value.\r | |
145 | Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.\r | |
146 | \r | |
147 | <b>Example usage</b>\r | |
148 | @code\r | |
149 | MSR_SILVERMONT_SMI_COUNT_REGISTER Msr;\r | |
150 | \r | |
151 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT);\r | |
152 | @endcode\r | |
94fe1b5f | 153 | @note MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r |
053a6ae9 MK |
154 | **/\r |
155 | #define MSR_SILVERMONT_SMI_COUNT 0x00000034\r | |
156 | \r | |
157 | /**\r | |
158 | MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT\r | |
159 | **/\r | |
160 | typedef union {\r | |
161 | ///\r | |
162 | /// Individual bit fields\r | |
163 | ///\r | |
164 | struct {\r | |
165 | ///\r | |
166 | /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last\r | |
167 | /// RESET.\r | |
168 | ///\r | |
169 | UINT32 SMICount:32;\r | |
170 | UINT32 Reserved:32;\r | |
171 | } Bits;\r | |
172 | ///\r | |
173 | /// All bit fields as a 32-bit value\r | |
174 | ///\r | |
175 | UINT32 Uint32;\r | |
176 | ///\r | |
177 | /// All bit fields as a 64-bit value\r | |
178 | ///\r | |
179 | UINT64 Uint64;\r | |
180 | } MSR_SILVERMONT_SMI_COUNT_REGISTER;\r | |
181 | \r | |
182 | \r | |
0f16be6d HW |
183 | /**\r |
184 | Core. Control Features in Intel 64 Processor (R/W). See Table 35-2.\r | |
185 | \r | |
186 | @param ECX MSR_IA32_SILVERMONT_FEATURE_CONTROL (0x0000003A)\r | |
187 | @param EAX Lower 32-bits of MSR value.\r | |
188 | Described by the type\r | |
189 | MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.\r | |
190 | @param EDX Upper 32-bits of MSR value.\r | |
191 | Described by the type\r | |
192 | MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.\r | |
193 | \r | |
194 | <b>Example usage</b>\r | |
195 | @code\r | |
196 | MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER Msr;\r | |
197 | \r | |
198 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL);\r | |
199 | AsmWriteMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL, Msr.Uint64);\r | |
200 | @endcode\r | |
201 | @note MSR_SILVERMONT_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r | |
202 | **/\r | |
203 | #define MSR_SILVERMONT_IA32_FEATURE_CONTROL 0x0000003A\r | |
204 | \r | |
205 | /**\r | |
206 | MSR information returned for MSR index #MSR_SILVERMONT_IA32_FEATURE_CONTROL\r | |
207 | **/\r | |
208 | typedef union {\r | |
209 | ///\r | |
210 | /// Individual bit fields\r | |
211 | ///\r | |
212 | struct {\r | |
213 | ///\r | |
214 | /// [Bit 0] Lock (R/WL).\r | |
215 | ///\r | |
216 | UINT32 Lock:1;\r | |
217 | UINT32 Reserved1:1;\r | |
218 | ///\r | |
219 | /// [Bit 2] Enable VMX outside SMX operation (R/WL).\r | |
220 | ///\r | |
221 | UINT32 EnableVmxOutsideSmx:1;\r | |
222 | UINT32 Reserved2:29;\r | |
223 | UINT32 Reserved3:32;\r | |
224 | } Bits;\r | |
225 | ///\r | |
226 | /// All bit fields as a 32-bit value\r | |
227 | ///\r | |
228 | UINT32 Uint32;\r | |
229 | ///\r | |
230 | /// All bit fields as a 64-bit value\r | |
231 | ///\r | |
232 | UINT64 Uint64;\r | |
233 | } MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER;\r | |
234 | \r | |
235 | \r | |
053a6ae9 MK |
236 | /**\r |
237 | Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch\r | |
0f16be6d HW |
238 | record registers on the last branch record stack. The From_IP part of the\r |
239 | stack contains pointers to the source instruction. See also: - Last Branch\r | |
240 | Record Stack TOS at 1C9H - Section 17.5 and record format in Section\r | |
241 | 17.4.8.1.\r | |
053a6ae9 MK |
242 | \r |
243 | @param ECX MSR_SILVERMONT_LASTBRANCH_n_FROM_IP\r | |
244 | @param EAX Lower 32-bits of MSR value.\r | |
245 | @param EDX Upper 32-bits of MSR value.\r | |
246 | \r | |
247 | <b>Example usage</b>\r | |
248 | @code\r | |
249 | UINT64 Msr;\r | |
250 | \r | |
251 | Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);\r | |
252 | AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);\r | |
253 | @endcode\r | |
94fe1b5f JF |
254 | @note MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r |
255 | MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r | |
256 | MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r | |
257 | MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r | |
258 | MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r | |
259 | MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r | |
260 | MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r | |
261 | MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r | |
053a6ae9 MK |
262 | @{\r |
263 | **/\r | |
264 | #define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040\r | |
265 | #define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041\r | |
266 | #define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042\r | |
267 | #define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043\r | |
268 | #define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044\r | |
269 | #define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045\r | |
270 | #define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046\r | |
271 | #define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047\r | |
272 | /// @}\r | |
273 | \r | |
274 | \r | |
275 | /**\r | |
276 | Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch\r | |
0f16be6d HW |
277 | record registers on the last branch record stack. The To_IP part of the\r |
278 | stack contains pointers to the destination instruction.\r | |
053a6ae9 MK |
279 | \r |
280 | @param ECX MSR_SILVERMONT_LASTBRANCH_n_TO_IP\r | |
281 | @param EAX Lower 32-bits of MSR value.\r | |
282 | @param EDX Upper 32-bits of MSR value.\r | |
283 | \r | |
284 | <b>Example usage</b>\r | |
285 | @code\r | |
286 | UINT64 Msr;\r | |
287 | \r | |
288 | Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);\r | |
289 | AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);\r | |
290 | @endcode\r | |
94fe1b5f JF |
291 | @note MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r |
292 | MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r | |
293 | MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r | |
294 | MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r | |
295 | MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r | |
296 | MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r | |
297 | MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r | |
298 | MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r | |
053a6ae9 MK |
299 | @{\r |
300 | **/\r | |
301 | #define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060\r | |
302 | #define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061\r | |
303 | #define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062\r | |
304 | #define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063\r | |
305 | #define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064\r | |
306 | #define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065\r | |
307 | #define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066\r | |
308 | #define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067\r | |
309 | /// @}\r | |
310 | \r | |
311 | \r | |
312 | /**\r | |
0f16be6d | 313 | Module. Scalable Bus Speed(RO) This field indicates the intended scalable\r |
053a6ae9 MK |
314 | bus clock speed for processors based on Silvermont microarchitecture:.\r |
315 | \r | |
316 | @param ECX MSR_SILVERMONT_FSB_FREQ (0x000000CD)\r | |
317 | @param EAX Lower 32-bits of MSR value.\r | |
318 | Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.\r | |
319 | @param EDX Upper 32-bits of MSR value.\r | |
320 | Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.\r | |
321 | \r | |
322 | <b>Example usage</b>\r | |
323 | @code\r | |
324 | MSR_SILVERMONT_FSB_FREQ_REGISTER Msr;\r | |
325 | \r | |
326 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);\r | |
327 | @endcode\r | |
94fe1b5f | 328 | @note MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r |
053a6ae9 MK |
329 | **/\r |
330 | #define MSR_SILVERMONT_FSB_FREQ 0x000000CD\r | |
331 | \r | |
332 | /**\r | |
333 | MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ\r | |
334 | **/\r | |
335 | typedef union {\r | |
336 | ///\r | |
337 | /// Individual bit fields\r | |
338 | ///\r | |
339 | struct {\r | |
340 | ///\r | |
341 | /// [Bits 3:0] Scalable Bus Speed\r | |
342 | ///\r | |
343 | /// Silvermont Processor Family\r | |
344 | /// ---------------------------\r | |
345 | /// 100B: 080.0 MHz\r | |
346 | /// 000B: 083.3 MHz\r | |
347 | /// 001B: 100.0 MHz\r | |
348 | /// 010B: 133.3 MHz\r | |
349 | /// 011B: 116.7 MHz\r | |
350 | ///\r | |
351 | /// Airmont Processor Family\r | |
352 | /// ---------------------------\r | |
353 | /// 0000B: 083.3 MHz\r | |
354 | /// 0001B: 100.0 MHz\r | |
355 | /// 0010B: 133.3 MHz\r | |
356 | /// 0011B: 116.7 MHz\r | |
357 | /// 0100B: 080.0 MHz\r | |
358 | /// 0101B: 093.3 MHz\r | |
359 | /// 0110B: 090.0 MHz\r | |
360 | /// 0111B: 088.9 MHz\r | |
361 | /// 1000B: 087.5 MHz\r | |
362 | ///\r | |
363 | UINT32 ScalableBusSpeed:4;\r | |
364 | UINT32 Reserved1:28;\r | |
365 | UINT32 Reserved2:32;\r | |
366 | } Bits;\r | |
367 | ///\r | |
368 | /// All bit fields as a 32-bit value\r | |
369 | ///\r | |
370 | UINT32 Uint32;\r | |
371 | ///\r | |
372 | /// All bit fields as a 64-bit value\r | |
373 | ///\r | |
374 | UINT64 Uint64;\r | |
375 | } MSR_SILVERMONT_FSB_FREQ_REGISTER;\r | |
376 | \r | |
377 | \r | |
378 | /**\r | |
0f16be6d | 379 | Module. C-State Configuration Control (R/W) Note: C-state values are\r |
053a6ae9 MK |
380 | processor specific C-state code names, unrelated to MWAIT extension C-state\r |
381 | parameters or ACPI CStates. See http://biosbits.org.\r | |
382 | \r | |
383 | @param ECX MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
384 | @param EAX Lower 32-bits of MSR value.\r | |
385 | Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
386 | @param EDX Upper 32-bits of MSR value.\r | |
387 | Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
388 | \r | |
389 | <b>Example usage</b>\r | |
390 | @code\r | |
391 | MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
392 | \r | |
393 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL);\r | |
394 | AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
395 | @endcode\r | |
94fe1b5f | 396 | @note MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r |
053a6ae9 MK |
397 | **/\r |
398 | #define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r | |
399 | \r | |
400 | /**\r | |
401 | MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL\r | |
402 | **/\r | |
403 | typedef union {\r | |
404 | ///\r | |
405 | /// Individual bit fields\r | |
406 | ///\r | |
407 | struct {\r | |
408 | ///\r | |
409 | /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r | |
410 | /// processor-specific C-state code name (consuming the least power). for\r | |
411 | /// the package. The default is set as factory-configured package C-state\r | |
412 | /// limit. The following C-state code name encodings are supported: 000b:\r | |
413 | /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)\r | |
414 | /// 100b: C4 110b: C6 111b: C7 (Silvermont only).\r | |
415 | ///\r | |
416 | UINT32 Limit:3;\r | |
417 | UINT32 Reserved1:7;\r | |
418 | ///\r | |
419 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r | |
420 | /// IO_read instructions sent to IO register specified by\r | |
421 | /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r | |
422 | ///\r | |
423 | UINT32 IO_MWAIT:1;\r | |
424 | UINT32 Reserved2:4;\r | |
425 | ///\r | |
426 | /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r | |
427 | /// until next reset.\r | |
428 | ///\r | |
429 | UINT32 CFGLock:1;\r | |
430 | UINT32 Reserved3:16;\r | |
431 | UINT32 Reserved4:32;\r | |
432 | } Bits;\r | |
433 | ///\r | |
434 | /// All bit fields as a 32-bit value\r | |
435 | ///\r | |
436 | UINT32 Uint32;\r | |
437 | ///\r | |
438 | /// All bit fields as a 64-bit value\r | |
439 | ///\r | |
440 | UINT64 Uint64;\r | |
441 | } MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER;\r | |
442 | \r | |
443 | \r | |
444 | /**\r | |
0f16be6d | 445 | Module. Power Management IO Redirection in C-state (R/W) See\r |
053a6ae9 MK |
446 | http://biosbits.org.\r |
447 | \r | |
448 | @param ECX MSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4)\r | |
449 | @param EAX Lower 32-bits of MSR value.\r | |
450 | Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.\r | |
451 | @param EDX Upper 32-bits of MSR value.\r | |
452 | Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.\r | |
453 | \r | |
454 | <b>Example usage</b>\r | |
455 | @code\r | |
456 | MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r | |
457 | \r | |
458 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE);\r | |
459 | AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r | |
460 | @endcode\r | |
94fe1b5f | 461 | @note MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r |
053a6ae9 MK |
462 | **/\r |
463 | #define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4\r | |
464 | \r | |
465 | /**\r | |
466 | MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE\r | |
467 | **/\r | |
468 | typedef union {\r | |
469 | ///\r | |
470 | /// Individual bit fields\r | |
471 | ///\r | |
472 | struct {\r | |
473 | ///\r | |
474 | /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address\r | |
475 | /// visible to software for IO redirection. If IO MWAIT Redirection is\r | |
476 | /// enabled, reads to this address will be consumed by the power\r | |
477 | /// management logic and decoded to MWAIT instructions. When IO port\r | |
478 | /// address redirection is enabled, this is the IO port address reported\r | |
479 | /// to the OS/software.\r | |
480 | ///\r | |
481 | UINT32 Lvl2Base:16;\r | |
482 | ///\r | |
483 | /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r | |
484 | /// maximum C-State code name to be included when IO read to MWAIT\r | |
485 | /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4\r | |
486 | /// is the max C-State to include 110b - C6 is the max C-State to include\r | |
487 | /// 111b - C7 is the max C-State to include.\r | |
488 | ///\r | |
489 | UINT32 CStateRange:3;\r | |
490 | UINT32 Reserved1:13;\r | |
491 | UINT32 Reserved2:32;\r | |
492 | } Bits;\r | |
493 | ///\r | |
494 | /// All bit fields as a 32-bit value\r | |
495 | ///\r | |
496 | UINT32 Uint32;\r | |
497 | ///\r | |
498 | /// All bit fields as a 64-bit value\r | |
499 | ///\r | |
500 | UINT64 Uint64;\r | |
501 | } MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER;\r | |
502 | \r | |
503 | \r | |
504 | /**\r | |
0f16be6d | 505 | Module.\r |
053a6ae9 MK |
506 | \r |
507 | @param ECX MSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E)\r | |
508 | @param EAX Lower 32-bits of MSR value.\r | |
509 | Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.\r | |
510 | @param EDX Upper 32-bits of MSR value.\r | |
511 | Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.\r | |
512 | \r | |
513 | <b>Example usage</b>\r | |
514 | @code\r | |
515 | MSR_SILVERMONT_BBL_CR_CTL3_REGISTER Msr;\r | |
516 | \r | |
517 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3);\r | |
518 | AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64);\r | |
519 | @endcode\r | |
94fe1b5f | 520 | @note MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r |
053a6ae9 MK |
521 | **/\r |
522 | #define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E\r | |
523 | \r | |
524 | /**\r | |
525 | MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3\r | |
526 | **/\r | |
527 | typedef union {\r | |
528 | ///\r | |
529 | /// Individual bit fields\r | |
530 | ///\r | |
531 | struct {\r | |
532 | ///\r | |
533 | /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r | |
534 | /// Indicates if the L2 is hardware-disabled.\r | |
535 | ///\r | |
536 | UINT32 L2HardwareEnabled:1;\r | |
537 | UINT32 Reserved1:7;\r | |
538 | ///\r | |
539 | /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =\r | |
540 | /// Disabled (default) Until this bit is set the processor will not\r | |
541 | /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r | |
542 | ///\r | |
543 | UINT32 L2Enabled:1;\r | |
544 | UINT32 Reserved2:14;\r | |
545 | ///\r | |
546 | /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r | |
547 | ///\r | |
548 | UINT32 L2NotPresent:1;\r | |
549 | UINT32 Reserved3:8;\r | |
550 | UINT32 Reserved4:32;\r | |
551 | } Bits;\r | |
552 | ///\r | |
553 | /// All bit fields as a 32-bit value\r | |
554 | ///\r | |
555 | UINT32 Uint32;\r | |
556 | ///\r | |
557 | /// All bit fields as a 64-bit value\r | |
558 | ///\r | |
559 | UINT64 Uint64;\r | |
560 | } MSR_SILVERMONT_BBL_CR_CTL3_REGISTER;\r | |
561 | \r | |
562 | \r | |
563 | /**\r | |
564 | Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r | |
565 | handler to handle unsuccessful read of this MSR.\r | |
566 | \r | |
567 | @param ECX MSR_SILVERMONT_FEATURE_CONFIG (0x0000013C)\r | |
568 | @param EAX Lower 32-bits of MSR value.\r | |
569 | Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.\r | |
570 | @param EDX Upper 32-bits of MSR value.\r | |
571 | Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.\r | |
572 | \r | |
573 | <b>Example usage</b>\r | |
574 | @code\r | |
575 | MSR_SILVERMONT_FEATURE_CONFIG_REGISTER Msr;\r | |
576 | \r | |
577 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG);\r | |
578 | AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64);\r | |
579 | @endcode\r | |
94fe1b5f | 580 | @note MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r |
053a6ae9 MK |
581 | **/\r |
582 | #define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C\r | |
583 | \r | |
584 | /**\r | |
585 | MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG\r | |
586 | **/\r | |
587 | typedef union {\r | |
588 | ///\r | |
589 | /// Individual bit fields\r | |
590 | ///\r | |
591 | struct {\r | |
592 | ///\r | |
593 | /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r | |
594 | /// MSR, the configuration of AES instruction set availability is as\r | |
595 | /// follows: 11b: AES instructions are not available until next RESET.\r | |
596 | /// otherwise, AES instructions are available. Note, AES instruction set\r | |
597 | /// is not available if read is unsuccessful. If the configuration is not\r | |
598 | /// 01b, AES instruction can be mis-configured if a privileged agent\r | |
599 | /// unintentionally writes 11b.\r | |
600 | ///\r | |
601 | UINT32 AESConfiguration:2;\r | |
602 | UINT32 Reserved1:30;\r | |
603 | UINT32 Reserved2:32;\r | |
604 | } Bits;\r | |
605 | ///\r | |
606 | /// All bit fields as a 32-bit value\r | |
607 | ///\r | |
608 | UINT32 Uint32;\r | |
609 | ///\r | |
610 | /// All bit fields as a 64-bit value\r | |
611 | ///\r | |
612 | UINT64 Uint64;\r | |
613 | } MSR_SILVERMONT_FEATURE_CONFIG_REGISTER;\r | |
614 | \r | |
615 | \r | |
616 | /**\r | |
617 | Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
618 | functions to be enabled and disabled.\r | |
619 | \r | |
620 | @param ECX MSR_SILVERMONT_IA32_MISC_ENABLE (0x000001A0)\r | |
621 | @param EAX Lower 32-bits of MSR value.\r | |
622 | Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.\r | |
623 | @param EDX Upper 32-bits of MSR value.\r | |
624 | Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.\r | |
625 | \r | |
626 | <b>Example usage</b>\r | |
627 | @code\r | |
628 | MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER Msr;\r | |
629 | \r | |
630 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE);\r | |
631 | AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64);\r | |
632 | @endcode\r | |
94fe1b5f | 633 | @note MSR_SILVERMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r |
053a6ae9 MK |
634 | **/\r |
635 | #define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0\r | |
636 | \r | |
637 | /**\r | |
638 | MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE\r | |
639 | **/\r | |
640 | typedef union {\r | |
641 | ///\r | |
642 | /// Individual bit fields\r | |
643 | ///\r | |
644 | struct {\r | |
645 | ///\r | |
646 | /// [Bit 0] Core. Fast-Strings Enable See Table 35-2.\r | |
647 | ///\r | |
648 | UINT32 FastStrings:1;\r | |
649 | UINT32 Reserved1:2;\r | |
650 | ///\r | |
0f16be6d HW |
651 | /// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See\r |
652 | /// Table 35-2. Default value is 0.\r | |
053a6ae9 MK |
653 | ///\r |
654 | UINT32 AutomaticThermalControlCircuit:1;\r | |
655 | UINT32 Reserved2:3;\r | |
656 | ///\r | |
657 | /// [Bit 7] Core. Performance Monitoring Available (R) See Table 35-2.\r | |
658 | ///\r | |
659 | UINT32 PerformanceMonitoring:1;\r | |
660 | UINT32 Reserved3:3;\r | |
661 | ///\r | |
662 | /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 35-2.\r | |
663 | ///\r | |
664 | UINT32 BTS:1;\r | |
665 | ///\r | |
0f16be6d HW |
666 | /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See\r |
667 | /// Table 35-2.\r | |
053a6ae9 MK |
668 | ///\r |
669 | UINT32 PEBS:1;\r | |
670 | UINT32 Reserved4:3;\r | |
671 | ///\r | |
0f16be6d | 672 | /// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See\r |
053a6ae9 MK |
673 | /// Table 35-2.\r |
674 | ///\r | |
675 | UINT32 EIST:1;\r | |
676 | UINT32 Reserved5:1;\r | |
677 | ///\r | |
678 | /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 35-2.\r | |
679 | ///\r | |
680 | UINT32 MONITOR:1;\r | |
681 | UINT32 Reserved6:3;\r | |
682 | ///\r | |
683 | /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 35-2.\r | |
684 | ///\r | |
685 | UINT32 LimitCpuidMaxval:1;\r | |
686 | ///\r | |
0f16be6d | 687 | /// [Bit 23] Module. xTPR Message Disable (R/W) See Table 35-2.\r |
053a6ae9 MK |
688 | ///\r |
689 | UINT32 xTPR_Message_Disable:1;\r | |
690 | UINT32 Reserved7:8;\r | |
691 | UINT32 Reserved8:2;\r | |
692 | ///\r | |
693 | /// [Bit 34] Core. XD Bit Disable (R/W) See Table 35-2.\r | |
694 | ///\r | |
695 | UINT32 XD:1;\r | |
696 | UINT32 Reserved9:3;\r | |
697 | ///\r | |
0f16be6d | 698 | /// [Bit 38] Module. Turbo Mode Disable (R/W) When set to 1 on processors\r |
053a6ae9 MK |
699 | /// that support Intel Turbo Boost Technology, the turbo mode feature is\r |
700 | /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r | |
701 | /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r | |
702 | /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r | |
703 | /// the power-on default value is used by BIOS to detect hardware support\r | |
704 | /// of turbo mode. If power-on default value is 1, turbo mode is available\r | |
705 | /// in the processor. If power-on default value is 0, turbo mode is not\r | |
706 | /// available.\r | |
707 | ///\r | |
708 | UINT32 TurboModeDisable:1;\r | |
709 | UINT32 Reserved10:25;\r | |
710 | } Bits;\r | |
711 | ///\r | |
712 | /// All bit fields as a 64-bit value\r | |
713 | ///\r | |
714 | UINT64 Uint64;\r | |
715 | } MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER;\r | |
716 | \r | |
717 | \r | |
718 | /**\r | |
719 | Package.\r | |
720 | \r | |
721 | @param ECX MSR_SILVERMONT_TEMPERATURE_TARGET (0x000001A2)\r | |
722 | @param EAX Lower 32-bits of MSR value.\r | |
723 | Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.\r | |
724 | @param EDX Upper 32-bits of MSR value.\r | |
725 | Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.\r | |
726 | \r | |
727 | <b>Example usage</b>\r | |
728 | @code\r | |
729 | MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER Msr;\r | |
730 | \r | |
731 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET);\r | |
732 | AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64);\r | |
733 | @endcode\r | |
94fe1b5f | 734 | @note MSR_SILVERMONT_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r |
053a6ae9 MK |
735 | **/\r |
736 | #define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2\r | |
737 | \r | |
738 | /**\r | |
739 | MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET\r | |
740 | **/\r | |
741 | typedef union {\r | |
742 | ///\r | |
743 | /// Individual bit fields\r | |
744 | ///\r | |
745 | struct {\r | |
746 | UINT32 Reserved1:16;\r | |
747 | ///\r | |
748 | /// [Bits 23:16] Temperature Target (R) The default thermal throttling or\r | |
749 | /// PROCHOT# activation temperature in degree C, The effective temperature\r | |
750 | /// for thermal throttling or PROCHOT# activation is "Temperature Target"\r | |
751 | /// + "Target Offset".\r | |
752 | ///\r | |
753 | UINT32 TemperatureTarget:8;\r | |
754 | ///\r | |
755 | /// [Bits 29:24] Target Offset (R/W) Specifies an offset in degrees C to\r | |
756 | /// adjust the throttling and PROCHOT# activation temperature from the\r | |
757 | /// default target specified in TEMPERATURE_TARGET (bits 23:16).\r | |
758 | ///\r | |
759 | UINT32 TargetOffset:6;\r | |
760 | UINT32 Reserved2:2;\r | |
761 | UINT32 Reserved3:32;\r | |
762 | } Bits;\r | |
763 | ///\r | |
764 | /// All bit fields as a 32-bit value\r | |
765 | ///\r | |
766 | UINT32 Uint32;\r | |
767 | ///\r | |
768 | /// All bit fields as a 64-bit value\r | |
769 | ///\r | |
770 | UINT64 Uint64;\r | |
771 | } MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER;\r | |
772 | \r | |
773 | \r | |
774 | /**\r | |
0f16be6d HW |
775 | Miscellaneous Feature Control (R/W).\r |
776 | \r | |
777 | @param ECX MSR_SILVERMONT_MISC_FEATURE_CONTROL (0x000001A4)\r | |
778 | @param EAX Lower 32-bits of MSR value.\r | |
779 | Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.\r | |
780 | @param EDX Upper 32-bits of MSR value.\r | |
781 | Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.\r | |
782 | \r | |
783 | <b>Example usage</b>\r | |
784 | @code\r | |
785 | MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER Msr;\r | |
786 | \r | |
787 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL);\r | |
788 | AsmWriteMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL, Msr.Uint64);\r | |
789 | @endcode\r | |
790 | @note MSR_SILVERMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r | |
791 | **/\r | |
792 | #define MSR_SILVERMONT_MISC_FEATURE_CONTROL 0x000001A4\r | |
793 | \r | |
794 | /**\r | |
795 | MSR information returned for MSR index #MSR_SILVERMONT_MISC_FEATURE_CONTROL\r | |
796 | **/\r | |
797 | typedef union {\r | |
798 | ///\r | |
799 | /// Individual bit fields\r | |
800 | ///\r | |
801 | struct {\r | |
802 | ///\r | |
803 | /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r | |
804 | /// L2 hardware prefetcher, which fetches additional lines of code or data\r | |
805 | /// into the L2 cache.\r | |
806 | ///\r | |
807 | UINT32 L2HardwarePrefetcherDisable:1;\r | |
808 | UINT32 Reserved1:1;\r | |
809 | ///\r | |
810 | /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r | |
811 | /// the L1 data cache prefetcher, which fetches the next cache line into\r | |
812 | /// L1 data cache.\r | |
813 | ///\r | |
814 | UINT32 DCUHardwarePrefetcherDisable:1;\r | |
815 | UINT32 Reserved2:29;\r | |
816 | UINT32 Reserved3:32;\r | |
817 | } Bits;\r | |
818 | ///\r | |
819 | /// All bit fields as a 32-bit value\r | |
820 | ///\r | |
821 | UINT32 Uint32;\r | |
822 | ///\r | |
823 | /// All bit fields as a 64-bit value\r | |
824 | ///\r | |
825 | UINT64 Uint64;\r | |
826 | } MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER;\r | |
827 | \r | |
828 | \r | |
829 | /**\r | |
830 | Module. Offcore Response Event Select Register (R/W).\r | |
053a6ae9 MK |
831 | \r |
832 | @param ECX MSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6)\r | |
833 | @param EAX Lower 32-bits of MSR value.\r | |
834 | @param EDX Upper 32-bits of MSR value.\r | |
835 | \r | |
836 | <b>Example usage</b>\r | |
837 | @code\r | |
838 | UINT64 Msr;\r | |
839 | \r | |
840 | Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0);\r | |
841 | AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr);\r | |
842 | @endcode\r | |
94fe1b5f | 843 | @note MSR_SILVERMONT_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r |
053a6ae9 MK |
844 | **/\r |
845 | #define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6\r | |
846 | \r | |
847 | \r | |
848 | /**\r | |
0f16be6d | 849 | Module. Offcore Response Event Select Register (R/W).\r |
053a6ae9 MK |
850 | \r |
851 | @param ECX MSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7)\r | |
852 | @param EAX Lower 32-bits of MSR value.\r | |
853 | @param EDX Upper 32-bits of MSR value.\r | |
854 | \r | |
855 | <b>Example usage</b>\r | |
856 | @code\r | |
857 | UINT64 Msr;\r | |
858 | \r | |
859 | Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1);\r | |
860 | AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr);\r | |
861 | @endcode\r | |
94fe1b5f | 862 | @note MSR_SILVERMONT_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r |
053a6ae9 MK |
863 | **/\r |
864 | #define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7\r | |
865 | \r | |
866 | \r | |
867 | /**\r | |
868 | Package. Maximum Ratio Limit of Turbo Mode (RW).\r | |
869 | \r | |
870 | @param ECX MSR_SILVERMONT_TURBO_RATIO_LIMIT (0x000001AD)\r | |
871 | @param EAX Lower 32-bits of MSR value.\r | |
872 | Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.\r | |
873 | @param EDX Upper 32-bits of MSR value.\r | |
874 | Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.\r | |
875 | \r | |
876 | <b>Example usage</b>\r | |
877 | @code\r | |
878 | MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
879 | \r | |
880 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT);\r | |
881 | AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64);\r | |
882 | @endcode\r | |
94fe1b5f | 883 | @note MSR_SILVERMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r |
053a6ae9 MK |
884 | **/\r |
885 | #define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD\r | |
886 | \r | |
887 | /**\r | |
888 | MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT\r | |
889 | **/\r | |
890 | typedef union {\r | |
891 | ///\r | |
892 | /// Individual bit fields\r | |
893 | ///\r | |
894 | struct {\r | |
895 | ///\r | |
896 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r | |
897 | /// limit of 1 core active.\r | |
898 | ///\r | |
899 | UINT32 Maximum1C:8;\r | |
900 | ///\r | |
901 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r | |
902 | /// limit of 2 core active.\r | |
903 | ///\r | |
904 | UINT32 Maximum2C:8;\r | |
905 | ///\r | |
906 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r | |
907 | /// limit of 3 core active.\r | |
908 | ///\r | |
909 | UINT32 Maximum3C:8;\r | |
910 | ///\r | |
911 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r | |
912 | /// limit of 4 core active.\r | |
913 | ///\r | |
914 | UINT32 Maximum4C:8;\r | |
915 | ///\r | |
916 | /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r | |
917 | /// limit of 5 core active.\r | |
918 | ///\r | |
919 | UINT32 Maximum5C:8;\r | |
920 | ///\r | |
921 | /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r | |
922 | /// limit of 6 core active.\r | |
923 | ///\r | |
924 | UINT32 Maximum6C:8;\r | |
925 | ///\r | |
926 | /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r | |
927 | /// limit of 7 core active.\r | |
928 | ///\r | |
929 | UINT32 Maximum7C:8;\r | |
930 | ///\r | |
931 | /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r | |
932 | /// limit of 8 core active.\r | |
933 | ///\r | |
934 | UINT32 Maximum8C:8;\r | |
935 | } Bits;\r | |
936 | ///\r | |
937 | /// All bit fields as a 64-bit value\r | |
938 | ///\r | |
939 | UINT64 Uint64;\r | |
940 | } MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER;\r | |
941 | \r | |
942 | \r | |
0f16be6d HW |
943 | /**\r |
944 | Core. Last Branch Record Filtering Select Register (R/W) See Section\r | |
945 | 17.7.2, "Filtering of Last Branch Records.".\r | |
946 | \r | |
947 | @param ECX MSR_SILVERMONT_LBR_SELECT (0x000001C8)\r | |
948 | @param EAX Lower 32-bits of MSR value.\r | |
949 | Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.\r | |
950 | @param EDX Upper 32-bits of MSR value.\r | |
951 | Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.\r | |
952 | \r | |
953 | <b>Example usage</b>\r | |
954 | @code\r | |
955 | MSR_SILVERMONT_LBR_SELECT_REGISTER Msr;\r | |
956 | \r | |
957 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_LBR_SELECT);\r | |
958 | AsmWriteMsr64 (MSR_SILVERMONT_LBR_SELECT, Msr.Uint64);\r | |
959 | @endcode\r | |
960 | @note MSR_SILVERMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r | |
961 | **/\r | |
962 | #define MSR_SILVERMONT_LBR_SELECT 0x000001C8\r | |
963 | \r | |
964 | /**\r | |
965 | MSR information returned for MSR index #MSR_SILVERMONT_LBR_SELECT\r | |
966 | **/\r | |
967 | typedef union {\r | |
968 | ///\r | |
969 | /// Individual bit fields\r | |
970 | ///\r | |
971 | struct {\r | |
972 | ///\r | |
973 | /// [Bit 0] CPL_EQ_0.\r | |
974 | ///\r | |
975 | UINT32 CPL_EQ_0:1;\r | |
976 | ///\r | |
977 | /// [Bit 1] CPL_NEQ_0.\r | |
978 | ///\r | |
979 | UINT32 CPL_NEQ_0:1;\r | |
980 | ///\r | |
981 | /// [Bit 2] JCC.\r | |
982 | ///\r | |
983 | UINT32 JCC:1;\r | |
984 | ///\r | |
985 | /// [Bit 3] NEAR_REL_CALL.\r | |
986 | ///\r | |
987 | UINT32 NEAR_REL_CALL:1;\r | |
988 | ///\r | |
989 | /// [Bit 4] NEAR_IND_CALL.\r | |
990 | ///\r | |
991 | UINT32 NEAR_IND_CALL:1;\r | |
992 | ///\r | |
993 | /// [Bit 5] NEAR_RET.\r | |
994 | ///\r | |
995 | UINT32 NEAR_RET:1;\r | |
996 | ///\r | |
997 | /// [Bit 6] NEAR_IND_JMP.\r | |
998 | ///\r | |
999 | UINT32 NEAR_IND_JMP:1;\r | |
1000 | ///\r | |
1001 | /// [Bit 7] NEAR_REL_JMP.\r | |
1002 | ///\r | |
1003 | UINT32 NEAR_REL_JMP:1;\r | |
1004 | ///\r | |
1005 | /// [Bit 8] FAR_BRANCH.\r | |
1006 | ///\r | |
1007 | UINT32 FAR_BRANCH:1;\r | |
1008 | UINT32 Reserved1:23;\r | |
1009 | UINT32 Reserved2:32;\r | |
1010 | } Bits;\r | |
1011 | ///\r | |
1012 | /// All bit fields as a 32-bit value\r | |
1013 | ///\r | |
1014 | UINT32 Uint32;\r | |
1015 | ///\r | |
1016 | /// All bit fields as a 64-bit value\r | |
1017 | ///\r | |
1018 | UINT64 Uint64;\r | |
1019 | } MSR_SILVERMONT_LBR_SELECT_REGISTER;\r | |
1020 | \r | |
1021 | \r | |
053a6ae9 MK |
1022 | /**\r |
1023 | Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that\r | |
1024 | points to the MSR containing the most recent branch record. See\r | |
0f16be6d | 1025 | MSR_LASTBRANCH_0_FROM_IP.\r |
053a6ae9 MK |
1026 | \r |
1027 | @param ECX MSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9)\r | |
1028 | @param EAX Lower 32-bits of MSR value.\r | |
1029 | @param EDX Upper 32-bits of MSR value.\r | |
1030 | \r | |
1031 | <b>Example usage</b>\r | |
1032 | @code\r | |
1033 | UINT64 Msr;\r | |
1034 | \r | |
1035 | Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS);\r | |
1036 | AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr);\r | |
1037 | @endcode\r | |
94fe1b5f | 1038 | @note MSR_SILVERMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r |
053a6ae9 MK |
1039 | **/\r |
1040 | #define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9\r | |
1041 | \r | |
1042 | \r | |
1043 | /**\r | |
1044 | Core. Last Exception Record From Linear IP (R) Contains a pointer to the\r | |
1045 | last branch instruction that the processor executed prior to the last\r | |
1046 | exception that was generated or the last interrupt that was handled.\r | |
1047 | \r | |
1048 | @param ECX MSR_SILVERMONT_LER_FROM_LIP (0x000001DD)\r | |
1049 | @param EAX Lower 32-bits of MSR value.\r | |
1050 | @param EDX Upper 32-bits of MSR value.\r | |
1051 | \r | |
1052 | <b>Example usage</b>\r | |
1053 | @code\r | |
1054 | UINT64 Msr;\r | |
1055 | \r | |
1056 | Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP);\r | |
1057 | @endcode\r | |
94fe1b5f | 1058 | @note MSR_SILVERMONT_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r |
053a6ae9 MK |
1059 | **/\r |
1060 | #define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD\r | |
1061 | \r | |
1062 | \r | |
1063 | /**\r | |
1064 | Core. Last Exception Record To Linear IP (R) This area contains a pointer\r | |
1065 | to the target of the last branch instruction that the processor executed\r | |
1066 | prior to the last exception that was generated or the last interrupt that\r | |
1067 | was handled.\r | |
1068 | \r | |
1069 | @param ECX MSR_SILVERMONT_LER_TO_LIP (0x000001DE)\r | |
1070 | @param EAX Lower 32-bits of MSR value.\r | |
1071 | @param EDX Upper 32-bits of MSR value.\r | |
1072 | \r | |
1073 | <b>Example usage</b>\r | |
1074 | @code\r | |
1075 | UINT64 Msr;\r | |
1076 | \r | |
1077 | Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP);\r | |
1078 | @endcode\r | |
94fe1b5f | 1079 | @note MSR_SILVERMONT_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r |
053a6ae9 MK |
1080 | **/\r |
1081 | #define MSR_SILVERMONT_LER_TO_LIP 0x000001DE\r | |
1082 | \r | |
1083 | \r | |
1084 | /**\r | |
0f16be6d | 1085 | Core. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling\r |
053a6ae9 MK |
1086 | (PEBS).".\r |
1087 | \r | |
1088 | @param ECX MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)\r | |
1089 | @param EAX Lower 32-bits of MSR value.\r | |
1090 | Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.\r | |
1091 | @param EDX Upper 32-bits of MSR value.\r | |
1092 | Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.\r | |
1093 | \r | |
1094 | <b>Example usage</b>\r | |
1095 | @code\r | |
1096 | MSR_SILVERMONT_PEBS_ENABLE_REGISTER Msr;\r | |
1097 | \r | |
1098 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE);\r | |
1099 | AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64);\r | |
1100 | @endcode\r | |
94fe1b5f | 1101 | @note MSR_SILVERMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r |
053a6ae9 MK |
1102 | **/\r |
1103 | #define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1\r | |
1104 | \r | |
1105 | /**\r | |
1106 | MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE\r | |
1107 | **/\r | |
1108 | typedef union {\r | |
1109 | ///\r | |
1110 | /// Individual bit fields\r | |
1111 | ///\r | |
1112 | struct {\r | |
1113 | ///\r | |
0f16be6d | 1114 | /// [Bit 0] Enable PEBS for precise event on IA32_PMC0. (R/W).\r |
053a6ae9 MK |
1115 | ///\r |
1116 | UINT32 PEBS:1;\r | |
1117 | UINT32 Reserved1:31;\r | |
1118 | UINT32 Reserved2:32;\r | |
1119 | } Bits;\r | |
1120 | ///\r | |
1121 | /// All bit fields as a 32-bit value\r | |
1122 | ///\r | |
1123 | UINT32 Uint32;\r | |
1124 | ///\r | |
1125 | /// All bit fields as a 64-bit value\r | |
1126 | ///\r | |
1127 | UINT64 Uint64;\r | |
1128 | } MSR_SILVERMONT_PEBS_ENABLE_REGISTER;\r | |
1129 | \r | |
1130 | \r | |
1131 | /**\r | |
1132 | Package. Note: C-state values are processor specific C-state code names,\r | |
1133 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r | |
1134 | Residency Counter. (R/O) Value since last reset that this package is in\r | |
1135 | processor-specific C6 states. Counts at the TSC Frequency.\r | |
1136 | \r | |
1137 | @param ECX MSR_SILVERMONT_PKG_C6_RESIDENCY (0x000003FA)\r | |
1138 | @param EAX Lower 32-bits of MSR value.\r | |
1139 | @param EDX Upper 32-bits of MSR value.\r | |
1140 | \r | |
1141 | <b>Example usage</b>\r | |
1142 | @code\r | |
1143 | UINT64 Msr;\r | |
1144 | \r | |
1145 | Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY);\r | |
1146 | AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr);\r | |
1147 | @endcode\r | |
94fe1b5f | 1148 | @note MSR_SILVERMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r |
053a6ae9 MK |
1149 | **/\r |
1150 | #define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA\r | |
1151 | \r | |
1152 | \r | |
1153 | /**\r | |
1154 | Core. Note: C-state values are processor specific C-state code names,\r | |
1155 | unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6\r | |
1156 | Residency Counter. (R/O) Value since last reset that this core is in\r | |
1157 | processor-specific C6 states. Counts at the TSC Frequency.\r | |
1158 | \r | |
1159 | @param ECX MSR_SILVERMONT_CORE_C6_RESIDENCY (0x000003FD)\r | |
1160 | @param EAX Lower 32-bits of MSR value.\r | |
1161 | @param EDX Upper 32-bits of MSR value.\r | |
1162 | \r | |
1163 | <b>Example usage</b>\r | |
1164 | @code\r | |
1165 | UINT64 Msr;\r | |
1166 | \r | |
1167 | Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY);\r | |
1168 | AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr);\r | |
1169 | @endcode\r | |
94fe1b5f | 1170 | @note MSR_SILVERMONT_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r |
053a6ae9 MK |
1171 | **/\r |
1172 | #define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD\r | |
1173 | \r | |
1174 | \r | |
053a6ae9 MK |
1175 | /**\r |
1176 | Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.\r | |
1177 | \r | |
1178 | @param ECX MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r | |
1179 | @param EAX Lower 32-bits of MSR value.\r | |
1180 | @param EDX Upper 32-bits of MSR value.\r | |
1181 | \r | |
1182 | <b>Example usage</b>\r | |
1183 | @code\r | |
1184 | UINT64 Msr;\r | |
1185 | \r | |
1186 | Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM);\r | |
1187 | @endcode\r | |
94fe1b5f | 1188 | @note MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r |
053a6ae9 MK |
1189 | **/\r |
1190 | #define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r | |
1191 | \r | |
1192 | \r | |
1193 | /**\r | |
1194 | Core. Capability Reporting Register of VM-function Controls (R/O) See Table\r | |
1195 | 35-2.\r | |
1196 | \r | |
1197 | @param ECX MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491)\r | |
1198 | @param EAX Lower 32-bits of MSR value.\r | |
1199 | @param EDX Upper 32-bits of MSR value.\r | |
1200 | \r | |
1201 | <b>Example usage</b>\r | |
1202 | @code\r | |
1203 | UINT64 Msr;\r | |
1204 | \r | |
1205 | Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC);\r | |
1206 | @endcode\r | |
94fe1b5f | 1207 | @note MSR_SILVERMONT_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.\r |
053a6ae9 MK |
1208 | **/\r |
1209 | #define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491\r | |
1210 | \r | |
1211 | \r | |
1212 | /**\r | |
1213 | Core. Note: C-state values are processor specific C-state code names,\r | |
1214 | unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C1\r | |
1215 | Residency Counter. (R/O) Value since last reset that this core is in\r | |
1216 | processor-specific C1 states. Counts at the TSC frequency.\r | |
1217 | \r | |
1218 | @param ECX MSR_SILVERMONT_CORE_C1_RESIDENCY (0x00000660)\r | |
1219 | @param EAX Lower 32-bits of MSR value.\r | |
1220 | @param EDX Upper 32-bits of MSR value.\r | |
1221 | \r | |
1222 | <b>Example usage</b>\r | |
1223 | @code\r | |
1224 | UINT64 Msr;\r | |
1225 | \r | |
1226 | Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY);\r | |
1227 | AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr);\r | |
1228 | @endcode\r | |
94fe1b5f | 1229 | @note MSR_SILVERMONT_CORE_C1_RESIDENCY is defined as MSR_CORE_C1_RESIDENCY in SDM.\r |
053a6ae9 MK |
1230 | **/\r |
1231 | #define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660\r | |
1232 | \r | |
1233 | \r | |
1234 | /**\r | |
1235 | Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r | |
1236 | "RAPL Interfaces.".\r | |
1237 | \r | |
1238 | @param ECX MSR_SILVERMONT_RAPL_POWER_UNIT (0x00000606)\r | |
1239 | @param EAX Lower 32-bits of MSR value.\r | |
1240 | Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.\r | |
1241 | @param EDX Upper 32-bits of MSR value.\r | |
1242 | Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.\r | |
1243 | \r | |
1244 | <b>Example usage</b>\r | |
1245 | @code\r | |
1246 | MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER Msr;\r | |
1247 | \r | |
1248 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT);\r | |
1249 | @endcode\r | |
94fe1b5f | 1250 | @note MSR_SILVERMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r |
053a6ae9 MK |
1251 | **/\r |
1252 | #define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606\r | |
1253 | \r | |
1254 | /**\r | |
1255 | MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT\r | |
1256 | **/\r | |
1257 | typedef union {\r | |
1258 | ///\r | |
1259 | /// Individual bit fields\r | |
1260 | ///\r | |
1261 | struct {\r | |
1262 | ///\r | |
1263 | /// [Bits 3:0] Power Units. Power related information (in milliWatts) is\r | |
1264 | /// based on the multiplier, 2^PU; where PU is an unsigned integer\r | |
1265 | /// represented by bits 3:0. Default value is 0101b, indicating power unit\r | |
1266 | /// is in 32 milliWatts increment.\r | |
1267 | ///\r | |
1268 | UINT32 PowerUnits:4;\r | |
1269 | UINT32 Reserved1:4;\r | |
1270 | ///\r | |
1271 | /// [Bits 12:8] Energy Status Units. Energy related information (in\r | |
1272 | /// microJoules) is based on the multiplier, 2^ESU; where ESU is an\r | |
1273 | /// unsigned integer represented by bits 12:8. Default value is 00101b,\r | |
1274 | /// indicating energy unit is in 32 microJoules increment.\r | |
1275 | ///\r | |
1276 | UINT32 EnergyStatusUnits:5;\r | |
1277 | UINT32 Reserved2:3;\r | |
1278 | ///\r | |
1279 | /// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in\r | |
1280 | /// one second.\r | |
1281 | ///\r | |
1282 | UINT32 TimeUnits:4;\r | |
1283 | UINT32 Reserved3:12;\r | |
1284 | UINT32 Reserved4:32;\r | |
1285 | } Bits;\r | |
1286 | ///\r | |
1287 | /// All bit fields as a 32-bit value\r | |
1288 | ///\r | |
1289 | UINT32 Uint32;\r | |
1290 | ///\r | |
1291 | /// All bit fields as a 64-bit value\r | |
1292 | ///\r | |
1293 | UINT64 Uint64;\r | |
1294 | } MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER;\r | |
1295 | \r | |
1296 | \r | |
1297 | /**\r | |
1298 | Package. PKG RAPL Power Limit Control (R/W).\r | |
1299 | \r | |
1300 | @param ECX MSR_SILVERMONT_PKG_POWER_LIMIT (0x00000610)\r | |
1301 | @param EAX Lower 32-bits of MSR value.\r | |
1302 | Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.\r | |
1303 | @param EDX Upper 32-bits of MSR value.\r | |
1304 | Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.\r | |
1305 | \r | |
1306 | <b>Example usage</b>\r | |
1307 | @code\r | |
1308 | MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER Msr;\r | |
1309 | \r | |
1310 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT);\r | |
1311 | AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64);\r | |
1312 | @endcode\r | |
94fe1b5f | 1313 | @note MSR_SILVERMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r |
053a6ae9 MK |
1314 | **/\r |
1315 | #define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610\r | |
1316 | \r | |
1317 | /**\r | |
1318 | MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT\r | |
1319 | **/\r | |
1320 | typedef union {\r | |
1321 | ///\r | |
1322 | /// Individual bit fields\r | |
1323 | ///\r | |
1324 | struct {\r | |
1325 | ///\r | |
1326 | /// [Bits 14:0] Package Power Limit #1. (R/W) See Section 14.9.3, "Package\r | |
0f16be6d | 1327 | /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 35-8.\r |
053a6ae9 MK |
1328 | ///\r |
1329 | UINT32 Limit:15;\r | |
1330 | ///\r | |
1331 | /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package\r | |
1332 | /// RAPL Domain.".\r | |
1333 | ///\r | |
1334 | UINT32 Enable:1;\r | |
1335 | ///\r | |
1336 | /// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3,\r | |
1337 | /// "Package RAPL Domain.".\r | |
1338 | ///\r | |
1339 | UINT32 ClampingLimit:1;\r | |
1340 | ///\r | |
1341 | /// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second.\r | |
1342 | /// If 0 is specified in bits [23:17], defaults to 1 second window.\r | |
1343 | ///\r | |
1344 | UINT32 Time:7;\r | |
1345 | UINT32 Reserved1:8;\r | |
1346 | UINT32 Reserved2:32;\r | |
1347 | } Bits;\r | |
1348 | ///\r | |
1349 | /// All bit fields as a 32-bit value\r | |
1350 | ///\r | |
1351 | UINT32 Uint32;\r | |
1352 | ///\r | |
1353 | /// All bit fields as a 64-bit value\r | |
1354 | ///\r | |
1355 | UINT64 Uint64;\r | |
1356 | } MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER;\r | |
1357 | \r | |
1358 | \r | |
1359 | /**\r | |
1360 | Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."\r | |
0f16be6d | 1361 | and MSR_RAPL_POWER_UNIT in Table 35-8.\r |
053a6ae9 MK |
1362 | \r |
1363 | @param ECX MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)\r | |
1364 | @param EAX Lower 32-bits of MSR value.\r | |
1365 | @param EDX Upper 32-bits of MSR value.\r | |
1366 | \r | |
1367 | <b>Example usage</b>\r | |
1368 | @code\r | |
1369 | UINT64 Msr;\r | |
1370 | \r | |
1371 | Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS);\r | |
1372 | @endcode\r | |
94fe1b5f | 1373 | @note MSR_SILVERMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r |
053a6ae9 MK |
1374 | **/\r |
1375 | #define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611\r | |
1376 | \r | |
1377 | \r | |
1378 | /**\r | |
1379 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
0f16be6d | 1380 | Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.\r |
053a6ae9 MK |
1381 | \r |
1382 | @param ECX MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)\r | |
1383 | @param EAX Lower 32-bits of MSR value.\r | |
1384 | @param EDX Upper 32-bits of MSR value.\r | |
1385 | \r | |
1386 | <b>Example usage</b>\r | |
1387 | @code\r | |
1388 | UINT64 Msr;\r | |
1389 | \r | |
1390 | Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS);\r | |
1391 | @endcode\r | |
94fe1b5f | 1392 | @note MSR_SILVERMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r |
053a6ae9 MK |
1393 | **/\r |
1394 | #define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639\r | |
1395 | \r | |
1396 | \r | |
1397 | /**\r | |
1398 | Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion\r | |
1399 | policy. Writing a value of 0 disables core level HW demotion policy.\r | |
1400 | \r | |
1401 | @param ECX MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG (0x00000668)\r | |
1402 | @param EAX Lower 32-bits of MSR value.\r | |
1403 | @param EDX Upper 32-bits of MSR value.\r | |
1404 | \r | |
1405 | <b>Example usage</b>\r | |
1406 | @code\r | |
1407 | UINT64 Msr;\r | |
1408 | \r | |
1409 | Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG);\r | |
1410 | AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr);\r | |
1411 | @endcode\r | |
94fe1b5f | 1412 | @note MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG is defined as MSR_CC6_DEMOTION_POLICY_CONFIG in SDM.\r |
053a6ae9 MK |
1413 | **/\r |
1414 | #define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668\r | |
1415 | \r | |
1416 | \r | |
1417 | /**\r | |
1418 | Package. Module C6 demotion policy config MSR. Controls module (i.e. two\r | |
1419 | cores sharing the second-level cache) C6 demotion policy. Writing a value of\r | |
1420 | 0 disables module level HW demotion policy.\r | |
1421 | \r | |
1422 | @param ECX MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG (0x00000669)\r | |
1423 | @param EAX Lower 32-bits of MSR value.\r | |
1424 | @param EDX Upper 32-bits of MSR value.\r | |
1425 | \r | |
1426 | <b>Example usage</b>\r | |
1427 | @code\r | |
1428 | UINT64 Msr;\r | |
1429 | \r | |
1430 | Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG);\r | |
1431 | AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr);\r | |
1432 | @endcode\r | |
94fe1b5f | 1433 | @note MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG is defined as MSR_MC6_DEMOTION_POLICY_CONFIG in SDM.\r |
053a6ae9 MK |
1434 | **/\r |
1435 | #define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669\r | |
1436 | \r | |
1437 | \r | |
1438 | /**\r | |
1439 | Module. Module C6 Residency Counter (R/0) Note: C-state values are processor\r | |
1440 | specific C-state code names, unrelated to MWAIT extension C-state parameters\r | |
1441 | or ACPI CStates. Time that this module is in module-specific C6 states since\r | |
1442 | last reset. Counts at 1 Mhz frequency.\r | |
1443 | \r | |
1444 | @param ECX MSR_SILVERMONT_MC6_RESIDENCY_COUNTER (0x00000664)\r | |
1445 | @param EAX Lower 32-bits of MSR value.\r | |
1446 | @param EDX Upper 32-bits of MSR value.\r | |
1447 | \r | |
1448 | <b>Example usage</b>\r | |
1449 | @code\r | |
1450 | UINT64 Msr;\r | |
1451 | \r | |
1452 | Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER);\r | |
1453 | @endcode\r | |
94fe1b5f | 1454 | @note MSR_SILVERMONT_MC6_RESIDENCY_COUNTER is defined as MSR_MC6_RESIDENCY_COUNTER in SDM.\r |
053a6ae9 MK |
1455 | **/\r |
1456 | #define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664\r | |
1457 | \r | |
1458 | \r | |
1459 | /**\r | |
1460 | Package. PKG RAPL Parameter (R/0).\r | |
1461 | \r | |
1462 | @param ECX MSR_SILVERMONT_PKG_POWER_INFO (0x0000066E)\r | |
1463 | @param EAX Lower 32-bits of MSR value.\r | |
1464 | Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.\r | |
1465 | @param EDX Upper 32-bits of MSR value.\r | |
1466 | Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.\r | |
1467 | \r | |
1468 | <b>Example usage</b>\r | |
1469 | @code\r | |
1470 | MSR_SILVERMONT_PKG_POWER_INFO_REGISTER Msr;\r | |
1471 | \r | |
1472 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO);\r | |
1473 | @endcode\r | |
94fe1b5f | 1474 | @note MSR_SILVERMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r |
053a6ae9 MK |
1475 | **/\r |
1476 | #define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E\r | |
1477 | \r | |
1478 | /**\r | |
1479 | MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO\r | |
1480 | **/\r | |
1481 | typedef union {\r | |
1482 | ///\r | |
1483 | /// Individual bit fields\r | |
1484 | ///\r | |
1485 | struct {\r | |
1486 | ///\r | |
1487 | /// [Bits 14:0] Thermal Spec Power. (R/0) The unsigned integer value is\r | |
1488 | /// the equivalent of thermal specification power of the package domain.\r | |
1489 | /// The unit of this field is specified by the "Power Units" field of\r | |
1490 | /// MSR_RAPL_POWER_UNIT.\r | |
1491 | ///\r | |
1492 | UINT32 ThermalSpecPower:15;\r | |
1493 | UINT32 Reserved1:17;\r | |
1494 | UINT32 Reserved2:32;\r | |
1495 | } Bits;\r | |
1496 | ///\r | |
1497 | /// All bit fields as a 32-bit value\r | |
1498 | ///\r | |
1499 | UINT32 Uint32;\r | |
1500 | ///\r | |
1501 | /// All bit fields as a 64-bit value\r | |
1502 | ///\r | |
1503 | UINT64 Uint64;\r | |
1504 | } MSR_SILVERMONT_PKG_POWER_INFO_REGISTER;\r | |
1505 | \r | |
1506 | \r | |
1507 | /**\r | |
1508 | Package. PP0 RAPL Power Limit Control (R/W).\r | |
1509 | \r | |
1510 | @param ECX MSR_SILVERMONT_PP0_POWER_LIMIT (0x00000638)\r | |
1511 | @param EAX Lower 32-bits of MSR value.\r | |
1512 | Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.\r | |
1513 | @param EDX Upper 32-bits of MSR value.\r | |
1514 | Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.\r | |
1515 | \r | |
1516 | <b>Example usage</b>\r | |
1517 | @code\r | |
1518 | MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER Msr;\r | |
1519 | \r | |
1520 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT);\r | |
1521 | AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64);\r | |
1522 | @endcode\r | |
94fe1b5f | 1523 | @note MSR_SILVERMONT_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r |
053a6ae9 MK |
1524 | **/\r |
1525 | #define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638\r | |
1526 | \r | |
1527 | /**\r | |
1528 | MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT\r | |
1529 | **/\r | |
1530 | typedef union {\r | |
1531 | ///\r | |
1532 | /// Individual bit fields\r | |
1533 | ///\r | |
1534 | struct {\r | |
1535 | ///\r | |
1536 | /// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1\r | |
0f16be6d | 1537 | /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.\r |
053a6ae9 MK |
1538 | ///\r |
1539 | UINT32 Limit:15;\r | |
1540 | ///\r | |
1541 | /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1\r | |
1542 | /// RAPL Domains.".\r | |
1543 | ///\r | |
1544 | UINT32 Enable:1;\r | |
1545 | UINT32 Reserved1:1;\r | |
1546 | ///\r | |
1547 | /// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time\r | |
1548 | /// duration over which the average power must remain below\r | |
1549 | /// PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time\r | |
1550 | /// duration. 0x1: 5 second time duration (Default). 0x2: 10 second time\r | |
1551 | /// duration. 0x3: 15 second time duration. 0x4: 20 second time duration.\r | |
1552 | /// 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35\r | |
1553 | /// second time duration. 0x8: 40 second time duration. 0x9: 45 second\r | |
1554 | /// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.\r | |
1555 | ///\r | |
1556 | UINT32 Time:7;\r | |
1557 | UINT32 Reserved2:8;\r | |
1558 | UINT32 Reserved3:32;\r | |
1559 | } Bits;\r | |
1560 | ///\r | |
1561 | /// All bit fields as a 32-bit value\r | |
1562 | ///\r | |
1563 | UINT32 Uint32;\r | |
1564 | ///\r | |
1565 | /// All bit fields as a 64-bit value\r | |
1566 | ///\r | |
1567 | UINT64 Uint64;\r | |
1568 | } MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER;\r | |
1569 | \r | |
1570 | #endif\r |