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UefiCpuPkg/Msr: Add CPUID signature check MACROs
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / XeonDMsr.h
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54307cea
MK		 1/** @file\r
2 MSR Definitions for Intel(R) Xeon(R) Processor D product Family.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
f4c982bf 9 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
54307cea
MK		 10 This program and the accompanying materials\r
11 are licensed and made available under the terms and conditions of the BSD License\r
12 which accompanies this distribution. The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
0f16be6d 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.14.\r
54307cea
MK		 21\r
22**/\r
23\r
24#ifndef __XEON_D_MSR_H__\r
25#define __XEON_D_MSR_H__\r
26\r
27#include <Register/ArchitecturalMsr.h>\r
28\r
f4c982bf
JF		 29/**\r
30 Is Intel(R) Xeon(R) Processor D product Family?\r
31\r
32 @param DisplayFamily Display Family ID\r
33 @param DisplayModel Display Model ID\r
34\r
35 @retval TRUE Yes, it is.\r
36 @retval FALSE No, it isn't.\r
37**/\r
38#define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \\r
39 (DisplayFamily == 0x06 && \\r
40 ( \\r
41 DisplayModel == 0x4F || \\r
42 DisplayModel == 0x56 \\r
43 ) \\r
44 )\r
45\r
54307cea
MK		 46/**\r
47 Package. Protected Processor Inventory Number Enable Control (R/W).\r
48\r
49 @param ECX MSR_XEON_D_PPIN_CTL (0x0000004E)\r
50 @param EAX Lower 32-bits of MSR value.\r
51 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.\r
52 @param EDX Upper 32-bits of MSR value.\r
53 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.\r
54\r
55 <b>Example usage</b>\r
56 @code\r
57 MSR_XEON_D_PPIN_CTL_REGISTER Msr;\r
58\r
59 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL);\r
60 AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64);\r
61 @endcode\r
b6ae7578 62 @note MSR_XEON_D_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.\r
54307cea
MK		 63**/\r
64#define MSR_XEON_D_PPIN_CTL 0x0000004E\r
65\r
66/**\r
67 MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL\r
68**/\r
69typedef union {\r
70 ///\r
71 /// Individual bit fields\r
72 ///\r
73 struct {\r
74 ///\r
0f16be6d 75 /// [Bit 0] LockOut (R/WO) See Table 35-24.\r
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MK		 76 ///\r
77 UINT32 LockOut:1;\r
78 ///\r
0f16be6d 79 /// [Bit 1] Enable_PPIN (R/W) See Table 35-24.\r
54307cea
MK		 80 ///\r
81 UINT32 Enable_PPIN:1;\r
82 UINT32 Reserved1:30;\r
83 UINT32 Reserved2:32;\r
84 } Bits;\r
85 ///\r
86 /// All bit fields as a 32-bit value\r
87 ///\r
88 UINT32 Uint32;\r
89 ///\r
90 /// All bit fields as a 64-bit value\r
91 ///\r
92 UINT64 Uint64;\r
93} MSR_XEON_D_PPIN_CTL_REGISTER;\r
94\r
95\r
96/**\r
97 Package. Protected Processor Inventory Number (R/O). Protected Processor\r
0f16be6d 98 Inventory Number (R/O) See Table 35-24.\r
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MK		 99\r
100 @param ECX MSR_XEON_D_PPIN (0x0000004F)\r
101 @param EAX Lower 32-bits of MSR value.\r
102 @param EDX Upper 32-bits of MSR value.\r
103\r
104 <b>Example usage</b>\r
105 @code\r
106 UINT64 Msr;\r
107\r
108 Msr = AsmReadMsr64 (MSR_XEON_D_PPIN);\r
109 @endcode\r
b6ae7578 110 @note MSR_XEON_D_PPIN is defined as MSR_PPIN in SDM.\r
54307cea
MK		 111**/\r
112#define MSR_XEON_D_PPIN 0x0000004F\r
113\r
114\r
115/**\r
116 Package. See http://biosbits.org.\r
117\r
118 @param ECX MSR_XEON_D_PLATFORM_INFO (0x000000CE)\r
119 @param EAX Lower 32-bits of MSR value.\r
120 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.\r
121 @param EDX Upper 32-bits of MSR value.\r
122 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.\r
123\r
124 <b>Example usage</b>\r
125 @code\r
126 MSR_XEON_D_PLATFORM_INFO_REGISTER Msr;\r
127\r
128 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO);\r
129 AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64);\r
130 @endcode\r
b6ae7578 131 @note MSR_XEON_D_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
54307cea
MK		 132**/\r
133#define MSR_XEON_D_PLATFORM_INFO 0x000000CE\r
134\r
135/**\r
136 MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO\r
137**/\r
138typedef union {\r
139 ///\r
140 /// Individual bit fields\r
141 ///\r
142 struct {\r
143 UINT32 Reserved1:8;\r
144 ///\r
0f16be6d 145 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 35-24.\r
54307cea
MK		 146 ///\r
147 UINT32 MaximumNonTurboRatio:8;\r
148 UINT32 Reserved2:7;\r
149 ///\r
0f16be6d 150 /// [Bit 23] Package. PPIN_CAP (R/O) See Table 35-24.\r
54307cea
MK		 151 ///\r
152 UINT32 PPIN_CAP:1;\r
153 UINT32 Reserved3:4;\r
154 ///\r
155 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
0f16be6d 156 /// Table 35-24.\r
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MK		 157 ///\r
158 UINT32 RatioLimit:1;\r
159 ///\r
160 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
0f16be6d 161 /// Table 35-24.\r
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MK		 162 ///\r
163 UINT32 TDPLimit:1;\r
164 ///\r
0f16be6d 165 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 35-24.\r
54307cea
MK		 166 ///\r
167 UINT32 TJOFFSET:1;\r
168 UINT32 Reserved4:1;\r
169 UINT32 Reserved5:8;\r
170 ///\r
0f16be6d 171 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 35-24.\r
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MK		 172 ///\r
173 UINT32 MaximumEfficiencyRatio:8;\r
174 UINT32 Reserved6:16;\r
175 } Bits;\r
176 ///\r
177 /// All bit fields as a 64-bit value\r
178 ///\r
179 UINT64 Uint64;\r
180} MSR_XEON_D_PLATFORM_INFO_REGISTER;\r
181\r
182\r
183/**\r
184 Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
185 specific C-state code names, unrelated to MWAIT extension C-state parameters\r
186 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
187\r
188 @param ECX MSR_XEON_D_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
189 @param EAX Lower 32-bits of MSR value.\r
190 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.\r
191 @param EDX Upper 32-bits of MSR value.\r
192 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.\r
193\r
194 <b>Example usage</b>\r
195 @code\r
196 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
197\r
198 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL);\r
199 AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
200 @endcode\r
b6ae7578 201 @note MSR_XEON_D_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
54307cea
MK		 202**/\r
203#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2\r
204\r
205/**\r
206 MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL\r
207**/\r
208typedef union {\r
209 ///\r
210 /// Individual bit fields\r
211 ///\r
212 struct {\r
213 ///\r
214 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
215 /// processor-specific C-state code name (consuming the least power) for\r
216 /// the package. The default is set as factory-configured package C-state\r
217 /// limit. The following C-state code name encodings are supported: 000b:\r
218 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r
219 /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
220 /// supported by the processor are available.\r
221 ///\r
222 UINT32 Limit:3;\r
223 UINT32 Reserved1:7;\r
224 ///\r
225 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
226 ///\r
227 UINT32 IO_MWAIT:1;\r
228 UINT32 Reserved2:4;\r
229 ///\r
230 /// [Bit 15] CFG Lock (R/WO).\r
231 ///\r
232 UINT32 CFGLock:1;\r
233 ///\r
234 /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor\r
235 /// will convert HALT or MWAT(C1) to MWAIT(C6).\r
236 ///\r
237 UINT32 CStateConversion:1;\r
238 UINT32 Reserved3:8;\r
239 ///\r
240 /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
241 ///\r
242 UINT32 C3AutoDemotion:1;\r
243 ///\r
244 /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
245 ///\r
246 UINT32 C1AutoDemotion:1;\r
247 ///\r
248 /// [Bit 27] Enable C3 Undemotion (R/W).\r
249 ///\r
250 UINT32 C3Undemotion:1;\r
251 ///\r
252 /// [Bit 28] Enable C1 Undemotion (R/W).\r
253 ///\r
254 UINT32 C1Undemotion:1;\r
255 ///\r
256 /// [Bit 29] Package C State Demotion Enable (R/W).\r
257 ///\r
258 UINT32 CStateDemotion:1;\r
259 ///\r
260 /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
261 ///\r
262 UINT32 CStateUndemotion:1;\r
263 UINT32 Reserved4:1;\r
264 UINT32 Reserved5:32;\r
265 } Bits;\r
266 ///\r
267 /// All bit fields as a 32-bit value\r
268 ///\r
269 UINT32 Uint32;\r
270 ///\r
271 /// All bit fields as a 64-bit value\r
272 ///\r
273 UINT64 Uint64;\r
274} MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER;\r
275\r
276\r
277/**\r
278 Thread. Global Machine Check Capability (R/O).\r
279\r
280 @param ECX MSR_XEON_D_IA32_MCG_CAP (0x00000179)\r
281 @param EAX Lower 32-bits of MSR value.\r
282 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.\r
283 @param EDX Upper 32-bits of MSR value.\r
284 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.\r
285\r
286 <b>Example usage</b>\r
287 @code\r
288 MSR_XEON_D_IA32_MCG_CAP_REGISTER Msr;\r
289\r
290 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP);\r
291 @endcode\r
b6ae7578 292 @note MSR_XEON_D_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
54307cea
MK		 293**/\r
294#define MSR_XEON_D_IA32_MCG_CAP 0x00000179\r
295\r
296/**\r
297 MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP\r
298**/\r
299typedef union {\r
300 ///\r
301 /// Individual bit fields\r
302 ///\r
303 struct {\r
304 ///\r
305 /// [Bits 7:0] Count.\r
306 ///\r
307 UINT32 Count:8;\r
308 ///\r
309 /// [Bit 8] MCG_CTL_P.\r
310 ///\r
311 UINT32 MCG_CTL_P:1;\r
312 ///\r
313 /// [Bit 9] MCG_EXT_P.\r
314 ///\r
315 UINT32 MCG_EXT_P:1;\r
316 ///\r
317 /// [Bit 10] MCP_CMCI_P.\r
318 ///\r
319 UINT32 MCP_CMCI_P:1;\r
320 ///\r
321 /// [Bit 11] MCG_TES_P.\r
322 ///\r
323 UINT32 MCG_TES_P:1;\r
324 UINT32 Reserved1:4;\r
325 ///\r
326 /// [Bits 23:16] MCG_EXT_CNT.\r
327 ///\r
328 UINT32 MCG_EXT_CNT:8;\r
329 ///\r
330 /// [Bit 24] MCG_SER_P.\r
331 ///\r
332 UINT32 MCG_SER_P:1;\r
333 ///\r
334 /// [Bit 25] MCG_EM_P.\r
335 ///\r
336 UINT32 MCG_EM_P:1;\r
337 ///\r
338 /// [Bit 26] MCG_ELOG_P.\r
339 ///\r
340 UINT32 MCG_ELOG_P:1;\r
341 UINT32 Reserved2:5;\r
342 UINT32 Reserved3:32;\r
343 } Bits;\r
344 ///\r
345 /// All bit fields as a 32-bit value\r
346 ///\r
347 UINT32 Uint32;\r
348 ///\r
349 /// All bit fields as a 64-bit value\r
350 ///\r
351 UINT64 Uint64;\r
352} MSR_XEON_D_IA32_MCG_CAP_REGISTER;\r
353\r
354\r
355/**\r
356 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
357 Enhancement. Accessible only while in SMM.\r
358\r
359 @param ECX MSR_XEON_D_SMM_MCA_CAP (0x0000017D)\r
360 @param EAX Lower 32-bits of MSR value.\r
361 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.\r
362 @param EDX Upper 32-bits of MSR value.\r
363 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.\r
364\r
365 <b>Example usage</b>\r
366 @code\r
367 MSR_XEON_D_SMM_MCA_CAP_REGISTER Msr;\r
368\r
369 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP);\r
370 AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64);\r
371 @endcode\r
b6ae7578 372 @note MSR_XEON_D_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
54307cea
MK		 373**/\r
374#define MSR_XEON_D_SMM_MCA_CAP 0x0000017D\r
375\r
376/**\r
377 MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP\r
378**/\r
379typedef union {\r
380 ///\r
381 /// Individual bit fields\r
382 ///\r
383 struct {\r
384 UINT32 Reserved1:32;\r
385 UINT32 Reserved2:26;\r
386 ///\r
387 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
388 /// SMM code access restriction is supported and a host-space interface\r
389 /// available to SMM handler.\r
390 ///\r
391 UINT32 SMM_Code_Access_Chk:1;\r
392 ///\r
393 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
394 /// SMM long flow indicator is supported and a host-space interface\r
395 /// available to SMM handler.\r
396 ///\r
397 UINT32 Long_Flow_Indication:1;\r
398 UINT32 Reserved3:4;\r
399 } Bits;\r
400 ///\r
401 /// All bit fields as a 64-bit value\r
402 ///\r
403 UINT64 Uint64;\r
404} MSR_XEON_D_SMM_MCA_CAP_REGISTER;\r
405\r
406\r
407/**\r
408 Package.\r
409\r
410 @param ECX MSR_XEON_D_TEMPERATURE_TARGET (0x000001A2)\r
411 @param EAX Lower 32-bits of MSR value.\r
412 Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.\r
413 @param EDX Upper 32-bits of MSR value.\r
414 Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.\r
415\r
416 <b>Example usage</b>\r
417 @code\r
418 MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Msr;\r
419\r
420 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET);\r
421 AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64);\r
422 @endcode\r
b6ae7578 423 @note MSR_XEON_D_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
54307cea
MK		 424**/\r
425#define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2\r
426\r
427/**\r
428 MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET\r
429**/\r
430typedef union {\r
431 ///\r
432 /// Individual bit fields\r
433 ///\r
434 struct {\r
435 UINT32 Reserved1:16;\r
436 ///\r
0f16be6d 437 /// [Bits 23:16] Temperature Target (RO) See Table 35-24.\r
54307cea
MK		 438 ///\r
439 UINT32 TemperatureTarget:8;\r
440 ///\r
0f16be6d 441 /// [Bits 27:24] TCC Activation Offset (R/W) See Table 35-24.\r
54307cea
MK		 442 ///\r
443 UINT32 TCCActivationOffset:4;\r
444 UINT32 Reserved2:4;\r
445 UINT32 Reserved3:32;\r
446 } Bits;\r
447 ///\r
448 /// All bit fields as a 32-bit value\r
449 ///\r
450 UINT32 Uint32;\r
451 ///\r
452 /// All bit fields as a 64-bit value\r
453 ///\r
454 UINT64 Uint64;\r
455} MSR_XEON_D_TEMPERATURE_TARGET_REGISTER;\r
456\r
457\r
458/**\r
459 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
460 RW if MSR_PLATFORM_INFO.[28] = 1.\r
461\r
462 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT (0x000001AD)\r
463 @param EAX Lower 32-bits of MSR value.\r
464 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.\r
465 @param EDX Upper 32-bits of MSR value.\r
466 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.\r
467\r
468 <b>Example usage</b>\r
469 @code\r
470 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Msr;\r
471\r
472 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT);\r
473 @endcode\r
b6ae7578 474 @note MSR_XEON_D_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
54307cea
MK		 475**/\r
476#define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD\r
477\r
478/**\r
479 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT\r
480**/\r
481typedef union {\r
482 ///\r
483 /// Individual bit fields\r
484 ///\r
485 struct {\r
486 ///\r
487 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C.\r
488 ///\r
489 UINT32 Maximum1C:8;\r
490 ///\r
491 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C.\r
492 ///\r
493 UINT32 Maximum2C:8;\r
494 ///\r
495 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C.\r
496 ///\r
497 UINT32 Maximum3C:8;\r
498 ///\r
499 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C.\r
500 ///\r
501 UINT32 Maximum4C:8;\r
502 ///\r
503 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C.\r
504 ///\r
505 UINT32 Maximum5C:8;\r
506 ///\r
507 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C.\r
508 ///\r
509 UINT32 Maximum6C:8;\r
510 ///\r
511 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C.\r
512 ///\r
513 UINT32 Maximum7C:8;\r
514 ///\r
515 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C.\r
516 ///\r
517 UINT32 Maximum8C:8;\r
518 } Bits;\r
519 ///\r
520 /// All bit fields as a 64-bit value\r
521 ///\r
522 UINT64 Uint64;\r
523} MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER;\r
524\r
525\r
526/**\r
527 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
528 RW if MSR_PLATFORM_INFO.[28] = 1.\r
529\r
530 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT1 (0x000001AE)\r
531 @param EAX Lower 32-bits of MSR value.\r
532 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.\r
533 @param EDX Upper 32-bits of MSR value.\r
534 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.\r
535\r
536 <b>Example usage</b>\r
537 @code\r
538 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Msr;\r
539\r
540 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1);\r
541 @endcode\r
b6ae7578 542 @note MSR_XEON_D_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
54307cea
MK		 543**/\r
544#define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE\r
545\r
546/**\r
547 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1\r
548**/\r
549typedef union {\r
550 ///\r
551 /// Individual bit fields\r
552 ///\r
553 struct {\r
554 ///\r
555 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C.\r
556 ///\r
557 UINT32 Maximum9C:8;\r
558 ///\r
559 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C.\r
560 ///\r
561 UINT32 Maximum10C:8;\r
562 ///\r
563 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C.\r
564 ///\r
565 UINT32 Maximum11C:8;\r
566 ///\r
567 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C.\r
568 ///\r
569 UINT32 Maximum12C:8;\r
570 ///\r
571 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C.\r
572 ///\r
573 UINT32 Maximum13C:8;\r
574 ///\r
575 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C.\r
576 ///\r
577 UINT32 Maximum14C:8;\r
578 ///\r
579 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C.\r
580 ///\r
581 UINT32 Maximum15C:8;\r
582 ///\r
583 /// [Bits 63:56] Package. Maximum Ratio Limit for 16C.\r
584 ///\r
585 UINT32 Maximum16C:8;\r
586 } Bits;\r
587 ///\r
588 /// All bit fields as a 64-bit value\r
589 ///\r
590 UINT64 Uint64;\r
591} MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER;\r
592\r
593\r
594/**\r
595 Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
596\r
597 @param ECX MSR_XEON_D_RAPL_POWER_UNIT (0x00000606)\r
598 @param EAX Lower 32-bits of MSR value.\r
599 Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.\r
600 @param EDX Upper 32-bits of MSR value.\r
601 Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.\r
602\r
603 <b>Example usage</b>\r
604 @code\r
605 MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Msr;\r
606\r
607 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT);\r
608 @endcode\r
b6ae7578 609 @note MSR_XEON_D_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
54307cea
MK		 610**/\r
611#define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606\r
612\r
613/**\r
614 MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT\r
615**/\r
616typedef union {\r
617 ///\r
618 /// Individual bit fields\r
619 ///\r
620 struct {\r
621 ///\r
622 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
623 ///\r
624 UINT32 PowerUnits:4;\r
625 UINT32 Reserved1:4;\r
626 ///\r
627 /// [Bits 12:8] Package. Energy Status Units Energy related information\r
628 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
629 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
630 /// micro-joules).\r
631 ///\r
632 UINT32 EnergyStatusUnits:5;\r
633 UINT32 Reserved2:3;\r
634 ///\r
635 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
636 /// Interfaces.".\r
637 ///\r
638 UINT32 TimeUnits:4;\r
639 UINT32 Reserved3:12;\r
640 UINT32 Reserved4:32;\r
641 } Bits;\r
642 ///\r
643 /// All bit fields as a 32-bit value\r
644 ///\r
645 UINT32 Uint32;\r
646 ///\r
647 /// All bit fields as a 64-bit value\r
648 ///\r
649 UINT64 Uint64;\r
650} MSR_XEON_D_RAPL_POWER_UNIT_REGISTER;\r
651\r
652\r
653/**\r
654 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
655 Domain.".\r
656\r
657 @param ECX MSR_XEON_D_DRAM_POWER_LIMIT (0x00000618)\r
658 @param EAX Lower 32-bits of MSR value.\r
659 @param EDX Upper 32-bits of MSR value.\r
660\r
661 <b>Example usage</b>\r
662 @code\r
663 UINT64 Msr;\r
664\r
665 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT);\r
666 AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr);\r
667 @endcode\r
b6ae7578 668 @note MSR_XEON_D_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
54307cea
MK		 669**/\r
670#define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618\r
671\r
672\r
673/**\r
0f16be6d 674 Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.\r
54307cea
MK		 675\r
676 @param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619)\r
677 @param EAX Lower 32-bits of MSR value.\r
0f16be6d 678 Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.\r
54307cea 679 @param EDX Upper 32-bits of MSR value.\r
0f16be6d 680 Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.\r
54307cea
MK		 681\r
682 <b>Example usage</b>\r
683 @code\r
0f16be6d 684 MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER Msr;\r
54307cea 685\r
0f16be6d 686 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);\r
54307cea 687 @endcode\r
b6ae7578 688 @note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
54307cea
MK		 689**/\r
690#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619\r
691\r
0f16be6d
HW		 692/**\r
693 MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS\r
694**/\r
695typedef union {\r
696 ///\r
697 /// Individual bit fields\r
698 ///\r
699 struct {\r
700 ///\r
701 /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
702 /// to enable DRAM RAPL mode 0 (Direct VR).\r
703 ///\r
704 UINT32 Energy:32;\r
705 UINT32 Reserved:32;\r
706 } Bits;\r
707 ///\r
708 /// All bit fields as a 32-bit value\r
709 ///\r
710 UINT32 Uint32;\r
711 ///\r
712 /// All bit fields as a 64-bit value\r
713 ///\r
714 UINT64 Uint64;\r
715} MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER;\r
716\r
54307cea
MK		 717\r
718/**\r
719 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
720 RAPL Domain.".\r
721\r
722 @param ECX MSR_XEON_D_DRAM_PERF_STATUS (0x0000061B)\r
723 @param EAX Lower 32-bits of MSR value.\r
724 @param EDX Upper 32-bits of MSR value.\r
725\r
726 <b>Example usage</b>\r
727 @code\r
728 UINT64 Msr;\r
729\r
730 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS);\r
731 @endcode\r
b6ae7578 732 @note MSR_XEON_D_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
54307cea
MK		 733**/\r
734#define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B\r
735\r
736\r
737/**\r
738 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
739\r
740 @param ECX MSR_XEON_D_DRAM_POWER_INFO (0x0000061C)\r
741 @param EAX Lower 32-bits of MSR value.\r
742 @param EDX Upper 32-bits of MSR value.\r
743\r
744 <b>Example usage</b>\r
745 @code\r
746 UINT64 Msr;\r
747\r
748 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO);\r
749 AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr);\r
750 @endcode\r
b6ae7578 751 @note MSR_XEON_D_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
54307cea
MK		 752**/\r
753#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C\r
754\r
755\r
0f16be6d
HW		 756/**\r
757 Package. Reserved (R/O) Reads return 0.\r
758\r
759 @param ECX MSR_XEON_D_PP0_ENERGY_STATUS (0x00000639)\r
760 @param EAX Lower 32-bits of MSR value.\r
761 @param EDX Upper 32-bits of MSR value.\r
762\r
763 <b>Example usage</b>\r
764 @code\r
765 UINT64 Msr;\r
766\r
767 Msr = AsmReadMsr64 (MSR_XEON_D_PP0_ENERGY_STATUS);\r
768 @endcode\r
769 @note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
770**/\r
771#define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639\r
772\r
773\r
54307cea
MK		 774/**\r
775 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
776 refers to processor core frequency).\r
777\r
778 @param ECX MSR_XEON_D_CORE_PERF_LIMIT_REASONS (0x00000690)\r
779 @param EAX Lower 32-bits of MSR value.\r
780 Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.\r
781 @param EDX Upper 32-bits of MSR value.\r
782 Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.\r
783\r
784 <b>Example usage</b>\r
785 @code\r
786 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
787\r
788 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS);\r
789 AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
790 @endcode\r
b6ae7578 791 @note MSR_XEON_D_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
54307cea
MK		 792**/\r
793#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690\r
794\r
795/**\r
796 MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS\r
797**/\r
798typedef union {\r
799 ///\r
800 /// Individual bit fields\r
801 ///\r
802 struct {\r
803 ///\r
804 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r
805 /// reduced below the operating system request due to assertion of\r
806 /// external PROCHOT.\r
807 ///\r
808 UINT32 PROCHOT_Status:1;\r
809 ///\r
810 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
811 /// operating system request due to a thermal event.\r
812 ///\r
813 UINT32 ThermalStatus:1;\r
814 ///\r
815 /// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r
816 /// reduced below the operating system request due to PBM limit.\r
817 ///\r
818 UINT32 PowerBudgetManagementStatus:1;\r
819 ///\r
820 /// [Bit 3] Platform Configuration Services Status (R0) When set,\r
821 /// frequency is reduced below the operating system request due to PCS\r
822 /// limit.\r
823 ///\r
824 UINT32 PlatformConfigurationServicesStatus:1;\r
825 UINT32 Reserved1:1;\r
826 ///\r
827 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
828 /// When set, frequency is reduced below the operating system request\r
829 /// because the processor has detected that utilization is low.\r
830 ///\r
831 UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
832 ///\r
833 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
834 /// below the operating system request due to a thermal alert from the\r
835 /// Voltage Regulator.\r
836 ///\r
837 UINT32 VRThermAlertStatus:1;\r
838 UINT32 Reserved2:1;\r
839 ///\r
840 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
841 /// reduced below the operating system request due to electrical design\r
842 /// point constraints (e.g. maximum electrical current consumption).\r
843 ///\r
844 UINT32 ElectricalDesignPointStatus:1;\r
845 UINT32 Reserved3:1;\r
846 ///\r
847 /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r
848 /// below the operating system request due to Multi-Core Turbo limits.\r
849 ///\r
850 UINT32 MultiCoreTurboStatus:1;\r
851 UINT32 Reserved4:2;\r
852 ///\r
853 /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r
854 /// below max non-turbo P1.\r
855 ///\r
856 UINT32 FrequencyP1Status:1;\r
857 ///\r
858 /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r
859 /// set, frequency is reduced below max n-core turbo frequency.\r
860 ///\r
861 UINT32 TurboFrequencyLimitingStatus:1;\r
862 ///\r
863 /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r
864 /// reduced below the operating system request.\r
865 ///\r
866 UINT32 FrequencyLimitingStatus:1;\r
867 ///\r
868 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
869 /// has asserted since the log bit was last cleared. This log bit will\r
870 /// remain set until cleared by software writing 0.\r
871 ///\r
872 UINT32 PROCHOT_Log:1;\r
873 ///\r
874 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
875 /// has asserted since the log bit was last cleared. This log bit will\r
876 /// remain set until cleared by software writing 0.\r
877 ///\r
878 UINT32 ThermalLog:1;\r
879 ///\r
880 /// [Bit 18] Power Budget Management Log When set, indicates that the PBM\r
881 /// Status bit has asserted since the log bit was last cleared. This log\r
882 /// bit will remain set until cleared by software writing 0.\r
883 ///\r
884 UINT32 PowerBudgetManagementLog:1;\r
885 ///\r
886 /// [Bit 19] Platform Configuration Services Log When set, indicates that\r
887 /// the PCS Status bit has asserted since the log bit was last cleared.\r
888 /// This log bit will remain set until cleared by software writing 0.\r
889 ///\r
890 UINT32 PlatformConfigurationServicesLog:1;\r
891 UINT32 Reserved5:1;\r
892 ///\r
893 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
894 /// indicates that the AUBFC Status bit has asserted since the log bit was\r
895 /// last cleared. This log bit will remain set until cleared by software\r
896 /// writing 0.\r
897 ///\r
898 UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
899 ///\r
900 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
901 /// Alert Status bit has asserted since the log bit was last cleared. This\r
902 /// log bit will remain set until cleared by software writing 0.\r
903 ///\r
904 UINT32 VRThermAlertLog:1;\r
905 UINT32 Reserved6:1;\r
906 ///\r
907 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
908 /// Status bit has asserted since the log bit was last cleared. This log\r
909 /// bit will remain set until cleared by software writing 0.\r
910 ///\r
911 UINT32 ElectricalDesignPointLog:1;\r
912 UINT32 Reserved7:1;\r
913 ///\r
914 /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core\r
915 /// Turbo Status bit has asserted since the log bit was last cleared. This\r
916 /// log bit will remain set until cleared by software writing 0.\r
917 ///\r
918 UINT32 MultiCoreTurboLog:1;\r
919 UINT32 Reserved8:2;\r
920 ///\r
921 /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r
922 /// Frequency P1 Status bit has asserted since the log bit was last\r
923 /// cleared. This log bit will remain set until cleared by software\r
924 /// writing 0.\r
925 ///\r
926 UINT32 CoreFrequencyP1Log:1;\r
927 ///\r
928 /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r
929 /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r
930 /// has asserted since the log bit was last cleared. This log bit will\r
931 /// remain set until cleared by software writing 0.\r
932 ///\r
933 UINT32 TurboFrequencyLimitingLog:1;\r
934 ///\r
935 /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r
936 /// Frequency Limiting Status bit has asserted since the log bit was last\r
937 /// cleared. This log bit will remain set until cleared by software\r
938 /// writing 0.\r
939 ///\r
940 UINT32 CoreFrequencyLimitingLog:1;\r
941 UINT32 Reserved9:32;\r
942 } Bits;\r
943 ///\r
944 /// All bit fields as a 32-bit value\r
945 ///\r
946 UINT32 Uint32;\r
947 ///\r
948 /// All bit fields as a 64-bit value\r
949 ///\r
950 UINT64 Uint64;\r
951} MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER;\r
952\r
953\r
954/**\r
955 THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,\r
0f16be6d 956 ECX=0):EBX.RDT-M[bit 12] = 1.\r
54307cea
MK		 957\r
958 @param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D)\r
959 @param EAX Lower 32-bits of MSR value.\r
960 Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.\r
961 @param EDX Upper 32-bits of MSR value.\r
962 Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.\r
963\r
964 <b>Example usage</b>\r
965 @code\r
966 MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Msr;\r
967\r
968 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL);\r
969 AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64);\r
970 @endcode\r
b6ae7578 971 @note MSR_XEON_D_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
54307cea
MK		 972**/\r
973#define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D\r
974\r
975/**\r
976 MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL\r
977**/\r
978typedef union {\r
979 ///\r
980 /// Individual bit fields\r
981 ///\r
982 struct {\r
983 ///\r
984 /// [Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3\r
985 /// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03:\r
986 /// Local memory bandwidth monitoring All other encoding reserved.\r
987 ///\r
988 UINT32 EventID:8;\r
989 UINT32 Reserved1:24;\r
990 ///\r
991 /// [Bits 41:32] RMID (RW).\r
992 ///\r
993 UINT32 RMID:10;\r
994 UINT32 Reserved2:22;\r
995 } Bits;\r
996 ///\r
997 /// All bit fields as a 64-bit value\r
998 ///\r
999 UINT64 Uint64;\r
1000} MSR_XEON_D_IA32_QM_EVTSEL_REGISTER;\r
1001\r
1002\r
1003/**\r
1004 THREAD. Resource Association Register (R/W).\r
1005\r
1006 @param ECX MSR_XEON_D_IA32_PQR_ASSOC (0x00000C8F)\r
1007 @param EAX Lower 32-bits of MSR value.\r
1008 Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.\r
1009 @param EDX Upper 32-bits of MSR value.\r
1010 Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.\r
1011\r
1012 <b>Example usage</b>\r
1013 @code\r
1014 MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Msr;\r
1015\r
1016 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC);\r
1017 AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64);\r
1018 @endcode\r
b6ae7578 1019 @note MSR_XEON_D_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
54307cea
MK		 1020**/\r
1021#define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F\r
1022\r
1023/**\r
1024 MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC\r
1025**/\r
1026typedef union {\r
1027 ///\r
1028 /// Individual bit fields\r
1029 ///\r
1030 struct {\r
1031 ///\r
1032 /// [Bits 9:0] RMID.\r
1033 ///\r
1034 UINT32 RMID:10;\r
1035 UINT32 Reserved1:22;\r
1036 ///\r
1037 /// [Bits 51:32] COS (R/W).\r
1038 ///\r
1039 UINT32 COS:20;\r
1040 UINT32 Reserved2:12;\r
1041 } Bits;\r
1042 ///\r
1043 /// All bit fields as a 64-bit value\r
1044 ///\r
1045 UINT64 Uint64;\r
1046} MSR_XEON_D_IA32_PQR_ASSOC_REGISTER;\r
1047\r
1048\r
1049/**\r
1050 Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,\r
1051 ECX=1):EDX.COS_MAX[15:0] >= n.\r
1052\r
1053 @param ECX MSR_XEON_D_IA32_L3_QOS_MASK_n\r
1054 @param EAX Lower 32-bits of MSR value.\r
1055 Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.\r
1056 @param EDX Upper 32-bits of MSR value.\r
1057 Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.\r
1058\r
1059 <b>Example usage</b>\r
1060 @code\r
1061 MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;\r
1062\r
1063 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);\r
1064 AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);\r
1065 @endcode\r
b6ae7578
JF		 1066 @note MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM.\r
1067 MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM.\r
1068 MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM.\r
1069 MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM.\r
1070 MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM.\r
1071 MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM.\r
1072 MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM.\r
1073 MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM.\r
1074 MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM.\r
1075 MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM.\r
1076 MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM.\r
1077 MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM.\r
1078 MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM.\r
1079 MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM.\r
1080 MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM.\r
1081 MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.\r
54307cea
MK		 1082 @{\r
1083**/\r
1084#define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90\r
1085#define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91\r
1086#define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92\r
1087#define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93\r
1088#define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94\r
1089#define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95\r
1090#define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96\r
1091#define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97\r
1092#define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98\r
1093#define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99\r
1094#define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A\r
1095#define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B\r
1096#define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C\r
1097#define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D\r
1098#define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E\r
1099#define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F\r
1100/// @}\r
1101\r
1102/**\r
1103 MSR information returned for MSR indexes #MSR_XEON_D_IA32_L3_QOS_MASK_0\r
1104 to #MSR_XEON_D_IA32_L3_QOS_MASK_15.\r
1105**/\r
1106typedef union {\r
1107 ///\r
1108 /// Individual bit fields\r
1109 ///\r
1110 struct {\r
1111 ///\r
1112 /// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement.\r
1113 ///\r
1114 UINT32 CBM:20;\r
1115 UINT32 Reserved2:12;\r
1116 UINT32 Reserved3:32;\r
1117 } Bits;\r
1118 ///\r
1119 /// All bit fields as a 32-bit value\r
1120 ///\r
1121 UINT32 Uint32;\r
1122 ///\r
1123 /// All bit fields as a 64-bit value\r
1124 ///\r
1125 UINT64 Uint64;\r
1126} MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER;\r
1127\r
1128\r
1129/**\r
1130 Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
1131 RW if MSR_PLATFORM_INFO.[28] = 1.\r
1132\r
1133 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT3 (0x000001AC)\r
1134 @param EAX Lower 32-bits of MSR value.\r
1135 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.\r
1136 @param EDX Upper 32-bits of MSR value.\r
1137 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.\r
1138\r
1139 <b>Example usage</b>\r
1140 @code\r
1141 MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Msr;\r
1142\r
1143 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3);\r
1144 @endcode\r
b6ae7578 1145 @note MSR_XEON_D_TURBO_RATIO_LIMIT3 is defined as MSR_TURBO_RATIO_LIMIT3 in SDM.\r
54307cea
MK		 1146**/\r
1147#define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC\r
1148\r
1149/**\r
1150 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3\r
1151**/\r
1152typedef union {\r
1153 ///\r
1154 /// Individual bit fields\r
1155 ///\r
1156 struct {\r
1157 UINT32 Reserved1:32;\r
1158 UINT32 Reserved2:31;\r
1159 ///\r
1160 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
1161 /// the processor uses override configuration specified in\r
1162 /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r
1163 /// uses factory-set configuration (Default).\r
1164 ///\r
1165 UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
1166 } Bits;\r
1167 ///\r
1168 /// All bit fields as a 64-bit value\r
1169 ///\r
1170 UINT64 Uint64;\r
1171} MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER;\r
1172\r
1173\r
54307cea
MK		 1174/**\r
1175 Package. Cache Allocation Technology Configuration (R/W).\r
1176\r
1177 @param ECX MSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81)\r
1178 @param EAX Lower 32-bits of MSR value.\r
1179 Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.\r
1180 @param EDX Upper 32-bits of MSR value.\r
1181 Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.\r
1182\r
1183 <b>Example usage</b>\r
1184 @code\r
1185 MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Msr;\r
1186\r
1187 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG);\r
1188 AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64);\r
1189 @endcode\r
b6ae7578 1190 @note MSR_XEON_D_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.\r
54307cea
MK		 1191**/\r
1192#define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81\r
1193\r
1194/**\r
1195 MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG\r
1196**/\r
1197typedef union {\r
1198 ///\r
1199 /// Individual bit fields\r
1200 ///\r
1201 struct {\r
1202 ///\r
1203 /// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology.\r
1204 ///\r
1205 UINT32 CAT:1;\r
1206 UINT32 Reserved1:31;\r
1207 UINT32 Reserved2:32;\r
1208 } Bits;\r
1209 ///\r
1210 /// All bit fields as a 32-bit value\r
1211 ///\r
1212 UINT32 Uint32;\r
1213 ///\r
1214 /// All bit fields as a 64-bit value\r
1215 ///\r
1216 UINT64 Uint64;\r
1217} MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER;\r
1218\r
1219#endif\r
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