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ebb74e4a MK |
1 | /** @file\r |
2 | MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
9 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
10 | This program and the accompanying materials\r | |
11 | are licensed and made available under the terms and conditions of the BSD License\r | |
12 | which accompanies this distribution. The full text of the license may be found at\r | |
13 | http://opensource.org/licenses/bsd-license.php\r | |
14 | \r | |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | \r | |
18 | @par Specification Reference:\r | |
19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
0f16be6d | 20 | September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.8.\r |
ebb74e4a MK |
21 | \r |
22 | **/\r | |
23 | \r | |
24 | #ifndef __XEON_E7_MSR_H__\r | |
25 | #define __XEON_E7_MSR_H__\r | |
26 | \r | |
27 | #include <Register/ArchitecturalMsr.h>\r | |
28 | \r | |
0f16be6d HW |
29 | /**\r |
30 | Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r | |
31 | handler to handle unsuccessful read of this MSR.\r | |
32 | \r | |
33 | @param ECX MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)\r | |
34 | @param EAX Lower 32-bits of MSR value.\r | |
35 | Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r | |
36 | @param EDX Upper 32-bits of MSR value.\r | |
37 | Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r | |
38 | \r | |
39 | <b>Example usage</b>\r | |
40 | @code\r | |
41 | MSR_XEON_E7_FEATURE_CONFIG_REGISTER Msr;\r | |
42 | \r | |
43 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);\r | |
44 | AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);\r | |
45 | @endcode\r | |
46 | @note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r | |
47 | **/\r | |
48 | #define MSR_XEON_E7_FEATURE_CONFIG 0x0000013C\r | |
49 | \r | |
50 | /**\r | |
51 | MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG\r | |
52 | **/\r | |
53 | typedef union {\r | |
54 | ///\r | |
55 | /// Individual bit fields\r | |
56 | ///\r | |
57 | struct {\r | |
58 | ///\r | |
59 | /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r | |
60 | /// MSR, the configuration of AES instruction set availability is as\r | |
61 | /// follows: 11b: AES instructions are not available until next RESET.\r | |
62 | /// otherwise, AES instructions are available. Note, AES instruction set\r | |
63 | /// is not available if read is unsuccessful. If the configuration is not\r | |
64 | /// 01b, AES instruction can be mis-configured if a privileged agent\r | |
65 | /// unintentionally writes 11b.\r | |
66 | ///\r | |
67 | UINT32 AESConfiguration:2;\r | |
68 | UINT32 Reserved1:30;\r | |
69 | UINT32 Reserved2:32;\r | |
70 | } Bits;\r | |
71 | ///\r | |
72 | /// All bit fields as a 32-bit value\r | |
73 | ///\r | |
74 | UINT32 Uint32;\r | |
75 | ///\r | |
76 | /// All bit fields as a 64-bit value\r | |
77 | ///\r | |
78 | UINT64 Uint64;\r | |
79 | } MSR_XEON_E7_FEATURE_CONFIG_REGISTER;\r | |
80 | \r | |
81 | \r | |
82 | /**\r | |
83 | Thread. Offcore Response Event Select Register (R/W).\r | |
84 | \r | |
85 | @param ECX MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)\r | |
86 | @param EAX Lower 32-bits of MSR value.\r | |
87 | @param EDX Upper 32-bits of MSR value.\r | |
88 | \r | |
89 | <b>Example usage</b>\r | |
90 | @code\r | |
91 | UINT64 Msr;\r | |
92 | \r | |
93 | Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);\r | |
94 | AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);\r | |
95 | @endcode\r | |
96 | @note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r | |
97 | **/\r | |
98 | #define MSR_XEON_E7_OFFCORE_RSP_1 0x000001A7\r | |
99 | \r | |
100 | \r | |
ebb74e4a MK |
101 | /**\r |
102 | Package. Reserved Attempt to read/write will cause #UD.\r | |
103 | \r | |
104 | @param ECX MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)\r | |
105 | @param EAX Lower 32-bits of MSR value.\r | |
106 | @param EDX Upper 32-bits of MSR value.\r | |
107 | \r | |
108 | <b>Example usage</b>\r | |
109 | @code\r | |
110 | UINT64 Msr;\r | |
111 | \r | |
112 | Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);\r | |
113 | AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);\r | |
114 | @endcode\r | |
97ea5b7f | 115 | @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r |
ebb74e4a MK |
116 | **/\r |
117 | #define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD\r | |
118 | \r | |
119 | \r | |
120 | /**\r | |
121 | Package. Uncore C-box 8 perfmon local box control MSR.\r | |
122 | \r | |
123 | @param ECX MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)\r | |
124 | @param EAX Lower 32-bits of MSR value.\r | |
125 | @param EDX Upper 32-bits of MSR value.\r | |
126 | \r | |
127 | <b>Example usage</b>\r | |
128 | @code\r | |
129 | UINT64 Msr;\r | |
130 | \r | |
131 | Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);\r | |
132 | AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);\r | |
133 | @endcode\r | |
97ea5b7f | 134 | @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.\r |
ebb74e4a MK |
135 | **/\r |
136 | #define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40\r | |
137 | \r | |
138 | \r | |
139 | /**\r | |
140 | Package. Uncore C-box 8 perfmon local box status MSR.\r | |
141 | \r | |
142 | @param ECX MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)\r | |
143 | @param EAX Lower 32-bits of MSR value.\r | |
144 | @param EDX Upper 32-bits of MSR value.\r | |
145 | \r | |
146 | <b>Example usage</b>\r | |
147 | @code\r | |
148 | UINT64 Msr;\r | |
149 | \r | |
150 | Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);\r | |
151 | AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);\r | |
152 | @endcode\r | |
97ea5b7f | 153 | @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r |
ebb74e4a MK |
154 | **/\r |
155 | #define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41\r | |
156 | \r | |
157 | \r | |
158 | /**\r | |
159 | Package. Uncore C-box 8 perfmon local box overflow control MSR.\r | |
160 | \r | |
161 | @param ECX MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)\r | |
162 | @param EAX Lower 32-bits of MSR value.\r | |
163 | @param EDX Upper 32-bits of MSR value.\r | |
164 | \r | |
165 | <b>Example usage</b>\r | |
166 | @code\r | |
167 | UINT64 Msr;\r | |
168 | \r | |
169 | Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);\r | |
170 | AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);\r | |
171 | @endcode\r | |
97ea5b7f | 172 | @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.\r |
ebb74e4a MK |
173 | **/\r |
174 | #define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42\r | |
175 | \r | |
176 | \r | |
177 | /**\r | |
178 | Package. Uncore C-box 8 perfmon event select MSR.\r | |
179 | \r | |
180 | @param ECX MSR_XEON_E7_C8_PMON_EVNT_SELn\r | |
181 | @param EAX Lower 32-bits of MSR value.\r | |
182 | @param EDX Upper 32-bits of MSR value.\r | |
183 | \r | |
184 | <b>Example usage</b>\r | |
185 | @code\r | |
186 | UINT64 Msr;\r | |
187 | \r | |
188 | Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);\r | |
189 | AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);\r | |
190 | @endcode\r | |
97ea5b7f JF |
191 | @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.\r |
192 | MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.\r | |
193 | MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.\r | |
194 | MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.\r | |
195 | MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.\r | |
196 | MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.\r | |
ebb74e4a MK |
197 | @{\r |
198 | **/\r | |
199 | #define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50\r | |
200 | #define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52\r | |
201 | #define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54\r | |
202 | #define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56\r | |
203 | #define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58\r | |
204 | #define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A\r | |
205 | /// @}\r | |
206 | \r | |
207 | \r | |
208 | /**\r | |
209 | Package. Uncore C-box 8 perfmon counter MSR.\r | |
210 | \r | |
211 | @param ECX MSR_XEON_E7_C8_PMON_CTRn\r | |
212 | @param EAX Lower 32-bits of MSR value.\r | |
213 | @param EDX Upper 32-bits of MSR value.\r | |
214 | \r | |
215 | <b>Example usage</b>\r | |
216 | @code\r | |
217 | UINT64 Msr;\r | |
218 | \r | |
219 | Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);\r | |
220 | AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);\r | |
221 | @endcode\r | |
97ea5b7f JF |
222 | @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r |
223 | MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r | |
224 | MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r | |
225 | MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r | |
226 | MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.\r | |
227 | MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.\r | |
ebb74e4a MK |
228 | @{\r |
229 | **/\r | |
230 | #define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51\r | |
231 | #define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53\r | |
232 | #define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55\r | |
233 | #define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57\r | |
234 | #define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59\r | |
235 | #define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B\r | |
236 | /// @}\r | |
237 | \r | |
238 | \r | |
239 | /**\r | |
240 | Package. Uncore C-box 9 perfmon local box control MSR.\r | |
241 | \r | |
242 | @param ECX MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)\r | |
243 | @param EAX Lower 32-bits of MSR value.\r | |
244 | @param EDX Upper 32-bits of MSR value.\r | |
245 | \r | |
246 | <b>Example usage</b>\r | |
247 | @code\r | |
248 | UINT64 Msr;\r | |
249 | \r | |
250 | Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);\r | |
251 | AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);\r | |
252 | @endcode\r | |
97ea5b7f | 253 | @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.\r |
ebb74e4a MK |
254 | **/\r |
255 | #define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0\r | |
256 | \r | |
257 | \r | |
258 | /**\r | |
259 | Package. Uncore C-box 9 perfmon local box status MSR.\r | |
260 | \r | |
261 | @param ECX MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)\r | |
262 | @param EAX Lower 32-bits of MSR value.\r | |
263 | @param EDX Upper 32-bits of MSR value.\r | |
264 | \r | |
265 | <b>Example usage</b>\r | |
266 | @code\r | |
267 | UINT64 Msr;\r | |
268 | \r | |
269 | Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);\r | |
270 | AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);\r | |
271 | @endcode\r | |
97ea5b7f | 272 | @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r |
ebb74e4a MK |
273 | **/\r |
274 | #define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1\r | |
275 | \r | |
276 | \r | |
277 | /**\r | |
278 | Package. Uncore C-box 9 perfmon local box overflow control MSR.\r | |
279 | \r | |
280 | @param ECX MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)\r | |
281 | @param EAX Lower 32-bits of MSR value.\r | |
282 | @param EDX Upper 32-bits of MSR value.\r | |
283 | \r | |
284 | <b>Example usage</b>\r | |
285 | @code\r | |
286 | UINT64 Msr;\r | |
287 | \r | |
288 | Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);\r | |
289 | AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);\r | |
290 | @endcode\r | |
97ea5b7f | 291 | @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.\r |
ebb74e4a MK |
292 | **/\r |
293 | #define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2\r | |
294 | \r | |
295 | \r | |
296 | /**\r | |
297 | Package. Uncore C-box 9 perfmon event select MSR.\r | |
298 | \r | |
299 | @param ECX MSR_XEON_E7_C9_PMON_EVNT_SELn\r | |
300 | @param EAX Lower 32-bits of MSR value.\r | |
301 | @param EDX Upper 32-bits of MSR value.\r | |
302 | \r | |
303 | <b>Example usage</b>\r | |
304 | @code\r | |
305 | UINT64 Msr;\r | |
306 | \r | |
307 | Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);\r | |
308 | AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);\r | |
309 | @endcode\r | |
97ea5b7f JF |
310 | @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.\r |
311 | MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.\r | |
312 | MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.\r | |
313 | MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.\r | |
314 | MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.\r | |
315 | MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.\r | |
ebb74e4a MK |
316 | @{\r |
317 | **/\r | |
318 | #define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0\r | |
319 | #define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2\r | |
320 | #define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4\r | |
321 | #define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6\r | |
322 | #define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8\r | |
323 | #define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA\r | |
324 | /// @}\r | |
325 | \r | |
326 | \r | |
327 | /**\r | |
328 | Package. Uncore C-box 9 perfmon counter MSR.\r | |
329 | \r | |
330 | @param ECX MSR_XEON_E7_C9_PMON_CTRn\r | |
331 | @param EAX Lower 32-bits of MSR value.\r | |
332 | @param EDX Upper 32-bits of MSR value.\r | |
333 | \r | |
334 | <b>Example usage</b>\r | |
335 | @code\r | |
336 | UINT64 Msr;\r | |
337 | \r | |
338 | Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);\r | |
339 | AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);\r | |
340 | @endcode\r | |
97ea5b7f JF |
341 | @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r |
342 | MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r | |
343 | MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r | |
344 | MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r | |
345 | MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.\r | |
346 | MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.\r | |
ebb74e4a MK |
347 | @{\r |
348 | **/\r | |
349 | #define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1\r | |
350 | #define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3\r | |
351 | #define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5\r | |
352 | #define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7\r | |
353 | #define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9\r | |
354 | #define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB\r | |
355 | /// @}\r | |
356 | \r | |
357 | #endif\r |