projects / mirror_edk2.git / blame
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| ebb74e4a MK |
1 | /** @file\r |
| 2 | MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.\r | |
| 3 | \r | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| 9 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
| 10 | This program and the accompanying materials\r | |
| 11 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 12 | which accompanies this distribution. The full text of the license may be found at\r | |
| 13 | http://opensource.org/licenses/bsd-license.php\r | |
| 14 | \r | |
| 15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 17 | \r | |
| 18 | @par Specification Reference:\r | |
| 19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
| 20 | December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-7.\r | |
| 21 | \r | |
| 22 | **/\r | |
| 23 | \r | |
| 24 | #ifndef __XEON_E7_MSR_H__\r | |
| 25 | #define __XEON_E7_MSR_H__\r | |
| 26 | \r | |
| 27 | #include <Register/ArchitecturalMsr.h>\r | |
| 28 | \r | |
| 29 | /**\r | |
| 30 | Package. Reserved Attempt to read/write will cause #UD.\r | |
| 31 | \r | |
| 32 | @param ECX MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)\r | |
| 33 | @param EAX Lower 32-bits of MSR value.\r | |
| 34 | @param EDX Upper 32-bits of MSR value.\r | |
| 35 | \r | |
| 36 | <b>Example usage</b>\r | |
| 37 | @code\r | |
| 38 | UINT64 Msr;\r | |
| 39 | \r | |
| 40 | Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);\r | |
| 41 | AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);\r | |
| 42 | @endcode\r | |
| 43 | **/\r | |
| 44 | #define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD\r | |
| 45 | \r | |
| 46 | \r | |
| 47 | /**\r | |
| 48 | Package. Uncore C-box 8 perfmon local box control MSR.\r | |
| 49 | \r | |
| 50 | @param ECX MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)\r | |
| 51 | @param EAX Lower 32-bits of MSR value.\r | |
| 52 | @param EDX Upper 32-bits of MSR value.\r | |
| 53 | \r | |
| 54 | <b>Example usage</b>\r | |
| 55 | @code\r | |
| 56 | UINT64 Msr;\r | |
| 57 | \r | |
| 58 | Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);\r | |
| 59 | AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);\r | |
| 60 | @endcode\r | |
| 61 | **/\r | |
| 62 | #define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40\r | |
| 63 | \r | |
| 64 | \r | |
| 65 | /**\r | |
| 66 | Package. Uncore C-box 8 perfmon local box status MSR.\r | |
| 67 | \r | |
| 68 | @param ECX MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)\r | |
| 69 | @param EAX Lower 32-bits of MSR value.\r | |
| 70 | @param EDX Upper 32-bits of MSR value.\r | |
| 71 | \r | |
| 72 | <b>Example usage</b>\r | |
| 73 | @code\r | |
| 74 | UINT64 Msr;\r | |
| 75 | \r | |
| 76 | Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);\r | |
| 77 | AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);\r | |
| 78 | @endcode\r | |
| 79 | **/\r | |
| 80 | #define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41\r | |
| 81 | \r | |
| 82 | \r | |
| 83 | /**\r | |
| 84 | Package. Uncore C-box 8 perfmon local box overflow control MSR.\r | |
| 85 | \r | |
| 86 | @param ECX MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)\r | |
| 87 | @param EAX Lower 32-bits of MSR value.\r | |
| 88 | @param EDX Upper 32-bits of MSR value.\r | |
| 89 | \r | |
| 90 | <b>Example usage</b>\r | |
| 91 | @code\r | |
| 92 | UINT64 Msr;\r | |
| 93 | \r | |
| 94 | Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);\r | |
| 95 | AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);\r | |
| 96 | @endcode\r | |
| 97 | **/\r | |
| 98 | #define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42\r | |
| 99 | \r | |
| 100 | \r | |
| 101 | /**\r | |
| 102 | Package. Uncore C-box 8 perfmon event select MSR.\r | |
| 103 | \r | |
| 104 | @param ECX MSR_XEON_E7_C8_PMON_EVNT_SELn\r | |
| 105 | @param EAX Lower 32-bits of MSR value.\r | |
| 106 | @param EDX Upper 32-bits of MSR value.\r | |
| 107 | \r | |
| 108 | <b>Example usage</b>\r | |
| 109 | @code\r | |
| 110 | UINT64 Msr;\r | |
| 111 | \r | |
| 112 | Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);\r | |
| 113 | AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);\r | |
| 114 | @endcode\r | |
| 115 | @{\r | |
| 116 | **/\r | |
| 117 | #define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50\r | |
| 118 | #define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52\r | |
| 119 | #define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54\r | |
| 120 | #define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56\r | |
| 121 | #define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58\r | |
| 122 | #define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A\r | |
| 123 | /// @}\r | |
| 124 | \r | |
| 125 | \r | |
| 126 | /**\r | |
| 127 | Package. Uncore C-box 8 perfmon counter MSR.\r | |
| 128 | \r | |
| 129 | @param ECX MSR_XEON_E7_C8_PMON_CTRn\r | |
| 130 | @param EAX Lower 32-bits of MSR value.\r | |
| 131 | @param EDX Upper 32-bits of MSR value.\r | |
| 132 | \r | |
| 133 | <b>Example usage</b>\r | |
| 134 | @code\r | |
| 135 | UINT64 Msr;\r | |
| 136 | \r | |
| 137 | Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);\r | |
| 138 | AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);\r | |
| 139 | @endcode\r | |
| 140 | @{\r | |
| 141 | **/\r | |
| 142 | #define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51\r | |
| 143 | #define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53\r | |
| 144 | #define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55\r | |
| 145 | #define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57\r | |
| 146 | #define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59\r | |
| 147 | #define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B\r | |
| 148 | /// @}\r | |
| 149 | \r | |
| 150 | \r | |
| 151 | /**\r | |
| 152 | Package. Uncore C-box 9 perfmon local box control MSR.\r | |
| 153 | \r | |
| 154 | @param ECX MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)\r | |
| 155 | @param EAX Lower 32-bits of MSR value.\r | |
| 156 | @param EDX Upper 32-bits of MSR value.\r | |
| 157 | \r | |
| 158 | <b>Example usage</b>\r | |
| 159 | @code\r | |
| 160 | UINT64 Msr;\r | |
| 161 | \r | |
| 162 | Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);\r | |
| 163 | AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);\r | |
| 164 | @endcode\r | |
| 165 | **/\r | |
| 166 | #define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0\r | |
| 167 | \r | |
| 168 | \r | |
| 169 | /**\r | |
| 170 | Package. Uncore C-box 9 perfmon local box status MSR.\r | |
| 171 | \r | |
| 172 | @param ECX MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)\r | |
| 173 | @param EAX Lower 32-bits of MSR value.\r | |
| 174 | @param EDX Upper 32-bits of MSR value.\r | |
| 175 | \r | |
| 176 | <b>Example usage</b>\r | |
| 177 | @code\r | |
| 178 | UINT64 Msr;\r | |
| 179 | \r | |
| 180 | Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);\r | |
| 181 | AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);\r | |
| 182 | @endcode\r | |
| 183 | **/\r | |
| 184 | #define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1\r | |
| 185 | \r | |
| 186 | \r | |
| 187 | /**\r | |
| 188 | Package. Uncore C-box 9 perfmon local box overflow control MSR.\r | |
| 189 | \r | |
| 190 | @param ECX MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)\r | |
| 191 | @param EAX Lower 32-bits of MSR value.\r | |
| 192 | @param EDX Upper 32-bits of MSR value.\r | |
| 193 | \r | |
| 194 | <b>Example usage</b>\r | |
| 195 | @code\r | |
| 196 | UINT64 Msr;\r | |
| 197 | \r | |
| 198 | Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);\r | |
| 199 | AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);\r | |
| 200 | @endcode\r | |
| 201 | **/\r | |
| 202 | #define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2\r | |
| 203 | \r | |
| 204 | \r | |
| 205 | /**\r | |
| 206 | Package. Uncore C-box 9 perfmon event select MSR.\r | |
| 207 | \r | |
| 208 | @param ECX MSR_XEON_E7_C9_PMON_EVNT_SELn\r | |
| 209 | @param EAX Lower 32-bits of MSR value.\r | |
| 210 | @param EDX Upper 32-bits of MSR value.\r | |
| 211 | \r | |
| 212 | <b>Example usage</b>\r | |
| 213 | @code\r | |
| 214 | UINT64 Msr;\r | |
| 215 | \r | |
| 216 | Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);\r | |
| 217 | AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);\r | |
| 218 | @endcode\r | |
| 219 | @{\r | |
| 220 | **/\r | |
| 221 | #define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0\r | |
| 222 | #define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2\r | |
| 223 | #define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4\r | |
| 224 | #define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6\r | |
| 225 | #define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8\r | |
| 226 | #define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA\r | |
| 227 | /// @}\r | |
| 228 | \r | |
| 229 | \r | |
| 230 | /**\r | |
| 231 | Package. Uncore C-box 9 perfmon counter MSR.\r | |
| 232 | \r | |
| 233 | @param ECX MSR_XEON_E7_C9_PMON_CTRn\r | |
| 234 | @param EAX Lower 32-bits of MSR value.\r | |
| 235 | @param EDX Upper 32-bits of MSR value.\r | |
| 236 | \r | |
| 237 | <b>Example usage</b>\r | |
| 238 | @code\r | |
| 239 | UINT64 Msr;\r | |
| 240 | \r | |
| 241 | Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);\r | |
| 242 | AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);\r | |
| 243 | @endcode\r | |
| 244 | @{\r | |
| 245 | **/\r | |
| 246 | #define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1\r | |
| 247 | #define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3\r | |
| 248 | #define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5\r | |
| 249 | #define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7\r | |
| 250 | #define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9\r | |
| 251 | #define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB\r | |
| 252 | /// @}\r | |
| 253 | \r | |
| 254 | #endif\r |