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git.proxmox.com Git - mirror_edk2.git/blob - UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
2 MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-7.
24 #ifndef __XEON_E7_MSR_H__
25 #define __XEON_E7_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Package. Reserved Attempt to read/write will cause #UD.
32 @param ECX MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)
33 @param EAX Lower 32-bits of MSR value.
34 @param EDX Upper 32-bits of MSR value.
40 Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);
41 AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);
44 #define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD
48 Package. Uncore C-box 8 perfmon local box control MSR.
50 @param ECX MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)
51 @param EAX Lower 32-bits of MSR value.
52 @param EDX Upper 32-bits of MSR value.
58 Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);
59 AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);
62 #define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40
66 Package. Uncore C-box 8 perfmon local box status MSR.
68 @param ECX MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)
69 @param EAX Lower 32-bits of MSR value.
70 @param EDX Upper 32-bits of MSR value.
76 Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);
77 AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);
80 #define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41
84 Package. Uncore C-box 8 perfmon local box overflow control MSR.
86 @param ECX MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)
87 @param EAX Lower 32-bits of MSR value.
88 @param EDX Upper 32-bits of MSR value.
94 Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);
95 AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);
98 #define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42
102 Package. Uncore C-box 8 perfmon event select MSR.
104 @param ECX MSR_XEON_E7_C8_PMON_EVNT_SELn
105 @param EAX Lower 32-bits of MSR value.
106 @param EDX Upper 32-bits of MSR value.
112 Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);
113 AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);
117 #define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50
118 #define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52
119 #define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54
120 #define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56
121 #define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58
122 #define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A
127 Package. Uncore C-box 8 perfmon counter MSR.
129 @param ECX MSR_XEON_E7_C8_PMON_CTRn
130 @param EAX Lower 32-bits of MSR value.
131 @param EDX Upper 32-bits of MSR value.
137 Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);
138 AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);
142 #define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51
143 #define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53
144 #define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55
145 #define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57
146 #define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59
147 #define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B
152 Package. Uncore C-box 9 perfmon local box control MSR.
154 @param ECX MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)
155 @param EAX Lower 32-bits of MSR value.
156 @param EDX Upper 32-bits of MSR value.
162 Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);
163 AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);
166 #define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0
170 Package. Uncore C-box 9 perfmon local box status MSR.
172 @param ECX MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)
173 @param EAX Lower 32-bits of MSR value.
174 @param EDX Upper 32-bits of MSR value.
180 Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);
181 AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);
184 #define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1
188 Package. Uncore C-box 9 perfmon local box overflow control MSR.
190 @param ECX MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)
191 @param EAX Lower 32-bits of MSR value.
192 @param EDX Upper 32-bits of MSR value.
198 Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);
199 AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);
202 #define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2
206 Package. Uncore C-box 9 perfmon event select MSR.
208 @param ECX MSR_XEON_E7_C9_PMON_EVNT_SELn
209 @param EAX Lower 32-bits of MSR value.
210 @param EDX Upper 32-bits of MSR value.
216 Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);
217 AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);
221 #define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0
222 #define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2
223 #define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4
224 #define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6
225 #define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8
226 #define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA
231 Package. Uncore C-box 9 perfmon counter MSR.
233 @param ECX MSR_XEON_E7_C9_PMON_CTRn
234 @param EAX Lower 32-bits of MSR value.
235 @param EDX Upper 32-bits of MSR value.
241 Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);
242 AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);
246 #define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1
247 #define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3
248 #define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5
249 #define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7
250 #define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9
251 #define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB