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bf73cc4b | 1 | /** @file\r |
2 | Local APIC Library.\r | |
3 | \r | |
4 | This local APIC library instance supports x2APIC capable processors\r | |
5 | which have xAPIC and x2APIC modes.\r | |
6 | \r | |
7f33d4f2 | 7 | Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>\r |
df667535 | 8 | Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.<BR>\r |
061ead7a | 9 | \r |
0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
bf73cc4b | 11 | \r |
12 | **/\r | |
13 | \r | |
01acb06c | 14 | #include <Register/Intel/Cpuid.h>\r |
061ead7a | 15 | #include <Register/Amd/Cpuid.h>\r |
01acb06c RN |
16 | #include <Register/Intel/Msr.h>\r |
17 | #include <Register/Intel/LocalApic.h>\r | |
bf73cc4b | 18 | \r |
19 | #include <Library/BaseLib.h>\r | |
20 | #include <Library/DebugLib.h>\r | |
21 | #include <Library/LocalApicLib.h>\r | |
22 | #include <Library/IoLib.h>\r | |
23 | #include <Library/TimerLib.h>\r | |
e9cd66d0 | 24 | #include <Library/PcdLib.h>\r |
df667535 | 25 | #include <Library/UefiCpuLib.h>\r |
bf73cc4b | 26 | \r |
27 | //\r | |
28 | // Library internal functions\r | |
29 | //\r | |
30 | \r | |
e9cd66d0 MK |
31 | /**\r |
32 | Determine if the CPU supports the Local APIC Base Address MSR.\r | |
33 | \r | |
34 | @retval TRUE The CPU supports the Local APIC Base Address MSR.\r | |
35 | @retval FALSE The CPU does not support the Local APIC Base Address MSR.\r | |
36 | \r | |
37 | **/\r | |
38 | BOOLEAN\r | |
39 | LocalApicBaseAddressMsrSupported (\r | |
40 | VOID\r | |
41 | )\r | |
42 | {\r | |
43 | UINT32 RegEax;\r | |
44 | UINTN FamilyId;\r | |
7367cc6c | 45 | \r |
e9cd66d0 MK |
46 | AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r |
47 | FamilyId = BitFieldRead32 (RegEax, 8, 11);\r | |
053e878b | 48 | if ((FamilyId == 0x04) || (FamilyId == 0x05)) {\r |
e9cd66d0 | 49 | //\r |
7367cc6c | 50 | // CPUs with a FamilyId of 0x04 or 0x05 do not support the\r |
e9cd66d0 MK |
51 | // Local APIC Base Address MSR\r |
52 | //\r | |
53 | return FALSE;\r | |
54 | }\r | |
053e878b | 55 | \r |
e9cd66d0 MK |
56 | return TRUE;\r |
57 | }\r | |
58 | \r | |
a66e0c7d | 59 | /**\r |
60 | Retrieve the base address of local APIC.\r | |
61 | \r | |
62 | @return The base address of local APIC.\r | |
63 | \r | |
64 | **/\r | |
65 | UINTN\r | |
66 | EFIAPI\r | |
67 | GetLocalApicBaseAddress (\r | |
68 | VOID\r | |
69 | )\r | |
70 | {\r | |
a742e186 | 71 | MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r |
e9cd66d0 MK |
72 | \r |
73 | if (!LocalApicBaseAddressMsrSupported ()) {\r | |
74 | //\r | |
75 | // If CPU does not support Local APIC Base Address MSR, then retrieve\r | |
76 | // Local APIC Base Address from PCD\r | |
77 | //\r | |
78 | return PcdGet32 (PcdCpuLocalApicBaseAddress);\r | |
79 | }\r | |
80 | \r | |
a742e186 | 81 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r |
7367cc6c | 82 | \r |
053e878b MK |
83 | return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r |
84 | (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r | |
a66e0c7d | 85 | }\r |
86 | \r | |
87 | /**\r | |
88 | Set the base address of local APIC.\r | |
89 | \r | |
90 | If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r | |
91 | \r | |
92 | @param[in] BaseAddress Local APIC base address to be set.\r | |
93 | \r | |
94 | **/\r | |
95 | VOID\r | |
96 | EFIAPI\r | |
97 | SetLocalApicBaseAddress (\r | |
053e878b | 98 | IN UINTN BaseAddress\r |
a66e0c7d | 99 | )\r |
100 | {\r | |
a742e186 | 101 | MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r |
a66e0c7d | 102 | \r |
103 | ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r | |
104 | \r | |
e9cd66d0 MK |
105 | if (!LocalApicBaseAddressMsrSupported ()) {\r |
106 | //\r | |
107 | // Ignore set request of the CPU does not support APIC Base Address MSR\r | |
108 | //\r | |
109 | return;\r | |
110 | }\r | |
111 | \r | |
a742e186 | 112 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r |
a66e0c7d | 113 | \r |
053e878b MK |
114 | ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12);\r |
115 | ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));\r | |
a66e0c7d | 116 | \r |
a742e186 | 117 | AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r |
a66e0c7d | 118 | }\r |
119 | \r | |
bf73cc4b | 120 | /**\r |
121 | Read from a local APIC register.\r | |
122 | \r | |
123 | This function reads from a local APIC register either in xAPIC or x2APIC mode.\r | |
124 | It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r | |
125 | accessed using multiple 32-bit loads or stores, so this function only performs\r | |
126 | 32-bit read.\r | |
127 | \r | |
128 | @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r | |
129 | It must be 16-byte aligned.\r | |
130 | \r | |
131 | @return 32-bit Value read from the register.\r | |
132 | **/\r | |
133 | UINT32\r | |
134 | EFIAPI\r | |
135 | ReadLocalApicReg (\r | |
136 | IN UINTN MmioOffset\r | |
137 | )\r | |
138 | {\r | |
053e878b | 139 | UINT32 MsrIndex;\r |
bf73cc4b | 140 | \r |
141 | ASSERT ((MmioOffset & 0xf) == 0);\r | |
142 | \r | |
143 | if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r | |
053e878b | 144 | return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset);\r |
bf73cc4b | 145 | } else {\r |
146 | //\r | |
147 | // DFR is not supported in x2APIC mode.\r | |
148 | //\r | |
149 | ASSERT (MmioOffset != XAPIC_ICR_DFR_OFFSET);\r | |
150 | //\r | |
151 | // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It\r | |
152 | // is not supported in this function for simplicity.\r | |
153 | //\r | |
154 | ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);\r | |
155 | \r | |
156 | MsrIndex = (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;\r | |
157 | return AsmReadMsr32 (MsrIndex);\r | |
158 | }\r | |
159 | }\r | |
160 | \r | |
161 | /**\r | |
162 | Write to a local APIC register.\r | |
163 | \r | |
164 | This function writes to a local APIC register either in xAPIC or x2APIC mode.\r | |
165 | It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r | |
166 | accessed using multiple 32-bit loads or stores, so this function only performs\r | |
167 | 32-bit write.\r | |
168 | \r | |
169 | if the register index is invalid or unsupported in current APIC mode, then ASSERT.\r | |
170 | \r | |
171 | @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r | |
172 | It must be 16-byte aligned.\r | |
173 | @param Value Value to be written to the register.\r | |
174 | **/\r | |
175 | VOID\r | |
176 | EFIAPI\r | |
177 | WriteLocalApicReg (\r | |
053e878b MK |
178 | IN UINTN MmioOffset,\r |
179 | IN UINT32 Value\r | |
bf73cc4b | 180 | )\r |
181 | {\r | |
053e878b | 182 | UINT32 MsrIndex;\r |
bf73cc4b | 183 | \r |
184 | ASSERT ((MmioOffset & 0xf) == 0);\r | |
185 | \r | |
186 | if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r | |
053e878b | 187 | MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value);\r |
bf73cc4b | 188 | } else {\r |
189 | //\r | |
190 | // DFR is not supported in x2APIC mode.\r | |
191 | //\r | |
192 | ASSERT (MmioOffset != XAPIC_ICR_DFR_OFFSET);\r | |
193 | //\r | |
194 | // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It\r | |
195 | // is not supported in this function for simplicity.\r | |
196 | //\r | |
197 | ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);\r | |
198 | ASSERT (MmioOffset != XAPIC_ICR_LOW_OFFSET);\r | |
199 | \r | |
200 | MsrIndex = (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;\r | |
201 | //\r | |
202 | // The serializing semantics of WRMSR are relaxed when writing to the APIC registers.\r | |
203 | // Use memory fence here to force the serializing semantics to be consisent with xAPIC mode.\r | |
204 | //\r | |
205 | MemoryFence ();\r | |
206 | AsmWriteMsr32 (MsrIndex, Value);\r | |
207 | }\r | |
208 | }\r | |
209 | \r | |
210 | /**\r | |
211 | Send an IPI by writing to ICR.\r | |
212 | \r | |
7367cc6c | 213 | This function returns after the IPI has been accepted by the target processor.\r |
bf73cc4b | 214 | \r |
215 | @param IcrLow 32-bit value to be written to the low half of ICR.\r | |
216 | @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r | |
217 | **/\r | |
218 | VOID\r | |
219 | SendIpi (\r | |
053e878b MK |
220 | IN UINT32 IcrLow,\r |
221 | IN UINT32 ApicId\r | |
bf73cc4b | 222 | )\r |
223 | {\r | |
053e878b MK |
224 | UINT64 MsrValue;\r |
225 | LOCAL_APIC_ICR_LOW IcrLowReg;\r | |
226 | UINTN LocalApciBaseAddress;\r | |
227 | UINT32 IcrHigh;\r | |
228 | BOOLEAN InterruptState;\r | |
bf73cc4b | 229 | \r |
9c71e1e0 JF |
230 | //\r |
231 | // Legacy APIC or X2APIC?\r | |
232 | //\r | |
bf73cc4b | 233 | if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r |
234 | ASSERT (ApicId <= 0xff);\r | |
235 | \r | |
9c71e1e0 JF |
236 | InterruptState = SaveAndDisableInterrupts ();\r |
237 | \r | |
bf73cc4b | 238 | //\r |
9c71e1e0 | 239 | // Get base address of this LAPIC\r |
bf73cc4b | 240 | //\r |
053e878b | 241 | LocalApciBaseAddress = GetLocalApicBaseAddress ();\r |
9c71e1e0 JF |
242 | \r |
243 | //\r | |
244 | // Save existing contents of ICR high 32 bits\r | |
245 | //\r | |
246 | IcrHigh = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET);\r | |
247 | \r | |
248 | //\r | |
249 | // Wait for DeliveryStatus clear in case a previous IPI\r | |
250 | // is still being sent\r | |
251 | //\r | |
252 | do {\r | |
253 | IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);\r | |
254 | } while (IcrLowReg.Bits.DeliveryStatus != 0);\r | |
255 | \r | |
256 | //\r | |
257 | // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r | |
258 | //\r | |
a66e0c7d | 259 | MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r |
260 | MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET, IcrLow);\r | |
9c71e1e0 JF |
261 | \r |
262 | //\r | |
263 | // Wait for DeliveryStatus clear again\r | |
264 | //\r | |
bf73cc4b | 265 | do {\r |
a66e0c7d | 266 | IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);\r |
bf73cc4b | 267 | } while (IcrLowReg.Bits.DeliveryStatus != 0);\r |
9c71e1e0 JF |
268 | \r |
269 | //\r | |
270 | // And restore old contents of ICR high\r | |
271 | //\r | |
272 | MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);\r | |
273 | \r | |
274 | SetInterruptState (InterruptState);\r | |
bf73cc4b | 275 | } else {\r |
276 | //\r | |
7367cc6c | 277 | // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an\r |
bf73cc4b | 278 | // interrupt in x2APIC mode.\r |
279 | //\r | |
053e878b | 280 | MsrValue = LShiftU64 ((UINT64)ApicId, 32) | IcrLow;\r |
bf73cc4b | 281 | AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);\r |
282 | }\r | |
283 | }\r | |
284 | \r | |
285 | //\r | |
286 | // Library API implementation functions\r | |
287 | //\r | |
288 | \r | |
289 | /**\r | |
290 | Get the current local APIC mode.\r | |
291 | \r | |
292 | If local APIC is disabled, then ASSERT.\r | |
293 | \r | |
294 | @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r | |
295 | @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r | |
296 | **/\r | |
297 | UINTN\r | |
298 | EFIAPI\r | |
299 | GetApicMode (\r | |
300 | VOID\r | |
301 | )\r | |
302 | {\r | |
a742e186 | 303 | MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r |
e9cd66d0 MK |
304 | \r |
305 | if (!LocalApicBaseAddressMsrSupported ()) {\r | |
306 | //\r | |
307 | // If CPU does not support APIC Base Address MSR, then return XAPIC mode\r | |
308 | //\r | |
309 | return LOCAL_APIC_MODE_XAPIC;\r | |
310 | }\r | |
bf73cc4b | 311 | \r |
a742e186 | 312 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r |
bf73cc4b | 313 | //\r |
314 | // Local APIC should have been enabled\r | |
315 | //\r | |
a742e186 JF |
316 | ASSERT (ApicBaseMsr.Bits.EN != 0);\r |
317 | if (ApicBaseMsr.Bits.EXTD != 0) {\r | |
bf73cc4b | 318 | return LOCAL_APIC_MODE_X2APIC;\r |
319 | } else {\r | |
320 | return LOCAL_APIC_MODE_XAPIC;\r | |
321 | }\r | |
322 | }\r | |
323 | \r | |
324 | /**\r | |
325 | Set the current local APIC mode.\r | |
326 | \r | |
327 | If the specified local APIC mode is not valid, then ASSERT.\r | |
328 | If the specified local APIC mode can't be set as current, then ASSERT.\r | |
329 | \r | |
330 | @param ApicMode APIC mode to be set.\r | |
9c71e1e0 JF |
331 | \r |
332 | @note This API must not be called from an interrupt handler or SMI handler.\r | |
333 | It may result in unpredictable behavior.\r | |
bf73cc4b | 334 | **/\r |
335 | VOID\r | |
336 | EFIAPI\r | |
337 | SetApicMode (\r | |
338 | IN UINTN ApicMode\r | |
339 | )\r | |
340 | {\r | |
a742e186 JF |
341 | UINTN CurrentMode;\r |
342 | MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r | |
e9cd66d0 MK |
343 | \r |
344 | if (!LocalApicBaseAddressMsrSupported ()) {\r | |
345 | //\r | |
346 | // Ignore set request if the CPU does not support APIC Base Address MSR\r | |
347 | //\r | |
348 | return;\r | |
349 | }\r | |
bf73cc4b | 350 | \r |
351 | CurrentMode = GetApicMode ();\r | |
352 | if (CurrentMode == LOCAL_APIC_MODE_XAPIC) {\r | |
353 | switch (ApicMode) {\r | |
354 | case LOCAL_APIC_MODE_XAPIC:\r | |
355 | break;\r | |
356 | case LOCAL_APIC_MODE_X2APIC:\r | |
053e878b | 357 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r |
a742e186 JF |
358 | ApicBaseMsr.Bits.EXTD = 1;\r |
359 | AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r | |
bf73cc4b | 360 | break;\r |
361 | default:\r | |
362 | ASSERT (FALSE);\r | |
363 | }\r | |
364 | } else {\r | |
365 | switch (ApicMode) {\r | |
366 | case LOCAL_APIC_MODE_XAPIC:\r | |
367 | //\r | |
368 | // Transition from x2APIC mode to xAPIC mode is a two-step process:\r | |
369 | // x2APIC -> Local APIC disabled -> xAPIC\r | |
370 | //\r | |
053e878b | 371 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r |
a742e186 | 372 | ApicBaseMsr.Bits.EXTD = 0;\r |
053e878b | 373 | ApicBaseMsr.Bits.EN = 0;\r |
a742e186 JF |
374 | AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r |
375 | ApicBaseMsr.Bits.EN = 1;\r | |
376 | AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r | |
bf73cc4b | 377 | break;\r |
378 | case LOCAL_APIC_MODE_X2APIC:\r | |
379 | break;\r | |
380 | default:\r | |
381 | ASSERT (FALSE);\r | |
382 | }\r | |
383 | }\r | |
384 | }\r | |
385 | \r | |
386 | /**\r | |
387 | Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r | |
388 | \r | |
6e3e4d70 | 389 | In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r |
7367cc6c | 390 | In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,\r |
bf73cc4b | 391 | the 32-bit local APIC ID is returned as initial APIC ID.\r |
392 | \r | |
393 | @return 32-bit initial local APIC ID of the executing processor.\r | |
394 | **/\r | |
395 | UINT32\r | |
396 | EFIAPI\r | |
397 | GetInitialApicId (\r | |
398 | VOID\r | |
399 | )\r | |
400 | {\r | |
053e878b MK |
401 | UINT32 ApicId;\r |
402 | UINT32 MaxCpuIdIndex;\r | |
403 | UINT32 RegEbx;\r | |
bf73cc4b | 404 | \r |
405 | if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r | |
6e3e4d70 JF |
406 | //\r |
407 | // Get the max index of basic CPUID\r | |
408 | //\r | |
409 | AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r | |
410 | //\r | |
7367cc6c | 411 | // If CPUID Leaf B is supported,\r |
4af3ae14 | 412 | // And CPUID.0BH:EBX[15:0] reports a non-zero value,\r |
6e3e4d70 JF |
413 | // Then the initial 32-bit APIC ID = CPUID.0BH:EDX\r |
414 | // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]\r | |
415 | //\r | |
416 | if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r | |
4af3ae14 LE |
417 | AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, &RegEbx, NULL, &ApicId);\r |
418 | if ((RegEbx & (BIT16 - 1)) != 0) {\r | |
419 | return ApicId;\r | |
420 | }\r | |
6e3e4d70 | 421 | }\r |
053e878b | 422 | \r |
bf73cc4b | 423 | AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r |
424 | return RegEbx >> 24;\r | |
425 | } else {\r | |
426 | return GetApicId ();\r | |
427 | }\r | |
428 | }\r | |
429 | \r | |
430 | /**\r | |
431 | Get the local APIC ID of the executing processor.\r | |
432 | \r | |
433 | @return 32-bit local APIC ID of the executing processor.\r | |
434 | **/\r | |
435 | UINT32\r | |
436 | EFIAPI\r | |
437 | GetApicId (\r | |
438 | VOID\r | |
439 | )\r | |
440 | {\r | |
053e878b MK |
441 | UINT32 ApicId;\r |
442 | UINT32 InitApicId;\r | |
bf73cc4b | 443 | \r |
444 | ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);\r | |
445 | if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r | |
6e3e4d70 | 446 | ApicId = ((InitApicId = GetInitialApicId ()) < 0x100) ? (ApicId >> 24) : InitApicId;\r |
bf73cc4b | 447 | }\r |
6e3e4d70 | 448 | \r |
bf73cc4b | 449 | return ApicId;\r |
450 | }\r | |
451 | \r | |
ae40aef1 | 452 | /**\r |
453 | Get the value of the local APIC version register.\r | |
454 | \r | |
455 | @return the value of the local APIC version register.\r | |
456 | **/\r | |
457 | UINT32\r | |
458 | EFIAPI\r | |
459 | GetApicVersion (\r | |
460 | VOID\r | |
461 | )\r | |
462 | {\r | |
463 | return ReadLocalApicReg (XAPIC_VERSION_OFFSET);\r | |
464 | }\r | |
465 | \r | |
466 | /**\r | |
467 | Send a Fixed IPI to a specified target processor.\r | |
468 | \r | |
7367cc6c | 469 | This function returns after the IPI has been accepted by the target processor.\r |
ae40aef1 | 470 | \r |
471 | @param ApicId The local APIC ID of the target processor.\r | |
472 | @param Vector The vector number of the interrupt being sent.\r | |
473 | **/\r | |
474 | VOID\r | |
475 | EFIAPI\r | |
476 | SendFixedIpi (\r | |
053e878b MK |
477 | IN UINT32 ApicId,\r |
478 | IN UINT8 Vector\r | |
ae40aef1 | 479 | )\r |
480 | {\r | |
053e878b | 481 | LOCAL_APIC_ICR_LOW IcrLow;\r |
ae40aef1 | 482 | \r |
053e878b | 483 | IcrLow.Uint32 = 0;\r |
ae40aef1 | 484 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r |
053e878b MK |
485 | IcrLow.Bits.Level = 1;\r |
486 | IcrLow.Bits.Vector = Vector;\r | |
ae40aef1 | 487 | SendIpi (IcrLow.Uint32, ApicId);\r |
488 | }\r | |
489 | \r | |
490 | /**\r | |
491 | Send a Fixed IPI to all processors excluding self.\r | |
492 | \r | |
7367cc6c | 493 | This function returns after the IPI has been accepted by the target processors.\r |
ae40aef1 | 494 | \r |
495 | @param Vector The vector number of the interrupt being sent.\r | |
496 | **/\r | |
497 | VOID\r | |
498 | EFIAPI\r | |
499 | SendFixedIpiAllExcludingSelf (\r | |
053e878b | 500 | IN UINT8 Vector\r |
ae40aef1 | 501 | )\r |
502 | {\r | |
053e878b | 503 | LOCAL_APIC_ICR_LOW IcrLow;\r |
ae40aef1 | 504 | \r |
053e878b MK |
505 | IcrLow.Uint32 = 0;\r |
506 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r | |
507 | IcrLow.Bits.Level = 1;\r | |
ae40aef1 | 508 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r |
053e878b | 509 | IcrLow.Bits.Vector = Vector;\r |
ae40aef1 | 510 | SendIpi (IcrLow.Uint32, 0);\r |
511 | }\r | |
512 | \r | |
bf73cc4b | 513 | /**\r |
514 | Send a SMI IPI to a specified target processor.\r | |
515 | \r | |
7367cc6c | 516 | This function returns after the IPI has been accepted by the target processor.\r |
bf73cc4b | 517 | \r |
518 | @param ApicId Specify the local APIC ID of the target processor.\r | |
519 | **/\r | |
520 | VOID\r | |
521 | EFIAPI\r | |
522 | SendSmiIpi (\r | |
053e878b | 523 | IN UINT32 ApicId\r |
bf73cc4b | 524 | )\r |
525 | {\r | |
053e878b | 526 | LOCAL_APIC_ICR_LOW IcrLow;\r |
bf73cc4b | 527 | \r |
053e878b | 528 | IcrLow.Uint32 = 0;\r |
bf73cc4b | 529 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r |
053e878b | 530 | IcrLow.Bits.Level = 1;\r |
bf73cc4b | 531 | SendIpi (IcrLow.Uint32, ApicId);\r |
532 | }\r | |
533 | \r | |
534 | /**\r | |
535 | Send a SMI IPI to all processors excluding self.\r | |
536 | \r | |
7367cc6c | 537 | This function returns after the IPI has been accepted by the target processors.\r |
bf73cc4b | 538 | **/\r |
539 | VOID\r | |
540 | EFIAPI\r | |
541 | SendSmiIpiAllExcludingSelf (\r | |
542 | VOID\r | |
543 | )\r | |
544 | {\r | |
053e878b | 545 | LOCAL_APIC_ICR_LOW IcrLow;\r |
bf73cc4b | 546 | \r |
053e878b MK |
547 | IcrLow.Uint32 = 0;\r |
548 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r | |
549 | IcrLow.Bits.Level = 1;\r | |
bf73cc4b | 550 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r |
551 | SendIpi (IcrLow.Uint32, 0);\r | |
552 | }\r | |
553 | \r | |
554 | /**\r | |
555 | Send an INIT IPI to a specified target processor.\r | |
556 | \r | |
7367cc6c | 557 | This function returns after the IPI has been accepted by the target processor.\r |
bf73cc4b | 558 | \r |
559 | @param ApicId Specify the local APIC ID of the target processor.\r | |
560 | **/\r | |
561 | VOID\r | |
562 | EFIAPI\r | |
563 | SendInitIpi (\r | |
053e878b | 564 | IN UINT32 ApicId\r |
bf73cc4b | 565 | )\r |
566 | {\r | |
053e878b | 567 | LOCAL_APIC_ICR_LOW IcrLow;\r |
bf73cc4b | 568 | \r |
053e878b | 569 | IcrLow.Uint32 = 0;\r |
bf73cc4b | 570 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r |
053e878b | 571 | IcrLow.Bits.Level = 1;\r |
bf73cc4b | 572 | SendIpi (IcrLow.Uint32, ApicId);\r |
573 | }\r | |
574 | \r | |
575 | /**\r | |
576 | Send an INIT IPI to all processors excluding self.\r | |
577 | \r | |
7367cc6c | 578 | This function returns after the IPI has been accepted by the target processors.\r |
bf73cc4b | 579 | **/\r |
580 | VOID\r | |
581 | EFIAPI\r | |
582 | SendInitIpiAllExcludingSelf (\r | |
583 | VOID\r | |
584 | )\r | |
585 | {\r | |
053e878b | 586 | LOCAL_APIC_ICR_LOW IcrLow;\r |
bf73cc4b | 587 | \r |
053e878b MK |
588 | IcrLow.Uint32 = 0;\r |
589 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r | |
590 | IcrLow.Bits.Level = 1;\r | |
bf73cc4b | 591 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r |
592 | SendIpi (IcrLow.Uint32, 0);\r | |
593 | }\r | |
594 | \r | |
595 | /**\r | |
596 | Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r | |
597 | \r | |
7367cc6c | 598 | This function returns after the IPI has been accepted by the target processor.\r |
bf73cc4b | 599 | \r |
600 | if StartupRoutine >= 1M, then ASSERT.\r | |
601 | if StartupRoutine is not multiple of 4K, then ASSERT.\r | |
602 | \r | |
603 | @param ApicId Specify the local APIC ID of the target processor.\r | |
604 | @param StartupRoutine Points to a start-up routine which is below 1M physical\r | |
605 | address and 4K aligned.\r | |
606 | **/\r | |
607 | VOID\r | |
608 | EFIAPI\r | |
609 | SendInitSipiSipi (\r | |
053e878b MK |
610 | IN UINT32 ApicId,\r |
611 | IN UINT32 StartupRoutine\r | |
bf73cc4b | 612 | )\r |
613 | {\r | |
053e878b | 614 | LOCAL_APIC_ICR_LOW IcrLow;\r |
bf73cc4b | 615 | \r |
616 | ASSERT (StartupRoutine < 0x100000);\r | |
617 | ASSERT ((StartupRoutine & 0xfff) == 0);\r | |
618 | \r | |
619 | SendInitIpi (ApicId);\r | |
053e878b MK |
620 | MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));\r |
621 | IcrLow.Uint32 = 0;\r | |
622 | IcrLow.Bits.Vector = (StartupRoutine >> 12);\r | |
bf73cc4b | 623 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r |
053e878b | 624 | IcrLow.Bits.Level = 1;\r |
bf73cc4b | 625 | SendIpi (IcrLow.Uint32, ApicId);\r |
bf252e29 ED |
626 | if (!StandardSignatureIsAuthenticAMD ()) {\r |
627 | MicroSecondDelay (200);\r | |
628 | SendIpi (IcrLow.Uint32, ApicId);\r | |
629 | }\r | |
bf73cc4b | 630 | }\r |
631 | \r | |
632 | /**\r | |
633 | Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r | |
634 | \r | |
7367cc6c | 635 | This function returns after the IPI has been accepted by the target processors.\r |
bf73cc4b | 636 | \r |
637 | if StartupRoutine >= 1M, then ASSERT.\r | |
638 | if StartupRoutine is not multiple of 4K, then ASSERT.\r | |
639 | \r | |
640 | @param StartupRoutine Points to a start-up routine which is below 1M physical\r | |
641 | address and 4K aligned.\r | |
642 | **/\r | |
643 | VOID\r | |
644 | EFIAPI\r | |
645 | SendInitSipiSipiAllExcludingSelf (\r | |
053e878b | 646 | IN UINT32 StartupRoutine\r |
bf73cc4b | 647 | )\r |
648 | {\r | |
053e878b | 649 | LOCAL_APIC_ICR_LOW IcrLow;\r |
bf73cc4b | 650 | \r |
651 | ASSERT (StartupRoutine < 0x100000);\r | |
652 | ASSERT ((StartupRoutine & 0xfff) == 0);\r | |
653 | \r | |
654 | SendInitIpiAllExcludingSelf ();\r | |
053e878b MK |
655 | MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));\r |
656 | IcrLow.Uint32 = 0;\r | |
657 | IcrLow.Bits.Vector = (StartupRoutine >> 12);\r | |
658 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r | |
659 | IcrLow.Bits.Level = 1;\r | |
bf73cc4b | 660 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r |
661 | SendIpi (IcrLow.Uint32, 0);\r | |
bf252e29 ED |
662 | if (!StandardSignatureIsAuthenticAMD ()) {\r |
663 | MicroSecondDelay (200);\r | |
664 | SendIpi (IcrLow.Uint32, 0);\r | |
665 | }\r | |
bf73cc4b | 666 | }\r |
667 | \r | |
14e4ca25 MK |
668 | /**\r |
669 | Initialize the state of the SoftwareEnable bit in the Local APIC\r | |
670 | Spurious Interrupt Vector register.\r | |
671 | \r | |
672 | @param Enable If TRUE, then set SoftwareEnable to 1\r | |
673 | If FALSE, then set SoftwareEnable to 0.\r | |
674 | \r | |
675 | **/\r | |
676 | VOID\r | |
677 | EFIAPI\r | |
678 | InitializeLocalApicSoftwareEnable (\r | |
679 | IN BOOLEAN Enable\r | |
680 | )\r | |
681 | {\r | |
682 | LOCAL_APIC_SVR Svr;\r | |
683 | \r | |
684 | //\r | |
685 | // Set local APIC software-enabled bit.\r | |
686 | //\r | |
687 | Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r | |
688 | if (Enable) {\r | |
689 | if (Svr.Bits.SoftwareEnable == 0) {\r | |
690 | Svr.Bits.SoftwareEnable = 1;\r | |
691 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
692 | }\r | |
693 | } else {\r | |
694 | if (Svr.Bits.SoftwareEnable == 1) {\r | |
695 | Svr.Bits.SoftwareEnable = 0;\r | |
696 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
697 | }\r | |
698 | }\r | |
699 | }\r | |
700 | \r | |
bf73cc4b | 701 | /**\r |
702 | Programming Virtual Wire Mode.\r | |
703 | \r | |
704 | This function programs the local APIC for virtual wire mode following\r | |
705 | the example described in chapter A.3 of the MP 1.4 spec.\r | |
706 | \r | |
707 | IOxAPIC is not involved in this type of virtual wire mode.\r | |
708 | **/\r | |
709 | VOID\r | |
710 | EFIAPI\r | |
711 | ProgramVirtualWireMode (\r | |
712 | VOID\r | |
713 | )\r | |
714 | {\r | |
053e878b MK |
715 | LOCAL_APIC_SVR Svr;\r |
716 | LOCAL_APIC_LVT_LINT Lint;\r | |
bf73cc4b | 717 | \r |
718 | //\r | |
719 | // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.\r | |
720 | //\r | |
053e878b | 721 | Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r |
bf73cc4b | 722 | Svr.Bits.SpuriousVector = 0xf;\r |
723 | Svr.Bits.SoftwareEnable = 1;\r | |
724 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
725 | \r | |
726 | //\r | |
727 | // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.\r | |
728 | //\r | |
053e878b MK |
729 | Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r |
730 | Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r | |
bf73cc4b | 731 | Lint.Bits.InputPinPolarity = 0;\r |
053e878b MK |
732 | Lint.Bits.TriggerMode = 0;\r |
733 | Lint.Bits.Mask = 0;\r | |
ae40aef1 | 734 | WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);\r |
bf73cc4b | 735 | \r |
736 | //\r | |
737 | // Program the LINT0 vector entry as NMI. Not masked, edge, active high.\r | |
738 | //\r | |
053e878b MK |
739 | Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r |
740 | Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;\r | |
bf73cc4b | 741 | Lint.Bits.InputPinPolarity = 0;\r |
053e878b MK |
742 | Lint.Bits.TriggerMode = 0;\r |
743 | Lint.Bits.Mask = 0;\r | |
ae40aef1 | 744 | WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);\r |
bf73cc4b | 745 | }\r |
746 | \r | |
b1b8c631 | 747 | /**\r |
748 | Disable LINT0 & LINT1 interrupts.\r | |
749 | \r | |
750 | This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r | |
751 | **/\r | |
752 | VOID\r | |
753 | EFIAPI\r | |
754 | DisableLvtInterrupts (\r | |
755 | VOID\r | |
756 | )\r | |
757 | {\r | |
053e878b | 758 | LOCAL_APIC_LVT_LINT LvtLint;\r |
b1b8c631 | 759 | \r |
053e878b | 760 | LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r |
b1b8c631 | 761 | LvtLint.Bits.Mask = 1;\r |
762 | WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);\r | |
763 | \r | |
053e878b | 764 | LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r |
b1b8c631 | 765 | LvtLint.Bits.Mask = 1;\r |
766 | WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);\r | |
767 | }\r | |
768 | \r | |
bf73cc4b | 769 | /**\r |
770 | Read the initial count value from the init-count register.\r | |
771 | \r | |
772 | @return The initial count value read from the init-count register.\r | |
773 | **/\r | |
774 | UINT32\r | |
775 | EFIAPI\r | |
776 | GetApicTimerInitCount (\r | |
777 | VOID\r | |
778 | )\r | |
779 | {\r | |
780 | return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);\r | |
781 | }\r | |
782 | \r | |
783 | /**\r | |
784 | Read the current count value from the current-count register.\r | |
785 | \r | |
786 | @return The current count value read from the current-count register.\r | |
787 | **/\r | |
788 | UINT32\r | |
789 | EFIAPI\r | |
790 | GetApicTimerCurrentCount (\r | |
791 | VOID\r | |
792 | )\r | |
793 | {\r | |
794 | return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);\r | |
795 | }\r | |
796 | \r | |
797 | /**\r | |
798 | Initialize the local APIC timer.\r | |
799 | \r | |
800 | The local APIC timer is initialized and enabled.\r | |
801 | \r | |
802 | @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r | |
803 | If it is 0, then use the current divide value in the DCR.\r | |
804 | @param InitCount The initial count value.\r | |
805 | @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r | |
806 | @param Vector The timer interrupt vector number.\r | |
807 | **/\r | |
808 | VOID\r | |
809 | EFIAPI\r | |
810 | InitializeApicTimer (\r | |
053e878b MK |
811 | IN UINTN DivideValue,\r |
812 | IN UINT32 InitCount,\r | |
813 | IN BOOLEAN PeriodicMode,\r | |
814 | IN UINT8 Vector\r | |
bf73cc4b | 815 | )\r |
816 | {\r | |
053e878b MK |
817 | LOCAL_APIC_DCR Dcr;\r |
818 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
819 | UINT32 Divisor;\r | |
bf73cc4b | 820 | \r |
821 | //\r | |
822 | // Ensure local APIC is in software-enabled state.\r | |
823 | //\r | |
14e4ca25 | 824 | InitializeLocalApicSoftwareEnable (TRUE);\r |
bf73cc4b | 825 | \r |
826 | //\r | |
827 | // Program init-count register.\r | |
828 | //\r | |
829 | WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);\r | |
830 | \r | |
831 | if (DivideValue != 0) {\r | |
832 | ASSERT (DivideValue <= 128);\r | |
053e878b | 833 | ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue));\r |
bf73cc4b | 834 | Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);\r |
835 | \r | |
053e878b | 836 | Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r |
bf73cc4b | 837 | Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r |
838 | Dcr.Bits.DivideValue2 = (Divisor >> 2);\r | |
7367cc6c | 839 | WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);\r |
bf73cc4b | 840 | }\r |
841 | \r | |
842 | //\r | |
843 | // Enable APIC timer interrupt with specified timer mode.\r | |
844 | //\r | |
845 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
846 | if (PeriodicMode) {\r | |
847 | LvtTimer.Bits.TimerMode = 1;\r | |
848 | } else {\r | |
849 | LvtTimer.Bits.TimerMode = 0;\r | |
850 | }\r | |
053e878b MK |
851 | \r |
852 | LvtTimer.Bits.Mask = 0;\r | |
bf73cc4b | 853 | LvtTimer.Bits.Vector = Vector;\r |
854 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
855 | }\r | |
856 | \r | |
ae40aef1 | 857 | /**\r |
858 | Get the state of the local APIC timer.\r | |
859 | \r | |
6d72ff7d HW |
860 | This function will ASSERT if the local APIC is not software enabled.\r |
861 | \r | |
ae40aef1 | 862 | @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r |
863 | @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r | |
864 | @param Vector Return the timer interrupt vector number.\r | |
865 | **/\r | |
866 | VOID\r | |
867 | EFIAPI\r | |
868 | GetApicTimerState (\r | |
869 | OUT UINTN *DivideValue OPTIONAL,\r | |
870 | OUT BOOLEAN *PeriodicMode OPTIONAL,\r | |
871 | OUT UINT8 *Vector OPTIONAL\r | |
872 | )\r | |
873 | {\r | |
053e878b MK |
874 | UINT32 Divisor;\r |
875 | LOCAL_APIC_DCR Dcr;\r | |
876 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
ae40aef1 | 877 | \r |
6d72ff7d HW |
878 | //\r |
879 | // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt\r | |
880 | // Vector Register.\r | |
881 | // This bit will be 1, if local APIC is software enabled.\r | |
882 | //\r | |
053e878b | 883 | ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);\r |
6d72ff7d | 884 | \r |
ae40aef1 | 885 | if (DivideValue != NULL) {\r |
053e878b MK |
886 | Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r |
887 | Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r | |
888 | Divisor = (Divisor + 1) & 0x7;\r | |
ae40aef1 | 889 | *DivideValue = ((UINTN)1) << Divisor;\r |
890 | }\r | |
891 | \r | |
053e878b | 892 | if ((PeriodicMode != NULL) || (Vector != NULL)) {\r |
ae40aef1 | 893 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r |
894 | if (PeriodicMode != NULL) {\r | |
895 | if (LvtTimer.Bits.TimerMode == 1) {\r | |
896 | *PeriodicMode = TRUE;\r | |
897 | } else {\r | |
898 | *PeriodicMode = FALSE;\r | |
899 | }\r | |
900 | }\r | |
053e878b | 901 | \r |
ae40aef1 | 902 | if (Vector != NULL) {\r |
053e878b | 903 | *Vector = (UINT8)LvtTimer.Bits.Vector;\r |
ae40aef1 | 904 | }\r |
905 | }\r | |
906 | }\r | |
907 | \r | |
bf73cc4b | 908 | /**\r |
909 | Enable the local APIC timer interrupt.\r | |
910 | **/\r | |
911 | VOID\r | |
912 | EFIAPI\r | |
913 | EnableApicTimerInterrupt (\r | |
914 | VOID\r | |
915 | )\r | |
916 | {\r | |
053e878b | 917 | LOCAL_APIC_LVT_TIMER LvtTimer;\r |
bf73cc4b | 918 | \r |
053e878b | 919 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r |
bf73cc4b | 920 | LvtTimer.Bits.Mask = 0;\r |
921 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
922 | }\r | |
923 | \r | |
924 | /**\r | |
925 | Disable the local APIC timer interrupt.\r | |
926 | **/\r | |
927 | VOID\r | |
928 | EFIAPI\r | |
929 | DisableApicTimerInterrupt (\r | |
930 | VOID\r | |
931 | )\r | |
932 | {\r | |
053e878b | 933 | LOCAL_APIC_LVT_TIMER LvtTimer;\r |
bf73cc4b | 934 | \r |
053e878b | 935 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r |
bf73cc4b | 936 | LvtTimer.Bits.Mask = 1;\r |
937 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
938 | }\r | |
939 | \r | |
940 | /**\r | |
941 | Get the local APIC timer interrupt state.\r | |
942 | \r | |
943 | @retval TRUE The local APIC timer interrupt is enabled.\r | |
944 | @retval FALSE The local APIC timer interrupt is disabled.\r | |
945 | **/\r | |
946 | BOOLEAN\r | |
947 | EFIAPI\r | |
948 | GetApicTimerInterruptState (\r | |
949 | VOID\r | |
950 | )\r | |
951 | {\r | |
053e878b | 952 | LOCAL_APIC_LVT_TIMER LvtTimer;\r |
bf73cc4b | 953 | \r |
954 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
955 | return (BOOLEAN)(LvtTimer.Bits.Mask == 0);\r | |
956 | }\r | |
957 | \r | |
958 | /**\r | |
959 | Send EOI to the local APIC.\r | |
960 | **/\r | |
961 | VOID\r | |
962 | EFIAPI\r | |
963 | SendApicEoi (\r | |
964 | VOID\r | |
965 | )\r | |
966 | {\r | |
967 | WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);\r | |
968 | }\r | |
969 | \r | |
5f867ad0 | 970 | /**\r |
7367cc6c | 971 | Get the 32-bit address that a device should use to send a Message Signaled\r |
5f867ad0 | 972 | Interrupt (MSI) to the Local APIC of the currently executing processor.\r |
973 | \r | |
974 | @return 32-bit address used to send an MSI to the Local APIC.\r | |
975 | **/\r | |
976 | UINT32\r | |
7367cc6c | 977 | EFIAPI\r |
5f867ad0 | 978 | GetApicMsiAddress (\r |
979 | VOID\r | |
980 | )\r | |
981 | {\r | |
982 | LOCAL_APIC_MSI_ADDRESS MsiAddress;\r | |
983 | \r | |
984 | //\r | |
7367cc6c | 985 | // Return address for an MSI interrupt to be delivered only to the APIC ID\r |
5f867ad0 | 986 | // of the currently executing processor.\r |
987 | //\r | |
988 | MsiAddress.Uint32 = 0;\r | |
989 | MsiAddress.Bits.BaseAddress = 0xFEE;\r | |
990 | MsiAddress.Bits.DestinationId = GetApicId ();\r | |
991 | return MsiAddress.Uint32;\r | |
992 | }\r | |
7367cc6c | 993 | \r |
5f867ad0 | 994 | /**\r |
7367cc6c | 995 | Get the 64-bit data value that a device should use to send a Message Signaled\r |
5f867ad0 | 996 | Interrupt (MSI) to the Local APIC of the currently executing processor.\r |
997 | \r | |
998 | If Vector is not in range 0x10..0xFE, then ASSERT().\r | |
999 | If DeliveryMode is not supported, then ASSERT().\r | |
7367cc6c LG |
1000 | \r |
1001 | @param Vector The 8-bit interrupt vector associated with the MSI.\r | |
5f867ad0 | 1002 | Must be in the range 0x10..0xFE\r |
7367cc6c | 1003 | @param DeliveryMode A 3-bit value that specifies how the recept of the MSI\r |
5f867ad0 | 1004 | is handled. The only supported values are:\r |
1005 | 0: LOCAL_APIC_DELIVERY_MODE_FIXED\r | |
1006 | 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r | |
1007 | 2: LOCAL_APIC_DELIVERY_MODE_SMI\r | |
1008 | 4: LOCAL_APIC_DELIVERY_MODE_NMI\r | |
1009 | 5: LOCAL_APIC_DELIVERY_MODE_INIT\r | |
1010 | 7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r | |
7367cc6c LG |
1011 | \r |
1012 | @param LevelTriggered TRUE specifies a level triggered interrupt.\r | |
5f867ad0 | 1013 | FALSE specifies an edge triggered interrupt.\r |
1014 | @param AssertionLevel Ignored if LevelTriggered is FALSE.\r | |
7367cc6c | 1015 | TRUE specifies a level triggered interrupt that active\r |
5f867ad0 | 1016 | when the interrupt line is asserted.\r |
7367cc6c | 1017 | FALSE specifies a level triggered interrupt that active\r |
5f867ad0 | 1018 | when the interrupt line is deasserted.\r |
1019 | \r | |
1020 | @return 64-bit data value used to send an MSI to the Local APIC.\r | |
1021 | **/\r | |
1022 | UINT64\r | |
7367cc6c | 1023 | EFIAPI\r |
5f867ad0 | 1024 | GetApicMsiValue (\r |
1025 | IN UINT8 Vector,\r | |
1026 | IN UINTN DeliveryMode,\r | |
1027 | IN BOOLEAN LevelTriggered,\r | |
1028 | IN BOOLEAN AssertionLevel\r | |
1029 | )\r | |
1030 | {\r | |
1031 | LOCAL_APIC_MSI_DATA MsiData;\r | |
1032 | \r | |
1033 | ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r | |
1034 | ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r | |
7367cc6c | 1035 | \r |
5f867ad0 | 1036 | MsiData.Uint64 = 0;\r |
1037 | MsiData.Bits.Vector = Vector;\r | |
1038 | MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r | |
1039 | if (LevelTriggered) {\r | |
1040 | MsiData.Bits.TriggerMode = 1;\r | |
1041 | if (AssertionLevel) {\r | |
1042 | MsiData.Bits.Level = 1;\r | |
1043 | }\r | |
1044 | }\r | |
053e878b | 1045 | \r |
5f867ad0 | 1046 | return MsiData.Uint64;\r |
1047 | }\r | |
73152f19 LD |
1048 | \r |
1049 | /**\r | |
1050 | Get Package ID/Core ID/Thread ID of a processor.\r | |
1051 | \r | |
1052 | The algorithm assumes the target system has symmetry across physical\r | |
1053 | package boundaries with respect to the number of logical processors\r | |
1054 | per package, number of cores per package.\r | |
1055 | \r | |
1056 | @param[in] InitialApicId Initial APIC ID of the target logical processor.\r | |
1057 | @param[out] Package Returns the processor package ID.\r | |
1058 | @param[out] Core Returns the processor core ID.\r | |
1059 | @param[out] Thread Returns the processor thread ID.\r | |
1060 | **/\r | |
1061 | VOID\r | |
1c8ca9a0 | 1062 | EFIAPI\r |
262128e5 | 1063 | GetProcessorLocationByApicId (\r |
73152f19 LD |
1064 | IN UINT32 InitialApicId,\r |
1065 | OUT UINT32 *Package OPTIONAL,\r | |
1066 | OUT UINT32 *Core OPTIONAL,\r | |
1067 | OUT UINT32 *Thread OPTIONAL\r | |
1068 | )\r | |
1069 | {\r | |
061ead7a LD |
1070 | BOOLEAN TopologyLeafSupported;\r |
1071 | CPUID_VERSION_INFO_EBX VersionInfoEbx;\r | |
1072 | CPUID_VERSION_INFO_EDX VersionInfoEdx;\r | |
1073 | CPUID_CACHE_PARAMS_EAX CacheParamsEax;\r | |
1074 | CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r | |
1075 | CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;\r | |
1076 | CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r | |
1077 | CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;\r | |
1078 | CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;\r | |
061ead7a LD |
1079 | CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;\r |
1080 | UINT32 MaxStandardCpuIdIndex;\r | |
1081 | UINT32 MaxExtendedCpuIdIndex;\r | |
1082 | UINT32 SubIndex;\r | |
1083 | UINTN LevelType;\r | |
1084 | UINT32 MaxLogicProcessorsPerPackage;\r | |
1085 | UINT32 MaxCoresPerPackage;\r | |
061ead7a LD |
1086 | UINTN ThreadBits;\r |
1087 | UINTN CoreBits;\r | |
73152f19 LD |
1088 | \r |
1089 | //\r | |
1090 | // Check if the processor is capable of supporting more than one logical processor.\r | |
1091 | //\r | |
ae66c6f1 | 1092 | AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r |
73152f19 LD |
1093 | if (VersionInfoEdx.Bits.HTT == 0) {\r |
1094 | if (Thread != NULL) {\r | |
061ead7a | 1095 | *Thread = 0;\r |
73152f19 | 1096 | }\r |
053e878b | 1097 | \r |
73152f19 | 1098 | if (Core != NULL) {\r |
061ead7a | 1099 | *Core = 0;\r |
73152f19 | 1100 | }\r |
053e878b | 1101 | \r |
73152f19 LD |
1102 | if (Package != NULL) {\r |
1103 | *Package = 0;\r | |
1104 | }\r | |
053e878b | 1105 | \r |
73152f19 LD |
1106 | return;\r |
1107 | }\r | |
1108 | \r | |
73152f19 | 1109 | //\r |
061ead7a | 1110 | // Assume three-level mapping of APIC ID: Package|Core|Thread.\r |
73152f19 | 1111 | //\r |
061ead7a | 1112 | ThreadBits = 0;\r |
053e878b | 1113 | CoreBits = 0;\r |
73152f19 LD |
1114 | \r |
1115 | //\r | |
061ead7a | 1116 | // Get max index of CPUID\r |
73152f19 | 1117 | //\r |
ae66c6f1 LD |
1118 | AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r |
1119 | AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);\r | |
73152f19 LD |
1120 | \r |
1121 | //\r | |
1122 | // If the extended topology enumeration leaf is available, it\r | |
1123 | // is the preferred mechanism for enumerating topology.\r | |
1124 | //\r | |
061ead7a LD |
1125 | TopologyLeafSupported = FALSE;\r |
1126 | if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r | |
053e878b | 1127 | AsmCpuidEx (\r |
73152f19 LD |
1128 | CPUID_EXTENDED_TOPOLOGY,\r |
1129 | 0,\r | |
1130 | &ExtendedTopologyEax.Uint32,\r | |
1131 | &ExtendedTopologyEbx.Uint32,\r | |
1132 | &ExtendedTopologyEcx.Uint32,\r | |
1133 | NULL\r | |
1134 | );\r | |
1135 | //\r | |
1136 | // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r | |
1137 | // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r | |
1138 | // supported on that processor.\r | |
1139 | //\r | |
1140 | if (ExtendedTopologyEbx.Uint32 != 0) {\r | |
1141 | TopologyLeafSupported = TRUE;\r | |
1142 | \r | |
1143 | //\r | |
1144 | // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r | |
1145 | // the SMT sub-field of x2APIC ID.\r | |
1146 | //\r | |
1147 | LevelType = ExtendedTopologyEcx.Bits.LevelType;\r | |
ae66c6f1 | 1148 | ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r |
73152f19 LD |
1149 | ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;\r |
1150 | \r | |
1151 | //\r | |
1152 | // Software must not assume any "level type" encoding\r | |
1153 | // value to be related to any sub-leaf index, except sub-leaf 0.\r | |
1154 | //\r | |
1155 | SubIndex = 1;\r | |
1156 | do {\r | |
ae66c6f1 | 1157 | AsmCpuidEx (\r |
73152f19 LD |
1158 | CPUID_EXTENDED_TOPOLOGY,\r |
1159 | SubIndex,\r | |
1160 | &ExtendedTopologyEax.Uint32,\r | |
1161 | NULL,\r | |
1162 | &ExtendedTopologyEcx.Uint32,\r | |
1163 | NULL\r | |
1164 | );\r | |
1165 | LevelType = ExtendedTopologyEcx.Bits.LevelType;\r | |
1166 | if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r | |
1167 | CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;\r | |
1168 | break;\r | |
1169 | }\r | |
053e878b | 1170 | \r |
73152f19 LD |
1171 | SubIndex++;\r |
1172 | } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r | |
1173 | }\r | |
1174 | }\r | |
1175 | \r | |
1176 | if (!TopologyLeafSupported) {\r | |
061ead7a LD |
1177 | //\r |
1178 | // Get logical processor count\r | |
1179 | //\r | |
ae66c6f1 | 1180 | AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);\r |
73152f19 | 1181 | MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;\r |
061ead7a LD |
1182 | \r |
1183 | //\r | |
1184 | // Assume single-core processor\r | |
1185 | //\r | |
1186 | MaxCoresPerPackage = 1;\r | |
1187 | \r | |
1188 | //\r | |
1189 | // Check for topology extensions on AMD processor\r | |
1190 | //\r | |
053e878b | 1191 | if (StandardSignatureIsAuthenticAMD ()) {\r |
061ead7a | 1192 | if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {\r |
ae66c6f1 | 1193 | AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r |
061ead7a | 1194 | if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {\r |
061ead7a | 1195 | //\r |
ae66c6f1 | 1196 | // Account for max possible thread count to decode ApicId\r |
061ead7a | 1197 | //\r |
ae66c6f1 LD |
1198 | AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);\r |
1199 | MaxLogicProcessorsPerPackage = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;\r | |
061ead7a LD |
1200 | \r |
1201 | //\r | |
ae66c6f1 | 1202 | // Get cores per processor package\r |
061ead7a | 1203 | //\r |
ae66c6f1 LD |
1204 | AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);\r |
1205 | MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r | |
061ead7a LD |
1206 | }\r |
1207 | }\r | |
053e878b | 1208 | } else {\r |
73152f19 | 1209 | //\r |
061ead7a | 1210 | // Extract core count based on CACHE information\r |
73152f19 | 1211 | //\r |
061ead7a | 1212 | if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {\r |
ae66c6f1 | 1213 | AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);\r |
061ead7a LD |
1214 | if (CacheParamsEax.Uint32 != 0) {\r |
1215 | MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;\r | |
1216 | }\r | |
1217 | }\r | |
73152f19 LD |
1218 | }\r |
1219 | \r | |
053e878b MK |
1220 | ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r |
1221 | CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1);\r | |
061ead7a | 1222 | }\r |
73152f19 LD |
1223 | \r |
1224 | if (Thread != NULL) {\r | |
061ead7a | 1225 | *Thread = InitialApicId & ((1 << ThreadBits) - 1);\r |
73152f19 | 1226 | }\r |
053e878b | 1227 | \r |
73152f19 | 1228 | if (Core != NULL) {\r |
061ead7a | 1229 | *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r |
73152f19 | 1230 | }\r |
053e878b | 1231 | \r |
73152f19 LD |
1232 | if (Package != NULL) {\r |
1233 | *Package = (InitialApicId >> (ThreadBits + CoreBits));\r | |
1234 | }\r | |
1235 | }\r | |
7f33d4f2 RN |
1236 | \r |
1237 | /**\r | |
1238 | Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor.\r | |
1239 | \r | |
1240 | The algorithm assumes the target system has symmetry across physical\r | |
1241 | package boundaries with respect to the number of threads per core, number of\r | |
1242 | cores per module, number of modules per tile, number of tiles per die, number\r | |
1243 | of dies per package.\r | |
1244 | \r | |
1245 | @param[in] InitialApicId Initial APIC ID of the target logical processor.\r | |
1246 | @param[out] Package Returns the processor package ID.\r | |
1247 | @param[out] Die Returns the processor die ID.\r | |
1248 | @param[out] Tile Returns the processor tile ID.\r | |
1249 | @param[out] Module Returns the processor module ID.\r | |
1250 | @param[out] Core Returns the processor core ID.\r | |
1251 | @param[out] Thread Returns the processor thread ID.\r | |
1252 | **/\r | |
1253 | VOID\r | |
1254 | EFIAPI\r | |
1255 | GetProcessorLocation2ByApicId (\r | |
1256 | IN UINT32 InitialApicId,\r | |
1257 | OUT UINT32 *Package OPTIONAL,\r | |
1258 | OUT UINT32 *Die OPTIONAL,\r | |
1259 | OUT UINT32 *Tile OPTIONAL,\r | |
1260 | OUT UINT32 *Module OPTIONAL,\r | |
1261 | OUT UINT32 *Core OPTIONAL,\r | |
1262 | OUT UINT32 *Thread OPTIONAL\r | |
1263 | )\r | |
1264 | {\r | |
053e878b MK |
1265 | CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;\r |
1266 | CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;\r | |
1267 | UINT32 MaxStandardCpuIdIndex;\r | |
1268 | UINT32 Index;\r | |
1269 | UINTN LevelType;\r | |
1270 | UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r | |
1271 | UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r | |
7f33d4f2 RN |
1272 | \r |
1273 | for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {\r | |
1274 | Bits[LevelType] = 0;\r | |
1275 | }\r | |
1276 | \r | |
1277 | //\r | |
1278 | // Get max index of CPUID\r | |
1279 | //\r | |
1280 | AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r | |
1281 | if (MaxStandardCpuIdIndex < CPUID_V2_EXTENDED_TOPOLOGY) {\r | |
1282 | if (Die != NULL) {\r | |
1283 | *Die = 0;\r | |
1284 | }\r | |
053e878b | 1285 | \r |
7f33d4f2 RN |
1286 | if (Tile != NULL) {\r |
1287 | *Tile = 0;\r | |
1288 | }\r | |
053e878b | 1289 | \r |
7f33d4f2 RN |
1290 | if (Module != NULL) {\r |
1291 | *Module = 0;\r | |
1292 | }\r | |
053e878b | 1293 | \r |
7f33d4f2 RN |
1294 | GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);\r |
1295 | return;\r | |
1296 | }\r | |
1297 | \r | |
1298 | //\r | |
1299 | // If the V2 extended topology enumeration leaf is available, it\r | |
1300 | // is the preferred mechanism for enumerating topology.\r | |
1301 | //\r | |
1302 | for (Index = 0; ; Index++) {\r | |
053e878b | 1303 | AsmCpuidEx (\r |
7f33d4f2 RN |
1304 | CPUID_V2_EXTENDED_TOPOLOGY,\r |
1305 | Index,\r | |
1306 | &ExtendedTopologyEax.Uint32,\r | |
1307 | NULL,\r | |
1308 | &ExtendedTopologyEcx.Uint32,\r | |
1309 | NULL\r | |
1310 | );\r | |
1311 | \r | |
1312 | LevelType = ExtendedTopologyEcx.Bits.LevelType;\r | |
1313 | \r | |
1314 | //\r | |
1315 | // first level reported should be SMT.\r | |
1316 | //\r | |
1317 | ASSERT ((Index != 0) || (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT));\r | |
1318 | if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {\r | |
1319 | break;\r | |
1320 | }\r | |
053e878b | 1321 | \r |
7f33d4f2 RN |
1322 | ASSERT (LevelType < ARRAY_SIZE (Bits));\r |
1323 | Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;\r | |
1324 | }\r | |
1325 | \r | |
1326 | for (LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE; LevelType < ARRAY_SIZE (Bits); LevelType++) {\r | |
1327 | //\r | |
1328 | // If there are more levels between level-1 (low-level) and level-2 (high-level), the unknown levels will be ignored\r | |
1329 | // and treated as an extension of the last known level (i.e., level-1 in this case).\r | |
1330 | //\r | |
1331 | if (Bits[LevelType] == 0) {\r | |
1332 | Bits[LevelType] = Bits[LevelType - 1];\r | |
1333 | }\r | |
1334 | }\r | |
1335 | \r | |
1336 | Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;\r | |
053e878b MK |
1337 | Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die;\r |
1338 | Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile;\r | |
1339 | Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module;\r | |
1340 | Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core;\r | |
1341 | Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread;\r | |
7f33d4f2 RN |
1342 | \r |
1343 | Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;\r | |
1344 | \r | |
1345 | for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT\r | |
053e878b MK |
1346 | ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1\r |
1347 | ; LevelType++\r | |
1348 | )\r | |
1349 | {\r | |
7f33d4f2 RN |
1350 | if (Location[LevelType] != NULL) {\r |
1351 | //\r | |
1352 | // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique\r | |
1353 | // topology ID of the next level type.\r | |
1354 | //\r | |
1355 | *Location[LevelType] = InitialApicId >> Bits[LevelType - 1];\r | |
1356 | \r | |
1357 | //\r | |
1358 | // Bits[i] - Bits[i-1] holds the number of bits for the next ONE level type.\r | |
1359 | //\r | |
1360 | *Location[LevelType] &= (1 << (Bits[LevelType] - Bits[LevelType - 1])) - 1;\r | |
1361 | }\r | |
1362 | }\r | |
1363 | }\r |