projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 2fba7d4e | 1 | ;------------------------------------------------------------------------------ ;\r |
| b4d7b9d2 | 2 | ; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>\r |
| 2fba7d4e RN |
3 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 4 | ;\r | |
| 5 | ; Module Name:\r | |
| 6 | ;\r | |
| 7 | ; MpEqu.inc\r | |
| 8 | ;\r | |
| 9 | ; Abstract:\r | |
| 10 | ;\r | |
| 11 | ; This is the equates file for Multiple Processor support\r | |
| 12 | ;\r | |
| 13 | ;-------------------------------------------------------------------------------\r | |
| 14 | %include "Nasm.inc"\r | |
| 15 | \r | |
| 2fba7d4e RN |
16 | CPU_SWITCH_STATE_IDLE equ 0\r |
| 17 | CPU_SWITCH_STATE_STORED equ 1\r | |
| 18 | CPU_SWITCH_STATE_LOADED equ 2\r | |
| 19 | \r | |
| 20 | ;\r | |
| 21 | ; Equivalent NASM structure of MP_ASSEMBLY_ADDRESS_MAP\r | |
| 22 | ;\r | |
| 23 | struc MP_ASSEMBLY_ADDRESS_MAP\r | |
| 24 | .RendezvousFunnelAddress CTYPE_UINTN 1\r | |
| 25 | .ModeEntryOffset CTYPE_UINTN 1\r | |
| 26 | .RendezvousFunnelSize CTYPE_UINTN 1\r | |
| 27 | .RelocateApLoopFuncAddress CTYPE_UINTN 1\r | |
| 28 | .RelocateApLoopFuncSize CTYPE_UINTN 1\r | |
| 29 | .ModeTransitionOffset CTYPE_UINTN 1\r | |
| 2fba7d4e RN |
30 | .SwitchToRealNoNxOffset CTYPE_UINTN 1\r |
| 31 | .SwitchToRealPM16ModeOffset CTYPE_UINTN 1\r | |
| 32 | .SwitchToRealPM16ModeSize CTYPE_UINTN 1\r | |
| 33 | endstruc\r | |
| 34 | \r | |
| 35 | ;\r | |
| 36 | ; Equivalent NASM structure of IA32_DESCRIPTOR\r | |
| 37 | ;\r | |
| 38 | struc IA32_DESCRIPTOR\r | |
| 39 | .Limit CTYPE_UINT16 1\r | |
| 40 | .Base CTYPE_UINTN 1\r | |
| 41 | endstruc\r | |
| 42 | \r | |
| 43 | ;\r | |
| 44 | ; Equivalent NASM structure of CPU_EXCHANGE_ROLE_INFO\r | |
| 45 | ;\r | |
| 46 | struc CPU_EXCHANGE_ROLE_INFO\r | |
| 47 | ; State is defined as UINT8 in C header file\r | |
| 48 | ; Define it as UINTN here to guarantee the fields that follow State\r | |
| 49 | ; is naturally aligned. The structure layout doesn't change.\r | |
| 50 | .State CTYPE_UINTN 1\r | |
| 51 | .StackPointer CTYPE_UINTN 1\r | |
| 52 | .Gdtr CTYPE_UINT8 IA32_DESCRIPTOR_size\r | |
| 53 | .Idtr CTYPE_UINT8 IA32_DESCRIPTOR_size\r | |
| 54 | endstruc\r | |
| 55 | \r | |
| 56 | ;\r | |
| 57 | ; Equivalent NASM structure of CPU_INFO_IN_HOB\r | |
| 58 | ;\r | |
| 59 | struc CPU_INFO_IN_HOB\r | |
| 60 | .InitialApicId CTYPE_UINT32 1\r | |
| 61 | .ApicId CTYPE_UINT32 1\r | |
| 62 | .Health CTYPE_UINT32 1\r | |
| 63 | .ApTopOfStack CTYPE_UINT64 1\r | |
| 64 | endstruc\r | |
| 65 | \r | |
| 66 | ;\r | |
| 67 | ; Equivalent NASM structure of MP_CPU_EXCHANGE_INFO\r | |
| 68 | ;\r | |
| 69 | struc MP_CPU_EXCHANGE_INFO\r | |
| 2fba7d4e RN |
70 | .StackStart: CTYPE_UINTN 1\r |
| 71 | .StackSize: CTYPE_UINTN 1\r | |
| 72 | .CFunction: CTYPE_UINTN 1\r | |
| 73 | .GdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size\r | |
| 74 | .IdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size\r | |
| 75 | .BufferStart: CTYPE_UINTN 1\r | |
| 76 | .ModeOffset: CTYPE_UINTN 1\r | |
| 77 | .ApIndex: CTYPE_UINTN 1\r | |
| 78 | .CodeSegment: CTYPE_UINTN 1\r | |
| 79 | .DataSegment: CTYPE_UINTN 1\r | |
| 80 | .EnableExecuteDisable: CTYPE_UINTN 1\r | |
| 81 | .Cr3: CTYPE_UINTN 1\r | |
| 82 | .InitFlag: CTYPE_UINTN 1\r | |
| 83 | .CpuInfo: CTYPE_UINTN 1\r | |
| 84 | .NumApsExecuting: CTYPE_UINTN 1\r | |
| 85 | .CpuMpData: CTYPE_UINTN 1\r | |
| 86 | .InitializeFloatingPointUnits: CTYPE_UINTN 1\r | |
| 87 | .ModeTransitionMemory: CTYPE_UINT32 1\r | |
| 88 | .ModeTransitionSegment: CTYPE_UINT16 1\r | |
| 89 | .ModeHighMemory: CTYPE_UINT32 1\r | |
| 90 | .ModeHighSegment: CTYPE_UINT16 1\r | |
| 91 | .Enable5LevelPaging: CTYPE_BOOLEAN 1\r | |
| 92 | .SevEsIsEnabled: CTYPE_BOOLEAN 1\r | |
| 9c703bc0 | 93 | .SevSnpIsEnabled CTYPE_BOOLEAN 1\r |
| 2fba7d4e | 94 | .GhcbBase: CTYPE_UINTN 1\r |
| d4d7c9ad | 95 | .ExtTopoAvail: CTYPE_BOOLEAN 1\r |
| 2fba7d4e RN |
96 | endstruc\r |
| 97 | \r | |
| 283ab943 | 98 | MP_CPU_EXCHANGE_INFO_OFFSET equ (Flat32Start - RendezvousFunnelProcStart)\r |
| 2fba7d4e | 99 | %define MP_CPU_EXCHANGE_INFO_FIELD(Field) (MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO. %+ Field)\r |