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1 | ;------------------------------------------------------------------------------ ;\r |
2 | ; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>\r | |
3 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
4 | ;\r | |
5 | ; Module Name:\r | |
6 | ;\r | |
7 | ; MpEqu.inc\r | |
8 | ;\r | |
9 | ; Abstract:\r | |
10 | ;\r | |
11 | ; This is the equates file for Multiple Processor support\r | |
12 | ;\r | |
13 | ;-------------------------------------------------------------------------------\r | |
14 | %include "Nasm.inc"\r | |
15 | \r | |
16 | VacantFlag equ 00h\r | |
17 | NotVacantFlag equ 0ffh\r | |
18 | \r | |
19 | CPU_SWITCH_STATE_IDLE equ 0\r | |
20 | CPU_SWITCH_STATE_STORED equ 1\r | |
21 | CPU_SWITCH_STATE_LOADED equ 2\r | |
22 | \r | |
23 | ;\r | |
24 | ; Equivalent NASM structure of MP_ASSEMBLY_ADDRESS_MAP\r | |
25 | ;\r | |
26 | struc MP_ASSEMBLY_ADDRESS_MAP\r | |
27 | .RendezvousFunnelAddress CTYPE_UINTN 1\r | |
28 | .ModeEntryOffset CTYPE_UINTN 1\r | |
29 | .RendezvousFunnelSize CTYPE_UINTN 1\r | |
30 | .RelocateApLoopFuncAddress CTYPE_UINTN 1\r | |
31 | .RelocateApLoopFuncSize CTYPE_UINTN 1\r | |
32 | .ModeTransitionOffset CTYPE_UINTN 1\r | |
33 | .SwitchToRealSize CTYPE_UINTN 1\r | |
34 | .SwitchToRealOffset CTYPE_UINTN 1\r | |
35 | .SwitchToRealNoNxOffset CTYPE_UINTN 1\r | |
36 | .SwitchToRealPM16ModeOffset CTYPE_UINTN 1\r | |
37 | .SwitchToRealPM16ModeSize CTYPE_UINTN 1\r | |
38 | endstruc\r | |
39 | \r | |
40 | ;\r | |
41 | ; Equivalent NASM structure of IA32_DESCRIPTOR\r | |
42 | ;\r | |
43 | struc IA32_DESCRIPTOR\r | |
44 | .Limit CTYPE_UINT16 1\r | |
45 | .Base CTYPE_UINTN 1\r | |
46 | endstruc\r | |
47 | \r | |
48 | ;\r | |
49 | ; Equivalent NASM structure of CPU_EXCHANGE_ROLE_INFO\r | |
50 | ;\r | |
51 | struc CPU_EXCHANGE_ROLE_INFO\r | |
52 | ; State is defined as UINT8 in C header file\r | |
53 | ; Define it as UINTN here to guarantee the fields that follow State\r | |
54 | ; is naturally aligned. The structure layout doesn't change.\r | |
55 | .State CTYPE_UINTN 1\r | |
56 | .StackPointer CTYPE_UINTN 1\r | |
57 | .Gdtr CTYPE_UINT8 IA32_DESCRIPTOR_size\r | |
58 | .Idtr CTYPE_UINT8 IA32_DESCRIPTOR_size\r | |
59 | endstruc\r | |
60 | \r | |
61 | ;\r | |
62 | ; Equivalent NASM structure of CPU_INFO_IN_HOB\r | |
63 | ;\r | |
64 | struc CPU_INFO_IN_HOB\r | |
65 | .InitialApicId CTYPE_UINT32 1\r | |
66 | .ApicId CTYPE_UINT32 1\r | |
67 | .Health CTYPE_UINT32 1\r | |
68 | .ApTopOfStack CTYPE_UINT64 1\r | |
69 | endstruc\r | |
70 | \r | |
71 | ;\r | |
72 | ; Equivalent NASM structure of MP_CPU_EXCHANGE_INFO\r | |
73 | ;\r | |
74 | struc MP_CPU_EXCHANGE_INFO\r | |
75 | .Lock: CTYPE_UINTN 1\r | |
76 | .StackStart: CTYPE_UINTN 1\r | |
77 | .StackSize: CTYPE_UINTN 1\r | |
78 | .CFunction: CTYPE_UINTN 1\r | |
79 | .GdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size\r | |
80 | .IdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size\r | |
81 | .BufferStart: CTYPE_UINTN 1\r | |
82 | .ModeOffset: CTYPE_UINTN 1\r | |
83 | .ApIndex: CTYPE_UINTN 1\r | |
84 | .CodeSegment: CTYPE_UINTN 1\r | |
85 | .DataSegment: CTYPE_UINTN 1\r | |
86 | .EnableExecuteDisable: CTYPE_UINTN 1\r | |
87 | .Cr3: CTYPE_UINTN 1\r | |
88 | .InitFlag: CTYPE_UINTN 1\r | |
89 | .CpuInfo: CTYPE_UINTN 1\r | |
90 | .NumApsExecuting: CTYPE_UINTN 1\r | |
91 | .CpuMpData: CTYPE_UINTN 1\r | |
92 | .InitializeFloatingPointUnits: CTYPE_UINTN 1\r | |
93 | .ModeTransitionMemory: CTYPE_UINT32 1\r | |
94 | .ModeTransitionSegment: CTYPE_UINT16 1\r | |
95 | .ModeHighMemory: CTYPE_UINT32 1\r | |
96 | .ModeHighSegment: CTYPE_UINT16 1\r | |
97 | .Enable5LevelPaging: CTYPE_BOOLEAN 1\r | |
98 | .SevEsIsEnabled: CTYPE_BOOLEAN 1\r | |
99 | .GhcbBase: CTYPE_UINTN 1\r | |
100 | endstruc\r | |
101 | \r | |
102 | MP_CPU_EXCHANGE_INFO_OFFSET equ (SwitchToRealProcEnd - RendezvousFunnelProcStart)\r | |
103 | %define MP_CPU_EXCHANGE_INFO_FIELD(Field) (MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO. %+ Field)\r |