## @file\r
# MP Initialize Library instance for DXE driver.\r
#\r
-# Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
##\r
#\r
\r
[Sources.IA32]\r
- Ia32/MpEqu.inc\r
Ia32/MpFuncs.nasm\r
\r
[Sources.X64]\r
- X64/MpEqu.inc\r
X64/MpFuncs.nasm\r
\r
[Sources.common]\r
+ MpEqu.inc\r
DxeMpLib.c\r
MpLib.c\r
MpLib.h\r
+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
-; SPDX-License-Identifier: BSD-2-Clause-Patent\r
-;\r
-; Module Name:\r
-;\r
-; MpEqu.inc\r
-;\r
-; Abstract:\r
-;\r
-; This is the equates file for Multiple Processor support\r
-;\r
-;-------------------------------------------------------------------------------\r
-\r
-VacantFlag equ 00h\r
-NotVacantFlag equ 0ffh\r
-\r
-CPU_SWITCH_STATE_IDLE equ 0\r
-CPU_SWITCH_STATE_STORED equ 1\r
-CPU_SWITCH_STATE_LOADED equ 2\r
-\r
-LockLocation equ (SwitchToRealProcEnd - RendezvousFunnelProcStart)\r
-StackStartAddressLocation equ LockLocation + 04h\r
-StackSizeLocation equ LockLocation + 08h\r
-ApProcedureLocation equ LockLocation + 0Ch\r
-GdtrLocation equ LockLocation + 10h\r
-IdtrLocation equ LockLocation + 16h\r
-BufferStartLocation equ LockLocation + 1Ch\r
-ModeOffsetLocation equ LockLocation + 20h\r
-ApIndexLocation equ LockLocation + 24h\r
-CodeSegmentLocation equ LockLocation + 28h\r
-DataSegmentLocation equ LockLocation + 2Ch\r
-EnableExecuteDisableLocation equ LockLocation + 30h\r
-Cr3Location equ LockLocation + 34h\r
-InitFlagLocation equ LockLocation + 38h\r
-CpuInfoLocation equ LockLocation + 3Ch\r
-NumApsExecutingLocation equ LockLocation + 40h\r
-InitializeFloatingPointUnitsAddress equ LockLocation + 48h\r
-ModeTransitionMemoryLocation equ LockLocation + 4Ch\r
-ModeTransitionSegmentLocation equ LockLocation + 50h\r
-ModeHighMemoryLocation equ LockLocation + 52h\r
-ModeHighSegmentLocation equ LockLocation + 56h\r
-\r
mov fs, ax\r
mov gs, ax\r
\r
- mov si, BufferStartLocation\r
+ mov si, MP_CPU_EXCHANGE_INFO_FIELD (BufferStart)\r
mov ebx, [si]\r
\r
- mov si, DataSegmentLocation\r
+ mov si, MP_CPU_EXCHANGE_INFO_FIELD (DataSegment)\r
mov edx, [si]\r
\r
;\r
; Get start address of 32-bit code in low memory (<1MB)\r
;\r
- mov edi, ModeTransitionMemoryLocation\r
+ mov edi, MP_CPU_EXCHANGE_INFO_FIELD (ModeTransitionMemory)\r
\r
- mov si, GdtrLocation\r
+ mov si, MP_CPU_EXCHANGE_INFO_FIELD (GdtrProfile)\r
o32 lgdt [cs:si]\r
\r
- mov si, IdtrLocation\r
+ mov si, MP_CPU_EXCHANGE_INFO_FIELD (IdtrProfile)\r
o32 lidt [cs:si]\r
\r
;\r
mov esi, ebx\r
\r
mov edi, esi\r
- add edi, EnableExecuteDisableLocation\r
+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (EnableExecuteDisable)\r
cmp byte [edi], 0\r
jz SkipEnableExecuteDisable\r
\r
wrmsr\r
\r
mov edi, esi\r
- add edi, Cr3Location\r
+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (Cr3)\r
mov eax, dword [edi]\r
mov cr3, eax\r
\r
\r
SkipEnableExecuteDisable:\r
mov edi, esi\r
- add edi, InitFlagLocation\r
+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (InitFlag)\r
cmp dword [edi], 1 ; 1 == ApInitConfig\r
jnz GetApicId\r
\r
; Increment the number of APs executing here as early as possible\r
; This is decremented in C code when AP is finished executing\r
mov edi, esi\r
- add edi, NumApsExecutingLocation\r
+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (NumApsExecuting)\r
lock inc dword [edi]\r
\r
; AP init\r
mov edi, esi\r
- add edi, LockLocation\r
+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (Lock)\r
mov eax, NotVacantFlag\r
\r
mov edi, esi\r
- add edi, ApIndexLocation\r
+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (ApIndex)\r
mov ebx, 1\r
lock xadd dword [edi], ebx ; EBX = ApIndex++\r
inc ebx ; EBX is CpuNumber\r
\r
mov edi, esi\r
- add edi, StackSizeLocation\r
+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (StackSize)\r
mov eax, [edi]\r
mov ecx, ebx\r
inc ecx\r
mul ecx ; EAX = StackSize * (CpuNumber + 1)\r
mov edi, esi\r
- add edi, StackStartAddressLocation\r
+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (StackStart)\r
add eax, [edi]\r
mov esp, eax\r
jmp CProcedureInvoke\r
; Note that BSP may become an AP due to SwitchBsp()\r
;\r
xor ebx, ebx\r
- lea eax, [esi + CpuInfoLocation]\r
+ lea eax, [esi + MP_CPU_EXCHANGE_INFO_FIELD (CpuInfo)]\r
mov edi, [eax]\r
\r
GetNextProcNumber:\r
- cmp [edi], edx ; APIC ID match?\r
+ cmp dword [edi + CPU_INFO_IN_HOB.InitialApicId], edx ; APIC ID match?\r
jz ProgramStack\r
- add edi, 20\r
+ add edi, CPU_INFO_IN_HOB_size\r
inc ebx\r
jmp GetNextProcNumber\r
\r
ProgramStack:\r
- mov esp, [edi + 12]\r
+ mov esp, dword [edi + CPU_INFO_IN_HOB.ApTopOfStack]\r
\r
CProcedureInvoke:\r
push ebp ; push BIST data at top of AP stack\r
\r
push ebx ; Push ApIndex\r
mov eax, esi\r
- add eax, LockLocation\r
+ add eax, MP_CPU_EXCHANGE_INFO_OFFSET\r
push eax ; push address of exchange info data buffer\r
\r
mov edi, esi\r
- add edi, ApProcedureLocation\r
+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (CFunction)\r
mov eax, [edi]\r
\r
call eax ; Invoke C function\r
mov ebp,esp\r
\r
mov ebx, [ebp + 24h]\r
- mov dword [ebx], RendezvousFunnelProcStart\r
- mov dword [ebx + 4h], Flat32Start - RendezvousFunnelProcStart\r
- mov dword [ebx + 8h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
- mov dword [ebx + 0Ch], AsmRelocateApLoopStart\r
- mov dword [ebx + 10h], AsmRelocateApLoopEnd - AsmRelocateApLoopStart\r
- mov dword [ebx + 14h], Flat32Start - RendezvousFunnelProcStart\r
- mov dword [ebx + 18h], SwitchToRealProcEnd - SwitchToRealProcStart ; SwitchToRealSize\r
- mov dword [ebx + 1Ch], SwitchToRealProcStart - RendezvousFunnelProcStart ; SwitchToRealOffset\r
- mov dword [ebx + 20h], SwitchToRealProcStart - Flat32Start ; SwitchToRealNoNxOffset\r
- mov dword [ebx + 24h], 0 ; SwitchToRealPM16ModeOffset\r
- mov dword [ebx + 28h], 0 ; SwitchToRealPM16ModeSize\r
+ mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.RendezvousFunnelAddress], RendezvousFunnelProcStart\r
+ mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.ModeEntryOffset], Flat32Start - RendezvousFunnelProcStart\r
+ mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.RendezvousFunnelSize], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
+ mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddress], AsmRelocateApLoopStart\r
+ mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize], AsmRelocateApLoopEnd - AsmRelocateApLoopStart\r
+ mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset], Flat32Start - RendezvousFunnelProcStart\r
+ mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealSize], SwitchToRealProcEnd - SwitchToRealProcStart\r
+ mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealOffset], SwitchToRealProcStart - RendezvousFunnelProcStart\r
+ mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealNoNxOffset], SwitchToRealProcStart - Flat32Start\r
+ mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeOffset], 0\r
+ mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeSize], 0\r
\r
popad\r
ret\r
mov eax, cr0\r
push eax\r
\r
- sgdt [esi + 8]\r
- sidt [esi + 14]\r
+ sgdt [esi + CPU_EXCHANGE_ROLE_INFO.Gdtr]\r
+ sidt [esi + CPU_EXCHANGE_ROLE_INFO.Idtr]\r
\r
; Store the its StackPointer\r
- mov [esi + 4],esp\r
+ mov [esi + CPU_EXCHANGE_ROLE_INFO.StackPointer],esp\r
\r
; update its switch state to STORED\r
- mov byte [esi], CPU_SWITCH_STATE_STORED\r
+ mov byte [esi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE_STORED\r
\r
WaitForOtherStored:\r
; wait until the other CPU finish storing its state\r
- cmp byte [edi], CPU_SWITCH_STATE_STORED\r
+ cmp byte [edi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE_STORED\r
jz OtherStored\r
pause\r
jmp WaitForOtherStored\r
OtherStored:\r
; Since another CPU already stored its state, load them\r
; load GDTR value\r
- lgdt [edi + 8]\r
+ lgdt [edi + CPU_EXCHANGE_ROLE_INFO.Gdtr]\r
\r
; load IDTR value\r
- lidt [edi + 14]\r
+ lidt [edi + CPU_EXCHANGE_ROLE_INFO.Idtr]\r
\r
; load its future StackPointer\r
- mov esp, [edi + 4]\r
+ mov esp, [edi + CPU_EXCHANGE_ROLE_INFO.StackPointer]\r
\r
; update the other CPU's switch state to LOADED\r
- mov byte [edi], CPU_SWITCH_STATE_LOADED\r
+ mov byte [edi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE_LOADED\r
\r
WaitForOtherLoaded:\r
; wait until the other CPU finish loading new state,\r
; otherwise the data in stack may corrupt\r
- cmp byte [esi], CPU_SWITCH_STATE_LOADED\r
+ cmp byte [esi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE_LOADED\r
jz OtherLoaded\r
pause\r
jmp WaitForOtherLoaded\r
--- /dev/null
+;------------------------------------------------------------------------------ ;\r
+; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+; Module Name:\r
+;\r
+; MpEqu.inc\r
+;\r
+; Abstract:\r
+;\r
+; This is the equates file for Multiple Processor support\r
+;\r
+;-------------------------------------------------------------------------------\r
+%include "Nasm.inc"\r
+\r
+VacantFlag equ 00h\r
+NotVacantFlag equ 0ffh\r
+\r
+CPU_SWITCH_STATE_IDLE equ 0\r
+CPU_SWITCH_STATE_STORED equ 1\r
+CPU_SWITCH_STATE_LOADED equ 2\r
+\r
+;\r
+; Equivalent NASM structure of MP_ASSEMBLY_ADDRESS_MAP\r
+;\r
+struc MP_ASSEMBLY_ADDRESS_MAP\r
+ .RendezvousFunnelAddress CTYPE_UINTN 1\r
+ .ModeEntryOffset CTYPE_UINTN 1\r
+ .RendezvousFunnelSize CTYPE_UINTN 1\r
+ .RelocateApLoopFuncAddress CTYPE_UINTN 1\r
+ .RelocateApLoopFuncSize CTYPE_UINTN 1\r
+ .ModeTransitionOffset CTYPE_UINTN 1\r
+ .SwitchToRealSize CTYPE_UINTN 1\r
+ .SwitchToRealOffset CTYPE_UINTN 1\r
+ .SwitchToRealNoNxOffset CTYPE_UINTN 1\r
+ .SwitchToRealPM16ModeOffset CTYPE_UINTN 1\r
+ .SwitchToRealPM16ModeSize CTYPE_UINTN 1\r
+endstruc\r
+\r
+;\r
+; Equivalent NASM structure of IA32_DESCRIPTOR\r
+;\r
+struc IA32_DESCRIPTOR\r
+ .Limit CTYPE_UINT16 1\r
+ .Base CTYPE_UINTN 1\r
+endstruc\r
+\r
+;\r
+; Equivalent NASM structure of CPU_EXCHANGE_ROLE_INFO\r
+;\r
+struc CPU_EXCHANGE_ROLE_INFO\r
+ ; State is defined as UINT8 in C header file\r
+ ; Define it as UINTN here to guarantee the fields that follow State\r
+ ; is naturally aligned. The structure layout doesn't change.\r
+ .State CTYPE_UINTN 1\r
+ .StackPointer CTYPE_UINTN 1\r
+ .Gdtr CTYPE_UINT8 IA32_DESCRIPTOR_size\r
+ .Idtr CTYPE_UINT8 IA32_DESCRIPTOR_size\r
+endstruc\r
+\r
+;\r
+; Equivalent NASM structure of CPU_INFO_IN_HOB\r
+;\r
+struc CPU_INFO_IN_HOB\r
+ .InitialApicId CTYPE_UINT32 1\r
+ .ApicId CTYPE_UINT32 1\r
+ .Health CTYPE_UINT32 1\r
+ .ApTopOfStack CTYPE_UINT64 1\r
+endstruc\r
+\r
+;\r
+; Equivalent NASM structure of MP_CPU_EXCHANGE_INFO\r
+;\r
+struc MP_CPU_EXCHANGE_INFO\r
+ .Lock: CTYPE_UINTN 1\r
+ .StackStart: CTYPE_UINTN 1\r
+ .StackSize: CTYPE_UINTN 1\r
+ .CFunction: CTYPE_UINTN 1\r
+ .GdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size\r
+ .IdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size\r
+ .BufferStart: CTYPE_UINTN 1\r
+ .ModeOffset: CTYPE_UINTN 1\r
+ .ApIndex: CTYPE_UINTN 1\r
+ .CodeSegment: CTYPE_UINTN 1\r
+ .DataSegment: CTYPE_UINTN 1\r
+ .EnableExecuteDisable: CTYPE_UINTN 1\r
+ .Cr3: CTYPE_UINTN 1\r
+ .InitFlag: CTYPE_UINTN 1\r
+ .CpuInfo: CTYPE_UINTN 1\r
+ .NumApsExecuting: CTYPE_UINTN 1\r
+ .CpuMpData: CTYPE_UINTN 1\r
+ .InitializeFloatingPointUnits: CTYPE_UINTN 1\r
+ .ModeTransitionMemory: CTYPE_UINT32 1\r
+ .ModeTransitionSegment: CTYPE_UINT16 1\r
+ .ModeHighMemory: CTYPE_UINT32 1\r
+ .ModeHighSegment: CTYPE_UINT16 1\r
+ .Enable5LevelPaging: CTYPE_BOOLEAN 1\r
+ .SevEsIsEnabled: CTYPE_BOOLEAN 1\r
+ .GhcbBase: CTYPE_UINTN 1\r
+endstruc\r
+\r
+MP_CPU_EXCHANGE_INFO_OFFSET equ (SwitchToRealProcEnd - RendezvousFunnelProcStart)\r
+%define MP_CPU_EXCHANGE_INFO_FIELD(Field) (MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO. %+ Field)\r
## @file\r
# MP Initialize Library instance for PEI driver.\r
#\r
-# Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
##\r
#\r
\r
[Sources.IA32]\r
- Ia32/MpEqu.inc\r
Ia32/MpFuncs.nasm\r
\r
[Sources.X64]\r
- X64/MpEqu.inc\r
X64/MpFuncs.nasm\r
\r
[Sources.common]\r
+ MpEqu.inc\r
PeiMpLib.c\r
MpLib.c\r
MpLib.h\r
+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
-; SPDX-License-Identifier: BSD-2-Clause-Patent\r
-;\r
-; Module Name:\r
-;\r
-; MpEqu.inc\r
-;\r
-; Abstract:\r
-;\r
-; This is the equates file for Multiple Processor support\r
-;\r
-;-------------------------------------------------------------------------------\r
-\r
-VacantFlag equ 00h\r
-NotVacantFlag equ 0ffh\r
-\r
-CPU_SWITCH_STATE_IDLE equ 0\r
-CPU_SWITCH_STATE_STORED equ 1\r
-CPU_SWITCH_STATE_LOADED equ 2\r
-\r
-LockLocation equ (SwitchToRealProcEnd - RendezvousFunnelProcStart)\r
-StackStartAddressLocation equ LockLocation + 08h\r
-StackSizeLocation equ LockLocation + 10h\r
-ApProcedureLocation equ LockLocation + 18h\r
-GdtrLocation equ LockLocation + 20h\r
-IdtrLocation equ LockLocation + 2Ah\r
-BufferStartLocation equ LockLocation + 34h\r
-ModeOffsetLocation equ LockLocation + 3Ch\r
-ApIndexLocation equ LockLocation + 44h\r
-CodeSegmentLocation equ LockLocation + 4Ch\r
-DataSegmentLocation equ LockLocation + 54h\r
-EnableExecuteDisableLocation equ LockLocation + 5Ch\r
-Cr3Location equ LockLocation + 64h\r
-InitFlagLocation equ LockLocation + 6Ch\r
-CpuInfoLocation equ LockLocation + 74h\r
-NumApsExecutingLocation equ LockLocation + 7Ch\r
-InitializeFloatingPointUnitsAddress equ LockLocation + 8Ch\r
-ModeTransitionMemoryLocation equ LockLocation + 94h\r
-ModeTransitionSegmentLocation equ LockLocation + 98h\r
-ModeHighMemoryLocation equ LockLocation + 9Ah\r
-ModeHighSegmentLocation equ LockLocation + 9Eh\r
-Enable5LevelPagingLocation equ LockLocation + 0A0h\r
-SevEsIsEnabledLocation equ LockLocation + 0A1h\r
-GhcbBaseLocation equ LockLocation + 0A2h\r
mov fs, ax\r
mov gs, ax\r
\r
- mov si, BufferStartLocation\r
+ mov si, MP_CPU_EXCHANGE_INFO_FIELD (BufferStart)\r
mov ebx, [si]\r
\r
- mov si, DataSegmentLocation\r
+ mov si, MP_CPU_EXCHANGE_INFO_FIELD (DataSegment)\r
mov edx, [si]\r
\r
;\r
; Get start address of 32-bit code in low memory (<1MB)\r
;\r
- mov edi, ModeTransitionMemoryLocation\r
+ mov edi, MP_CPU_EXCHANGE_INFO_FIELD (ModeTransitionMemory)\r
\r
- mov si, GdtrLocation\r
+ mov si, MP_CPU_EXCHANGE_INFO_FIELD (GdtrProfile)\r
o32 lgdt [cs:si]\r
\r
- mov si, IdtrLocation\r
+ mov si, MP_CPU_EXCHANGE_INFO_FIELD (IdtrProfile)\r
o32 lidt [cs:si]\r
\r
;\r
;\r
; Enable execute disable bit\r
;\r
- mov esi, EnableExecuteDisableLocation\r
+ mov esi, MP_CPU_EXCHANGE_INFO_FIELD (EnableExecuteDisable)\r
cmp byte [ebx + esi], 0\r
jz SkipEnableExecuteDisableBit\r
\r
mov eax, cr4\r
bts eax, 5\r
\r
- mov esi, Enable5LevelPagingLocation\r
+ mov esi, MP_CPU_EXCHANGE_INFO_FIELD (Enable5LevelPaging)\r
cmp byte [ebx + esi], 0\r
jz SkipEnable5LevelPaging\r
\r
;\r
; Load page table\r
;\r
- mov esi, Cr3Location ; Save CR3 in ecx\r
+ mov esi, MP_CPU_EXCHANGE_INFO_FIELD (Cr3) ; Save CR3 in ecx\r
mov ecx, [ebx + esi]\r
mov cr3, ecx ; Load CR3\r
\r
;\r
; Far jump to 64-bit code\r
;\r
- mov edi, ModeHighMemoryLocation\r
+ mov edi, MP_CPU_EXCHANGE_INFO_FIELD (ModeHighMemory)\r
add edi, ebx\r
jmp far [edi]\r
\r
BITS 64\r
LongModeStart:\r
mov esi, ebx\r
- lea edi, [esi + InitFlagLocation]\r
+ lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (InitFlag)]\r
cmp qword [edi], 1 ; ApInitConfig\r
jnz GetApicId\r
\r
; Increment the number of APs executing here as early as possible\r
; This is decremented in C code when AP is finished executing\r
mov edi, esi\r
- add edi, NumApsExecutingLocation\r
+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (NumApsExecuting)\r
lock inc dword [edi]\r
\r
; AP init\r
mov edi, esi\r
- add edi, LockLocation\r
+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (Lock)\r
mov rax, NotVacantFlag\r
\r
mov edi, esi\r
- add edi, ApIndexLocation\r
+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (ApIndex)\r
mov ebx, 1\r
lock xadd dword [edi], ebx ; EBX = ApIndex++\r
inc ebx ; EBX is CpuNumber\r
\r
; program stack\r
mov edi, esi\r
- add edi, StackSizeLocation\r
+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (StackSize)\r
mov eax, dword [edi]\r
mov ecx, ebx\r
inc ecx\r
mul ecx ; EAX = StackSize * (CpuNumber + 1)\r
mov edi, esi\r
- add edi, StackStartAddressLocation\r
+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (StackStart)\r
add rax, qword [edi]\r
mov rsp, rax\r
\r
- lea edi, [esi + SevEsIsEnabledLocation]\r
+ lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (SevEsIsEnabled)]\r
cmp byte [edi], 1 ; SevEsIsEnabled\r
jne CProcedureInvoke\r
\r
mov ecx, ebx\r
mul ecx ; EAX = SIZE_4K * 2 * CpuNumber\r
mov edi, esi\r
- add edi, GhcbBaseLocation\r
+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (GhcbBase)\r
add rax, qword [edi]\r
mov rdx, rax\r
shr rdx, 32\r
jmp CProcedureInvoke\r
\r
GetApicId:\r
- lea edi, [esi + SevEsIsEnabledLocation]\r
+ lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (SevEsIsEnabled)]\r
cmp byte [edi], 1 ; SevEsIsEnabled\r
jne DoCpuid\r
\r
; Note that BSP may become an AP due to SwitchBsp()\r
;\r
xor ebx, ebx\r
- lea eax, [esi + CpuInfoLocation]\r
+ lea eax, [esi + MP_CPU_EXCHANGE_INFO_FIELD (CpuInfo)]\r
mov rdi, [eax]\r
\r
GetNextProcNumber:\r
- cmp dword [rdi], edx ; APIC ID match?\r
+ cmp dword [rdi + CPU_INFO_IN_HOB.InitialApicId], edx ; APIC ID match?\r
jz ProgramStack\r
- add rdi, 20\r
+ add rdi, CPU_INFO_IN_HOB_size\r
inc ebx\r
jmp GetNextProcNumber\r
\r
ProgramStack:\r
- mov rsp, qword [rdi + 12]\r
+ mov rsp, qword [rdi + CPU_INFO_IN_HOB.ApTopOfStack]\r
\r
CProcedureInvoke:\r
push rbp ; Push BIST data at top of AP stack\r
push rbp\r
mov rbp, rsp\r
\r
- mov rax, qword [esi + InitializeFloatingPointUnitsAddress]\r
+ mov rax, qword [esi + MP_CPU_EXCHANGE_INFO_FIELD (InitializeFloatingPointUnits)]\r
sub rsp, 20h\r
call rax ; Call assembly function to initialize FPU per UEFI spec\r
add rsp, 20h\r
\r
mov edx, ebx ; edx is ApIndex\r
mov ecx, esi\r
- add ecx, LockLocation ; rcx is address of exchange info data buffer\r
+ add ecx, MP_CPU_EXCHANGE_INFO_OFFSET ; rcx is address of exchange info data buffer\r
\r
mov edi, esi\r
- add edi, ApProcedureLocation\r
+ add edi, MP_CPU_EXCHANGE_INFO_FIELD (CFunction)\r
mov rax, qword [edi]\r
\r
sub rsp, 20h\r
global ASM_PFX(AsmGetAddressMap)\r
ASM_PFX(AsmGetAddressMap):\r
lea rax, [ASM_PFX(RendezvousFunnelProc)]\r
- mov qword [rcx], rax\r
- mov qword [rcx + 8h], LongModeStart - RendezvousFunnelProcStart\r
- mov qword [rcx + 10h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
+ mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RendezvousFunnelAddress], rax\r
+ mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.ModeEntryOffset], LongModeStart - RendezvousFunnelProcStart\r
+ mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RendezvousFunnelSize], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
lea rax, [ASM_PFX(AsmRelocateApLoop)]\r
- mov qword [rcx + 18h], rax\r
- mov qword [rcx + 20h], AsmRelocateApLoopEnd - AsmRelocateApLoopStart\r
- mov qword [rcx + 28h], Flat32Start - RendezvousFunnelProcStart\r
- mov qword [rcx + 30h], SwitchToRealProcEnd - SwitchToRealProcStart ; SwitchToRealSize\r
- mov qword [rcx + 38h], SwitchToRealProcStart - RendezvousFunnelProcStart ; SwitchToRealOffset\r
- mov qword [rcx + 40h], SwitchToRealProcStart - Flat32Start ; SwitchToRealNoNxOffset\r
- mov qword [rcx + 48h], PM16Mode - RendezvousFunnelProcStart ; SwitchToRealPM16ModeOffset\r
- mov qword [rcx + 50h], SwitchToRealProcEnd - PM16Mode ; SwitchToRealPM16ModeSize\r
+ mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddress], rax\r
+ mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize], AsmRelocateApLoopEnd - AsmRelocateApLoopStart\r
+ mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset], Flat32Start - RendezvousFunnelProcStart\r
+ mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealSize], SwitchToRealProcEnd - SwitchToRealProcStart\r
+ mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealOffset], SwitchToRealProcStart - RendezvousFunnelProcStart\r
+ mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealNoNxOffset], SwitchToRealProcStart - Flat32Start\r
+ mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeOffset], PM16Mode - RendezvousFunnelProcStart\r
+ mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeSize], SwitchToRealProcEnd - PM16Mode\r
ret\r
\r
;-------------------------------------------------------------------------------------\r
\r
;Store EFLAGS, GDTR and IDTR regiter to stack\r
pushfq\r
- sgdt [rsi + 16]\r
- sidt [rsi + 26]\r
+ sgdt [rsi + CPU_EXCHANGE_ROLE_INFO.Gdtr]\r
+ sidt [rsi + CPU_EXCHANGE_ROLE_INFO.Idtr]\r
\r
; Store the its StackPointer\r
- mov [rsi + 8], rsp\r
+ mov [rsi + CPU_EXCHANGE_ROLE_INFO.StackPointer], rsp\r
\r
; update its switch state to STORED\r
- mov byte [rsi], CPU_SWITCH_STATE_STORED\r
+ mov byte [rsi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE_STORED\r
\r
WaitForOtherStored:\r
; wait until the other CPU finish storing its state\r
- cmp byte [rdi], CPU_SWITCH_STATE_STORED\r
+ cmp byte [rdi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE_STORED\r
jz OtherStored\r
pause\r
jmp WaitForOtherStored\r
OtherStored:\r
; Since another CPU already stored its state, load them\r
; load GDTR value\r
- lgdt [rdi + 16]\r
+ lgdt [rdi + CPU_EXCHANGE_ROLE_INFO.Gdtr]\r
\r
; load IDTR value\r
- lidt [rdi + 26]\r
+ lidt [rdi + CPU_EXCHANGE_ROLE_INFO.Idtr]\r
\r
; load its future StackPointer\r
- mov rsp, [rdi + 8]\r
+ mov rsp, [rdi + CPU_EXCHANGE_ROLE_INFO.StackPointer]\r
\r
; update the other CPU's switch state to LOADED\r
- mov byte [rdi], CPU_SWITCH_STATE_LOADED\r
+ mov byte [rdi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE_LOADED\r
\r
WaitForOtherLoaded:\r
; wait until the other CPU finish loading new state,\r
; otherwise the data in stack may corrupt\r
- cmp byte [rsi], CPU_SWITCH_STATE_LOADED\r
+ cmp byte [rsi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE_LOADED\r
jz OtherLoaded\r
pause\r
jmp WaitForOtherLoaded\r
projects / mirror_edk2.git / commitdiff