[mirror_edk2.git] / UefiCpuPkg / Library / MpInitLib / X64 / MpFuncs.nasm

;------------------------------------------------------------------------------ ;\r
; Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution.  The full text of the license may be found at\r
; http://opensource.org/licenses/bsd-license.php.\r
;\r
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
;\r
; Module Name:\r
;\r
;   MpFuncs.nasm\r
;\r
; Abstract:\r
;\r
;   This is the assembly code for MP support\r
;\r
;-------------------------------------------------------------------------------\r
\r
%include "MpEqu.inc"\r
extern ASM_PFX(InitializeFloatingPointUnits)\r
\r
DEFAULT REL\r
\r
SECTION .text\r
\r
;-------------------------------------------------------------------------------------\r
;RendezvousFunnelProc  procedure follows. All APs execute their procedure. This\r
;procedure serializes all the AP processors through an Init sequence. It must be\r
;noted that APs arrive here very raw...ie: real mode, no stack.\r
;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC\r
;IS IN MACHINE CODE.\r
;-------------------------------------------------------------------------------------\r
global ASM_PFX(RendezvousFunnelProc)\r
ASM_PFX(RendezvousFunnelProc):\r
RendezvousFunnelProcStart:\r
; At this point CS = 0x(vv00) and ip= 0x0.\r
; Save BIST information to ebp firstly\r
\r
BITS 16\r
    mov        ebp, eax                        ; Save BIST information\r
\r
    mov        ax, cs\r
    mov        ds, ax\r
    mov        es, ax\r
    mov        ss, ax\r
    xor        ax, ax\r
    mov        fs, ax\r
    mov        gs, ax\r
\r
    mov        si,  BufferStartLocation\r
    mov        ebx, [si]\r
\r
    mov        si,  DataSegmentLocation\r
    mov        edx, [si]\r
\r
    ;\r
    ; Get start address of 32-bit code in low memory (<1MB)\r
    ;\r
    mov        edi, ModeTransitionMemoryLocation\r
\r
    mov        si, GdtrLocation\r
o32 lgdt       [cs:si]\r
\r
    mov        si, IdtrLocation\r
o32 lidt       [cs:si]\r
\r
    ;\r
    ; Switch to protected mode\r
    ;\r
    mov        eax, cr0                    ; Get control register 0\r
    or         eax, 000000003h             ; Set PE bit (bit #0) & MP\r
    mov        cr0, eax\r
\r
    ; Switch to 32-bit code (>1MB)\r
o32 jmp far    [cs:di]\r
\r
;\r
; Following code must be copied to memory with type of EfiBootServicesCode.\r
; This is required if NX is enabled for EfiBootServicesCode of memory.\r
;\r
BITS 32\r
Flat32Start:                                   ; protected mode entry point\r
    mov        ds, dx\r
    mov        es, dx\r
    mov        fs, dx\r
    mov        gs, dx\r
    mov        ss, dx\r
\r
    ;\r
    ; Enable execute disable bit\r
    ;\r
    mov        esi, EnableExecuteDisableLocation\r
    cmp        byte [ebx + esi], 0\r
    jz         SkipEnableExecuteDisableBit\r
\r
    mov        ecx, 0c0000080h             ; EFER MSR number\r
    rdmsr                                  ; Read EFER\r
    bts        eax, 11                     ; Enable Execute Disable Bit\r
    wrmsr                                  ; Write EFER\r
\r
SkipEnableExecuteDisableBit:\r
    ;\r
    ; Enable PAE\r
    ;\r
    mov        eax, cr4\r
    bts        eax, 5\r
    mov        cr4, eax\r
\r
    ;\r
    ; Load page table\r
    ;\r
    mov        esi, Cr3Location             ; Save CR3 in ecx\r
    mov        ecx, [ebx + esi]\r
    mov        cr3, ecx                    ; Load CR3\r
\r
    ;\r
    ; Enable long mode\r
    ;\r
    mov        ecx, 0c0000080h             ; EFER MSR number\r
    rdmsr                                  ; Read EFER\r
    bts        eax, 8                      ; Set LME=1\r
    wrmsr                                  ; Write EFER\r
\r
    ;\r
    ; Enable paging\r
    ;\r
    mov        eax, cr0                    ; Read CR0\r
    bts        eax, 31                     ; Set PG=1\r
    mov        cr0, eax                    ; Write CR0\r
\r
    ;\r
    ; Far jump to 64-bit code\r
    ;\r
    mov        edi, ModeHighMemoryLocation\r
    add        edi, ebx\r
    jmp far    [edi]\r
\r
BITS 64\r
LongModeStart:\r
    mov        esi, ebx\r
    lea        edi, [esi + InitFlagLocation]\r
    cmp        qword [edi], 1       ; ApInitConfig\r
    jnz        GetApicId\r
\r
    ; Increment the number of APs executing here as early as possible\r
    ; This is decremented in C code when AP is finished executing\r
    mov        edi, esi\r
    add        edi, NumApsExecutingLocation\r
    lock inc   dword [edi]\r
\r
    ; AP init\r
    mov        edi, esi\r
    add        edi, LockLocation\r
    mov        rax, NotVacantFlag\r
\r
TestLock:\r
    xchg       qword [edi], rax\r
    cmp        rax, NotVacantFlag\r
    jz         TestLock\r
\r
    lea        ecx, [esi + ApIndexLocation]\r
    inc        dword [ecx]\r
    mov        ebx, [ecx]\r
\r
Releaselock:\r
    mov        rax, VacantFlag\r
    xchg       qword [edi], rax\r
    ; program stack\r
    mov        edi, esi\r
    add        edi, StackSizeLocation\r
    mov        eax, dword [edi]\r
    mov        ecx, ebx\r
    inc        ecx\r
    mul        ecx                               ; EAX = StackSize * (CpuNumber + 1)\r
    mov        edi, esi\r
    add        edi, StackStartAddressLocation\r
    add        rax, qword [edi]\r
    mov        rsp, rax\r
    jmp        CProcedureInvoke\r
\r
GetApicId:\r
    mov        eax, 0\r
    cpuid\r
    cmp        eax, 0bh\r
    jb         NoX2Apic             ; CPUID level below CPUID_EXTENDED_TOPOLOGY\r
\r
    mov        eax, 0bh\r
    xor        ecx, ecx\r
    cpuid\r
    test       ebx, 0ffffh\r
    jz         NoX2Apic             ; CPUID.0BH:EBX[15:0] is zero\r
\r
    ; Processor is x2APIC capable; 32-bit x2APIC ID is already in EDX\r
    jmp        GetProcessorNumber\r
\r
NoX2Apic:\r
    ; Processor is not x2APIC capable, so get 8-bit APIC ID\r
    mov        eax, 1\r
    cpuid\r
    shr        ebx, 24\r
    mov        edx, ebx\r
\r
GetProcessorNumber:\r
    ;\r
    ; Get processor number for this AP\r
    ; Note that BSP may become an AP due to SwitchBsp()\r
    ;\r
    xor         ebx, ebx\r
    lea         eax, [esi + CpuInfoLocation]\r
    mov         edi, [eax]\r
\r
GetNextProcNumber:\r
    cmp         dword [edi], edx                      ; APIC ID match?\r
    jz          ProgramStack\r
    add         edi, 20\r
    inc         ebx\r
    jmp         GetNextProcNumber    \r
\r
ProgramStack:\r
    mov         rsp, qword [edi + 12]\r
\r
CProcedureInvoke:\r
    push       rbp               ; Push BIST data at top of AP stack\r
    xor        rbp, rbp          ; Clear ebp for call stack trace\r
    push       rbp\r
    mov        rbp, rsp\r
\r
    mov        rax, qword [esi + InitializeFloatingPointUnitsAddress]\r
    sub        rsp, 20h\r
    call       rax               ; Call assembly function to initialize FPU per UEFI spec\r
    add        rsp, 20h\r
\r
    mov        edx, ebx          ; edx is ApIndex\r
    mov        ecx, esi\r
    add        ecx, LockLocation ; rcx is address of exchange info data buffer\r
\r
    mov        edi, esi\r
    add        edi, ApProcedureLocation\r
    mov        rax, qword [edi]\r
\r
    sub        rsp, 20h\r
    call       rax               ; Invoke C function\r
    add        rsp, 20h\r
    jmp        $                 ; Should never reach here\r
\r
RendezvousFunnelProcEnd:\r
\r
;-------------------------------------------------------------------------------------\r
;  AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfApStack, CountTofinish);\r
;-------------------------------------------------------------------------------------\r
global ASM_PFX(AsmRelocateApLoop)\r
ASM_PFX(AsmRelocateApLoop):\r
AsmRelocateApLoopStart:\r
    cli                          ; Disable interrupt before switching to 32-bit mode\r
    mov        rax, [rsp + 40]   ; CountTofinish\r
    lock dec   dword [rax]       ; (*CountTofinish)--\r
    mov        rsp, r9\r
    push       rcx\r
    push       rdx\r
\r
    lea        rsi, [PmEntry]    ; rsi <- The start address of transition code\r
\r
    push       r8\r
    push       rsi\r
    DB         0x48\r
    retf\r
BITS 32\r
PmEntry:\r
    mov        eax, cr0\r
    btr        eax, 31           ; Clear CR0.PG\r
    mov        cr0, eax          ; Disable paging and caches\r
\r
    mov        ebx, edx          ; Save EntryPoint to rbx, for rdmsr will overwrite rdx\r
    mov        ecx, 0xc0000080\r
    rdmsr\r
    and        ah, ~ 1           ; Clear LME\r
    wrmsr\r
    mov        eax, cr4\r
    and        al, ~ (1 << 5)    ; Clear PAE\r
    mov        cr4, eax\r
\r
    pop        edx\r
    add        esp, 4\r
    pop        ecx,\r
    add        esp, 4\r
    cmp        cl, 1              ; Check mwait-monitor support\r
    jnz        HltLoop\r
    mov        ebx, edx           ; Save C-State to ebx\r
MwaitLoop:\r
    cli\r
    mov        eax, esp           ; Set Monitor Address\r
    xor        ecx, ecx           ; ecx = 0\r
    xor        edx, edx           ; edx = 0\r
    monitor\r
    mov        eax, ebx           ; Mwait Cx, Target C-State per eax[7:4]\r
    shl        eax, 4\r
    mwait\r
    jmp        MwaitLoop\r
HltLoop:\r
    cli\r
    hlt\r
    jmp        HltLoop\r
BITS 64\r
AsmRelocateApLoopEnd:\r
\r
;-------------------------------------------------------------------------------------\r
;  AsmGetAddressMap (&AddressMap);\r
;-------------------------------------------------------------------------------------\r
global ASM_PFX(AsmGetAddressMap)\r
ASM_PFX(AsmGetAddressMap):\r
    lea        rax, [ASM_PFX(RendezvousFunnelProc)]\r
    mov        qword [rcx], rax\r
    mov        qword [rcx +  8h], LongModeStart - RendezvousFunnelProcStart\r
    mov        qword [rcx + 10h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
    lea        rax, [ASM_PFX(AsmRelocateApLoop)]\r
    mov        qword [rcx + 18h], rax\r
    mov        qword [rcx + 20h], AsmRelocateApLoopEnd - AsmRelocateApLoopStart\r
    mov        qword [rcx + 28h], Flat32Start - RendezvousFunnelProcStart\r
    ret\r
\r
;-------------------------------------------------------------------------------------\r
;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is\r
;about to become an AP. It switches its stack with the current AP.\r
;AsmExchangeRole (IN   CPU_EXCHANGE_INFO    *MyInfo, IN   CPU_EXCHANGE_INFO    *OthersInfo);\r
;-------------------------------------------------------------------------------------\r
global ASM_PFX(AsmExchangeRole)\r
ASM_PFX(AsmExchangeRole):\r
    ; DO NOT call other functions in this function, since 2 CPU may use 1 stack\r
    ; at the same time. If 1 CPU try to call a function, stack will be corrupted.\r
\r
    push       rax\r
    push       rbx\r
    push       rcx\r
    push       rdx\r
    push       rsi\r
    push       rdi\r
    push       rbp\r
    push       r8\r
    push       r9\r
    push       r10\r
    push       r11\r
    push       r12\r
    push       r13\r
    push       r14\r
    push       r15\r
\r
    mov        rax, cr0\r
    push       rax\r
\r
    mov        rax, cr4\r
    push       rax\r
\r
    ; rsi contains MyInfo pointer\r
    mov        rsi, rcx\r
\r
    ; rdi contains OthersInfo pointer\r
    mov        rdi, rdx\r
\r
    ;Store EFLAGS, GDTR and IDTR regiter to stack\r
    pushfq\r
    sgdt       [rsi + 16]\r
    sidt       [rsi + 26]\r
\r
    ; Store the its StackPointer\r
    mov        [rsi + 8], rsp\r
\r
    ; update its switch state to STORED\r
    mov        byte [rsi], CPU_SWITCH_STATE_STORED\r
\r
WaitForOtherStored:\r
    ; wait until the other CPU finish storing its state\r
    cmp        byte [rdi], CPU_SWITCH_STATE_STORED\r
    jz         OtherStored\r
    pause\r
    jmp        WaitForOtherStored\r
\r
OtherStored:\r
    ; Since another CPU already stored its state, load them\r
    ; load GDTR value\r
    lgdt       [rdi + 16]\r
\r
    ; load IDTR value\r
    lidt       [rdi + 26]\r
\r
    ; load its future StackPointer\r
    mov        rsp, [rdi + 8]\r
\r
    ; update the other CPU's switch state to LOADED\r
    mov        byte [rdi], CPU_SWITCH_STATE_LOADED\r
\r
WaitForOtherLoaded:\r
    ; wait until the other CPU finish loading new state,\r
    ; otherwise the data in stack may corrupt\r
    cmp        byte [rsi], CPU_SWITCH_STATE_LOADED\r
    jz         OtherLoaded\r
    pause\r
    jmp        WaitForOtherLoaded\r
\r
OtherLoaded:\r
    ; since the other CPU already get the data it want, leave this procedure\r
    popfq\r
\r
    pop        rax\r
    mov        cr4, rax\r
\r
    pop        rax\r
    mov        cr0, rax\r
\r
    pop        r15\r
    pop        r14\r
    pop        r13\r
    pop        r12\r
    pop        r11\r
    pop        r10\r
    pop        r9\r
    pop        r8\r
    pop        rbp\r
    pop        rdi\r
    pop        rsi\r
    pop        rdx\r
    pop        rcx\r
    pop        rbx\r
    pop        rax\r
\r
    ret\r
Commit	Line	Data
d94e5f67	1	;------------------------------------------------------------------------------ ;\r
a7bbe9d2	2	; Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
d94e5f67 JF	3	; This program and the accompanying materials\r
	4	; are licensed and made available under the terms and conditions of the BSD License\r
	5	; which accompanies this distribution. The full text of the license may be found at\r
	6	; http://opensource.org/licenses/bsd-license.php.\r
	7	;\r
	8	; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	9	; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	10	;\r
	11	; Module Name:\r
	12	;\r
	13	; MpFuncs.nasm\r
	14	;\r
	15	; Abstract:\r
	16	;\r
	17	; This is the assembly code for MP support\r
	18	;\r
	19	;-------------------------------------------------------------------------------\r
	20	\r
	21	%include "MpEqu.inc"\r
	22	extern ASM_PFX(InitializeFloatingPointUnits)\r
	23	\r
	24	DEFAULT REL\r
	25	\r
	26	SECTION .text\r
	27	\r
	28	;-------------------------------------------------------------------------------------\r
	29	;RendezvousFunnelProc procedure follows. All APs execute their procedure. This\r
	30	;procedure serializes all the AP processors through an Init sequence. It must be\r
	31	;noted that APs arrive here very raw...ie: real mode, no stack.\r
	32	;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC\r
	33	;IS IN MACHINE CODE.\r
	34	;-------------------------------------------------------------------------------------\r
	35	global ASM_PFX(RendezvousFunnelProc)\r
	36	ASM_PFX(RendezvousFunnelProc):\r
	37	RendezvousFunnelProcStart:\r
	38	; At this point CS = 0x(vv00) and ip= 0x0.\r
	39	; Save BIST information to ebp firstly\r
	40	\r
	41	BITS 16\r
	42	mov ebp, eax ; Save BIST information\r
	43	\r
	44	mov ax, cs\r
	45	mov ds, ax\r
	46	mov es, ax\r
	47	mov ss, ax\r
	48	xor ax, ax\r
	49	mov fs, ax\r
	50	mov gs, ax\r
	51	\r
	52	mov si, BufferStartLocation\r
	53	mov ebx, [si]\r
	54	\r
f32bfe6d JW	55	mov si, DataSegmentLocation\r
	56	mov edx, [si]\r
	57	\r
	58	;\r
	59	; Get start address of 32-bit code in low memory (<1MB)\r
	60	;\r
	61	mov edi, ModeTransitionMemoryLocation\r
d94e5f67 JF	62	\r
	63	mov si, GdtrLocation\r
	64	o32 lgdt [cs:si]\r
	65	\r
	66	mov si, IdtrLocation\r
	67	o32 lidt [cs:si]\r
	68	\r
f32bfe6d JW	69	;\r
	70	; Switch to protected mode\r
	71	;\r
	72	mov eax, cr0 ; Get control register 0\r
	73	or eax, 000000003h ; Set PE bit (bit #0) & MP\r
	74	mov cr0, eax\r
	75	\r
	76	; Switch to 32-bit code (>1MB)\r
	77	o32 jmp far [cs:di]\r
	78	\r
	79	;\r
	80	; Following code must be copied to memory with type of EfiBootServicesCode.\r
	81	; This is required if NX is enabled for EfiBootServicesCode of memory.\r
	82	;\r
	83	BITS 32\r
	84	Flat32Start: ; protected mode entry point\r
	85	mov ds, dx\r
	86	mov es, dx\r
	87	mov fs, dx\r
	88	mov gs, dx\r
	89	mov ss, dx\r
5c66d125 JF	90	\r
	91	;\r
	92	; Enable execute disable bit\r
	93	;\r
f32bfe6d JW	94	mov esi, EnableExecuteDisableLocation\r
	95	cmp byte [ebx + esi], 0\r
	96	jz SkipEnableExecuteDisableBit\r
	97	\r
5c66d125 JF	98	mov ecx, 0c0000080h ; EFER MSR number\r
	99	rdmsr ; Read EFER\r
	100	bts eax, 11 ; Enable Execute Disable Bit\r
	101	wrmsr ; Write EFER\r
	102	\r
	103	SkipEnableExecuteDisableBit:\r
f32bfe6d JW	104	;\r
	105	; Enable PAE\r
	106	;\r
d94e5f67 JF	107	mov eax, cr4\r
	108	bts eax, 5\r
	109	mov cr4, eax\r
	110	\r
f32bfe6d JW	111	;\r
	112	; Load page table\r
	113	;\r
	114	mov esi, Cr3Location ; Save CR3 in ecx\r
	115	mov ecx, [ebx + esi]\r
d94e5f67 JF	116	mov cr3, ecx ; Load CR3\r
d94e5f67 JF	117	\r
f32bfe6d JW	118	;\r
	119	; Enable long mode\r
	120	;\r
d94e5f67 JF	121	mov ecx, 0c0000080h ; EFER MSR number\r
	122	rdmsr ; Read EFER\r
	123	bts eax, 8 ; Set LME=1\r
	124	wrmsr ; Write EFER\r
	125	\r
f32bfe6d JW	126	;\r
	127	; Enable paging\r
	128	;\r
d94e5f67 JF	129	mov eax, cr0 ; Read CR0\r
	130	bts eax, 31 ; Set PG=1\r
	131	mov cr0, eax ; Write CR0\r
	132	\r
f32bfe6d JW	133	;\r
	134	; Far jump to 64-bit code\r
	135	;\r
	136	mov edi, ModeHighMemoryLocation\r
	137	add edi, ebx\r
	138	jmp far [edi]\r
	139	\r
d94e5f67 JF	140	BITS 64\r
d94e5f67 JF	141	LongModeStart:\r
845c5be1 JF	142	mov esi, ebx\r
	143	lea edi, [esi + InitFlagLocation]\r
	144	cmp qword [edi], 1 ; ApInitConfig\r
	145	jnz GetApicId\r
	146	\r
0594ec41 ED	147	; Increment the number of APs executing here as early as possible\r
	148	; This is decremented in C code when AP is finished executing\r
	149	mov edi, esi\r
	150	add edi, NumApsExecutingLocation\r
	151	lock inc dword [edi]\r
	152	\r
845c5be1	153	; AP init\r
d94e5f67 JF	154	mov edi, esi\r
	155	add edi, LockLocation\r
	156	mov rax, NotVacantFlag\r
	157	\r
	158	TestLock:\r
	159	xchg qword [edi], rax\r
	160	cmp rax, NotVacantFlag\r
	161	jz TestLock\r
	162	\r
37676b9f	163	lea ecx, [esi + ApIndexLocation]\r
845c5be1 JF	164	inc dword [ecx]\r
845c5be1 JF	165	mov ebx, [ecx]\r
d94e5f67	166	\r
845c5be1 JF	167	Releaselock:\r
	168	mov rax, VacantFlag\r
	169	xchg qword [edi], rax\r
	170	; program stack\r
d94e5f67 JF	171	mov edi, esi\r
d94e5f67 JF	172	add edi, StackSizeLocation\r
845c5be1 JF	173	mov eax, dword [edi]\r
	174	mov ecx, ebx\r
	175	inc ecx\r
	176	mul ecx ; EAX = StackSize * (CpuNumber + 1)\r
d94e5f67 JF	177	mov edi, esi\r
	178	add edi, StackStartAddressLocation\r
	179	add rax, qword [edi]\r
	180	mov rsp, rax\r
845c5be1 JF	181	jmp CProcedureInvoke\r
	182	\r
	183	GetApicId:\r
	184	mov eax, 0\r
	185	cpuid\r
	186	cmp eax, 0bh\r
1cbd8330 LE	187	jb NoX2Apic ; CPUID level below CPUID_EXTENDED_TOPOLOGY\r
	188	\r
	189	mov eax, 0bh\r
	190	xor ecx, ecx\r
	191	cpuid\r
	192	test ebx, 0ffffh\r
	193	jz NoX2Apic ; CPUID.0BH:EBX[15:0] is zero\r
	194	\r
	195	; Processor is x2APIC capable; 32-bit x2APIC ID is already in EDX\r
	196	jmp GetProcessorNumber\r
	197	\r
	198	NoX2Apic:\r
845c5be1 JF	199	; Processor is not x2APIC capable, so get 8-bit APIC ID\r
	200	mov eax, 1\r
	201	cpuid\r
	202	shr ebx, 24\r
	203	mov edx, ebx\r
845c5be1	204	\r
845c5be1 JF	205	GetProcessorNumber:\r
	206	;\r
	207	; Get processor number for this AP\r
	208	; Note that BSP may become an AP due to SwitchBsp()\r
	209	;\r
	210	xor ebx, ebx\r
	211	lea eax, [esi + CpuInfoLocation]\r
	212	mov edi, [eax]\r
d94e5f67	213	\r
845c5be1 JF	214	GetNextProcNumber:\r
	215	cmp dword [edi], edx ; APIC ID match?\r
	216	jz ProgramStack\r
dd3fa0cd	217	add edi, 20\r
845c5be1 JF	218	inc ebx\r
	219	jmp GetNextProcNumber \r
	220	\r
	221	ProgramStack:\r
dd3fa0cd	222	mov rsp, qword [edi + 12]\r
d94e5f67 JF	223	\r
d94e5f67 JF	224	CProcedureInvoke:\r
8396e2dd JF	225	push rbp ; Push BIST data at top of AP stack\r
8396e2dd JF	226	xor rbp, rbp ; Clear ebp for call stack trace\r
d94e5f67 JF	227	push rbp\r
	228	mov rbp, rsp\r
	229	\r
3b2928b4	230	mov rax, qword [esi + InitializeFloatingPointUnitsAddress]\r
d94e5f67 JF	231	sub rsp, 20h\r
	232	call rax ; Call assembly function to initialize FPU per UEFI spec\r
	233	add rsp, 20h\r
	234	\r
37676b9f	235	mov edx, ebx ; edx is ApIndex\r
d94e5f67 JF	236	mov ecx, esi\r
	237	add ecx, LockLocation ; rcx is address of exchange info data buffer\r
	238	\r
	239	mov edi, esi\r
	240	add edi, ApProcedureLocation\r
	241	mov rax, qword [edi]\r
	242	\r
	243	sub rsp, 20h\r
8396e2dd	244	call rax ; Invoke C function\r
d94e5f67	245	add rsp, 20h\r
8396e2dd	246	jmp $ ; Should never reach here\r
d94e5f67 JF	247	\r
	248	RendezvousFunnelProcEnd:\r
	249	\r
76157021	250	;-------------------------------------------------------------------------------------\r
9f91cb01	251	; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfApStack, CountTofinish);\r
76157021 JF	252	;-------------------------------------------------------------------------------------\r
	253	global ASM_PFX(AsmRelocateApLoop)\r
	254	ASM_PFX(AsmRelocateApLoop):\r
	255	AsmRelocateApLoopStart:\r
a7bbe9d2	256	cli ; Disable interrupt before switching to 32-bit mode\r
9f91cb01 JF	257	mov rax, [rsp + 40] ; CountTofinish\r
9f91cb01 JF	258	lock dec dword [rax] ; (*CountTofinish)--\r
bf2786dc	259	mov rsp, r9\r
76157021 JF	260	push rcx\r
	261	push rdx\r
	262	\r
	263	lea rsi, [PmEntry] ; rsi <- The start address of transition code\r
	264	\r
	265	push r8\r
	266	push rsi\r
	267	DB 0x48\r
	268	retf\r
	269	BITS 32\r
	270	PmEntry:\r
	271	mov eax, cr0\r
	272	btr eax, 31 ; Clear CR0.PG\r
	273	mov cr0, eax ; Disable paging and caches\r
	274	\r
	275	mov ebx, edx ; Save EntryPoint to rbx, for rdmsr will overwrite rdx\r
	276	mov ecx, 0xc0000080\r
	277	rdmsr\r
	278	and ah, ~ 1 ; Clear LME\r
	279	wrmsr\r
	280	mov eax, cr4\r
	281	and al, ~ (1 << 5) ; Clear PAE\r
	282	mov cr4, eax\r
	283	\r
	284	pop edx\r
	285	add esp, 4\r
	286	pop ecx,\r
	287	add esp, 4\r
	288	cmp cl, 1 ; Check mwait-monitor support\r
	289	jnz HltLoop\r
	290	mov ebx, edx ; Save C-State to ebx\r
	291	MwaitLoop:\r
a7bbe9d2	292	cli\r
76157021 JF	293	mov eax, esp ; Set Monitor Address\r
	294	xor ecx, ecx ; ecx = 0\r
	295	xor edx, edx ; edx = 0\r
	296	monitor\r
76157021	297	mov eax, ebx ; Mwait Cx, Target C-State per eax[7:4]\r
f56379f3	298	shl eax, 4\r
76157021 JF	299	mwait\r
	300	jmp MwaitLoop\r
	301	HltLoop:\r
	302	cli\r
	303	hlt\r
	304	jmp HltLoop\r
76157021 JF	305	BITS 64\r
	306	AsmRelocateApLoopEnd:\r
	307	\r
d94e5f67 JF	308	;-------------------------------------------------------------------------------------\r
	309	; AsmGetAddressMap (&AddressMap);\r
	310	;-------------------------------------------------------------------------------------\r
	311	global ASM_PFX(AsmGetAddressMap)\r
	312	ASM_PFX(AsmGetAddressMap):\r
3b2928b4	313	lea rax, [ASM_PFX(RendezvousFunnelProc)]\r
d94e5f67 JF	314	mov qword [rcx], rax\r
	315	mov qword [rcx + 8h], LongModeStart - RendezvousFunnelProcStart\r
	316	mov qword [rcx + 10h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
3b2928b4	317	lea rax, [ASM_PFX(AsmRelocateApLoop)]\r
f7f85d83 JF	318	mov qword [rcx + 18h], rax\r
f7f85d83 JF	319	mov qword [rcx + 20h], AsmRelocateApLoopEnd - AsmRelocateApLoopStart\r
f32bfe6d	320	mov qword [rcx + 28h], Flat32Start - RendezvousFunnelProcStart\r
d94e5f67 JF	321	ret\r
	322	\r
	323	;-------------------------------------------------------------------------------------\r
	324	;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is\r
8396e2dd	325	;about to become an AP. It switches its stack with the current AP.\r
d94e5f67 JF	326	;AsmExchangeRole (IN CPU_EXCHANGE_INFO MyInfo, IN CPU_EXCHANGE_INFO OthersInfo);\r
	327	;-------------------------------------------------------------------------------------\r
	328	global ASM_PFX(AsmExchangeRole)\r
	329	ASM_PFX(AsmExchangeRole):\r
	330	; DO NOT call other functions in this function, since 2 CPU may use 1 stack\r
	331	; at the same time. If 1 CPU try to call a function, stack will be corrupted.\r
	332	\r
	333	push rax\r
	334	push rbx\r
	335	push rcx\r
	336	push rdx\r
	337	push rsi\r
	338	push rdi\r
	339	push rbp\r
	340	push r8\r
	341	push r9\r
	342	push r10\r
	343	push r11\r
	344	push r12\r
	345	push r13\r
	346	push r14\r
	347	push r15\r
	348	\r
	349	mov rax, cr0\r
	350	push rax\r
	351	\r
	352	mov rax, cr4\r
	353	push rax\r
	354	\r
	355	; rsi contains MyInfo pointer\r
	356	mov rsi, rcx\r
	357	\r
	358	; rdi contains OthersInfo pointer\r
	359	mov rdi, rdx\r
	360	\r
	361	;Store EFLAGS, GDTR and IDTR regiter to stack\r
	362	pushfq\r
	363	sgdt [rsi + 16]\r
	364	sidt [rsi + 26]\r
	365	\r
	366	; Store the its StackPointer\r
	367	mov [rsi + 8], rsp\r
	368	\r
	369	; update its switch state to STORED\r
	370	mov byte [rsi], CPU_SWITCH_STATE_STORED\r
	371	\r
	372	WaitForOtherStored:\r
	373	; wait until the other CPU finish storing its state\r
	374	cmp byte [rdi], CPU_SWITCH_STATE_STORED\r
	375	jz OtherStored\r
	376	pause\r
	377	jmp WaitForOtherStored\r
	378	\r
	379	OtherStored:\r
	380	; Since another CPU already stored its state, load them\r
	381	; load GDTR value\r
	382	lgdt [rdi + 16]\r
	383	\r
	384	; load IDTR value\r
	385	lidt [rdi + 26]\r
	386	\r
	387	; load its future StackPointer\r
	388	mov rsp, [rdi + 8]\r
	389	\r
390	; update the other CPU's switch state to LOADED\r
391	mov byte [rdi], CPU_SWITCH_STATE_LOADED\r
392	\r
393	WaitForOtherLoaded:\r
394	; wait until the other CPU finish loading new state,\r
395	; otherwise the data in stack may corrupt\r
396	cmp byte [rsi], CPU_SWITCH_STATE_LOADED\r
397	jz OtherLoaded\r
398	pause\r
399	jmp WaitForOtherLoaded\r
400	\r
401	OtherLoaded:\r
402	; since the other CPU already get the data it want, leave this procedure\r
403	popfq\r
404	\r
405	pop rax\r
406	mov cr4, rax\r
407	\r
408	pop rax\r
409	mov cr0, rax\r
410	\r
411	pop r15\r
412	pop r14\r
413	pop r13\r
414	pop r12\r
415	pop r11\r
416	pop r10\r
417	pop r9\r
418	pop r8\r
419	pop rbp\r
420	pop rdi\r
421	pop rsi\r
422	pop rdx\r
423	pop rcx\r
424	pop rbx\r
425	pop rax\r
426	\r
427	ret\r