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09119a00 | 1 | ;------------------------------------------------------------------------------ ;\r |
6afc643c | 2 | ; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r |
09119a00 MK |
3 | ; This program and the accompanying materials\r |
4 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
5 | ; which accompanies this distribution. The full text of the license may be found at\r | |
6 | ; http://opensource.org/licenses/bsd-license.php.\r | |
7 | ;\r | |
8 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
9 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
10 | ;\r | |
11 | ; Module Name:\r | |
12 | ;\r | |
13 | ; SmiException.asm\r | |
14 | ;\r | |
15 | ; Abstract:\r | |
16 | ;\r | |
17 | ; Exception handlers used in SM mode\r | |
18 | ;\r | |
19 | ;-------------------------------------------------------------------------------\r | |
20 | \r | |
21 | .686p\r | |
22 | .model flat,C\r | |
23 | \r | |
24 | EXTERNDEF gcStmPsd:BYTE\r | |
25 | \r | |
26 | EXTERNDEF SmmStmExceptionHandler:PROC\r | |
27 | EXTERNDEF SmmStmSetup:PROC\r | |
28 | EXTERNDEF SmmStmTeardown:PROC\r | |
6afc643c | 29 | EXTERNDEF gStmXdSupported:BYTE\r |
09119a00 MK |
30 | \r |
31 | CODE_SEL = 08h\r | |
32 | DATA_SEL = 20h\r | |
33 | TSS_SEL = 40h\r | |
34 | \r | |
6afc643c JF |
35 | MSR_IA32_MISC_ENABLE EQU 1A0h\r |
36 | MSR_EFER EQU 0c0000080h\r | |
37 | MSR_EFER_XD EQU 0800h\r | |
38 | \r | |
09119a00 MK |
39 | .data\r |
40 | \r | |
41 | gcStmPsd LABEL BYTE\r | |
42 | DB 'TXTPSSIG'\r | |
43 | DW PSD_SIZE\r | |
44 | DW 1 ; Version\r | |
45 | DD 0 ; LocalApicId\r | |
46 | DB 05h ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr\r | |
47 | DB 0 ; BIOS to STM\r | |
48 | DB 0 ; STM to BIOS\r | |
49 | DB 0\r | |
50 | DW CODE_SEL\r | |
51 | DW DATA_SEL\r | |
52 | DW DATA_SEL\r | |
53 | DW DATA_SEL\r | |
54 | DW TSS_SEL\r | |
55 | DW 0\r | |
56 | DQ 0 ; SmmCr3\r | |
57 | DQ _OnStmSetup\r | |
58 | DQ _OnStmTeardown\r | |
59 | DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint\r | |
60 | DQ 0 ; SmmSmiHandlerRsp\r | |
61 | DQ 0\r | |
62 | DD 0\r | |
63 | DD 80010100h ; RequiredStmSmmRevId\r | |
64 | DQ _OnException\r | |
65 | DQ 0 ; ExceptionStack\r | |
66 | DW DATA_SEL\r | |
67 | DW 01Fh ; ExceptionFilter\r | |
68 | DD 0\r | |
69 | DQ 0\r | |
70 | DQ 0 ; BiosHwResourceRequirementsPtr\r | |
71 | DQ 0 ; AcpiRsdp\r | |
72 | DB 0 ; PhysicalAddressBits\r | |
73 | PSD_SIZE = $ - offset gcStmPsd\r | |
74 | \r | |
75 | .code\r | |
76 | ;------------------------------------------------------------------------------\r | |
77 | ; SMM Exception handlers\r | |
78 | ;------------------------------------------------------------------------------\r | |
79 | _OnException PROC\r | |
80 | mov ecx, esp\r | |
81 | push ecx\r | |
82 | call SmmStmExceptionHandler\r | |
83 | add esp, 4\r | |
84 | \r | |
85 | mov ebx, eax\r | |
86 | mov eax, 4\r | |
87 | DB 0fh, 01h, 0c1h ; VMCALL\r | |
88 | jmp $\r | |
89 | _OnException ENDP\r | |
90 | \r | |
91 | _OnStmSetup PROC\r | |
92 | ;\r | |
93 | ; Check XD disable bit\r | |
94 | ;\r | |
95 | xor esi, esi\r | |
6afc643c | 96 | mov eax, offset gStmXdSupported\r |
09119a00 MK |
97 | mov al, [eax]\r |
98 | cmp al, 0\r | |
99 | jz @StmXdDone1\r | |
100 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
101 | rdmsr\r | |
102 | mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]\r | |
103 | test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r | |
104 | jz @f\r | |
105 | and dx, 0FFFBh ; clear XD Disable bit if it is set\r | |
106 | wrmsr\r | |
107 | @@:\r | |
108 | mov ecx, MSR_EFER\r | |
109 | rdmsr\r | |
110 | or ax, MSR_EFER_XD ; enable NXE\r | |
111 | wrmsr\r | |
112 | @StmXdDone1:\r | |
113 | push esi\r | |
114 | \r | |
115 | call SmmStmSetup\r | |
116 | \r | |
6afc643c | 117 | mov eax, offset gStmXdSupported\r |
09119a00 MK |
118 | mov al, [eax]\r |
119 | cmp al, 0\r | |
120 | jz @f\r | |
121 | pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r | |
122 | test edx, BIT2\r | |
123 | jz @f\r | |
124 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
125 | rdmsr\r | |
126 | or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r | |
127 | wrmsr\r | |
128 | @@:\r | |
129 | \r | |
130 | rsm\r | |
131 | _OnStmSetup ENDP\r | |
132 | \r | |
133 | _OnStmTeardown PROC\r | |
134 | ;\r | |
135 | ; Check XD disable bit\r | |
136 | ;\r | |
137 | xor esi, esi\r | |
6afc643c | 138 | mov eax, offset gStmXdSupported\r |
09119a00 MK |
139 | mov al, [eax]\r |
140 | cmp al, 0\r | |
141 | jz @StmXdDone2\r | |
142 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
143 | rdmsr\r | |
144 | mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]\r | |
145 | test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r | |
146 | jz @f\r | |
147 | and dx, 0FFFBh ; clear XD Disable bit if it is set\r | |
148 | wrmsr\r | |
149 | @@:\r | |
150 | mov ecx, MSR_EFER\r | |
151 | rdmsr\r | |
152 | or ax, MSR_EFER_XD ; enable NXE\r | |
153 | wrmsr\r | |
154 | @StmXdDone2:\r | |
155 | push esi\r | |
156 | \r | |
157 | call SmmStmTeardown\r | |
158 | \r | |
6afc643c | 159 | mov eax, offset gStmXdSupported\r |
09119a00 MK |
160 | mov al, [eax]\r |
161 | cmp al, 0\r | |
162 | jz @f\r | |
163 | pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r | |
164 | test edx, BIT2\r | |
165 | jz @f\r | |
166 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
167 | rdmsr\r | |
168 | or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r | |
169 | wrmsr\r | |
170 | @@:\r | |
171 | \r | |
172 | rsm\r | |
173 | _OnStmTeardown ENDP\r | |
174 | \r | |
175 | END\r |