UefiCpuPkg: Update SmmCpuFeatureLib pass XCODE5 tool chain
[mirror_edk2.git] / UefiCpuPkg / Library / SmmCpuFeaturesLib / X64 / SmiException.nasm
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09119a00 1;------------------------------------------------------------------------------ ;\r
1c7a65eb 2; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
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3; This program and the accompanying materials\r
4; are licensed and made available under the terms and conditions of the BSD License\r
5; which accompanies this distribution. The full text of the license may be found at\r
6; http://opensource.org/licenses/bsd-license.php.\r
7;\r
8; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
9; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
10;\r
11; Module Name:\r
12;\r
13; SmiException.nasm\r
14;\r
15; Abstract:\r
16;\r
17; Exception handlers used in SM mode\r
18;\r
19;-------------------------------------------------------------------------------\r
20\r
21global ASM_PFX(gcStmPsd)\r
22\r
23extern ASM_PFX(SmmStmExceptionHandler)\r
24extern ASM_PFX(SmmStmSetup)\r
25extern ASM_PFX(SmmStmTeardown)\r
26extern ASM_PFX(gStmXdSupported)\r
27extern ASM_PFX(gStmSmiHandlerIdtr)\r
28\r
29%define MSR_IA32_MISC_ENABLE 0x1A0\r
30%define MSR_EFER 0xc0000080\r
31%define MSR_EFER_XD 0x800\r
32\r
33CODE_SEL equ 0x38\r
34DATA_SEL equ 0x20\r
35TR_SEL equ 0x40\r
36\r
37 SECTION .data\r
38\r
39;\r
40; This structure serves as a template for all processors.\r
41;\r
42ASM_PFX(gcStmPsd):\r
43 DB 'TXTPSSIG'\r
44 DW PSD_SIZE\r
45 DW 1 ; Version\r
46 DD 0 ; LocalApicId\r
47 DB 0x0F ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr\r
48 DB 0 ; BIOS to STM\r
49 DB 0 ; STM to BIOS\r
50 DB 0\r
51 DW CODE_SEL\r
52 DW DATA_SEL\r
53 DW DATA_SEL\r
54 DW DATA_SEL\r
55 DW TR_SEL\r
56 DW 0\r
57 DQ 0 ; SmmCr3\r
58 DQ ASM_PFX(OnStmSetup)\r
59 DQ ASM_PFX(OnStmTeardown)\r
60 DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint\r
61 DQ 0 ; SmmSmiHandlerRsp\r
62 DQ 0\r
63 DD 0\r
64 DD 0x80010100 ; RequiredStmSmmRevId\r
65 DQ ASM_PFX(OnException)\r
66 DQ 0 ; ExceptionStack\r
67 DW DATA_SEL\r
68 DW 0x01F ; ExceptionFilter\r
69 DD 0\r
70 DQ 0\r
71 DQ 0 ; BiosHwResourceRequirementsPtr\r
72 DQ 0 ; AcpiRsdp\r
73 DB 0 ; PhysicalAddressBits\r
74PSD_SIZE equ $ - ASM_PFX(gcStmPsd)\r
75\r
76 DEFAULT REL\r
77 SECTION .text\r
78;------------------------------------------------------------------------------\r
79; SMM Exception handlers\r
80;------------------------------------------------------------------------------\r
81global ASM_PFX(OnException)\r
82ASM_PFX(OnException):\r
83 mov rcx, rsp\r
84 add rsp, -0x28\r
85 call ASM_PFX(SmmStmExceptionHandler)\r
86 add rsp, 0x28\r
87 mov ebx, eax\r
88 mov eax, 4\r
4c34a8ea 89 vmcall\r
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90 jmp $\r
91\r
92global ASM_PFX(OnStmSetup)\r
93ASM_PFX(OnStmSetup):\r
94;\r
95; Check XD disable bit\r
96;\r
97 xor r8, r8\r
1c7a65eb 98 lea rax, [ASM_PFX(gStmXdSupported)]\r
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99 mov al, [rax]\r
100 cmp al, 0\r
101 jz @StmXdDone1\r
102 mov ecx, MSR_IA32_MISC_ENABLE\r
103 rdmsr\r
104 mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]\r
105 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
106 jz .01\r
107 and dx, 0xFFFB ; clear XD Disable bit if it is set\r
108 wrmsr\r
109.01:\r
110 mov ecx, MSR_EFER\r
111 rdmsr\r
112 or ax, MSR_EFER_XD ; enable NXE\r
113 wrmsr\r
114@StmXdDone1:\r
115 push r8\r
116\r
117 add rsp, -0x20\r
118 call ASM_PFX(SmmStmSetup)\r
119 add rsp, 0x20\r
120\r
1c7a65eb 121 lea rax, [ASM_PFX(gStmXdSupported)]\r
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122 mov al, [rax]\r
123 cmp al, 0\r
124 jz .11\r
125 pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r
126 test edx, BIT2\r
127 jz .11\r
128 mov ecx, MSR_IA32_MISC_ENABLE\r
129 rdmsr\r
130 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r
131 wrmsr\r
132\r
133.11:\r
134 rsm\r
135\r
136global ASM_PFX(OnStmTeardown)\r
137ASM_PFX(OnStmTeardown):\r
138;\r
139; Check XD disable bit\r
140;\r
141 xor r8, r8\r
1c7a65eb 142 lea rax, [ASM_PFX(gStmXdSupported)]\r
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143 mov al, [rax]\r
144 cmp al, 0\r
145 jz @StmXdDone2\r
146 mov ecx, MSR_IA32_MISC_ENABLE\r
147 rdmsr\r
148 mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]\r
149 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
150 jz .02\r
151 and dx, 0xFFFB ; clear XD Disable bit if it is set\r
152 wrmsr\r
153.02:\r
154 mov ecx, MSR_EFER\r
155 rdmsr\r
156 or ax, MSR_EFER_XD ; enable NXE\r
157 wrmsr\r
158@StmXdDone2:\r
159 push r8\r
160\r
161 add rsp, -0x20\r
162 call ASM_PFX(SmmStmTeardown)\r
163 add rsp, 0x20\r
164\r
1c7a65eb 165 lea rax, [ASM_PFX(gStmXdSupported)]\r
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166 mov al, [rax]\r
167 cmp al, 0\r
168 jz .12\r
169 pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r
170 test edx, BIT2\r
171 jz .12\r
172 mov ecx, MSR_IA32_MISC_ENABLE\r
173 rdmsr\r
174 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r
175 wrmsr\r
176\r
177.12:\r
178 rsm\r