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63a4f460 | 1 | ;------------------------------------------------------------------------------ ;\r |
e21e355e | 2 | ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
63a4f460 LG |
3 | ; This program and the accompanying materials\r |
4 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
5 | ; which accompanies this distribution. The full text of the license may be found at\r | |
6 | ; http://opensource.org/licenses/bsd-license.php.\r | |
7 | ;\r | |
8 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
9 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
10 | ;\r | |
11 | ; Module Name:\r | |
12 | ;\r | |
13 | ; SmiEntry.nasm\r | |
14 | ;\r | |
15 | ; Abstract:\r | |
16 | ;\r | |
17 | ; Code template of the SMI handler for a particular processor\r | |
18 | ;\r | |
19 | ;-------------------------------------------------------------------------------\r | |
20 | \r | |
717fb604 JY |
21 | %define MSR_IA32_MISC_ENABLE 0x1A0\r |
22 | %define MSR_EFER 0xc0000080\r | |
23 | %define MSR_EFER_XD 0x800\r | |
24 | \r | |
f12367a0 MK |
25 | ;\r |
26 | ; Constants relating to PROCESSOR_SMM_DESCRIPTOR\r | |
27 | ;\r | |
63a4f460 LG |
28 | %define DSC_OFFSET 0xfb00\r |
29 | %define DSC_GDTPTR 0x30\r | |
30 | %define DSC_GDTSIZ 0x38\r | |
31 | %define DSC_CS 14\r | |
32 | %define DSC_DS 16\r | |
33 | %define DSC_SS 18\r | |
34 | %define DSC_OTHERSEG 20\r | |
35 | \r | |
36 | %define PROTECT_MODE_CS 0x8\r | |
37 | %define PROTECT_MODE_DS 0x20\r | |
38 | %define TSS_SEGMENT 0x40\r | |
39 | \r | |
40 | extern ASM_PFX(SmiRendezvous)\r | |
41 | extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))\r | |
42 | extern ASM_PFX(CpuSmmDebugEntry)\r | |
43 | extern ASM_PFX(CpuSmmDebugExit)\r | |
44 | \r | |
45 | global ASM_PFX(gcSmiHandlerTemplate)\r | |
46 | global ASM_PFX(gcSmiHandlerSize)\r | |
c455687f | 47 | global ASM_PFX(gPatchSmiCr3)\r |
fc504fde | 48 | global ASM_PFX(gPatchSmiStack)\r |
5a1bfda4 | 49 | global ASM_PFX(gPatchSmbase)\r |
3c5ce64f LE |
50 | extern ASM_PFX(mXdSupported)\r |
51 | global ASM_PFX(gPatchXdSupported)\r | |
63a4f460 LG |
52 | extern ASM_PFX(gSmiHandlerIdtr)\r |
53 | \r | |
54 | SECTION .text\r | |
55 | \r | |
56 | BITS 16\r | |
57 | ASM_PFX(gcSmiHandlerTemplate):\r | |
58 | _SmiEntryPoint:\r | |
59 | mov bx, _GdtDesc - _SmiEntryPoint + 0x8000\r | |
60 | mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]\r | |
61 | dec ax\r | |
62 | mov [cs:bx], ax\r | |
63 | mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]\r | |
64 | mov [cs:bx + 2], eax\r | |
65 | mov ebp, eax ; ebp = GDT base\r | |
66 | o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]\r | |
67 | mov ax, PROTECT_MODE_CS\r | |
717fb604 | 68 | mov [cs:bx-0x2],ax\r |
5a1bfda4 LE |
69 | mov edi, strict dword 0 ; source operand will be patched\r |
70 | ASM_PFX(gPatchSmbase):\r | |
63a4f460 LG |
71 | lea eax, [edi + (@32bit - _SmiEntryPoint) + 0x8000]\r |
72 | mov [cs:bx-0x6],eax\r | |
73 | mov ebx, cr0\r | |
74 | and ebx, 0x9ffafff3\r | |
75 | or ebx, 0x23\r | |
76 | mov cr0, ebx\r | |
77 | jmp dword 0x0:0x0\r | |
717fb604 | 78 | _GdtDesc:\r |
63a4f460 LG |
79 | DW 0\r |
80 | DD 0\r | |
81 | \r | |
82 | BITS 32\r | |
83 | @32bit:\r | |
84 | mov ax, PROTECT_MODE_DS\r | |
85 | o16 mov ds, ax\r | |
86 | o16 mov es, ax\r | |
87 | o16 mov fs, ax\r | |
88 | o16 mov gs, ax\r | |
89 | o16 mov ss, ax\r | |
fc504fde LE |
90 | mov esp, strict dword 0 ; source operand will be patched\r |
91 | ASM_PFX(gPatchSmiStack):\r | |
63a4f460 LG |
92 | mov eax, ASM_PFX(gSmiHandlerIdtr)\r |
93 | lidt [eax]\r | |
94 | jmp ProtFlatMode\r | |
95 | \r | |
96 | ProtFlatMode:\r | |
c455687f LE |
97 | mov eax, strict dword 0 ; source operand will be patched\r |
98 | ASM_PFX(gPatchSmiCr3):\r | |
63a4f460 LG |
99 | mov cr3, eax\r |
100 | ;\r | |
101 | ; Need to test for CR4 specific bit support\r | |
102 | ;\r | |
103 | mov eax, 1\r | |
104 | cpuid ; use CPUID to determine if specific CR4 bits are supported\r | |
105 | xor eax, eax ; Clear EAX\r | |
106 | test edx, BIT2 ; Check for DE capabilities\r | |
107 | jz .0\r | |
108 | or eax, BIT3\r | |
109 | .0:\r | |
110 | test edx, BIT6 ; Check for PAE capabilities\r | |
111 | jz .1\r | |
112 | or eax, BIT5\r | |
113 | .1:\r | |
114 | test edx, BIT7 ; Check for MCE capabilities\r | |
115 | jz .2\r | |
116 | or eax, BIT6\r | |
117 | .2:\r | |
118 | test edx, BIT24 ; Check for FXSR capabilities\r | |
119 | jz .3\r | |
120 | or eax, BIT9\r | |
121 | .3:\r | |
122 | test edx, BIT25 ; Check for SSE capabilities\r | |
123 | jz .4\r | |
124 | or eax, BIT10\r | |
125 | .4: ; as cr4.PGE is not set here, refresh cr3\r | |
126 | mov cr4, eax ; in PreModifyMtrrs() to flush TLB.\r | |
717fb604 JY |
127 | \r |
128 | cmp byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0\r | |
129 | jz .6\r | |
130 | ; Load TSS\r | |
131 | mov byte [ebp + TSS_SEGMENT + 5], 0x89 ; clear busy flag\r | |
132 | mov eax, TSS_SEGMENT\r | |
133 | ltr ax\r | |
134 | .6:\r | |
135 | \r | |
136 | ; enable NXE if supported\r | |
3c5ce64f LE |
137 | mov al, strict byte 1 ; source operand may be patched\r |
138 | ASM_PFX(gPatchXdSupported):\r | |
717fb604 JY |
139 | cmp al, 0\r |
140 | jz @SkipXd\r | |
141 | ;\r | |
142 | ; Check XD disable bit\r | |
143 | ;\r | |
144 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
145 | rdmsr\r | |
146 | push edx ; save MSR_IA32_MISC_ENABLE[63-32]\r | |
147 | test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r | |
148 | jz .5\r | |
149 | and dx, 0xFFFB ; clear XD Disable bit if it is set\r | |
150 | wrmsr\r | |
151 | .5:\r | |
152 | mov ecx, MSR_EFER\r | |
153 | rdmsr\r | |
154 | or ax, MSR_EFER_XD ; enable NXE\r | |
155 | wrmsr\r | |
156 | jmp @XdDone\r | |
157 | @SkipXd:\r | |
158 | sub esp, 4\r | |
159 | @XdDone:\r | |
160 | \r | |
63a4f460 | 161 | mov ebx, cr0\r |
717fb604 | 162 | or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE\r |
63a4f460 LG |
163 | mov cr0, ebx\r |
164 | lea ebx, [edi + DSC_OFFSET]\r | |
165 | mov ax, [ebx + DSC_DS]\r | |
166 | mov ds, eax\r | |
167 | mov ax, [ebx + DSC_OTHERSEG]\r | |
168 | mov es, eax\r | |
169 | mov fs, eax\r | |
170 | mov gs, eax\r | |
171 | mov ax, [ebx + DSC_SS]\r | |
172 | mov ss, eax\r | |
173 | \r | |
63a4f460 LG |
174 | ; jmp _SmiHandler ; instruction is not needed\r |
175 | \r | |
176 | global ASM_PFX(SmiHandler)\r | |
177 | ASM_PFX(SmiHandler):\r | |
717fb604 | 178 | mov ebx, [esp + 4] ; CPU Index\r |
63a4f460 LG |
179 | push ebx\r |
180 | mov eax, ASM_PFX(CpuSmmDebugEntry)\r | |
181 | call eax\r | |
717fb604 | 182 | add esp, 4\r |
63a4f460 LG |
183 | \r |
184 | push ebx\r | |
185 | mov eax, ASM_PFX(SmiRendezvous)\r | |
186 | call eax\r | |
717fb604 JY |
187 | add esp, 4\r |
188 | \r | |
63a4f460 LG |
189 | push ebx\r |
190 | mov eax, ASM_PFX(CpuSmmDebugExit)\r | |
191 | call eax\r | |
717fb604 JY |
192 | add esp, 4\r |
193 | \r | |
194 | mov eax, ASM_PFX(mXdSupported)\r | |
195 | mov al, [eax]\r | |
196 | cmp al, 0\r | |
197 | jz .7\r | |
198 | pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]\r | |
199 | test edx, BIT2\r | |
200 | jz .7\r | |
201 | mov ecx, MSR_IA32_MISC_ENABLE\r | |
202 | rdmsr\r | |
203 | or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM\r | |
204 | wrmsr\r | |
205 | \r | |
206 | .7:\r | |
63a4f460 LG |
207 | rsm\r |
208 | \r | |
209 | ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint\r | |
210 | \r | |
e21e355e LG |
211 | global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)\r |
212 | ASM_PFX(PiSmmCpuSmiEntryFixupAddress):\r | |
213 | ret\r |