projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 529a5a86 MK |
1 | /** @file\r |
| 2 | Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r | |
| 3 | \r | |
| 3eb69b08 | 4 | Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.<BR>\r |
| 241f9149 LD |
5 | Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r |
| 6 | \r | |
| 0acd8697 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 529a5a86 MK |
8 | \r |
| 9 | **/\r | |
| 10 | \r | |
| 11 | #include "PiSmmCpuDxeSmm.h"\r | |
| 12 | \r | |
| 13 | //\r | |
| 14 | // SMM CPU Private Data structure that contains SMM Configuration Protocol\r | |
| 15 | // along its supporting fields.\r | |
| 16 | //\r | |
| 17 | SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData = {\r | |
| 18 | SMM_CPU_PRIVATE_DATA_SIGNATURE, // Signature\r | |
| 19 | NULL, // SmmCpuHandle\r | |
| 20 | NULL, // Pointer to ProcessorInfo array\r | |
| 21 | NULL, // Pointer to Operation array\r | |
| 22 | NULL, // Pointer to CpuSaveStateSize array\r | |
| 23 | NULL, // Pointer to CpuSaveState array\r | |
| 053e878b MK |
24 | {\r |
| 25 | { 0 }\r | |
| 26 | }, // SmmReservedSmramRegion\r | |
| 529a5a86 MK |
27 | {\r |
| 28 | SmmStartupThisAp, // SmmCoreEntryContext.SmmStartupThisAp\r | |
| 29 | 0, // SmmCoreEntryContext.CurrentlyExecutingCpu\r | |
| 30 | 0, // SmmCoreEntryContext.NumberOfCpus\r | |
| 31 | NULL, // SmmCoreEntryContext.CpuSaveStateSize\r | |
| 32 | NULL // SmmCoreEntryContext.CpuSaveState\r | |
| 33 | },\r | |
| 34 | NULL, // SmmCoreEntry\r | |
| 35 | {\r | |
| 36 | mSmmCpuPrivateData.SmmReservedSmramRegion, // SmmConfiguration.SmramReservedRegions\r | |
| 37 | RegisterSmmEntry // SmmConfiguration.RegisterSmmEntry\r | |
| 38 | },\r | |
| 51dd408a | 39 | NULL, // pointer to Ap Wrapper Func array\r |
| 053e878b | 40 | { NULL, NULL }, // List_Entry for Tokens.\r |
| 529a5a86 MK |
41 | };\r |
| 42 | \r | |
| 053e878b | 43 | CPU_HOT_PLUG_DATA mCpuHotPlugData = {\r |
| 529a5a86 MK |
44 | CPU_HOT_PLUG_DATA_REVISION_1, // Revision\r |
| 45 | 0, // Array Length of SmBase and APIC ID\r | |
| 46 | NULL, // Pointer to APIC ID array\r | |
| 47 | NULL, // Pointer to SMBASE array\r | |
| 48 | 0, // Reserved\r | |
| 49 | 0, // SmrrBase\r | |
| 50 | 0 // SmrrSize\r | |
| 51 | };\r | |
| 52 | \r | |
| 53 | //\r | |
| 54 | // Global pointer used to access mSmmCpuPrivateData from outside and inside SMM\r | |
| 55 | //\r | |
| 56 | SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate = &mSmmCpuPrivateData;\r | |
| 57 | \r | |
| 58 | //\r | |
| 59 | // SMM Relocation variables\r | |
| 60 | //\r | |
| 61 | volatile BOOLEAN *mRebased;\r | |
| 62 | volatile BOOLEAN mIsBsp;\r | |
| 63 | \r | |
| 64 | ///\r | |
| 65 | /// Handle for the SMM CPU Protocol\r | |
| 66 | ///\r | |
| 67 | EFI_HANDLE mSmmCpuHandle = NULL;\r | |
| 68 | \r | |
| 69 | ///\r | |
| 70 | /// SMM CPU Protocol instance\r | |
| 71 | ///\r | |
| 053e878b | 72 | EFI_SMM_CPU_PROTOCOL mSmmCpu = {\r |
| 529a5a86 MK |
73 | SmmReadSaveState,\r |
| 74 | SmmWriteSaveState\r | |
| 75 | };\r | |
| 76 | \r | |
| 827330cc JW |
77 | ///\r |
| 78 | /// SMM Memory Attribute Protocol instance\r | |
| 79 | ///\r | |
| 053e878b | 80 | EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute = {\r |
| 827330cc JW |
81 | EdkiiSmmGetMemoryAttributes,\r |
| 82 | EdkiiSmmSetMemoryAttributes,\r | |
| 83 | EdkiiSmmClearMemoryAttributes\r | |
| 84 | };\r | |
| 85 | \r | |
| 053e878b | 86 | EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];\r |
| 529a5a86 | 87 | \r |
| 529a5a86 MK |
88 | //\r |
| 89 | // SMM stack information\r | |
| 90 | //\r | |
| 053e878b MK |
91 | UINTN mSmmStackArrayBase;\r |
| 92 | UINTN mSmmStackArrayEnd;\r | |
| 93 | UINTN mSmmStackSize;\r | |
| 529a5a86 | 94 | \r |
| 053e878b MK |
95 | UINTN mSmmShadowStackSize;\r |
| 96 | BOOLEAN mCetSupported = TRUE;\r | |
| 3eb69b08 | 97 | \r |
| 053e878b MK |
98 | UINTN mMaxNumberOfCpus = 1;\r |
| 99 | UINTN mNumberOfCpus = 1;\r | |
| 529a5a86 MK |
100 | \r |
| 101 | //\r | |
| 102 | // SMM ready to lock flag\r | |
| 103 | //\r | |
| 053e878b | 104 | BOOLEAN mSmmReadyToLock = FALSE;\r |
| 529a5a86 MK |
105 | \r |
| 106 | //\r | |
| 107 | // Global used to cache PCD for SMM Code Access Check enable\r | |
| 108 | //\r | |
| 053e878b | 109 | BOOLEAN mSmmCodeAccessCheckEnable = FALSE;\r |
| 529a5a86 | 110 | \r |
| 241f9149 LD |
111 | //\r |
| 112 | // Global copy of the PcdPteMemoryEncryptionAddressOrMask\r | |
| 113 | //\r | |
| 053e878b | 114 | UINT64 mAddressEncMask = 0;\r |
| 241f9149 | 115 | \r |
| 529a5a86 MK |
116 | //\r |
| 117 | // Spin lock used to serialize setting of SMM Code Access Check feature\r | |
| 118 | //\r | |
| 053e878b | 119 | SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL;\r |
| 529a5a86 | 120 | \r |
| 7ed6f781 JF |
121 | //\r |
| 122 | // Saved SMM ranges information\r | |
| 123 | //\r | |
| 053e878b MK |
124 | EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;\r |
| 125 | UINTN mSmmCpuSmramRangeCount;\r | |
| 7ed6f781 | 126 | \r |
| 053e878b | 127 | UINT8 mPhysicalAddressBits;\r |
| 51ce27fd | 128 | \r |
| 351b49c1 LE |
129 | //\r |
| 130 | // Control register contents saved for SMM S3 resume state initialization.\r | |
| 131 | //\r | |
| 053e878b MK |
132 | UINT32 mSmmCr0;\r |
| 133 | UINT32 mSmmCr4;\r | |
| 351b49c1 | 134 | \r |
| 529a5a86 MK |
135 | /**\r |
| 136 | Initialize IDT to setup exception handlers for SMM.\r | |
| 137 | \r | |
| 138 | **/\r | |
| 139 | VOID\r | |
| 140 | InitializeSmmIdt (\r | |
| 141 | VOID\r | |
| 142 | )\r | |
| 143 | {\r | |
| 053e878b MK |
144 | EFI_STATUS Status;\r |
| 145 | BOOLEAN InterruptState;\r | |
| 146 | IA32_DESCRIPTOR DxeIdtr;\r | |
| 717fb604 JY |
147 | \r |
| 148 | //\r | |
| 149 | // There are 32 (not 255) entries in it since only processor\r | |
| 150 | // generated exceptions will be handled.\r | |
| 151 | //\r | |
| 053e878b | 152 | gcSmiIdtr.Limit = (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32) - 1;\r |
| 717fb604 JY |
153 | //\r |
| 154 | // Allocate page aligned IDT, because it might be set as read only.\r | |
| 155 | //\r | |
| 053e878b | 156 | gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES (gcSmiIdtr.Limit + 1));\r |
| 717fb604 JY |
157 | ASSERT (gcSmiIdtr.Base != 0);\r |
| 158 | ZeroMem ((VOID *)gcSmiIdtr.Base, gcSmiIdtr.Limit + 1);\r | |
| 159 | \r | |
| 529a5a86 MK |
160 | //\r |
| 161 | // Disable Interrupt and save DXE IDT table\r | |
| 162 | //\r | |
| 163 | InterruptState = SaveAndDisableInterrupts ();\r | |
| 164 | AsmReadIdtr (&DxeIdtr);\r | |
| 165 | //\r | |
| 166 | // Load SMM temporary IDT table\r | |
| 167 | //\r | |
| 168 | AsmWriteIdtr (&gcSmiIdtr);\r | |
| 169 | //\r | |
| 170 | // Setup SMM default exception handlers, SMM IDT table\r | |
| 171 | // will be updated and saved in gcSmiIdtr\r | |
| 172 | //\r | |
| 173 | Status = InitializeCpuExceptionHandlers (NULL);\r | |
| 174 | ASSERT_EFI_ERROR (Status);\r | |
| 175 | //\r | |
| 176 | // Restore DXE IDT table and CPU interrupt\r | |
| 177 | //\r | |
| 053e878b | 178 | AsmWriteIdtr ((IA32_DESCRIPTOR *)&DxeIdtr);\r |
| 529a5a86 MK |
179 | SetInterruptState (InterruptState);\r |
| 180 | }\r | |
| 181 | \r | |
| 182 | /**\r | |
| 183 | Search module name by input IP address and output it.\r | |
| 184 | \r | |
| 185 | @param CallerIpAddress Caller instruction pointer.\r | |
| 186 | \r | |
| 187 | **/\r | |
| 188 | VOID\r | |
| 189 | DumpModuleInfoByIp (\r | |
| 053e878b | 190 | IN UINTN CallerIpAddress\r |
| 529a5a86 MK |
191 | )\r |
| 192 | {\r | |
| 053e878b MK |
193 | UINTN Pe32Data;\r |
| 194 | VOID *PdbPointer;\r | |
| 529a5a86 MK |
195 | \r |
| 196 | //\r | |
| 197 | // Find Image Base\r | |
| 198 | //\r | |
| 9e981317 | 199 | Pe32Data = PeCoffSearchImageBase (CallerIpAddress);\r |
| 529a5a86 | 200 | if (Pe32Data != 0) {\r |
| 053e878b MK |
201 | DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *)CallerIpAddress));\r |
| 202 | PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)Pe32Data);\r | |
| 529a5a86 | 203 | if (PdbPointer != NULL) {\r |
| b8caae19 | 204 | DEBUG ((DEBUG_ERROR, " in module (%a)\n", PdbPointer));\r |
| 529a5a86 MK |
205 | }\r |
| 206 | }\r | |
| 207 | }\r | |
| 208 | \r | |
| 209 | /**\r | |
| 210 | Read information from the CPU save state.\r | |
| 211 | \r | |
| 212 | @param This EFI_SMM_CPU_PROTOCOL instance\r | |
| 213 | @param Width The number of bytes to read from the CPU save state.\r | |
| 214 | @param Register Specifies the CPU register to read form the save state.\r | |
| 215 | @param CpuIndex Specifies the zero-based index of the CPU save state.\r | |
| 216 | @param Buffer Upon return, this holds the CPU register value read from the save state.\r | |
| 217 | \r | |
| 218 | @retval EFI_SUCCESS The register was read from Save State\r | |
| 219 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r | |
| ef62da4f | 220 | @retval EFI_INVALID_PARAMETER This or Buffer is NULL.\r |
| 529a5a86 MK |
221 | \r |
| 222 | **/\r | |
| 223 | EFI_STATUS\r | |
| 224 | EFIAPI\r | |
| 225 | SmmReadSaveState (\r | |
| 053e878b MK |
226 | IN CONST EFI_SMM_CPU_PROTOCOL *This,\r |
| 227 | IN UINTN Width,\r | |
| 228 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
| 229 | IN UINTN CpuIndex,\r | |
| 230 | OUT VOID *Buffer\r | |
| 529a5a86 MK |
231 | )\r |
| 232 | {\r | |
| 233 | EFI_STATUS Status;\r | |
| 234 | \r | |
| 235 | //\r | |
| 236 | // Retrieve pointer to the specified CPU's SMM Save State buffer\r | |
| 237 | //\r | |
| 238 | if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {\r | |
| 239 | return EFI_INVALID_PARAMETER;\r | |
| 240 | }\r | |
| 053e878b | 241 | \r |
| 5b02be4d | 242 | //\r |
| b70ec0de HW |
243 | // The SpeculationBarrier() call here is to ensure the above check for the\r |
| 244 | // CpuIndex has been completed before the execution of subsequent codes.\r | |
| 5b02be4d | 245 | //\r |
| b70ec0de | 246 | SpeculationBarrier ();\r |
| 529a5a86 MK |
247 | \r |
| 248 | //\r | |
| 249 | // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID\r | |
| 250 | //\r | |
| 251 | if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) {\r | |
| 252 | //\r | |
| 253 | // The pseudo-register only supports the 64-bit size specified by Width.\r | |
| 254 | //\r | |
| 255 | if (Width != sizeof (UINT64)) {\r | |
| 256 | return EFI_INVALID_PARAMETER;\r | |
| 257 | }\r | |
| 053e878b | 258 | \r |
| 529a5a86 MK |
259 | //\r |
| 260 | // If the processor is in SMM at the time the SMI occurred,\r | |
| 261 | // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.\r | |
| 262 | // Otherwise, EFI_NOT_FOUND is returned.\r | |
| 263 | //\r | |
| ed3d5ecb | 264 | if (*(mSmmMpSyncData->CpuData[CpuIndex].Present)) {\r |
| 529a5a86 MK |
265 | *(UINT64 *)Buffer = gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId;\r |
| 266 | return EFI_SUCCESS;\r | |
| 267 | } else {\r | |
| 268 | return EFI_NOT_FOUND;\r | |
| 269 | }\r | |
| 270 | }\r | |
| 271 | \r | |
| ed3d5ecb | 272 | if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) {\r |
| 529a5a86 MK |
273 | return EFI_INVALID_PARAMETER;\r |
| 274 | }\r | |
| 275 | \r | |
| 276 | Status = SmmCpuFeaturesReadSaveStateRegister (CpuIndex, Register, Width, Buffer);\r | |
| 277 | if (Status == EFI_UNSUPPORTED) {\r | |
| 278 | Status = ReadSaveStateRegister (CpuIndex, Register, Width, Buffer);\r | |
| 279 | }\r | |
| 053e878b | 280 | \r |
| 529a5a86 MK |
281 | return Status;\r |
| 282 | }\r | |
| 283 | \r | |
| 284 | /**\r | |
| 285 | Write data to the CPU save state.\r | |
| 286 | \r | |
| 287 | @param This EFI_SMM_CPU_PROTOCOL instance\r | |
| 288 | @param Width The number of bytes to read from the CPU save state.\r | |
| 289 | @param Register Specifies the CPU register to write to the save state.\r | |
| 290 | @param CpuIndex Specifies the zero-based index of the CPU save state\r | |
| 291 | @param Buffer Upon entry, this holds the new CPU register value.\r | |
| 292 | \r | |
| 293 | @retval EFI_SUCCESS The register was written from Save State\r | |
| 294 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r | |
| ef62da4f | 295 | @retval EFI_INVALID_PARAMETER ProcessorIndex or Width is not correct\r |
| 529a5a86 MK |
296 | \r |
| 297 | **/\r | |
| 298 | EFI_STATUS\r | |
| 299 | EFIAPI\r | |
| 300 | SmmWriteSaveState (\r | |
| 053e878b MK |
301 | IN CONST EFI_SMM_CPU_PROTOCOL *This,\r |
| 302 | IN UINTN Width,\r | |
| 303 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
| 304 | IN UINTN CpuIndex,\r | |
| 305 | IN CONST VOID *Buffer\r | |
| 529a5a86 MK |
306 | )\r |
| 307 | {\r | |
| 308 | EFI_STATUS Status;\r | |
| 309 | \r | |
| 310 | //\r | |
| 311 | // Retrieve pointer to the specified CPU's SMM Save State buffer\r | |
| 312 | //\r | |
| 313 | if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {\r | |
| 314 | return EFI_INVALID_PARAMETER;\r | |
| 315 | }\r | |
| 316 | \r | |
| 317 | //\r | |
| 318 | // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored\r | |
| 319 | //\r | |
| 320 | if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) {\r | |
| 321 | return EFI_SUCCESS;\r | |
| 322 | }\r | |
| 323 | \r | |
| 324 | if (!mSmmMpSyncData->CpuData[CpuIndex].Present) {\r | |
| 325 | return EFI_INVALID_PARAMETER;\r | |
| 326 | }\r | |
| 327 | \r | |
| 328 | Status = SmmCpuFeaturesWriteSaveStateRegister (CpuIndex, Register, Width, Buffer);\r | |
| 329 | if (Status == EFI_UNSUPPORTED) {\r | |
| 330 | Status = WriteSaveStateRegister (CpuIndex, Register, Width, Buffer);\r | |
| 331 | }\r | |
| 053e878b | 332 | \r |
| 529a5a86 MK |
333 | return Status;\r |
| 334 | }\r | |
| 335 | \r | |
| 529a5a86 MK |
336 | /**\r |
| 337 | C function for SMI handler. To change all processor's SMMBase Register.\r | |
| 338 | \r | |
| 339 | **/\r | |
| 340 | VOID\r | |
| 341 | EFIAPI\r | |
| 342 | SmmInitHandler (\r | |
| 343 | VOID\r | |
| 344 | )\r | |
| 345 | {\r | |
| 053e878b MK |
346 | UINT32 ApicId;\r |
| 347 | UINTN Index;\r | |
| 529a5a86 MK |
348 | \r |
| 349 | //\r | |
| 350 | // Update SMM IDT entries' code segment and load IDT\r | |
| 351 | //\r | |
| 352 | AsmWriteIdtr (&gcSmiIdtr);\r | |
| 353 | ApicId = GetApicId ();\r | |
| 354 | \r | |
| bb767506 | 355 | ASSERT (mNumberOfCpus <= mMaxNumberOfCpus);\r |
| 529a5a86 MK |
356 | \r |
| 357 | for (Index = 0; Index < mNumberOfCpus; Index++) {\r | |
| 358 | if (ApicId == (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {\r | |
| 359 | //\r | |
| 360 | // Initialize SMM specific features on the currently executing CPU\r | |
| 361 | //\r | |
| 362 | SmmCpuFeaturesInitializeProcessor (\r | |
| 363 | Index,\r | |
| 364 | mIsBsp,\r | |
| 365 | gSmmCpuPrivate->ProcessorInfo,\r | |
| 366 | &mCpuHotPlugData\r | |
| 367 | );\r | |
| 368 | \r | |
| a46a4c90 JF |
369 | if (!mSmmS3Flag) {\r |
| 370 | //\r | |
| 371 | // Check XD and BTS features on each processor on normal boot\r | |
| 372 | //\r | |
| 51773d49 | 373 | CheckFeatureSupported ();\r |
| a46a4c90 JF |
374 | }\r |
| 375 | \r | |
| 529a5a86 MK |
376 | if (mIsBsp) {\r |
| 377 | //\r | |
| 378 | // BSP rebase is already done above.\r | |
| 379 | // Initialize private data during S3 resume\r | |
| 380 | //\r | |
| 381 | InitializeMpSyncData ();\r | |
| 382 | }\r | |
| 383 | \r | |
| 384 | //\r | |
| 385 | // Hook return after RSM to set SMM re-based flag\r | |
| 386 | //\r | |
| 387 | SemaphoreHook (Index, &mRebased[Index]);\r | |
| 388 | \r | |
| 389 | return;\r | |
| 390 | }\r | |
| 391 | }\r | |
| 053e878b | 392 | \r |
| 529a5a86 MK |
393 | ASSERT (FALSE);\r |
| 394 | }\r | |
| 395 | \r | |
| 396 | /**\r | |
| 397 | Relocate SmmBases for each processor.\r | |
| 398 | \r | |
| 399 | Execute on first boot and all S3 resumes\r | |
| 400 | \r | |
| 401 | **/\r | |
| 402 | VOID\r | |
| 403 | EFIAPI\r | |
| 404 | SmmRelocateBases (\r | |
| 405 | VOID\r | |
| 406 | )\r | |
| 407 | {\r | |
| 408 | UINT8 BakBuf[BACK_BUF_SIZE];\r | |
| 409 | SMRAM_SAVE_STATE_MAP BakBuf2;\r | |
| 410 | SMRAM_SAVE_STATE_MAP *CpuStatePtr;\r | |
| 411 | UINT8 *U8Ptr;\r | |
| 412 | UINT32 ApicId;\r | |
| 413 | UINTN Index;\r | |
| 414 | UINTN BspIndex;\r | |
| 415 | \r | |
| 416 | //\r | |
| 417 | // Make sure the reserved size is large enough for procedure SmmInitTemplate.\r | |
| 418 | //\r | |
| 419 | ASSERT (sizeof (BakBuf) >= gcSmmInitSize);\r | |
| 420 | \r | |
| 421 | //\r | |
| 422 | // Patch ASM code template with current CR0, CR3, and CR4 values\r | |
| 423 | //\r | |
| f0053e83 LE |
424 | mSmmCr0 = (UINT32)AsmReadCr0 ();\r |
| 425 | PatchInstructionX86 (gPatchSmmCr0, mSmmCr0, 4);\r | |
| 6b0841c1 | 426 | PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);\r |
| 351b49c1 | 427 | mSmmCr4 = (UINT32)AsmReadCr4 ();\r |
| 3eb69b08 | 428 | PatchInstructionX86 (gPatchSmmCr4, mSmmCr4 & (~CR4_CET_ENABLE), 4);\r |
| 529a5a86 MK |
429 | \r |
| 430 | //\r | |
| 431 | // Patch GDTR for SMM base relocation\r | |
| 432 | //\r | |
| 433 | gcSmiInitGdtr.Base = gcSmiGdtr.Base;\r | |
| 434 | gcSmiInitGdtr.Limit = gcSmiGdtr.Limit;\r | |
| 435 | \r | |
| 053e878b | 436 | U8Ptr = (UINT8 *)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET);\r |
| 529a5a86 MK |
437 | CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r |
| 438 | \r | |
| 439 | //\r | |
| 440 | // Backup original contents at address 0x38000\r | |
| 441 | //\r | |
| 442 | CopyMem (BakBuf, U8Ptr, sizeof (BakBuf));\r | |
| 443 | CopyMem (&BakBuf2, CpuStatePtr, sizeof (BakBuf2));\r | |
| 444 | \r | |
| 445 | //\r | |
| 446 | // Load image for relocation\r | |
| 447 | //\r | |
| 448 | CopyMem (U8Ptr, gcSmmInitTemplate, gcSmmInitSize);\r | |
| 449 | \r | |
| 450 | //\r | |
| 451 | // Retrieve the local APIC ID of current processor\r | |
| 452 | //\r | |
| 453 | ApicId = GetApicId ();\r | |
| 454 | \r | |
| 455 | //\r | |
| 456 | // Relocate SM bases for all APs\r | |
| 457 | // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate\r | |
| 458 | //\r | |
| 459 | mIsBsp = FALSE;\r | |
| 460 | BspIndex = (UINTN)-1;\r | |
| 461 | for (Index = 0; Index < mNumberOfCpus; Index++) {\r | |
| 462 | mRebased[Index] = FALSE;\r | |
| 463 | if (ApicId != (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {\r | |
| 464 | SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);\r | |
| 465 | //\r | |
| 466 | // Wait for this AP to finish its 1st SMI\r | |
| 467 | //\r | |
| 053e878b MK |
468 | while (!mRebased[Index]) {\r |
| 469 | }\r | |
| 529a5a86 MK |
470 | } else {\r |
| 471 | //\r | |
| 472 | // BSP will be Relocated later\r | |
| 473 | //\r | |
| 474 | BspIndex = Index;\r | |
| 475 | }\r | |
| 476 | }\r | |
| 477 | \r | |
| 478 | //\r | |
| 479 | // Relocate BSP's SMM base\r | |
| 480 | //\r | |
| 481 | ASSERT (BspIndex != (UINTN)-1);\r | |
| 482 | mIsBsp = TRUE;\r | |
| 483 | SendSmiIpi (ApicId);\r | |
| 484 | //\r | |
| 485 | // Wait for the BSP to finish its 1st SMI\r | |
| 486 | //\r | |
| 053e878b MK |
487 | while (!mRebased[BspIndex]) {\r |
| 488 | }\r | |
| 529a5a86 MK |
489 | \r |
| 490 | //\r | |
| 491 | // Restore contents at address 0x38000\r | |
| 492 | //\r | |
| 493 | CopyMem (CpuStatePtr, &BakBuf2, sizeof (BakBuf2));\r | |
| 494 | CopyMem (U8Ptr, BakBuf, sizeof (BakBuf));\r | |
| 495 | }\r | |
| 496 | \r | |
| 529a5a86 MK |
497 | /**\r |
| 498 | SMM Ready To Lock event notification handler.\r | |
| 499 | \r | |
| 500 | The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to\r | |
| 501 | perform additional lock actions that must be performed from SMM on the next SMI.\r | |
| 502 | \r | |
| 503 | @param[in] Protocol Points to the protocol's unique identifier.\r | |
| 504 | @param[in] Interface Points to the interface instance.\r | |
| 505 | @param[in] Handle The handle on which the interface was installed.\r | |
| 506 | \r | |
| 507 | @retval EFI_SUCCESS Notification handler runs successfully.\r | |
| 508 | **/\r | |
| 509 | EFI_STATUS\r | |
| 510 | EFIAPI\r | |
| 511 | SmmReadyToLockEventNotify (\r | |
| 512 | IN CONST EFI_GUID *Protocol,\r | |
| 513 | IN VOID *Interface,\r | |
| 514 | IN EFI_HANDLE Handle\r | |
| 515 | )\r | |
| 516 | {\r | |
| 0bdc9e75 | 517 | GetAcpiCpuData ();\r |
| 529a5a86 | 518 | \r |
| d2fc7711 JY |
519 | //\r |
| 520 | // Cache a copy of UEFI memory map before we start profiling feature.\r | |
| 521 | //\r | |
| 522 | GetUefiMemoryMap ();\r | |
| 523 | \r | |
| 529a5a86 MK |
524 | //\r |
| 525 | // Set SMM ready to lock flag and return\r | |
| 526 | //\r | |
| 527 | mSmmReadyToLock = TRUE;\r | |
| 528 | return EFI_SUCCESS;\r | |
| 529 | }\r | |
| 530 | \r | |
| 531 | /**\r | |
| 532 | The module Entry Point of the CPU SMM driver.\r | |
| 533 | \r | |
| 534 | @param ImageHandle The firmware allocated handle for the EFI image.\r | |
| 535 | @param SystemTable A pointer to the EFI System Table.\r | |
| 536 | \r | |
| 537 | @retval EFI_SUCCESS The entry point is executed successfully.\r | |
| 538 | @retval Other Some error occurs when executing this entry point.\r | |
| 539 | \r | |
| 540 | **/\r | |
| 541 | EFI_STATUS\r | |
| 542 | EFIAPI\r | |
| 543 | PiCpuSmmEntry (\r | |
| 544 | IN EFI_HANDLE ImageHandle,\r | |
| 545 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
| 546 | )\r | |
| 547 | {\r | |
| 053e878b MK |
548 | EFI_STATUS Status;\r |
| 549 | EFI_MP_SERVICES_PROTOCOL *MpServices;\r | |
| 550 | UINTN NumberOfEnabledProcessors;\r | |
| 551 | UINTN Index;\r | |
| 552 | VOID *Buffer;\r | |
| 553 | UINTN BufferPages;\r | |
| 554 | UINTN TileCodeSize;\r | |
| 555 | UINTN TileDataSize;\r | |
| 556 | UINTN TileSize;\r | |
| 557 | UINT8 *Stacks;\r | |
| 558 | VOID *Registration;\r | |
| 559 | UINT32 RegEax;\r | |
| 560 | UINT32 RegEbx;\r | |
| 561 | UINT32 RegEcx;\r | |
| 562 | UINT32 RegEdx;\r | |
| 563 | UINTN FamilyId;\r | |
| 564 | UINTN ModelId;\r | |
| 565 | UINT32 Cr3;\r | |
| 529a5a86 | 566 | \r |
| e21e355e LG |
567 | //\r |
| 568 | // Initialize address fixup\r | |
| 569 | //\r | |
| 570 | PiSmmCpuSmmInitFixupAddress ();\r | |
| 571 | PiSmmCpuSmiEntryFixupAddress ();\r | |
| 572 | \r | |
| 529a5a86 MK |
573 | //\r |
| 574 | // Initialize Debug Agent to support source level debug in SMM code\r | |
| 575 | //\r | |
| 576 | InitializeDebugAgent (DEBUG_AGENT_INIT_SMM, NULL, NULL);\r | |
| 577 | \r | |
| 578 | //\r | |
| 579 | // Report the start of CPU SMM initialization.\r | |
| 580 | //\r | |
| 581 | REPORT_STATUS_CODE (\r | |
| 582 | EFI_PROGRESS_CODE,\r | |
| 583 | EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_INIT\r | |
| 584 | );\r | |
| 585 | \r | |
| 529a5a86 MK |
586 | //\r |
| 587 | // Find out SMRR Base and SMRR Size\r | |
| 588 | //\r | |
| 589 | FindSmramInfo (&mCpuHotPlugData.SmrrBase, &mCpuHotPlugData.SmrrSize);\r | |
| 590 | \r | |
| 591 | //\r | |
| 592 | // Get MP Services Protocol\r | |
| 593 | //\r | |
| 594 | Status = SystemTable->BootServices->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices);\r | |
| 595 | ASSERT_EFI_ERROR (Status);\r | |
| 596 | \r | |
| 597 | //\r | |
| 598 | // Use MP Services Protocol to retrieve the number of processors and number of enabled processors\r | |
| 599 | //\r | |
| 600 | Status = MpServices->GetNumberOfProcessors (MpServices, &mNumberOfCpus, &NumberOfEnabledProcessors);\r | |
| 601 | ASSERT_EFI_ERROR (Status);\r | |
| 602 | ASSERT (mNumberOfCpus <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r | |
| 603 | \r | |
| 604 | //\r | |
| 605 | // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.\r | |
| 606 | // A constant BSP index makes no sense because it may be hot removed.\r | |
| 607 | //\r | |
| 7c2a6033 | 608 | DEBUG_CODE_BEGIN ();\r |
| 053e878b MK |
609 | if (FeaturePcdGet (PcdCpuHotPlugSupport)) {\r |
| 610 | ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection));\r | |
| 611 | }\r | |
| 529a5a86 | 612 | \r |
| 7c2a6033 | 613 | DEBUG_CODE_END ();\r |
| 529a5a86 MK |
614 | \r |
| 615 | //\r | |
| 616 | // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.\r | |
| 617 | //\r | |
| 618 | mSmmCodeAccessCheckEnable = PcdGetBool (PcdCpuSmmCodeAccessCheckEnable);\r | |
| 96e1cba5 | 619 | DEBUG ((DEBUG_INFO, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable));\r |
| 529a5a86 | 620 | \r |
| 241f9149 LD |
621 | //\r |
| 622 | // Save the PcdPteMemoryEncryptionAddressOrMask value into a global variable.\r | |
| 623 | // Make sure AddressEncMask is contained to smallest supported address field.\r | |
| 624 | //\r | |
| 625 | mAddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r | |
| 96e1cba5 | 626 | DEBUG ((DEBUG_INFO, "mAddressEncMask = 0x%lx\n", mAddressEncMask));\r |
| 241f9149 | 627 | \r |
| 529a5a86 MK |
628 | //\r |
| 629 | // If support CPU hot plug, we need to allocate resources for possibly hot-added processors\r | |
| 630 | //\r | |
| 631 | if (FeaturePcdGet (PcdCpuHotPlugSupport)) {\r | |
| 632 | mMaxNumberOfCpus = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r | |
| 633 | } else {\r | |
| 634 | mMaxNumberOfCpus = mNumberOfCpus;\r | |
| 635 | }\r | |
| 053e878b | 636 | \r |
| 529a5a86 MK |
637 | gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus;\r |
| 638 | \r | |
| 639 | //\r | |
| 640 | // The CPU save state and code for the SMI entry point are tiled within an SMRAM\r | |
| 641 | // allocated buffer. The minimum size of this buffer for a uniprocessor system\r | |
| 642 | // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area\r | |
| 643 | // just below SMBASE + 64KB. If more than one CPU is present in the platform,\r | |
| 644 | // then the SMI entry point and the CPU save state areas can be tiles to minimize\r | |
| 645 | // the total amount SMRAM required for all the CPUs. The tile size can be computed\r | |
| 646 | // by adding the // CPU save state size, any extra CPU specific context, and\r | |
| 647 | // the size of code that must be placed at the SMI entry point to transfer\r | |
| 648 | // control to a C function in the native SMM execution mode. This size is\r | |
| 649 | // rounded up to the nearest power of 2 to give the tile size for a each CPU.\r | |
| 650 | // The total amount of memory required is the maximum number of CPUs that\r | |
| 651 | // platform supports times the tile size. The picture below shows the tiling,\r | |
| 652 | // where m is the number of tiles that fit in 32KB.\r | |
| 653 | //\r | |
| 654 | // +-----------------------------+ <-- 2^n offset from Base of allocated buffer\r | |
| 655 | // | CPU m+1 Save State |\r | |
| 656 | // +-----------------------------+\r | |
| 657 | // | CPU m+1 Extra Data |\r | |
| 658 | // +-----------------------------+\r | |
| 659 | // | Padding |\r | |
| 660 | // +-----------------------------+\r | |
| 661 | // | CPU 2m SMI Entry |\r | |
| 662 | // +#############################+ <-- Base of allocated buffer + 64 KB\r | |
| 663 | // | CPU m-1 Save State |\r | |
| 664 | // +-----------------------------+\r | |
| 665 | // | CPU m-1 Extra Data |\r | |
| 666 | // +-----------------------------+\r | |
| 667 | // | Padding |\r | |
| 668 | // +-----------------------------+\r | |
| 669 | // | CPU 2m-1 SMI Entry |\r | |
| 670 | // +=============================+ <-- 2^n offset from Base of allocated buffer\r | |
| 671 | // | . . . . . . . . . . . . |\r | |
| 672 | // +=============================+ <-- 2^n offset from Base of allocated buffer\r | |
| 673 | // | CPU 2 Save State |\r | |
| 674 | // +-----------------------------+\r | |
| 675 | // | CPU 2 Extra Data |\r | |
| 676 | // +-----------------------------+\r | |
| 677 | // | Padding |\r | |
| 678 | // +-----------------------------+\r | |
| 679 | // | CPU m+1 SMI Entry |\r | |
| 680 | // +=============================+ <-- Base of allocated buffer + 32 KB\r | |
| 681 | // | CPU 1 Save State |\r | |
| 682 | // +-----------------------------+\r | |
| 683 | // | CPU 1 Extra Data |\r | |
| 684 | // +-----------------------------+\r | |
| 685 | // | Padding |\r | |
| 686 | // +-----------------------------+\r | |
| 687 | // | CPU m SMI Entry |\r | |
| 688 | // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB\r | |
| 689 | // | CPU 0 Save State |\r | |
| 690 | // +-----------------------------+\r | |
| 691 | // | CPU 0 Extra Data |\r | |
| 692 | // +-----------------------------+\r | |
| 693 | // | Padding |\r | |
| 694 | // +-----------------------------+\r | |
| 695 | // | CPU m-1 SMI Entry |\r | |
| 696 | // +=============================+ <-- 2^n offset from Base of allocated buffer\r | |
| 697 | // | . . . . . . . . . . . . |\r | |
| 698 | // +=============================+ <-- 2^n offset from Base of allocated buffer\r | |
| 699 | // | Padding |\r | |
| 700 | // +-----------------------------+\r | |
| 701 | // | CPU 1 SMI Entry |\r | |
| 702 | // +=============================+ <-- 2^n offset from Base of allocated buffer\r | |
| 703 | // | Padding |\r | |
| 704 | // +-----------------------------+\r | |
| 705 | // | CPU 0 SMI Entry |\r | |
| 706 | // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB\r | |
| 707 | //\r | |
| 708 | \r | |
| 709 | //\r | |
| 710 | // Retrieve CPU Family\r | |
| 711 | //\r | |
| e9b3a6c9 | 712 | AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);\r |
| 529a5a86 | 713 | FamilyId = (RegEax >> 8) & 0xf;\r |
| 053e878b MK |
714 | ModelId = (RegEax >> 4) & 0xf;\r |
| 715 | if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {\r | |
| 529a5a86 MK |
716 | ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r |
| 717 | }\r | |
| 718 | \r | |
| e9b3a6c9 MK |
719 | RegEdx = 0;\r |
| 720 | AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r | |
| 721 | if (RegEax >= CPUID_EXTENDED_CPU_SIG) {\r | |
| 722 | AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);\r | |
| 723 | }\r | |
| 053e878b | 724 | \r |
| 529a5a86 MK |
725 | //\r |
| 726 | // Determine the mode of the CPU at the time an SMI occurs\r | |
| 727 | // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r | |
| 728 | // Volume 3C, Section 34.4.1.1\r | |
| 729 | //\r | |
| 730 | mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;\r | |
| 731 | if ((RegEdx & BIT29) != 0) {\r | |
| 732 | mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;\r | |
| 733 | }\r | |
| 053e878b | 734 | \r |
| 529a5a86 | 735 | if (FamilyId == 0x06) {\r |
| 053e878b | 736 | if ((ModelId == 0x17) || (ModelId == 0x0f) || (ModelId == 0x1c)) {\r |
| 529a5a86 MK |
737 | mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;\r |
| 738 | }\r | |
| 739 | }\r | |
| 740 | \r | |
| 3eb69b08 JY |
741 | DEBUG ((DEBUG_INFO, "PcdControlFlowEnforcementPropertyMask = %d\n", PcdGet32 (PcdControlFlowEnforcementPropertyMask)));\r |
| 742 | if (PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) {\r | |
| 5d34cc49 WH |
743 | AsmCpuid (CPUID_SIGNATURE, &RegEax, NULL, NULL, NULL);\r |
| 744 | if (RegEax >= CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS) {\r | |
| 3eb69b08 JY |
745 | AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL, NULL, &RegEcx, &RegEdx);\r |
| 746 | DEBUG ((DEBUG_INFO, "CPUID[7/0] ECX - 0x%08x\n", RegEcx));\r | |
| 747 | DEBUG ((DEBUG_INFO, " CET_SS - 0x%08x\n", RegEcx & CPUID_CET_SS));\r | |
| 748 | DEBUG ((DEBUG_INFO, " CET_IBT - 0x%08x\n", RegEdx & CPUID_CET_IBT));\r | |
| 749 | if ((RegEcx & CPUID_CET_SS) == 0) {\r | |
| 750 | mCetSupported = FALSE;\r | |
| 751 | PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);\r | |
| 752 | }\r | |
| 053e878b | 753 | \r |
| 3eb69b08 JY |
754 | if (mCetSupported) {\r |
| 755 | AsmCpuidEx (CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF, NULL, &RegEbx, &RegEcx, NULL);\r | |
| 756 | DEBUG ((DEBUG_INFO, "CPUID[D/1] EBX - 0x%08x, ECX - 0x%08x\n", RegEbx, RegEcx));\r | |
| 757 | AsmCpuidEx (CPUID_EXTENDED_STATE, 11, &RegEax, NULL, &RegEcx, NULL);\r | |
| 758 | DEBUG ((DEBUG_INFO, "CPUID[D/11] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx));\r | |
| 053e878b | 759 | AsmCpuidEx (CPUID_EXTENDED_STATE, 12, &RegEax, NULL, &RegEcx, NULL);\r |
| 3eb69b08 JY |
760 | DEBUG ((DEBUG_INFO, "CPUID[D/12] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx));\r |
| 761 | }\r | |
| 5d34cc49 WH |
762 | } else {\r |
| 763 | mCetSupported = FALSE;\r | |
| 053e878b | 764 | PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);\r |
| 3eb69b08 JY |
765 | }\r |
| 766 | } else {\r | |
| 767 | mCetSupported = FALSE;\r | |
| 768 | PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);\r | |
| 769 | }\r | |
| 770 | \r | |
| 529a5a86 MK |
771 | //\r |
| 772 | // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU\r | |
| f12367a0 MK |
773 | // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.\r |
| 774 | // This size is rounded up to nearest power of 2.\r | |
| 529a5a86 | 775 | //\r |
| ae82a30b | 776 | TileCodeSize = GetSmiHandlerSize ();\r |
| 053e878b | 777 | TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB);\r |
| f12367a0 | 778 | TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);\r |
| 053e878b MK |
779 | TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB);\r |
| 780 | TileSize = TileDataSize + TileCodeSize - 1;\r | |
| 781 | TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);\r | |
| 96e1cba5 | 782 | DEBUG ((DEBUG_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));\r |
| 529a5a86 MK |
783 | \r |
| 784 | //\r | |
| f12367a0 MK |
785 | // If the TileSize is larger than space available for the SMI Handler of\r |
| 786 | // CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save\r | |
| 787 | // State Map of CPU[i+1], then ASSERT(). If this ASSERT() is triggered, then\r | |
| 788 | // the SMI Handler size must be reduced or the size of the extra CPU specific\r | |
| 789 | // context must be reduced.\r | |
| 529a5a86 MK |
790 | //\r |
| 791 | ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));\r | |
| 792 | \r | |
| 793 | //\r | |
| 794 | // Allocate buffer for all of the tiles.\r | |
| 795 | //\r | |
| 796 | // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r | |
| 797 | // Volume 3C, Section 34.11 SMBASE Relocation\r | |
| 798 | // For Pentium and Intel486 processors, the SMBASE values must be\r | |
| 799 | // aligned on a 32-KByte boundary or the processor will enter shutdown\r | |
| 800 | // state during the execution of a RSM instruction.\r | |
| 801 | //\r | |
| 802 | // Intel486 processors: FamilyId is 4\r | |
| 803 | // Pentium processors : FamilyId is 5\r | |
| 804 | //\r | |
| ae82a30b | 805 | BufferPages = EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1));\r |
| 529a5a86 | 806 | if ((FamilyId == 4) || (FamilyId == 5)) {\r |
| 717fb604 | 807 | Buffer = AllocateAlignedCodePages (BufferPages, SIZE_32KB);\r |
| 529a5a86 | 808 | } else {\r |
| 717fb604 | 809 | Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB);\r |
| 529a5a86 | 810 | }\r |
| 053e878b | 811 | \r |
| 529a5a86 | 812 | ASSERT (Buffer != NULL);\r |
| 053e878b | 813 | DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages)));\r |
| 529a5a86 MK |
814 | \r |
| 815 | //\r | |
| 816 | // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.\r | |
| 817 | //\r | |
| 818 | gSmmCpuPrivate->ProcessorInfo = (EFI_PROCESSOR_INFORMATION *)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION) * mMaxNumberOfCpus);\r | |
| 819 | ASSERT (gSmmCpuPrivate->ProcessorInfo != NULL);\r | |
| 820 | \r | |
| 821 | gSmmCpuPrivate->Operation = (SMM_CPU_OPERATION *)AllocatePool (sizeof (SMM_CPU_OPERATION) * mMaxNumberOfCpus);\r | |
| 822 | ASSERT (gSmmCpuPrivate->Operation != NULL);\r | |
| 823 | \r | |
| 824 | gSmmCpuPrivate->CpuSaveStateSize = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus);\r | |
| 825 | ASSERT (gSmmCpuPrivate->CpuSaveStateSize != NULL);\r | |
| 826 | \r | |
| 827 | gSmmCpuPrivate->CpuSaveState = (VOID **)AllocatePool (sizeof (VOID *) * mMaxNumberOfCpus);\r | |
| 828 | ASSERT (gSmmCpuPrivate->CpuSaveState != NULL);\r | |
| 829 | \r | |
| 830 | mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveStateSize = gSmmCpuPrivate->CpuSaveStateSize;\r | |
| 831 | mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveState = gSmmCpuPrivate->CpuSaveState;\r | |
| 529a5a86 MK |
832 | \r |
| 833 | //\r | |
| 834 | // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.\r | |
| 835 | //\r | |
| 836 | mCpuHotPlugData.ApicId = (UINT64 *)AllocatePool (sizeof (UINT64) * mMaxNumberOfCpus);\r | |
| 837 | ASSERT (mCpuHotPlugData.ApicId != NULL);\r | |
| 838 | mCpuHotPlugData.SmBase = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus);\r | |
| 839 | ASSERT (mCpuHotPlugData.SmBase != NULL);\r | |
| 840 | mCpuHotPlugData.ArrayLength = (UINT32)mMaxNumberOfCpus;\r | |
| 841 | \r | |
| 842 | //\r | |
| 843 | // Retrieve APIC ID of each enabled processor from the MP Services protocol.\r | |
| 844 | // Also compute the SMBASE address, CPU Save State address, and CPU Save state\r | |
| 845 | // size for each CPU in the platform\r | |
| 846 | //\r | |
| 847 | for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r | |
| 053e878b MK |
848 | mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;\r |
| 849 | gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof (SMRAM_SAVE_STATE_MAP);\r | |
| 529a5a86 | 850 | gSmmCpuPrivate->CpuSaveState[Index] = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET);\r |
| 053e878b | 851 | gSmmCpuPrivate->Operation[Index] = SmmCpuNone;\r |
| 529a5a86 MK |
852 | \r |
| 853 | if (Index < mNumberOfCpus) {\r | |
| 854 | Status = MpServices->GetProcessorInfo (MpServices, Index, &gSmmCpuPrivate->ProcessorInfo[Index]);\r | |
| 855 | ASSERT_EFI_ERROR (Status);\r | |
| 856 | mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId;\r | |
| 857 | \r | |
| 053e878b MK |
858 | DEBUG ((\r |
| 859 | DEBUG_INFO,\r | |
| 860 | "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",\r | |
| 529a5a86 MK |
861 | Index,\r |
| 862 | (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId,\r | |
| 863 | mCpuHotPlugData.SmBase[Index],\r | |
| 864 | gSmmCpuPrivate->CpuSaveState[Index],\r | |
| 865 | gSmmCpuPrivate->CpuSaveStateSize[Index]\r | |
| 866 | ));\r | |
| 867 | } else {\r | |
| 868 | gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = INVALID_APIC_ID;\r | |
| 053e878b | 869 | mCpuHotPlugData.ApicId[Index] = INVALID_APIC_ID;\r |
| 529a5a86 MK |
870 | }\r |
| 871 | }\r | |
| 872 | \r | |
| 873 | //\r | |
| 874 | // Allocate SMI stacks for all processors.\r | |
| 875 | //\r | |
| 3eb69b08 | 876 | mSmmStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize)));\r |
| 529a5a86 MK |
877 | if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r |
| 878 | //\r | |
| 455b0347 S |
879 | // SMM Stack Guard Enabled\r |
| 880 | // 2 more pages is allocated for each processor, one is guard page and the other is known good stack.\r | |
| 529a5a86 | 881 | //\r |
| 455b0347 S |
882 | // +--------------------------------------------------+-----+--------------------------------------------------+\r |
| 883 | // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack |\r | |
| 884 | // +--------------------------------------------------+-----+--------------------------------------------------+\r | |
| 885 | // | 4K | 4K PcdCpuSmmStackSize| | 4K | 4K PcdCpuSmmStackSize|\r | |
| 886 | // |<---------------- mSmmStackSize ----------------->| |<---------------- mSmmStackSize ----------------->|\r | |
| 887 | // | | | |\r | |
| 888 | // |<------------------ Processor 0 ----------------->| |<------------------ Processor n ----------------->|\r | |
| 529a5a86 | 889 | //\r |
| 3eb69b08 JY |
890 | mSmmStackSize += EFI_PAGES_TO_SIZE (2);\r |
| 891 | }\r | |
| 892 | \r | |
| 893 | mSmmShadowStackSize = 0;\r | |
| 894 | if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {\r | |
| 3eb69b08 | 895 | mSmmShadowStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmShadowStackSize)));\r |
| 455b0347 | 896 | \r |
| 3eb69b08 | 897 | if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r |
| 455b0347 S |
898 | //\r |
| 899 | // SMM Stack Guard Enabled\r | |
| 900 | // Append Shadow Stack after normal stack\r | |
| 901 | // 2 more pages is allocated for each processor, one is guard page and the other is known good shadow stack.\r | |
| 902 | //\r | |
| 903 | // |= Stacks\r | |
| 904 | // +--------------------------------------------------+---------------------------------------------------------------+\r | |
| 905 | // | Known Good Stack | Guard Page | SMM Stack | Known Good Shadow Stack | Guard Page | SMM Shadow Stack |\r | |
| 906 | // +--------------------------------------------------+---------------------------------------------------------------+\r | |
| 907 | // | 4K | 4K |PcdCpuSmmStackSize| 4K | 4K |PcdCpuSmmShadowStackSize|\r | |
| 908 | // |<---------------- mSmmStackSize ----------------->|<--------------------- mSmmShadowStackSize ------------------->|\r | |
| 909 | // | |\r | |
| 910 | // |<-------------------------------------------- Processor N ------------------------------------------------------->|\r | |
| 911 | //\r | |
| 3eb69b08 | 912 | mSmmShadowStackSize += EFI_PAGES_TO_SIZE (2);\r |
| 455b0347 S |
913 | } else {\r |
| 914 | //\r | |
| 915 | // SMM Stack Guard Disabled (Known Good Stack is still required for potential stack switch.)\r | |
| 916 | // Append Shadow Stack after normal stack with 1 more page as known good shadow stack.\r | |
| 917 | // 1 more pages is allocated for each processor, it is known good stack.\r | |
| 918 | //\r | |
| 919 | //\r | |
| 920 | // |= Stacks\r | |
| 921 | // +-------------------------------------+--------------------------------------------------+\r | |
| 922 | // | Known Good Stack | SMM Stack | Known Good Shadow Stack | SMM Shadow Stack |\r | |
| 923 | // +-------------------------------------+--------------------------------------------------+\r | |
| 924 | // | 4K |PcdCpuSmmStackSize| 4K |PcdCpuSmmShadowStackSize|\r | |
| 925 | // |<---------- mSmmStackSize ---------->|<--------------- mSmmShadowStackSize ------------>|\r | |
| 926 | // | |\r | |
| 927 | // |<-------------------------------- Processor N ----------------------------------------->|\r | |
| 928 | //\r | |
| 929 | mSmmShadowStackSize += EFI_PAGES_TO_SIZE (1);\r | |
| 930 | mSmmStackSize += EFI_PAGES_TO_SIZE (1);\r | |
| 3eb69b08 JY |
931 | }\r |
| 932 | }\r | |
| 933 | \r | |
| 053e878b | 934 | Stacks = (UINT8 *)AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (mSmmStackSize + mSmmShadowStackSize)));\r |
| 3eb69b08 JY |
935 | ASSERT (Stacks != NULL);\r |
| 936 | mSmmStackArrayBase = (UINTN)Stacks;\r | |
| 053e878b | 937 | mSmmStackArrayEnd = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (mSmmStackSize + mSmmShadowStackSize) - 1;\r |
| 3eb69b08 JY |
938 | \r |
| 939 | DEBUG ((DEBUG_INFO, "Stacks - 0x%x\n", Stacks));\r | |
| 940 | DEBUG ((DEBUG_INFO, "mSmmStackSize - 0x%x\n", mSmmStackSize));\r | |
| 941 | DEBUG ((DEBUG_INFO, "PcdCpuSmmStackGuard - 0x%x\n", FeaturePcdGet (PcdCpuSmmStackGuard)));\r | |
| 942 | if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {\r | |
| 943 | DEBUG ((DEBUG_INFO, "mSmmShadowStackSize - 0x%x\n", mSmmShadowStackSize));\r | |
| 529a5a86 MK |
944 | }\r |
| 945 | \r | |
| 946 | //\r | |
| 947 | // Set SMI stack for SMM base relocation\r | |
| 948 | //\r | |
| 5830d2c3 LE |
949 | PatchInstructionX86 (\r |
| 950 | gPatchSmmInitStack,\r | |
| 053e878b | 951 | (UINTN)(Stacks + mSmmStackSize - sizeof (UINTN)),\r |
| 5830d2c3 LE |
952 | sizeof (UINTN)\r |
| 953 | );\r | |
| 529a5a86 MK |
954 | \r |
| 955 | //\r | |
| 956 | // Initialize IDT\r | |
| 957 | //\r | |
| 958 | InitializeSmmIdt ();\r | |
| 959 | \r | |
| 960 | //\r | |
| 961 | // Relocate SMM Base addresses to the ones allocated from SMRAM\r | |
| 962 | //\r | |
| 963 | mRebased = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberOfCpus);\r | |
| 964 | ASSERT (mRebased != NULL);\r | |
| 965 | SmmRelocateBases ();\r | |
| 966 | \r | |
| 967 | //\r | |
| 968 | // Call hook for BSP to perform extra actions in normal mode after all\r | |
| 969 | // SMM base addresses have been relocated on all CPUs\r | |
| 970 | //\r | |
| 971 | SmmCpuFeaturesSmmRelocationComplete ();\r | |
| 972 | \r | |
| 717fb604 JY |
973 | DEBUG ((DEBUG_INFO, "mXdSupported - 0x%x\n", mXdSupported));\r |
| 974 | \r | |
| 529a5a86 MK |
975 | //\r |
| 976 | // SMM Time initialization\r | |
| 977 | //\r | |
| 978 | InitializeSmmTimer ();\r | |
| 979 | \r | |
| 980 | //\r | |
| 981 | // Initialize MP globals\r | |
| 982 | //\r | |
| 3eb69b08 JY |
983 | Cr3 = InitializeMpServiceData (Stacks, mSmmStackSize, mSmmShadowStackSize);\r |
| 984 | \r | |
| 985 | if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {\r | |
| 986 | for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {\r | |
| 987 | SetShadowStack (\r | |
| 988 | Cr3,\r | |
| 989 | (EFI_PHYSICAL_ADDRESS)(UINTN)Stacks + mSmmStackSize + (mSmmStackSize + mSmmShadowStackSize) * Index,\r | |
| 990 | mSmmShadowStackSize\r | |
| 991 | );\r | |
| 992 | if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r | |
| 993 | SetNotPresentPage (\r | |
| 994 | Cr3,\r | |
| 053e878b MK |
995 | (EFI_PHYSICAL_ADDRESS)(UINTN)Stacks + mSmmStackSize + EFI_PAGES_TO_SIZE (1) + (mSmmStackSize + mSmmShadowStackSize) * Index,\r |
| 996 | EFI_PAGES_TO_SIZE (1)\r | |
| 3eb69b08 JY |
997 | );\r |
| 998 | }\r | |
| 999 | }\r | |
| 1000 | }\r | |
| 529a5a86 MK |
1001 | \r |
| 1002 | //\r | |
| 1003 | // Fill in SMM Reserved Regions\r | |
| 1004 | //\r | |
| 1005 | gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedStart = 0;\r | |
| 1006 | gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedSize = 0;\r | |
| 1007 | \r | |
| 1008 | //\r | |
| 1009 | // Install the SMM Configuration Protocol onto a new handle on the handle database.\r | |
| 1010 | // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer\r | |
| 1011 | // to an SMRAM address will be present in the handle database\r | |
| 1012 | //\r | |
| 1013 | Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces (\r | |
| 1014 | &gSmmCpuPrivate->SmmCpuHandle,\r | |
| 053e878b MK |
1015 | &gEfiSmmConfigurationProtocolGuid,\r |
| 1016 | &gSmmCpuPrivate->SmmConfiguration,\r | |
| 529a5a86 MK |
1017 | NULL\r |
| 1018 | );\r | |
| 1019 | ASSERT_EFI_ERROR (Status);\r | |
| 1020 | \r | |
| 1021 | //\r | |
| 1022 | // Install the SMM CPU Protocol into SMM protocol database\r | |
| 1023 | //\r | |
| 1024 | Status = gSmst->SmmInstallProtocolInterface (\r | |
| 1025 | &mSmmCpuHandle,\r | |
| 1026 | &gEfiSmmCpuProtocolGuid,\r | |
| 1027 | EFI_NATIVE_INTERFACE,\r | |
| 1028 | &mSmmCpu\r | |
| 1029 | );\r | |
| 1030 | ASSERT_EFI_ERROR (Status);\r | |
| 1031 | \r | |
| 827330cc JW |
1032 | //\r |
| 1033 | // Install the SMM Memory Attribute Protocol into SMM protocol database\r | |
| 1034 | //\r | |
| 1035 | Status = gSmst->SmmInstallProtocolInterface (\r | |
| 1036 | &mSmmCpuHandle,\r | |
| 1037 | &gEdkiiSmmMemoryAttributeProtocolGuid,\r | |
| 1038 | EFI_NATIVE_INTERFACE,\r | |
| 1039 | &mSmmMemoryAttribute\r | |
| 1040 | );\r | |
| 1041 | ASSERT_EFI_ERROR (Status);\r | |
| 1042 | \r | |
| 51dd408a ED |
1043 | //\r |
| 1044 | // Initialize global buffer for MM MP.\r | |
| 1045 | //\r | |
| 1046 | InitializeDataForMmMp ();\r | |
| 1047 | \r | |
| c14c4719 WJ |
1048 | //\r |
| 1049 | // Initialize Package First Thread Index Info.\r | |
| 1050 | //\r | |
| 1051 | InitPackageFirstThreadIndexInfo ();\r | |
| 1052 | \r | |
| 51dd408a ED |
1053 | //\r |
| 1054 | // Install the SMM Mp Protocol into SMM protocol database\r | |
| 1055 | //\r | |
| 1056 | Status = gSmst->SmmInstallProtocolInterface (\r | |
| 1057 | &mSmmCpuHandle,\r | |
| 1058 | &gEfiMmMpProtocolGuid,\r | |
| 1059 | EFI_NATIVE_INTERFACE,\r | |
| 1060 | &mSmmMp\r | |
| 1061 | );\r | |
| 1062 | ASSERT_EFI_ERROR (Status);\r | |
| 1063 | \r | |
| 529a5a86 MK |
1064 | //\r |
| 1065 | // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.\r | |
| 1066 | //\r | |
| 1067 | if (FeaturePcdGet (PcdCpuHotPlugSupport)) {\r | |
| 9838b016 MK |
1068 | Status = PcdSet64S (PcdCpuHotPlugDataAddress, (UINT64)(UINTN)&mCpuHotPlugData);\r |
| 1069 | ASSERT_EFI_ERROR (Status);\r | |
| 529a5a86 MK |
1070 | }\r |
| 1071 | \r | |
| 1072 | //\r | |
| 1073 | // Initialize SMM CPU Services Support\r | |
| 1074 | //\r | |
| 1075 | Status = InitializeSmmCpuServices (mSmmCpuHandle);\r | |
| 1076 | ASSERT_EFI_ERROR (Status);\r | |
| 1077 | \r | |
| 529a5a86 MK |
1078 | //\r |
| 1079 | // register SMM Ready To Lock Protocol notification\r | |
| 1080 | //\r | |
| 1081 | Status = gSmst->SmmRegisterProtocolNotify (\r | |
| 1082 | &gEfiSmmReadyToLockProtocolGuid,\r | |
| 1083 | SmmReadyToLockEventNotify,\r | |
| 1084 | &Registration\r | |
| 1085 | );\r | |
| 1086 | ASSERT_EFI_ERROR (Status);\r | |
| 1087 | \r | |
| 529a5a86 MK |
1088 | //\r |
| 1089 | // Initialize SMM Profile feature\r | |
| 1090 | //\r | |
| 1091 | InitSmmProfile (Cr3);\r | |
| 1092 | \r | |
| b10d5ddc | 1093 | GetAcpiS3EnableFlag ();\r |
| 0bdc9e75 | 1094 | InitSmmS3ResumeState (Cr3);\r |
| 529a5a86 | 1095 | \r |
| 96e1cba5 | 1096 | DEBUG ((DEBUG_INFO, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));\r |
| 529a5a86 MK |
1097 | \r |
| 1098 | return EFI_SUCCESS;\r | |
| 1099 | }\r | |
| 1100 | \r | |
| 1101 | /**\r | |
| 1102 | \r | |
| 1103 | Find out SMRAM information including SMRR base and SMRR size.\r | |
| 1104 | \r | |
| 1105 | @param SmrrBase SMRR base\r | |
| 1106 | @param SmrrSize SMRR size\r | |
| 1107 | \r | |
| 1108 | **/\r | |
| 1109 | VOID\r | |
| 1110 | FindSmramInfo (\r | |
| 053e878b MK |
1111 | OUT UINT32 *SmrrBase,\r |
| 1112 | OUT UINT32 *SmrrSize\r | |
| 529a5a86 MK |
1113 | )\r |
| 1114 | {\r | |
| 053e878b MK |
1115 | EFI_STATUS Status;\r |
| 1116 | UINTN Size;\r | |
| 1117 | EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;\r | |
| 1118 | EFI_SMRAM_DESCRIPTOR *CurrentSmramRange;\r | |
| 1119 | UINTN Index;\r | |
| 1120 | UINT64 MaxSize;\r | |
| 1121 | BOOLEAN Found;\r | |
| 529a5a86 MK |
1122 | \r |
| 1123 | //\r | |
| 1124 | // Get SMM Access Protocol\r | |
| 1125 | //\r | |
| 1126 | Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **)&SmmAccess);\r | |
| 1127 | ASSERT_EFI_ERROR (Status);\r | |
| 1128 | \r | |
| 1129 | //\r | |
| 1130 | // Get SMRAM information\r | |
| 1131 | //\r | |
| 053e878b | 1132 | Size = 0;\r |
| 529a5a86 MK |
1133 | Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL);\r |
| 1134 | ASSERT (Status == EFI_BUFFER_TOO_SMALL);\r | |
| 1135 | \r | |
| 7ed6f781 JF |
1136 | mSmmCpuSmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);\r |
| 1137 | ASSERT (mSmmCpuSmramRanges != NULL);\r | |
| 529a5a86 | 1138 | \r |
| 7ed6f781 | 1139 | Status = SmmAccess->GetCapabilities (SmmAccess, &Size, mSmmCpuSmramRanges);\r |
| 529a5a86 MK |
1140 | ASSERT_EFI_ERROR (Status);\r |
| 1141 | \r | |
| 7ed6f781 | 1142 | mSmmCpuSmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);\r |
| 529a5a86 MK |
1143 | \r |
| 1144 | //\r | |
| 1145 | // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size\r | |
| 1146 | //\r | |
| 1147 | CurrentSmramRange = NULL;\r | |
| 7ed6f781 | 1148 | for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index < mSmmCpuSmramRangeCount; Index++) {\r |
| 529a5a86 MK |
1149 | //\r |
| 1150 | // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization\r | |
| 1151 | //\r | |
| 7ed6f781 | 1152 | if ((mSmmCpuSmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {\r |
| 529a5a86 MK |
1153 | continue;\r |
| 1154 | }\r | |
| 1155 | \r | |
| 7ed6f781 JF |
1156 | if (mSmmCpuSmramRanges[Index].CpuStart >= BASE_1MB) {\r |
| 1157 | if ((mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) <= SMRR_MAX_ADDRESS) {\r | |
| 1158 | if (mSmmCpuSmramRanges[Index].PhysicalSize >= MaxSize) {\r | |
| 053e878b | 1159 | MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize;\r |
| 7ed6f781 | 1160 | CurrentSmramRange = &mSmmCpuSmramRanges[Index];\r |
| 529a5a86 MK |
1161 | }\r |
| 1162 | }\r | |
| 1163 | }\r | |
| 1164 | }\r | |
| 1165 | \r | |
| 1166 | ASSERT (CurrentSmramRange != NULL);\r | |
| 1167 | \r | |
| 1168 | *SmrrBase = (UINT32)CurrentSmramRange->CpuStart;\r | |
| 1169 | *SmrrSize = (UINT32)CurrentSmramRange->PhysicalSize;\r | |
| 1170 | \r | |
| 1171 | do {\r | |
| 1172 | Found = FALSE;\r | |
| 7ed6f781 | 1173 | for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {\r |
| 053e878b MK |
1174 | if ((mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase) &&\r |
| 1175 | (*SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)))\r | |
| 1176 | {\r | |
| 7ed6f781 JF |
1177 | *SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart;\r |
| 1178 | *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);\r | |
| 053e878b MK |
1179 | Found = TRUE;\r |
| 1180 | } else if (((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart) && (mSmmCpuSmramRanges[Index].PhysicalSize > 0)) {\r | |
| 7ed6f781 | 1181 | *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);\r |
| 053e878b | 1182 | Found = TRUE;\r |
| 529a5a86 MK |
1183 | }\r |
| 1184 | }\r | |
| 1185 | } while (Found);\r | |
| 1186 | \r | |
| 96e1cba5 | 1187 | DEBUG ((DEBUG_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *SmrrSize));\r |
| 529a5a86 MK |
1188 | }\r |
| 1189 | \r | |
| 1190 | /**\r | |
| 1191 | Configure SMM Code Access Check feature on an AP.\r | |
| 1192 | SMM Feature Control MSR will be locked after configuration.\r | |
| 1193 | \r | |
| 1194 | @param[in,out] Buffer Pointer to private data buffer.\r | |
| 1195 | **/\r | |
| 1196 | VOID\r | |
| 1197 | EFIAPI\r | |
| 1198 | ConfigSmmCodeAccessCheckOnCurrentProcessor (\r | |
| 1199 | IN OUT VOID *Buffer\r | |
| 1200 | )\r | |
| 1201 | {\r | |
| 1202 | UINTN CpuIndex;\r | |
| 1203 | UINT64 SmmFeatureControlMsr;\r | |
| 1204 | UINT64 NewSmmFeatureControlMsr;\r | |
| 1205 | \r | |
| 1206 | //\r | |
| 1207 | // Retrieve the CPU Index from the context passed in\r | |
| 1208 | //\r | |
| 1209 | CpuIndex = *(UINTN *)Buffer;\r | |
| 1210 | \r | |
| 1211 | //\r | |
| 1212 | // Get the current SMM Feature Control MSR value\r | |
| 1213 | //\r | |
| 1214 | SmmFeatureControlMsr = SmmCpuFeaturesGetSmmRegister (CpuIndex, SmmRegFeatureControl);\r | |
| 1215 | \r | |
| 1216 | //\r | |
| 1217 | // Compute the new SMM Feature Control MSR value\r | |
| 1218 | //\r | |
| 1219 | NewSmmFeatureControlMsr = SmmFeatureControlMsr;\r | |
| 1220 | if (mSmmCodeAccessCheckEnable) {\r | |
| 1221 | NewSmmFeatureControlMsr |= SMM_CODE_CHK_EN_BIT;\r | |
| f6bc3a6d JF |
1222 | if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock)) {\r |
| 1223 | NewSmmFeatureControlMsr |= SMM_FEATURE_CONTROL_LOCK_BIT;\r | |
| 1224 | }\r | |
| 529a5a86 MK |
1225 | }\r |
| 1226 | \r | |
| 1227 | //\r | |
| 1228 | // Only set the SMM Feature Control MSR value if the new value is different than the current value\r | |
| 1229 | //\r | |
| 1230 | if (NewSmmFeatureControlMsr != SmmFeatureControlMsr) {\r | |
| 1231 | SmmCpuFeaturesSetSmmRegister (CpuIndex, SmmRegFeatureControl, NewSmmFeatureControlMsr);\r | |
| 1232 | }\r | |
| 1233 | \r | |
| 1234 | //\r | |
| 1235 | // Release the spin lock user to serialize the updates to the SMM Feature Control MSR\r | |
| 1236 | //\r | |
| fe3a75bc | 1237 | ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);\r |
| 529a5a86 MK |
1238 | }\r |
| 1239 | \r | |
| 1240 | /**\r | |
| 1241 | Configure SMM Code Access Check feature for all processors.\r | |
| 1242 | SMM Feature Control MSR will be locked after configuration.\r | |
| 1243 | **/\r | |
| 1244 | VOID\r | |
| 1245 | ConfigSmmCodeAccessCheck (\r | |
| 1246 | VOID\r | |
| 1247 | )\r | |
| 1248 | {\r | |
| 1249 | UINTN Index;\r | |
| 1250 | EFI_STATUS Status;\r | |
| 1251 | \r | |
| 1252 | //\r | |
| 1253 | // Check to see if the Feature Control MSR is supported on this CPU\r | |
| 1254 | //\r | |
| f6b0cb17 | 1255 | Index = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu;\r |
| 529a5a86 MK |
1256 | if (!SmmCpuFeaturesIsSmmRegisterSupported (Index, SmmRegFeatureControl)) {\r |
| 1257 | mSmmCodeAccessCheckEnable = FALSE;\r | |
| 1258 | return;\r | |
| 1259 | }\r | |
| 1260 | \r | |
| 1261 | //\r | |
| 1262 | // Check to see if the CPU supports the SMM Code Access Check feature\r | |
| 1263 | // Do not access this MSR unless the CPU supports the SmmRegFeatureControl\r | |
| 1264 | //\r | |
| 1265 | if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) == 0) {\r | |
| 1266 | mSmmCodeAccessCheckEnable = FALSE;\r | |
| 529a5a86 MK |
1267 | return;\r |
| 1268 | }\r | |
| 1269 | \r | |
| 1270 | //\r | |
| 1271 | // Initialize the lock used to serialize the MSR programming in BSP and all APs\r | |
| 1272 | //\r | |
| fe3a75bc | 1273 | InitializeSpinLock (mConfigSmmCodeAccessCheckLock);\r |
| 529a5a86 MK |
1274 | \r |
| 1275 | //\r | |
| 1276 | // Acquire Config SMM Code Access Check spin lock. The BSP will release the\r | |
| 1277 | // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().\r | |
| 1278 | //\r | |
| fe3a75bc | 1279 | AcquireSpinLock (mConfigSmmCodeAccessCheckLock);\r |
| 529a5a86 MK |
1280 | \r |
| 1281 | //\r | |
| 1282 | // Enable SMM Code Access Check feature on the BSP.\r | |
| 1283 | //\r | |
| 1284 | ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index);\r | |
| 1285 | \r | |
| 1286 | //\r | |
| 1287 | // Enable SMM Code Access Check feature for the APs.\r | |
| 1288 | //\r | |
| 1289 | for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {\r | |
| f6b0cb17 | 1290 | if (Index != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {\r |
| b7025df8 JF |
1291 | if (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {\r |
| 1292 | //\r | |
| 1293 | // If this processor does not exist\r | |
| 1294 | //\r | |
| 1295 | continue;\r | |
| 1296 | }\r | |
| 053e878b | 1297 | \r |
| 529a5a86 MK |
1298 | //\r |
| 1299 | // Acquire Config SMM Code Access Check spin lock. The AP will release the\r | |
| 1300 | // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().\r | |
| 1301 | //\r | |
| fe3a75bc | 1302 | AcquireSpinLock (mConfigSmmCodeAccessCheckLock);\r |
| 529a5a86 MK |
1303 | \r |
| 1304 | //\r | |
| 1305 | // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.\r | |
| 1306 | //\r | |
| 1307 | Status = gSmst->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor, Index, &Index);\r | |
| 1308 | ASSERT_EFI_ERROR (Status);\r | |
| 1309 | \r | |
| 1310 | //\r | |
| 1311 | // Wait for the AP to release the Config SMM Code Access Check spin lock.\r | |
| 1312 | //\r | |
| fe3a75bc | 1313 | while (!AcquireSpinLockOrFail (mConfigSmmCodeAccessCheckLock)) {\r |
| 529a5a86 MK |
1314 | CpuPause ();\r |
| 1315 | }\r | |
| 1316 | \r | |
| 1317 | //\r | |
| 1318 | // Release the Config SMM Code Access Check spin lock.\r | |
| 1319 | //\r | |
| fe3a75bc | 1320 | ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);\r |
| 529a5a86 MK |
1321 | }\r |
| 1322 | }\r | |
| 1323 | }\r | |
| 1324 | \r | |
| 21c17193 JY |
1325 | /**\r |
| 1326 | This API provides a way to allocate memory for page table.\r | |
| 1327 | \r | |
| 1328 | This API can be called more once to allocate memory for page tables.\r | |
| 1329 | \r | |
| 1330 | Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r | |
| 1331 | allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r | |
| 1332 | is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r | |
| 1333 | returned.\r | |
| 1334 | \r | |
| 1335 | @param Pages The number of 4 KB pages to allocate.\r | |
| 1336 | \r | |
| 1337 | @return A pointer to the allocated buffer or NULL if allocation fails.\r | |
| 1338 | \r | |
| 1339 | **/\r | |
| 1340 | VOID *\r | |
| 1341 | AllocatePageTableMemory (\r | |
| 053e878b | 1342 | IN UINTN Pages\r |
| 21c17193 JY |
1343 | )\r |
| 1344 | {\r | |
| 1345 | VOID *Buffer;\r | |
| 1346 | \r | |
| 1347 | Buffer = SmmCpuFeaturesAllocatePageTableMemory (Pages);\r | |
| 1348 | if (Buffer != NULL) {\r | |
| 1349 | return Buffer;\r | |
| 1350 | }\r | |
| 053e878b | 1351 | \r |
| 21c17193 JY |
1352 | return AllocatePages (Pages);\r |
| 1353 | }\r | |
| 1354 | \r | |
| 717fb604 JY |
1355 | /**\r |
| 1356 | Allocate pages for code.\r | |
| 1357 | \r | |
| 1358 | @param[in] Pages Number of pages to be allocated.\r | |
| 1359 | \r | |
| 1360 | @return Allocated memory.\r | |
| 1361 | **/\r | |
| 1362 | VOID *\r | |
| 1363 | AllocateCodePages (\r | |
| 053e878b | 1364 | IN UINTN Pages\r |
| 717fb604 JY |
1365 | )\r |
| 1366 | {\r | |
| 1367 | EFI_STATUS Status;\r | |
| 1368 | EFI_PHYSICAL_ADDRESS Memory;\r | |
| 1369 | \r | |
| 1370 | if (Pages == 0) {\r | |
| 1371 | return NULL;\r | |
| 1372 | }\r | |
| 1373 | \r | |
| 1374 | Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, Pages, &Memory);\r | |
| 1375 | if (EFI_ERROR (Status)) {\r | |
| 1376 | return NULL;\r | |
| 1377 | }\r | |
| 053e878b MK |
1378 | \r |
| 1379 | return (VOID *)(UINTN)Memory;\r | |
| 717fb604 JY |
1380 | }\r |
| 1381 | \r | |
| 1382 | /**\r | |
| 1383 | Allocate aligned pages for code.\r | |
| 1384 | \r | |
| 1385 | @param[in] Pages Number of pages to be allocated.\r | |
| 1386 | @param[in] Alignment The requested alignment of the allocation.\r | |
| 1387 | Must be a power of two.\r | |
| 1388 | If Alignment is zero, then byte alignment is used.\r | |
| 1389 | \r | |
| 1390 | @return Allocated memory.\r | |
| 1391 | **/\r | |
| 1392 | VOID *\r | |
| 1393 | AllocateAlignedCodePages (\r | |
| 053e878b MK |
1394 | IN UINTN Pages,\r |
| 1395 | IN UINTN Alignment\r | |
| 717fb604 JY |
1396 | )\r |
| 1397 | {\r | |
| 1398 | EFI_STATUS Status;\r | |
| 1399 | EFI_PHYSICAL_ADDRESS Memory;\r | |
| 1400 | UINTN AlignedMemory;\r | |
| 1401 | UINTN AlignmentMask;\r | |
| 1402 | UINTN UnalignedPages;\r | |
| 1403 | UINTN RealPages;\r | |
| 1404 | \r | |
| 1405 | //\r | |
| 1406 | // Alignment must be a power of two or zero.\r | |
| 1407 | //\r | |
| 1408 | ASSERT ((Alignment & (Alignment - 1)) == 0);\r | |
| 1409 | \r | |
| 1410 | if (Pages == 0) {\r | |
| 1411 | return NULL;\r | |
| 1412 | }\r | |
| 053e878b | 1413 | \r |
| 717fb604 JY |
1414 | if (Alignment > EFI_PAGE_SIZE) {\r |
| 1415 | //\r | |
| 1416 | // Calculate the total number of pages since alignment is larger than page size.\r | |
| 1417 | //\r | |
| 053e878b MK |
1418 | AlignmentMask = Alignment - 1;\r |
| 1419 | RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);\r | |
| 717fb604 JY |
1420 | //\r |
| 1421 | // Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.\r | |
| 1422 | //\r | |
| 1423 | ASSERT (RealPages > Pages);\r | |
| 1424 | \r | |
| 053e878b | 1425 | Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, RealPages, &Memory);\r |
| 717fb604 JY |
1426 | if (EFI_ERROR (Status)) {\r |
| 1427 | return NULL;\r | |
| 1428 | }\r | |
| 053e878b MK |
1429 | \r |
| 1430 | AlignedMemory = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask;\r | |
| 1431 | UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory);\r | |
| 717fb604 JY |
1432 | if (UnalignedPages > 0) {\r |
| 1433 | //\r | |
| 1434 | // Free first unaligned page(s).\r | |
| 1435 | //\r | |
| 1436 | Status = gSmst->SmmFreePages (Memory, UnalignedPages);\r | |
| 1437 | ASSERT_EFI_ERROR (Status);\r | |
| 1438 | }\r | |
| 053e878b | 1439 | \r |
| 8491e302 | 1440 | Memory = AlignedMemory + EFI_PAGES_TO_SIZE (Pages);\r |
| 717fb604 JY |
1441 | UnalignedPages = RealPages - Pages - UnalignedPages;\r |
| 1442 | if (UnalignedPages > 0) {\r | |
| 1443 | //\r | |
| 1444 | // Free last unaligned page(s).\r | |
| 1445 | //\r | |
| 1446 | Status = gSmst->SmmFreePages (Memory, UnalignedPages);\r | |
| 1447 | ASSERT_EFI_ERROR (Status);\r | |
| 1448 | }\r | |
| 1449 | } else {\r | |
| 1450 | //\r | |
| 1451 | // Do not over-allocate pages in this case.\r | |
| 1452 | //\r | |
| 1453 | Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, Pages, &Memory);\r | |
| 1454 | if (EFI_ERROR (Status)) {\r | |
| 1455 | return NULL;\r | |
| 1456 | }\r | |
| 053e878b MK |
1457 | \r |
| 1458 | AlignedMemory = (UINTN)Memory;\r | |
| 717fb604 | 1459 | }\r |
| 053e878b MK |
1460 | \r |
| 1461 | return (VOID *)AlignedMemory;\r | |
| 717fb604 JY |
1462 | }\r |
| 1463 | \r | |
| 529a5a86 MK |
1464 | /**\r |
| 1465 | Perform the remaining tasks.\r | |
| 1466 | \r | |
| 1467 | **/\r | |
| 1468 | VOID\r | |
| 1469 | PerformRemainingTasks (\r | |
| 1470 | VOID\r | |
| 1471 | )\r | |
| 1472 | {\r | |
| 1473 | if (mSmmReadyToLock) {\r | |
| 1474 | //\r | |
| 1475 | // Start SMM Profile feature\r | |
| 1476 | //\r | |
| 1477 | if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {\r | |
| 1478 | SmmProfileStart ();\r | |
| 1479 | }\r | |
| 053e878b | 1480 | \r |
| 529a5a86 MK |
1481 | //\r |
| 1482 | // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.\r | |
| 1483 | //\r | |
| 1484 | InitPaging ();\r | |
| 717fb604 JY |
1485 | \r |
| 1486 | //\r | |
| 1487 | // Mark critical region to be read-only in page table\r | |
| 1488 | //\r | |
| d2fc7711 JY |
1489 | SetMemMapAttributes ();\r |
| 1490 | \r | |
| 79186ddc RN |
1491 | if (IsRestrictedMemoryAccess ()) {\r |
| 1492 | //\r | |
| 1493 | // For outside SMRAM, we only map SMM communication buffer or MMIO.\r | |
| 1494 | //\r | |
| 1495 | SetUefiMemMapAttributes ();\r | |
| 30f61485 | 1496 | \r |
| 79186ddc RN |
1497 | //\r |
| 1498 | // Set page table itself to be read-only\r | |
| 1499 | //\r | |
| 1500 | SetPageTableAttributes ();\r | |
| 1501 | }\r | |
| 717fb604 | 1502 | \r |
| 529a5a86 MK |
1503 | //\r |
| 1504 | // Configure SMM Code Access Check feature if available.\r | |
| 1505 | //\r | |
| 1506 | ConfigSmmCodeAccessCheck ();\r | |
| 1507 | \r | |
| 21c17193 JY |
1508 | SmmCpuFeaturesCompleteSmmReadyToLock ();\r |
| 1509 | \r | |
| 529a5a86 MK |
1510 | //\r |
| 1511 | // Clean SMM ready to lock flag\r | |
| 1512 | //\r | |
| 1513 | mSmmReadyToLock = FALSE;\r | |
| 1514 | }\r | |
| 1515 | }\r | |
| 9f419739 JY |
1516 | \r |
| 1517 | /**\r | |
| 1518 | Perform the pre tasks.\r | |
| 1519 | \r | |
| 1520 | **/\r | |
| 1521 | VOID\r | |
| 1522 | PerformPreTasks (\r | |
| 1523 | VOID\r | |
| 1524 | )\r | |
| 1525 | {\r | |
| 0bdc9e75 | 1526 | RestoreSmmConfigurationInS3 ();\r |
| 9f419739 | 1527 | }\r |