[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.c

/** @file\r
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
\r
Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "PiSmmCpuDxeSmm.h"\r
\r
//\r
// SMM CPU Private Data structure that contains SMM Configuration Protocol\r
// along its supporting fields.\r
//\r
SMM_CPU_PRIVATE_DATA  mSmmCpuPrivateData = {\r
  SMM_CPU_PRIVATE_DATA_SIGNATURE,               // Signature\r
  NULL,                                         // SmmCpuHandle\r
  NULL,                                         // Pointer to ProcessorInfo array\r
  NULL,                                         // Pointer to Operation array\r
  NULL,                                         // Pointer to CpuSaveStateSize array\r
  NULL,                                         // Pointer to CpuSaveState array\r
  {\r
    { 0    }\r
  },                                            // SmmReservedSmramRegion\r
  {\r
    SmmStartupThisAp,                           // SmmCoreEntryContext.SmmStartupThisAp\r
    0,                                          // SmmCoreEntryContext.CurrentlyExecutingCpu\r
    0,                                          // SmmCoreEntryContext.NumberOfCpus\r
    NULL,                                       // SmmCoreEntryContext.CpuSaveStateSize\r
    NULL                                        // SmmCoreEntryContext.CpuSaveState\r
  },\r
  NULL,                                         // SmmCoreEntry\r
  {\r
    mSmmCpuPrivateData.SmmReservedSmramRegion,  // SmmConfiguration.SmramReservedRegions\r
    RegisterSmmEntry                            // SmmConfiguration.RegisterSmmEntry\r
  },\r
  NULL,                                         // pointer to Ap Wrapper Func array\r
  { NULL, NULL },                               // List_Entry for Tokens.\r
};\r
\r
CPU_HOT_PLUG_DATA  mCpuHotPlugData = {\r
  CPU_HOT_PLUG_DATA_REVISION_1,                 // Revision\r
  0,                                            // Array Length of SmBase and APIC ID\r
  NULL,                                         // Pointer to APIC ID array\r
  NULL,                                         // Pointer to SMBASE array\r
  0,                                            // Reserved\r
  0,                                            // SmrrBase\r
  0                                             // SmrrSize\r
};\r
\r
//\r
// Global pointer used to access mSmmCpuPrivateData from outside and inside SMM\r
//\r
SMM_CPU_PRIVATE_DATA  *gSmmCpuPrivate = &mSmmCpuPrivateData;\r
\r
//\r
// SMM Relocation variables\r
//\r
volatile BOOLEAN  *mRebased;\r
volatile BOOLEAN  mIsBsp;\r
\r
///\r
/// Handle for the SMM CPU Protocol\r
///\r
EFI_HANDLE  mSmmCpuHandle = NULL;\r
\r
///\r
/// SMM CPU Protocol instance\r
///\r
EFI_SMM_CPU_PROTOCOL  mSmmCpu = {\r
  SmmReadSaveState,\r
  SmmWriteSaveState\r
};\r
\r
///\r
/// SMM Memory Attribute Protocol instance\r
///\r
EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL  mSmmMemoryAttribute = {\r
  EdkiiSmmGetMemoryAttributes,\r
  EdkiiSmmSetMemoryAttributes,\r
  EdkiiSmmClearMemoryAttributes\r
};\r
\r
EFI_CPU_INTERRUPT_HANDLER  mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];\r
\r
//\r
// SMM stack information\r
//\r
UINTN  mSmmStackArrayBase;\r
UINTN  mSmmStackArrayEnd;\r
UINTN  mSmmStackSize;\r
\r
UINTN    mSmmShadowStackSize;\r
BOOLEAN  mCetSupported = TRUE;\r
\r
UINTN  mMaxNumberOfCpus = 1;\r
UINTN  mNumberOfCpus    = 1;\r
\r
//\r
// SMM ready to lock flag\r
//\r
BOOLEAN  mSmmReadyToLock = FALSE;\r
\r
//\r
// Global used to cache PCD for SMM Code Access Check enable\r
//\r
BOOLEAN  mSmmCodeAccessCheckEnable = FALSE;\r
\r
//\r
// Global copy of the PcdPteMemoryEncryptionAddressOrMask\r
//\r
UINT64  mAddressEncMask = 0;\r
\r
//\r
// Spin lock used to serialize setting of SMM Code Access Check feature\r
//\r
SPIN_LOCK  *mConfigSmmCodeAccessCheckLock = NULL;\r
\r
//\r
// Saved SMM ranges information\r
//\r
EFI_SMRAM_DESCRIPTOR  *mSmmCpuSmramRanges;\r
UINTN                 mSmmCpuSmramRangeCount;\r
\r
UINT8  mPhysicalAddressBits;\r
\r
//\r
// Control register contents saved for SMM S3 resume state initialization.\r
//\r
UINT32  mSmmCr0;\r
UINT32  mSmmCr4;\r
\r
/**\r
  Initialize IDT to setup exception handlers for SMM.\r
\r
**/\r
VOID\r
InitializeSmmIdt (\r
  VOID\r
  )\r
{\r
  EFI_STATUS       Status;\r
  BOOLEAN          InterruptState;\r
  IA32_DESCRIPTOR  DxeIdtr;\r
\r
  //\r
  // There are 32 (not 255) entries in it since only processor\r
  // generated exceptions will be handled.\r
  //\r
  gcSmiIdtr.Limit = (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32) - 1;\r
  //\r
  // Allocate page aligned IDT, because it might be set as read only.\r
  //\r
  gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES (gcSmiIdtr.Limit + 1));\r
  ASSERT (gcSmiIdtr.Base != 0);\r
  ZeroMem ((VOID *)gcSmiIdtr.Base, gcSmiIdtr.Limit + 1);\r
\r
  //\r
  // Disable Interrupt and save DXE IDT table\r
  //\r
  InterruptState = SaveAndDisableInterrupts ();\r
  AsmReadIdtr (&DxeIdtr);\r
  //\r
  // Load SMM temporary IDT table\r
  //\r
  AsmWriteIdtr (&gcSmiIdtr);\r
  //\r
  // Setup SMM default exception handlers, SMM IDT table\r
  // will be updated and saved in gcSmiIdtr\r
  //\r
  Status = InitializeCpuExceptionHandlers (NULL);\r
  ASSERT_EFI_ERROR (Status);\r
  //\r
  // Restore DXE IDT table and CPU interrupt\r
  //\r
  AsmWriteIdtr ((IA32_DESCRIPTOR *)&DxeIdtr);\r
  SetInterruptState (InterruptState);\r
}\r
\r
/**\r
  Search module name by input IP address and output it.\r
\r
  @param CallerIpAddress   Caller instruction pointer.\r
\r
**/\r
VOID\r
DumpModuleInfoByIp (\r
  IN  UINTN  CallerIpAddress\r
  )\r
{\r
  UINTN  Pe32Data;\r
  VOID   *PdbPointer;\r
\r
  //\r
  // Find Image Base\r
  //\r
  Pe32Data = PeCoffSearchImageBase (CallerIpAddress);\r
  if (Pe32Data != 0) {\r
    DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *)CallerIpAddress));\r
    PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)Pe32Data);\r
    if (PdbPointer != NULL) {\r
      DEBUG ((DEBUG_ERROR, " in module (%a)\n", PdbPointer));\r
    }\r
  }\r
}\r
\r
/**\r
  Read information from the CPU save state.\r
\r
  @param  This      EFI_SMM_CPU_PROTOCOL instance\r
  @param  Width     The number of bytes to read from the CPU save state.\r
  @param  Register  Specifies the CPU register to read form the save state.\r
  @param  CpuIndex  Specifies the zero-based index of the CPU save state.\r
  @param  Buffer    Upon return, this holds the CPU register value read from the save state.\r
\r
  @retval EFI_SUCCESS   The register was read from Save State\r
  @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
  @retval EFI_INVALID_PARAMETER   This or Buffer is NULL.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmReadSaveState (\r
  IN CONST EFI_SMM_CPU_PROTOCOL   *This,\r
  IN UINTN                        Width,\r
  IN EFI_SMM_SAVE_STATE_REGISTER  Register,\r
  IN UINTN                        CpuIndex,\r
  OUT VOID                        *Buffer\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  //\r
  // Retrieve pointer to the specified CPU's SMM Save State buffer\r
  //\r
  if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // The SpeculationBarrier() call here is to ensure the above check for the\r
  // CpuIndex has been completed before the execution of subsequent codes.\r
  //\r
  SpeculationBarrier ();\r
\r
  //\r
  // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID\r
  //\r
  if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) {\r
    //\r
    // The pseudo-register only supports the 64-bit size specified by Width.\r
    //\r
    if (Width != sizeof (UINT64)) {\r
      return EFI_INVALID_PARAMETER;\r
    }\r
\r
    //\r
    // If the processor is in SMM at the time the SMI occurred,\r
    // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.\r
    // Otherwise, EFI_NOT_FOUND is returned.\r
    //\r
    if (*(mSmmMpSyncData->CpuData[CpuIndex].Present)) {\r
      *(UINT64 *)Buffer = gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId;\r
      return EFI_SUCCESS;\r
    } else {\r
      return EFI_NOT_FOUND;\r
    }\r
  }\r
\r
  if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Status = SmmCpuFeaturesReadSaveStateRegister (CpuIndex, Register, Width, Buffer);\r
  if (Status == EFI_UNSUPPORTED) {\r
    Status = ReadSaveStateRegister (CpuIndex, Register, Width, Buffer);\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Write data to the CPU save state.\r
\r
  @param  This      EFI_SMM_CPU_PROTOCOL instance\r
  @param  Width     The number of bytes to read from the CPU save state.\r
  @param  Register  Specifies the CPU register to write to the save state.\r
  @param  CpuIndex  Specifies the zero-based index of the CPU save state\r
  @param  Buffer    Upon entry, this holds the new CPU register value.\r
\r
  @retval EFI_SUCCESS   The register was written from Save State\r
  @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r
  @retval EFI_INVALID_PARAMETER   ProcessorIndex or Width is not correct\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
SmmWriteSaveState (\r
  IN CONST EFI_SMM_CPU_PROTOCOL   *This,\r
  IN UINTN                        Width,\r
  IN EFI_SMM_SAVE_STATE_REGISTER  Register,\r
  IN UINTN                        CpuIndex,\r
  IN CONST VOID                   *Buffer\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  //\r
  // Retrieve pointer to the specified CPU's SMM Save State buffer\r
  //\r
  if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored\r
  //\r
  if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  if (!mSmmMpSyncData->CpuData[CpuIndex].Present) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Status = SmmCpuFeaturesWriteSaveStateRegister (CpuIndex, Register, Width, Buffer);\r
  if (Status == EFI_UNSUPPORTED) {\r
    Status = WriteSaveStateRegister (CpuIndex, Register, Width, Buffer);\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  C function for SMI handler. To change all processor's SMMBase Register.\r
\r
**/\r
VOID\r
EFIAPI\r
SmmInitHandler (\r
  VOID\r
  )\r
{\r
  UINT32  ApicId;\r
  UINTN   Index;\r
\r
  //\r
  // Update SMM IDT entries' code segment and load IDT\r
  //\r
  AsmWriteIdtr (&gcSmiIdtr);\r
  ApicId = GetApicId ();\r
\r
  ASSERT (mNumberOfCpus <= mMaxNumberOfCpus);\r
\r
  for (Index = 0; Index < mNumberOfCpus; Index++) {\r
    if (ApicId == (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {\r
      //\r
      // Initialize SMM specific features on the currently executing CPU\r
      //\r
      SmmCpuFeaturesInitializeProcessor (\r
        Index,\r
        mIsBsp,\r
        gSmmCpuPrivate->ProcessorInfo,\r
        &mCpuHotPlugData\r
        );\r
\r
      if (!mSmmS3Flag) {\r
        //\r
        // Check XD and BTS features on each processor on normal boot\r
        //\r
        CheckFeatureSupported ();\r
      } else if (mIsBsp) {\r
        //\r
        // BSP rebase is already done above.\r
        // Initialize private data during S3 resume\r
        //\r
        InitializeMpSyncData ();\r
      }\r
\r
      //\r
      // Hook return after RSM to set SMM re-based flag\r
      //\r
      SemaphoreHook (Index, &mRebased[Index]);\r
\r
      return;\r
    }\r
  }\r
\r
  ASSERT (FALSE);\r
}\r
\r
/**\r
  Relocate SmmBases for each processor.\r
\r
  Execute on first boot and all S3 resumes\r
\r
**/\r
VOID\r
EFIAPI\r
SmmRelocateBases (\r
  VOID\r
  )\r
{\r
  UINT8                 BakBuf[BACK_BUF_SIZE];\r
  SMRAM_SAVE_STATE_MAP  BakBuf2;\r
  SMRAM_SAVE_STATE_MAP  *CpuStatePtr;\r
  UINT8                 *U8Ptr;\r
  UINT32                ApicId;\r
  UINTN                 Index;\r
  UINTN                 BspIndex;\r
\r
  //\r
  // Make sure the reserved size is large enough for procedure SmmInitTemplate.\r
  //\r
  ASSERT (sizeof (BakBuf) >= gcSmmInitSize);\r
\r
  //\r
  // Patch ASM code template with current CR0, CR3, and CR4 values\r
  //\r
  mSmmCr0 = (UINT32)AsmReadCr0 ();\r
  PatchInstructionX86 (gPatchSmmCr0, mSmmCr0, 4);\r
  PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);\r
  mSmmCr4 = (UINT32)AsmReadCr4 ();\r
  PatchInstructionX86 (gPatchSmmCr4, mSmmCr4 & (~CR4_CET_ENABLE), 4);\r
\r
  //\r
  // Patch GDTR for SMM base relocation\r
  //\r
  gcSmiInitGdtr.Base  = gcSmiGdtr.Base;\r
  gcSmiInitGdtr.Limit = gcSmiGdtr.Limit;\r
\r
  U8Ptr       = (UINT8 *)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET);\r
  CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
\r
  //\r
  // Backup original contents at address 0x38000\r
  //\r
  CopyMem (BakBuf, U8Ptr, sizeof (BakBuf));\r
  CopyMem (&BakBuf2, CpuStatePtr, sizeof (BakBuf2));\r
\r
  //\r
  // Load image for relocation\r
  //\r
  CopyMem (U8Ptr, gcSmmInitTemplate, gcSmmInitSize);\r
\r
  //\r
  // Retrieve the local APIC ID of current processor\r
  //\r
  ApicId = GetApicId ();\r
\r
  //\r
  // Relocate SM bases for all APs\r
  // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate\r
  //\r
  mIsBsp   = FALSE;\r
  BspIndex = (UINTN)-1;\r
  for (Index = 0; Index < mNumberOfCpus; Index++) {\r
    mRebased[Index] = FALSE;\r
    if (ApicId != (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {\r
      SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);\r
      //\r
      // Wait for this AP to finish its 1st SMI\r
      //\r
      while (!mRebased[Index]) {\r
      }\r
    } else {\r
      //\r
      // BSP will be Relocated later\r
      //\r
      BspIndex = Index;\r
    }\r
  }\r
\r
  //\r
  // Relocate BSP's SMM base\r
  //\r
  ASSERT (BspIndex != (UINTN)-1);\r
  mIsBsp = TRUE;\r
  SendSmiIpi (ApicId);\r
  //\r
  // Wait for the BSP to finish its 1st SMI\r
  //\r
  while (!mRebased[BspIndex]) {\r
  }\r
\r
  //\r
  // Restore contents at address 0x38000\r
  //\r
  CopyMem (CpuStatePtr, &BakBuf2, sizeof (BakBuf2));\r
  CopyMem (U8Ptr, BakBuf, sizeof (BakBuf));\r
}\r
\r
/**\r
  SMM Ready To Lock event notification handler.\r
\r
  The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to\r
  perform additional lock actions that must be performed from SMM on the next SMI.\r
\r
  @param[in] Protocol   Points to the protocol's unique identifier.\r
  @param[in] Interface  Points to the interface instance.\r
  @param[in] Handle     The handle on which the interface was installed.\r
\r
  @retval EFI_SUCCESS   Notification handler runs successfully.\r
 **/\r
EFI_STATUS\r
EFIAPI\r
SmmReadyToLockEventNotify (\r
  IN CONST EFI_GUID  *Protocol,\r
  IN VOID            *Interface,\r
  IN EFI_HANDLE      Handle\r
  )\r
{\r
  GetAcpiCpuData ();\r
\r
  //\r
  // Cache a copy of UEFI memory map before we start profiling feature.\r
  //\r
  GetUefiMemoryMap ();\r
\r
  //\r
  // Set SMM ready to lock flag and return\r
  //\r
  mSmmReadyToLock = TRUE;\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  The module Entry Point of the CPU SMM driver.\r
\r
  @param  ImageHandle    The firmware allocated handle for the EFI image.\r
  @param  SystemTable    A pointer to the EFI System Table.\r
\r
  @retval EFI_SUCCESS    The entry point is executed successfully.\r
  @retval Other          Some error occurs when executing this entry point.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PiCpuSmmEntry (\r
  IN EFI_HANDLE        ImageHandle,\r
  IN EFI_SYSTEM_TABLE  *SystemTable\r
  )\r
{\r
  EFI_STATUS                Status;\r
  EFI_MP_SERVICES_PROTOCOL  *MpServices;\r
  UINTN                     NumberOfEnabledProcessors;\r
  UINTN                     Index;\r
  VOID                      *Buffer;\r
  UINTN                     BufferPages;\r
  UINTN                     TileCodeSize;\r
  UINTN                     TileDataSize;\r
  UINTN                     TileSize;\r
  UINT8                     *Stacks;\r
  VOID                      *Registration;\r
  UINT32                    RegEax;\r
  UINT32                    RegEbx;\r
  UINT32                    RegEcx;\r
  UINT32                    RegEdx;\r
  UINTN                     FamilyId;\r
  UINTN                     ModelId;\r
  UINT32                    Cr3;\r
\r
  //\r
  // Initialize address fixup\r
  //\r
  PiSmmCpuSmmInitFixupAddress ();\r
  PiSmmCpuSmiEntryFixupAddress ();\r
\r
  //\r
  // Initialize Debug Agent to support source level debug in SMM code\r
  //\r
  InitializeDebugAgent (DEBUG_AGENT_INIT_SMM, NULL, NULL);\r
\r
  //\r
  // Report the start of CPU SMM initialization.\r
  //\r
  REPORT_STATUS_CODE (\r
    EFI_PROGRESS_CODE,\r
    EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_INIT\r
    );\r
\r
  //\r
  // Find out SMRR Base and SMRR Size\r
  //\r
  FindSmramInfo (&mCpuHotPlugData.SmrrBase, &mCpuHotPlugData.SmrrSize);\r
\r
  //\r
  // Get MP Services Protocol\r
  //\r
  Status = SystemTable->BootServices->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Use MP Services Protocol to retrieve the number of processors and number of enabled processors\r
  //\r
  Status = MpServices->GetNumberOfProcessors (MpServices, &mNumberOfCpus, &NumberOfEnabledProcessors);\r
  ASSERT_EFI_ERROR (Status);\r
  ASSERT (mNumberOfCpus <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
\r
  //\r
  // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.\r
  // A constant BSP index makes no sense because it may be hot removed.\r
  //\r
  DEBUG_CODE_BEGIN ();\r
  if (FeaturePcdGet (PcdCpuHotPlugSupport)) {\r
    ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection));\r
  }\r
\r
  DEBUG_CODE_END ();\r
\r
  //\r
  // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.\r
  //\r
  mSmmCodeAccessCheckEnable = PcdGetBool (PcdCpuSmmCodeAccessCheckEnable);\r
  DEBUG ((DEBUG_INFO, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable));\r
\r
  //\r
  // Save the PcdPteMemoryEncryptionAddressOrMask value into a global variable.\r
  // Make sure AddressEncMask is contained to smallest supported address field.\r
  //\r
  mAddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
  DEBUG ((DEBUG_INFO, "mAddressEncMask = 0x%lx\n", mAddressEncMask));\r
\r
  //\r
  // If support CPU hot plug, we need to allocate resources for possibly hot-added processors\r
  //\r
  if (FeaturePcdGet (PcdCpuHotPlugSupport)) {\r
    mMaxNumberOfCpus = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
  } else {\r
    mMaxNumberOfCpus = mNumberOfCpus;\r
  }\r
\r
  gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus;\r
\r
  //\r
  // The CPU save state and code for the SMI entry point are tiled within an SMRAM\r
  // allocated buffer.  The minimum size of this buffer for a uniprocessor system\r
  // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area\r
  // just below SMBASE + 64KB.  If more than one CPU is present in the platform,\r
  // then the SMI entry point and the CPU save state areas can be tiles to minimize\r
  // the total amount SMRAM required for all the CPUs.  The tile size can be computed\r
  // by adding the   // CPU save state size, any extra CPU specific context, and\r
  // the size of code that must be placed at the SMI entry point to transfer\r
  // control to a C function in the native SMM execution mode.  This size is\r
  // rounded up to the nearest power of 2 to give the tile size for a each CPU.\r
  // The total amount of memory required is the maximum number of CPUs that\r
  // platform supports times the tile size.  The picture below shows the tiling,\r
  // where m is the number of tiles that fit in 32KB.\r
  //\r
  //  +-----------------------------+  <-- 2^n offset from Base of allocated buffer\r
  //  |   CPU m+1 Save State        |\r
  //  +-----------------------------+\r
  //  |   CPU m+1 Extra Data        |\r
  //  +-----------------------------+\r
  //  |   Padding                   |\r
  //  +-----------------------------+\r
  //  |   CPU 2m  SMI Entry         |\r
  //  +#############################+  <-- Base of allocated buffer + 64 KB\r
  //  |   CPU m-1 Save State        |\r
  //  +-----------------------------+\r
  //  |   CPU m-1 Extra Data        |\r
  //  +-----------------------------+\r
  //  |   Padding                   |\r
  //  +-----------------------------+\r
  //  |   CPU 2m-1 SMI Entry        |\r
  //  +=============================+  <-- 2^n offset from Base of allocated buffer\r
  //  |   . . . . . . . . . . . .   |\r
  //  +=============================+  <-- 2^n offset from Base of allocated buffer\r
  //  |   CPU 2 Save State          |\r
  //  +-----------------------------+\r
  //  |   CPU 2 Extra Data          |\r
  //  +-----------------------------+\r
  //  |   Padding                   |\r
  //  +-----------------------------+\r
  //  |   CPU m+1 SMI Entry         |\r
  //  +=============================+  <-- Base of allocated buffer + 32 KB\r
  //  |   CPU 1 Save State          |\r
  //  +-----------------------------+\r
  //  |   CPU 1 Extra Data          |\r
  //  +-----------------------------+\r
  //  |   Padding                   |\r
  //  +-----------------------------+\r
  //  |   CPU m SMI Entry           |\r
  //  +#############################+  <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB\r
  //  |   CPU 0 Save State          |\r
  //  +-----------------------------+\r
  //  |   CPU 0 Extra Data          |\r
  //  +-----------------------------+\r
  //  |   Padding                   |\r
  //  +-----------------------------+\r
  //  |   CPU m-1 SMI Entry         |\r
  //  +=============================+  <-- 2^n offset from Base of allocated buffer\r
  //  |   . . . . . . . . . . . .   |\r
  //  +=============================+  <-- 2^n offset from Base of allocated buffer\r
  //  |   Padding                   |\r
  //  +-----------------------------+\r
  //  |   CPU 1 SMI Entry           |\r
  //  +=============================+  <-- 2^n offset from Base of allocated buffer\r
  //  |   Padding                   |\r
  //  +-----------------------------+\r
  //  |   CPU 0 SMI Entry           |\r
  //  +#############################+  <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB\r
  //\r
\r
  //\r
  // Retrieve CPU Family\r
  //\r
  AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);\r
  FamilyId = (RegEax >> 8) & 0xf;\r
  ModelId  = (RegEax >> 4) & 0xf;\r
  if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {\r
    ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
  }\r
\r
  RegEdx = 0;\r
  AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r
  if (RegEax >= CPUID_EXTENDED_CPU_SIG) {\r
    AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);\r
  }\r
\r
  //\r
  // Determine the mode of the CPU at the time an SMI occurs\r
  //   Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
  //   Volume 3C, Section 34.4.1.1\r
  //\r
  mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;\r
  if ((RegEdx & BIT29) != 0) {\r
    mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;\r
  }\r
\r
  if (FamilyId == 0x06) {\r
    if ((ModelId == 0x17) || (ModelId == 0x0f) || (ModelId == 0x1c)) {\r
      mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;\r
    }\r
  }\r
\r
  DEBUG ((DEBUG_INFO, "PcdControlFlowEnforcementPropertyMask = %d\n", PcdGet32 (PcdControlFlowEnforcementPropertyMask)));\r
  if (PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) {\r
    AsmCpuid (CPUID_SIGNATURE, &RegEax, NULL, NULL, NULL);\r
    if (RegEax >= CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS) {\r
      AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL, NULL, &RegEcx, &RegEdx);\r
      DEBUG ((DEBUG_INFO, "CPUID[7/0] ECX - 0x%08x\n", RegEcx));\r
      DEBUG ((DEBUG_INFO, "  CET_SS  - 0x%08x\n", RegEcx & CPUID_CET_SS));\r
      DEBUG ((DEBUG_INFO, "  CET_IBT - 0x%08x\n", RegEdx & CPUID_CET_IBT));\r
      if ((RegEcx & CPUID_CET_SS) == 0) {\r
        mCetSupported = FALSE;\r
        PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);\r
      }\r
\r
      if (mCetSupported) {\r
        AsmCpuidEx (CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF, NULL, &RegEbx, &RegEcx, NULL);\r
        DEBUG ((DEBUG_INFO, "CPUID[D/1] EBX - 0x%08x, ECX - 0x%08x\n", RegEbx, RegEcx));\r
        AsmCpuidEx (CPUID_EXTENDED_STATE, 11, &RegEax, NULL, &RegEcx, NULL);\r
        DEBUG ((DEBUG_INFO, "CPUID[D/11] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx));\r
        AsmCpuidEx (CPUID_EXTENDED_STATE, 12, &RegEax, NULL, &RegEcx, NULL);\r
        DEBUG ((DEBUG_INFO, "CPUID[D/12] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx));\r
      }\r
    } else {\r
      mCetSupported = FALSE;\r
      PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);\r
    }\r
  } else {\r
    mCetSupported = FALSE;\r
    PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);\r
  }\r
\r
  //\r
  // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU\r
  // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.\r
  // This size is rounded up to nearest power of 2.\r
  //\r
  TileCodeSize = GetSmiHandlerSize ();\r
  TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB);\r
  TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);\r
  TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB);\r
  TileSize     = TileDataSize + TileCodeSize - 1;\r
  TileSize     = 2 * GetPowerOfTwo32 ((UINT32)TileSize);\r
  DEBUG ((DEBUG_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));\r
\r
  //\r
  // If the TileSize is larger than space available for the SMI Handler of\r
  // CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save\r
  // State Map of CPU[i+1], then ASSERT().  If this ASSERT() is triggered, then\r
  // the SMI Handler size must be reduced or the size of the extra CPU specific\r
  // context must be reduced.\r
  //\r
  ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));\r
\r
  //\r
  // Allocate buffer for all of the tiles.\r
  //\r
  // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
  // Volume 3C, Section 34.11 SMBASE Relocation\r
  //   For Pentium and Intel486 processors, the SMBASE values must be\r
  //   aligned on a 32-KByte boundary or the processor will enter shutdown\r
  //   state during the execution of a RSM instruction.\r
  //\r
  // Intel486 processors: FamilyId is 4\r
  // Pentium processors : FamilyId is 5\r
  //\r
  BufferPages = EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1));\r
  if ((FamilyId == 4) || (FamilyId == 5)) {\r
    Buffer = AllocateAlignedCodePages (BufferPages, SIZE_32KB);\r
  } else {\r
    Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB);\r
  }\r
\r
  ASSERT (Buffer != NULL);\r
  DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages)));\r
\r
  //\r
  // Allocate buffer for pointers to array in  SMM_CPU_PRIVATE_DATA.\r
  //\r
  gSmmCpuPrivate->ProcessorInfo = (EFI_PROCESSOR_INFORMATION *)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION) * mMaxNumberOfCpus);\r
  ASSERT (gSmmCpuPrivate->ProcessorInfo != NULL);\r
\r
  gSmmCpuPrivate->Operation = (SMM_CPU_OPERATION *)AllocatePool (sizeof (SMM_CPU_OPERATION) * mMaxNumberOfCpus);\r
  ASSERT (gSmmCpuPrivate->Operation != NULL);\r
\r
  gSmmCpuPrivate->CpuSaveStateSize = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus);\r
  ASSERT (gSmmCpuPrivate->CpuSaveStateSize != NULL);\r
\r
  gSmmCpuPrivate->CpuSaveState = (VOID **)AllocatePool (sizeof (VOID *) * mMaxNumberOfCpus);\r
  ASSERT (gSmmCpuPrivate->CpuSaveState != NULL);\r
\r
  mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveStateSize = gSmmCpuPrivate->CpuSaveStateSize;\r
  mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveState     = gSmmCpuPrivate->CpuSaveState;\r
\r
  //\r
  // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.\r
  //\r
  mCpuHotPlugData.ApicId = (UINT64 *)AllocatePool (sizeof (UINT64) * mMaxNumberOfCpus);\r
  ASSERT (mCpuHotPlugData.ApicId != NULL);\r
  mCpuHotPlugData.SmBase = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus);\r
  ASSERT (mCpuHotPlugData.SmBase != NULL);\r
  mCpuHotPlugData.ArrayLength = (UINT32)mMaxNumberOfCpus;\r
\r
  //\r
  // Retrieve APIC ID of each enabled processor from the MP Services protocol.\r
  // Also compute the SMBASE address, CPU Save State address, and CPU Save state\r
  // size for each CPU in the platform\r
  //\r
  for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r
    mCpuHotPlugData.SmBase[Index]           = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;\r
    gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof (SMRAM_SAVE_STATE_MAP);\r
    gSmmCpuPrivate->CpuSaveState[Index]     = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET);\r
    gSmmCpuPrivate->Operation[Index]        = SmmCpuNone;\r
\r
    if (Index < mNumberOfCpus) {\r
      Status = MpServices->GetProcessorInfo (MpServices, Index, &gSmmCpuPrivate->ProcessorInfo[Index]);\r
      ASSERT_EFI_ERROR (Status);\r
      mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId;\r
\r
      DEBUG ((\r
        DEBUG_INFO,\r
        "CPU[%03x]  APIC ID=%04x  SMBASE=%08x  SaveState=%08x  Size=%08x\n",\r
        Index,\r
        (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId,\r
        mCpuHotPlugData.SmBase[Index],\r
        gSmmCpuPrivate->CpuSaveState[Index],\r
        gSmmCpuPrivate->CpuSaveStateSize[Index]\r
        ));\r
    } else {\r
      gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = INVALID_APIC_ID;\r
      mCpuHotPlugData.ApicId[Index]                    = INVALID_APIC_ID;\r
    }\r
  }\r
\r
  //\r
  // Allocate SMI stacks for all processors.\r
  //\r
  mSmmStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize)));\r
  if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
    //\r
    // SMM Stack Guard Enabled\r
    //   2 more pages is allocated for each processor, one is guard page and the other is known good stack.\r
    //\r
    // +--------------------------------------------------+-----+--------------------------------------------------+\r
    // | Known Good Stack | Guard Page |     SMM Stack    | ... | Known Good Stack | Guard Page |     SMM Stack    |\r
    // +--------------------------------------------------+-----+--------------------------------------------------+\r
    // |        4K        |    4K       PcdCpuSmmStackSize|     |        4K        |    4K       PcdCpuSmmStackSize|\r
    // |<---------------- mSmmStackSize ----------------->|     |<---------------- mSmmStackSize ----------------->|\r
    // |                                                  |     |                                                  |\r
    // |<------------------ Processor 0 ----------------->|     |<------------------ Processor n ----------------->|\r
    //\r
    mSmmStackSize += EFI_PAGES_TO_SIZE (2);\r
  }\r
\r
  mSmmShadowStackSize = 0;\r
  if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {\r
    mSmmShadowStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmShadowStackSize)));\r
\r
    if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
      //\r
      // SMM Stack Guard Enabled\r
      // Append Shadow Stack after normal stack\r
      //   2 more pages is allocated for each processor, one is guard page and the other is known good shadow stack.\r
      //\r
      // |= Stacks\r
      // +--------------------------------------------------+---------------------------------------------------------------+\r
      // | Known Good Stack | Guard Page |    SMM Stack     | Known Good Shadow Stack | Guard Page |    SMM Shadow Stack    |\r
      // +--------------------------------------------------+---------------------------------------------------------------+\r
      // |         4K       |    4K      |PcdCpuSmmStackSize|            4K           |    4K      |PcdCpuSmmShadowStackSize|\r
      // |<---------------- mSmmStackSize ----------------->|<--------------------- mSmmShadowStackSize ------------------->|\r
      // |                                                                                                                  |\r
      // |<-------------------------------------------- Processor N ------------------------------------------------------->|\r
      //\r
      mSmmShadowStackSize += EFI_PAGES_TO_SIZE (2);\r
    } else {\r
      //\r
      // SMM Stack Guard Disabled (Known Good Stack is still required for potential stack switch.)\r
      //   Append Shadow Stack after normal stack with 1 more page as known good shadow stack.\r
      //   1 more pages is allocated for each processor, it is known good stack.\r
      //\r
      //\r
      // |= Stacks\r
      // +-------------------------------------+--------------------------------------------------+\r
      // | Known Good Stack |    SMM Stack     | Known Good Shadow Stack |    SMM Shadow Stack    |\r
      // +-------------------------------------+--------------------------------------------------+\r
      // |        4K        |PcdCpuSmmStackSize|          4K             |PcdCpuSmmShadowStackSize|\r
      // |<---------- mSmmStackSize ---------->|<--------------- mSmmShadowStackSize ------------>|\r
      // |                                                                                        |\r
      // |<-------------------------------- Processor N ----------------------------------------->|\r
      //\r
      mSmmShadowStackSize += EFI_PAGES_TO_SIZE (1);\r
      mSmmStackSize       += EFI_PAGES_TO_SIZE (1);\r
    }\r
  }\r
\r
  Stacks = (UINT8 *)AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (mSmmStackSize + mSmmShadowStackSize)));\r
  ASSERT (Stacks != NULL);\r
  mSmmStackArrayBase = (UINTN)Stacks;\r
  mSmmStackArrayEnd  = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (mSmmStackSize + mSmmShadowStackSize) - 1;\r
\r
  DEBUG ((DEBUG_INFO, "Stacks                   - 0x%x\n", Stacks));\r
  DEBUG ((DEBUG_INFO, "mSmmStackSize            - 0x%x\n", mSmmStackSize));\r
  DEBUG ((DEBUG_INFO, "PcdCpuSmmStackGuard      - 0x%x\n", FeaturePcdGet (PcdCpuSmmStackGuard)));\r
  if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {\r
    DEBUG ((DEBUG_INFO, "mSmmShadowStackSize      - 0x%x\n", mSmmShadowStackSize));\r
  }\r
\r
  //\r
  // Set SMI stack for SMM base relocation\r
  //\r
  PatchInstructionX86 (\r
    gPatchSmmInitStack,\r
    (UINTN)(Stacks + mSmmStackSize - sizeof (UINTN)),\r
    sizeof (UINTN)\r
    );\r
\r
  //\r
  // Initialize IDT\r
  //\r
  InitializeSmmIdt ();\r
\r
  //\r
  // Relocate SMM Base addresses to the ones allocated from SMRAM\r
  //\r
  mRebased = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberOfCpus);\r
  ASSERT (mRebased != NULL);\r
  SmmRelocateBases ();\r
\r
  //\r
  // Call hook for BSP to perform extra actions in normal mode after all\r
  // SMM base addresses have been relocated on all CPUs\r
  //\r
  SmmCpuFeaturesSmmRelocationComplete ();\r
\r
  DEBUG ((DEBUG_INFO, "mXdSupported - 0x%x\n", mXdSupported));\r
\r
  //\r
  // SMM Time initialization\r
  //\r
  InitializeSmmTimer ();\r
\r
  //\r
  // Initialize MP globals\r
  //\r
  Cr3 = InitializeMpServiceData (Stacks, mSmmStackSize, mSmmShadowStackSize);\r
\r
  if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {\r
    for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {\r
      SetShadowStack (\r
        Cr3,\r
        (EFI_PHYSICAL_ADDRESS)(UINTN)Stacks + mSmmStackSize + (mSmmStackSize + mSmmShadowStackSize) * Index,\r
        mSmmShadowStackSize\r
        );\r
      if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
        SetNotPresentPage (\r
          Cr3,\r
          (EFI_PHYSICAL_ADDRESS)(UINTN)Stacks + mSmmStackSize + EFI_PAGES_TO_SIZE (1) + (mSmmStackSize + mSmmShadowStackSize) * Index,\r
          EFI_PAGES_TO_SIZE (1)\r
          );\r
      }\r
    }\r
  }\r
\r
  //\r
  // Fill in SMM Reserved Regions\r
  //\r
  gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedStart = 0;\r
  gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedSize  = 0;\r
\r
  //\r
  // Install the SMM Configuration Protocol onto a new handle on the handle database.\r
  // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer\r
  // to an SMRAM address will be present in the handle database\r
  //\r
  Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces (\r
                                        &gSmmCpuPrivate->SmmCpuHandle,\r
                                        &gEfiSmmConfigurationProtocolGuid,\r
                                        &gSmmCpuPrivate->SmmConfiguration,\r
                                        NULL\r
                                        );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Install the SMM CPU Protocol into SMM protocol database\r
  //\r
  Status = gSmst->SmmInstallProtocolInterface (\r
                    &mSmmCpuHandle,\r
                    &gEfiSmmCpuProtocolGuid,\r
                    EFI_NATIVE_INTERFACE,\r
                    &mSmmCpu\r
                    );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Install the SMM Memory Attribute Protocol into SMM protocol database\r
  //\r
  Status = gSmst->SmmInstallProtocolInterface (\r
                    &mSmmCpuHandle,\r
                    &gEdkiiSmmMemoryAttributeProtocolGuid,\r
                    EFI_NATIVE_INTERFACE,\r
                    &mSmmMemoryAttribute\r
                    );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Initialize global buffer for MM MP.\r
  //\r
  InitializeDataForMmMp ();\r
\r
  //\r
  // Initialize Package First Thread Index Info.\r
  //\r
  InitPackageFirstThreadIndexInfo ();\r
\r
  //\r
  // Install the SMM Mp Protocol into SMM protocol database\r
  //\r
  Status = gSmst->SmmInstallProtocolInterface (\r
                    &mSmmCpuHandle,\r
                    &gEfiMmMpProtocolGuid,\r
                    EFI_NATIVE_INTERFACE,\r
                    &mSmmMp\r
                    );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.\r
  //\r
  if (FeaturePcdGet (PcdCpuHotPlugSupport)) {\r
    Status = PcdSet64S (PcdCpuHotPlugDataAddress, (UINT64)(UINTN)&mCpuHotPlugData);\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
\r
  //\r
  // Initialize SMM CPU Services Support\r
  //\r
  Status = InitializeSmmCpuServices (mSmmCpuHandle);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // register SMM Ready To Lock Protocol notification\r
  //\r
  Status = gSmst->SmmRegisterProtocolNotify (\r
                    &gEfiSmmReadyToLockProtocolGuid,\r
                    SmmReadyToLockEventNotify,\r
                    &Registration\r
                    );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Initialize SMM Profile feature\r
  //\r
  InitSmmProfile (Cr3);\r
\r
  GetAcpiS3EnableFlag ();\r
  InitSmmS3ResumeState (Cr3);\r
\r
  DEBUG ((DEBUG_INFO, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
\r
  Find out SMRAM information including SMRR base and SMRR size.\r
\r
  @param          SmrrBase          SMRR base\r
  @param          SmrrSize          SMRR size\r
\r
**/\r
VOID\r
FindSmramInfo (\r
  OUT UINT32  *SmrrBase,\r
  OUT UINT32  *SmrrSize\r
  )\r
{\r
  EFI_STATUS                Status;\r
  UINTN                     Size;\r
  EFI_SMM_ACCESS2_PROTOCOL  *SmmAccess;\r
  EFI_SMRAM_DESCRIPTOR      *CurrentSmramRange;\r
  UINTN                     Index;\r
  UINT64                    MaxSize;\r
  BOOLEAN                   Found;\r
\r
  //\r
  // Get SMM Access Protocol\r
  //\r
  Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **)&SmmAccess);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Get SMRAM information\r
  //\r
  Size   = 0;\r
  Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL);\r
  ASSERT (Status == EFI_BUFFER_TOO_SMALL);\r
\r
  mSmmCpuSmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);\r
  ASSERT (mSmmCpuSmramRanges != NULL);\r
\r
  Status = SmmAccess->GetCapabilities (SmmAccess, &Size, mSmmCpuSmramRanges);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  mSmmCpuSmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);\r
\r
  //\r
  // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size\r
  //\r
  CurrentSmramRange = NULL;\r
  for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index < mSmmCpuSmramRangeCount; Index++) {\r
    //\r
    // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization\r
    //\r
    if ((mSmmCpuSmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {\r
      continue;\r
    }\r
\r
    if (mSmmCpuSmramRanges[Index].CpuStart >= BASE_1MB) {\r
      if ((mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) <= SMRR_MAX_ADDRESS) {\r
        if (mSmmCpuSmramRanges[Index].PhysicalSize >= MaxSize) {\r
          MaxSize           = mSmmCpuSmramRanges[Index].PhysicalSize;\r
          CurrentSmramRange = &mSmmCpuSmramRanges[Index];\r
        }\r
      }\r
    }\r
  }\r
\r
  ASSERT (CurrentSmramRange != NULL);\r
\r
  *SmrrBase = (UINT32)CurrentSmramRange->CpuStart;\r
  *SmrrSize = (UINT32)CurrentSmramRange->PhysicalSize;\r
\r
  do {\r
    Found = FALSE;\r
    for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {\r
      if ((mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase) &&\r
          (*SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)))\r
      {\r
        *SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart;\r
        *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);\r
        Found     = TRUE;\r
      } else if (((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart) && (mSmmCpuSmramRanges[Index].PhysicalSize > 0)) {\r
        *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);\r
        Found     = TRUE;\r
      }\r
    }\r
  } while (Found);\r
\r
  DEBUG ((DEBUG_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *SmrrSize));\r
}\r
\r
/**\r
Configure SMM Code Access Check feature on an AP.\r
SMM Feature Control MSR will be locked after configuration.\r
\r
@param[in,out] Buffer  Pointer to private data buffer.\r
**/\r
VOID\r
EFIAPI\r
ConfigSmmCodeAccessCheckOnCurrentProcessor (\r
  IN OUT VOID  *Buffer\r
  )\r
{\r
  UINTN   CpuIndex;\r
  UINT64  SmmFeatureControlMsr;\r
  UINT64  NewSmmFeatureControlMsr;\r
\r
  //\r
  // Retrieve the CPU Index from the context passed in\r
  //\r
  CpuIndex = *(UINTN *)Buffer;\r
\r
  //\r
  // Get the current SMM Feature Control MSR value\r
  //\r
  SmmFeatureControlMsr = SmmCpuFeaturesGetSmmRegister (CpuIndex, SmmRegFeatureControl);\r
\r
  //\r
  // Compute the new SMM Feature Control MSR value\r
  //\r
  NewSmmFeatureControlMsr = SmmFeatureControlMsr;\r
  if (mSmmCodeAccessCheckEnable) {\r
    NewSmmFeatureControlMsr |= SMM_CODE_CHK_EN_BIT;\r
    if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock)) {\r
      NewSmmFeatureControlMsr |= SMM_FEATURE_CONTROL_LOCK_BIT;\r
    }\r
  }\r
\r
  //\r
  // Only set the SMM Feature Control MSR value if the new value is different than the current value\r
  //\r
  if (NewSmmFeatureControlMsr != SmmFeatureControlMsr) {\r
    SmmCpuFeaturesSetSmmRegister (CpuIndex, SmmRegFeatureControl, NewSmmFeatureControlMsr);\r
  }\r
\r
  //\r
  // Release the spin lock user to serialize the updates to the SMM Feature Control MSR\r
  //\r
  ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);\r
}\r
\r
/**\r
Configure SMM Code Access Check feature for all processors.\r
SMM Feature Control MSR will be locked after configuration.\r
**/\r
VOID\r
ConfigSmmCodeAccessCheck (\r
  VOID\r
  )\r
{\r
  UINTN       Index;\r
  EFI_STATUS  Status;\r
\r
  //\r
  // Check to see if the Feature Control MSR is supported on this CPU\r
  //\r
  Index = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu;\r
  if (!SmmCpuFeaturesIsSmmRegisterSupported (Index, SmmRegFeatureControl)) {\r
    mSmmCodeAccessCheckEnable = FALSE;\r
    return;\r
  }\r
\r
  //\r
  // Check to see if the CPU supports the SMM Code Access Check feature\r
  // Do not access this MSR unless the CPU supports the SmmRegFeatureControl\r
  //\r
  if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) == 0) {\r
    mSmmCodeAccessCheckEnable = FALSE;\r
    return;\r
  }\r
\r
  //\r
  // Initialize the lock used to serialize the MSR programming in BSP and all APs\r
  //\r
  InitializeSpinLock (mConfigSmmCodeAccessCheckLock);\r
\r
  //\r
  // Acquire Config SMM Code Access Check spin lock.  The BSP will release the\r
  // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().\r
  //\r
  AcquireSpinLock (mConfigSmmCodeAccessCheckLock);\r
\r
  //\r
  // Enable SMM Code Access Check feature on the BSP.\r
  //\r
  ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index);\r
\r
  //\r
  // Enable SMM Code Access Check feature for the APs.\r
  //\r
  for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {\r
    if (Index != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {\r
      if (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {\r
        //\r
        // If this processor does not exist\r
        //\r
        continue;\r
      }\r
\r
      //\r
      // Acquire Config SMM Code Access Check spin lock.  The AP will release the\r
      // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().\r
      //\r
      AcquireSpinLock (mConfigSmmCodeAccessCheckLock);\r
\r
      //\r
      // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.\r
      //\r
      Status = gSmst->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor, Index, &Index);\r
      ASSERT_EFI_ERROR (Status);\r
\r
      //\r
      // Wait for the AP to release the Config SMM Code Access Check spin lock.\r
      //\r
      while (!AcquireSpinLockOrFail (mConfigSmmCodeAccessCheckLock)) {\r
        CpuPause ();\r
      }\r
\r
      //\r
      // Release the Config SMM Code Access Check spin lock.\r
      //\r
      ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);\r
    }\r
  }\r
}\r
\r
/**\r
  Allocate pages for code.\r
\r
  @param[in]  Pages Number of pages to be allocated.\r
\r
  @return Allocated memory.\r
**/\r
VOID *\r
AllocateCodePages (\r
  IN UINTN  Pages\r
  )\r
{\r
  EFI_STATUS            Status;\r
  EFI_PHYSICAL_ADDRESS  Memory;\r
\r
  if (Pages == 0) {\r
    return NULL;\r
  }\r
\r
  Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, Pages, &Memory);\r
  if (EFI_ERROR (Status)) {\r
    return NULL;\r
  }\r
\r
  return (VOID *)(UINTN)Memory;\r
}\r
\r
/**\r
  Allocate aligned pages for code.\r
\r
  @param[in]  Pages                 Number of pages to be allocated.\r
  @param[in]  Alignment             The requested alignment of the allocation.\r
                                    Must be a power of two.\r
                                    If Alignment is zero, then byte alignment is used.\r
\r
  @return Allocated memory.\r
**/\r
VOID *\r
AllocateAlignedCodePages (\r
  IN UINTN  Pages,\r
  IN UINTN  Alignment\r
  )\r
{\r
  EFI_STATUS            Status;\r
  EFI_PHYSICAL_ADDRESS  Memory;\r
  UINTN                 AlignedMemory;\r
  UINTN                 AlignmentMask;\r
  UINTN                 UnalignedPages;\r
  UINTN                 RealPages;\r
\r
  //\r
  // Alignment must be a power of two or zero.\r
  //\r
  ASSERT ((Alignment & (Alignment - 1)) == 0);\r
\r
  if (Pages == 0) {\r
    return NULL;\r
  }\r
\r
  if (Alignment > EFI_PAGE_SIZE) {\r
    //\r
    // Calculate the total number of pages since alignment is larger than page size.\r
    //\r
    AlignmentMask = Alignment - 1;\r
    RealPages     = Pages + EFI_SIZE_TO_PAGES (Alignment);\r
    //\r
    // Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.\r
    //\r
    ASSERT (RealPages > Pages);\r
\r
    Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, RealPages, &Memory);\r
    if (EFI_ERROR (Status)) {\r
      return NULL;\r
    }\r
\r
    AlignedMemory  = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask;\r
    UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory);\r
    if (UnalignedPages > 0) {\r
      //\r
      // Free first unaligned page(s).\r
      //\r
      Status = gSmst->SmmFreePages (Memory, UnalignedPages);\r
      ASSERT_EFI_ERROR (Status);\r
    }\r
\r
    Memory         = AlignedMemory + EFI_PAGES_TO_SIZE (Pages);\r
    UnalignedPages = RealPages - Pages - UnalignedPages;\r
    if (UnalignedPages > 0) {\r
      //\r
      // Free last unaligned page(s).\r
      //\r
      Status = gSmst->SmmFreePages (Memory, UnalignedPages);\r
      ASSERT_EFI_ERROR (Status);\r
    }\r
  } else {\r
    //\r
    // Do not over-allocate pages in this case.\r
    //\r
    Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, Pages, &Memory);\r
    if (EFI_ERROR (Status)) {\r
      return NULL;\r
    }\r
\r
    AlignedMemory = (UINTN)Memory;\r
  }\r
\r
  return (VOID *)AlignedMemory;\r
}\r
\r
/**\r
  Perform the remaining tasks.\r
\r
**/\r
VOID\r
PerformRemainingTasks (\r
  VOID\r
  )\r
{\r
  if (mSmmReadyToLock) {\r
    //\r
    // Start SMM Profile feature\r
    //\r
    if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {\r
      SmmProfileStart ();\r
    }\r
\r
    //\r
    // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.\r
    //\r
    InitPaging ();\r
\r
    //\r
    // Mark critical region to be read-only in page table\r
    //\r
    SetMemMapAttributes ();\r
\r
    if (IsRestrictedMemoryAccess ()) {\r
      //\r
      // For outside SMRAM, we only map SMM communication buffer or MMIO.\r
      //\r
      SetUefiMemMapAttributes ();\r
\r
      //\r
      // Set page table itself to be read-only\r
      //\r
      SetPageTableAttributes ();\r
    }\r
\r
    //\r
    // Configure SMM Code Access Check feature if available.\r
    //\r
    ConfigSmmCodeAccessCheck ();\r
\r
    SmmCpuFeaturesCompleteSmmReadyToLock ();\r
\r
    //\r
    // Clean SMM ready to lock flag\r
    //\r
    mSmmReadyToLock = FALSE;\r
  }\r
}\r
\r
/**\r
  Perform the pre tasks.\r
\r
**/\r
VOID\r
PerformPreTasks (\r
  VOID\r
  )\r
{\r
  RestoreSmmConfigurationInS3 ();\r
}\r