[mirror_edk2.git] / Vlv2DeviceRefCodePkg / AcpiTablesPCAT / Facp / Facp.aslc

/*++\r
\r
Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
\r
  This program and the accompanying materials are licensed and made available under\r
  the terms and conditions of the BSD License that accompanies this distribution.\r
  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
\r
\r
Module Name:\r
\r
  Facp.c\r
\r
\r
Abstract: The fixed ACPI description Table (FADT) Structure\r
\r
\r
--*/\r
#ifdef ECP_FLAG\r
#include "EDKIIGlueDxe.h"\r
#else\r
#include <PiDxe.h>\r
#endif\r
#include <IndustryStandard/Acpi50.h>\r
#include "AcpiTablePlatform.h"\r
\r
EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {\r
  {\r
    EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
    sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
    EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
    0,                                                                                    // to make sum of entire table == 0\r
    EFI_ACPI_OEM_ID,         // OEMID is a 6 bytes long field\r
    EFI_ACPI_OEM_TABLE_ID,      // OEM table identification(8 bytes long)\r
    EFI_ACPI_OEM_REVISION,      // OEM revision number\r
    EFI_ACPI_CREATOR_ID,        // ASL compiler vendor ID\r
    EFI_ACPI_CREATOR_REVISION   // ASL compiler revision number\r
  },\r
  0,                                                                                    // Physical addesss of FACS\r
  0,                                                                                    // Physical address of DSDT\r
  INT_MODEL,                                                                                    // System Interrupt Model (ignored in 2k and later, must be 0 for 98)\r
  PM_PROFILE,                                                                                   // Preferred PM Profile\r
  SCI_INT_VECTOR,                                                                       // System vector of SCI interrupt\r
  SMI_CMD_IO_PORT,                                                                      // Port address of SMI command port\r
  ACPI_ENABLE,                                                                          // value to write to port smi_cmd to enable ACPI\r
  ACPI_DISABLE,                                                                         // value to write to port smi_cmd to disable ACPI\r
  S4BIOS_REQ,                                                                           // Value to write to SMI CMD port to enter the S4BIOS state\r
  PSTATE_CNT,       // PState control\r
  PM1a_EVT_BLK,                                                                         // Port address of Power Mgt 1a Event Reg Blk\r
  PM1b_EVT_BLK,                                                                         // Port address of Power Mgt 1b Event Reg Blk\r
  PM1a_CNT_BLK,                                                                         // Port address of Power Mgt 1a Ctrl Reg Blk\r
  PM1b_CNT_BLK,                                                                         // Port address of Power Mgt 1b Ctrl Reg Blk\r
  PM2_CNT_BLK,                                                                          // Port address of Power Mgt 2  Ctrl Reg Blk\r
  PM_TMR_BLK,                                                                           // Port address of Power Mgt Timer Ctrl Reg Blk\r
  GPE0_BLK,                                                                             // Port addr of General Purpose Event 0 Reg Blk\r
  GPE1_BLK,                                                                             // Port addr of General Purpose Event 1 Reg Blk\r
  PM1_EVT_LEN,                                                                          // Byte Length of ports at pm1X_evt_blk\r
  PM1_CNT_LEN,                                                                          // Byte Length of ports at pm1X_cnt_blk\r
  PM2_CNT_LEN,                                                                          // Byte Length of ports at pm2_cnt_blk\r
  PM_TM_LEN,                                                                            // Byte Length of ports at pm_tm_blk\r
  GPE0_BLK_LEN,                                                                         // Byte Length of ports at gpe0_blk\r
  GPE1_BLK_LEN,                                                                         // Byte Length of ports at gpe1_blk\r
  GPE1_BASE,                                                                            // offset in gpe model where gpe1 events start\r
  CST_CNT,          // _CST support\r
  P_LVL2_LAT,                                                                           // worst case HW latency to enter/exit C2 state\r
  P_LVL3_LAT,                                                                           // worst case HW latency to enter/exit C3 state\r
  FLUSH_SIZE,                                                                           // Size of area read to flush caches\r
  FLUSH_STRIDE,                                                                         // Stride used in flushing caches\r
  DUTY_OFFSET,                                                                          // bit location of duty cycle field in p_cnt reg\r
  DUTY_WIDTH,                                                                           // bit width of duty cycle field in p_cnt reg\r
  DAY_ALRM,                                                                             // index to day-of-month alarm in RTC CMOS RAM\r
  MON_ALRM,                                                                             // index to month-of-year alarm in RTC CMOS RAM\r
  CENTURY,                                                                              // index to century in RTC CMOS RAM\r
  IAPC_BOOT_ARCH,                                                                       // IA-PCI Boot Architecture Flag\r
  RESERVED,                                                                             // reserved\r
  FLAG,\r
  {\r
    EFI_ACPI_5_0_SYSTEM_IO,\r
    8,\r
    0,\r
    0,\r
    0xCF9\r
  },\r
  0x06,             // Hardware reset value\r
  0, 0, 0,          // Reserved\r
  0,                // XFirmwareCtrl\r
  0,                // XDsdt\r
  //\r
  // X_PM1a Event Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x20,\r
  0x00,\r
  EFI_ACPI_3_0_DWORD,\r
  PM1a_EVT_BLK,\r
\r
  //\r
  // X_PM1b Event Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x00,\r
  0x00,\r
  EFI_ACPI_RESERVED_BYTE,\r
  PM1b_EVT_BLK,\r
\r
  //\r
  // X_PM1a Control Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x10,\r
  0x00,\r
  EFI_ACPI_3_0_WORD,\r
  PM1a_CNT_BLK,\r
\r
  //\r
  // X_PM1b Control Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x00,\r
  0x00,\r
  EFI_ACPI_RESERVED_BYTE,\r
  PM1b_CNT_BLK,\r
\r
  //\r
  // X_PM2 Control Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x08,\r
  0x00,\r
  EFI_ACPI_3_0_BYTE,\r
  PM2_CNT_BLK,\r
\r
  //\r
  // X_PM Timer Control Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x20,\r
  0x00,\r
  EFI_ACPI_3_0_DWORD,\r
  PM_TMR_BLK,\r
\r
  //\r
  // X_General Purpose Event 0 Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x80,\r
  0x00,\r
  EFI_ACPI_RESERVED_BYTE,\r
  GPE0_BLK,\r
\r
  //\r
  // X_General Purpose Event 1 Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x00,\r
  0x00,\r
  EFI_ACPI_RESERVED_BYTE,\r
  GPE1_BLK,\r
\r
  //\r
  // Sleep Control Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x08,\r
  0x00,\r
  EFI_ACPI_RESERVED_BYTE,\r
  0,\r
\r
  //\r
  // Sleep Status Register Block\r
  //\r
  EFI_ACPI_5_0_SYSTEM_IO,\r
  0x08,\r
  0x00,\r
  EFI_ACPI_RESERVED_BYTE,\r
  0,\r
};\r
\r
VOID*\r
ReferenceAcpiTable (\r
  VOID\r
  )\r
{\r
  //\r
  // Reference the table being generated to prevent the optimizer from\r
  // removing the data structure from the executable\r
  //\r
  return (VOID*)&FACP;\r
}\r
Commit	Line	Data
3cbfba02 DW	1	/*++\r
	2	\r
	3	Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
	4	\r
	5	This program and the accompanying materials are licensed and made available under\r
	6	the terms and conditions of the BSD License that accompanies this distribution.\r
	7	The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php.\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	\r
	14	\r
	15	Module Name:\r
	16	\r
	17	Facp.c\r
	18	\r
	19	\r
	20	Abstract: The fixed ACPI description Table (FADT) Structure\r
	21	\r
	22	\r
	23	--*/\r
	24	#ifdef ECP_FLAG\r
	25	#include "EDKIIGlueDxe.h"\r
	26	#else\r
	27	#include <PiDxe.h>\r
	28	#endif\r
	29	#include <IndustryStandard/Acpi50.h>\r
	30	#include "AcpiTablePlatform.h"\r
	31	\r
	32	EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {\r
	33	{\r
	34	EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
	35	sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
	36	EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
	37	0, // to make sum of entire table == 0\r
	38	EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field\r
	39	EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)\r
	40	EFI_ACPI_OEM_REVISION, // OEM revision number\r
	41	EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID\r
	42	EFI_ACPI_CREATOR_REVISION // ASL compiler revision number\r
	43	},\r
	44	0, // Physical addesss of FACS\r
	45	0, // Physical address of DSDT\r
	46	INT_MODEL, // System Interrupt Model (ignored in 2k and later, must be 0 for 98)\r
	47	PM_PROFILE, // Preferred PM Profile\r
	48	SCI_INT_VECTOR, // System vector of SCI interrupt\r
	49	SMI_CMD_IO_PORT, // Port address of SMI command port\r
	50	ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI\r
	51	ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI\r
	52	S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state\r
	53	PSTATE_CNT, // PState control\r
	54	PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk\r
	55	PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk\r
	56	PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk\r
	57	PM1b_CNT_BLK, // Port address of Power Mgt 1b Ctrl Reg Blk\r
	58	PM2_CNT_BLK, // Port address of Power Mgt 2 Ctrl Reg Blk\r
	59	PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk\r
	60	GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk\r
	61	GPE1_BLK, // Port addr of General Purpose Event 1 Reg Blk\r
	62	PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk\r
	63	PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk\r
	64	PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk\r
65	PM_TM_LEN, // Byte Length of ports at pm_tm_blk\r
66	GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk\r
67	GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk\r
68	GPE1_BASE, // offset in gpe model where gpe1 events start\r
69	CST_CNT, // _CST support\r
70	P_LVL2_LAT, // worst case HW latency to enter/exit C2 state\r
71	P_LVL3_LAT, // worst case HW latency to enter/exit C3 state\r
72	FLUSH_SIZE, // Size of area read to flush caches\r
73	FLUSH_STRIDE, // Stride used in flushing caches\r
74	DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg\r
75	DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg\r
76	DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM\r
77	MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM\r
78	CENTURY, // index to century in RTC CMOS RAM\r
79	IAPC_BOOT_ARCH, // IA-PCI Boot Architecture Flag\r
80	RESERVED, // reserved\r
81	FLAG,\r
82	{\r
83	EFI_ACPI_5_0_SYSTEM_IO,\r
84	8,\r
85	0,\r
86	0,\r
87	0xCF9\r
88	},\r
89	0x06, // Hardware reset value\r
90	0, 0, 0, // Reserved\r
91	0, // XFirmwareCtrl\r
92	0, // XDsdt\r
93	//\r
94	// X_PM1a Event Register Block\r
95	//\r
96	EFI_ACPI_5_0_SYSTEM_IO,\r
97	0x20,\r
98	0x00,\r
99	EFI_ACPI_3_0_DWORD,\r
100	PM1a_EVT_BLK,\r
101	\r
102	//\r
103	// X_PM1b Event Register Block\r
104	//\r
105	EFI_ACPI_5_0_SYSTEM_IO,\r
106	0x00,\r
107	0x00,\r
108	EFI_ACPI_RESERVED_BYTE,\r
109	PM1b_EVT_BLK,\r
110	\r
111	//\r
112	// X_PM1a Control Register Block\r
113	//\r
114	EFI_ACPI_5_0_SYSTEM_IO,\r
115	0x10,\r
116	0x00,\r
117	EFI_ACPI_3_0_WORD,\r
118	PM1a_CNT_BLK,\r
119	\r
120	//\r
121	// X_PM1b Control Register Block\r
122	//\r
123	EFI_ACPI_5_0_SYSTEM_IO,\r
124	0x00,\r
125	0x00,\r
126	EFI_ACPI_RESERVED_BYTE,\r
127	PM1b_CNT_BLK,\r
128	\r
129	//\r
130	// X_PM2 Control Register Block\r
131	//\r
132	EFI_ACPI_5_0_SYSTEM_IO,\r
133	0x08,\r
134	0x00,\r
135	EFI_ACPI_3_0_BYTE,\r
136	PM2_CNT_BLK,\r
137	\r
138	//\r
139	// X_PM Timer Control Register Block\r
140	//\r
141	EFI_ACPI_5_0_SYSTEM_IO,\r
142	0x20,\r
143	0x00,\r
144	EFI_ACPI_3_0_DWORD,\r
145	PM_TMR_BLK,\r
146	\r
147	//\r
148	// X_General Purpose Event 0 Register Block\r
149	//\r
150	EFI_ACPI_5_0_SYSTEM_IO,\r
151	0x80,\r
152	0x00,\r
153	EFI_ACPI_RESERVED_BYTE,\r
154	GPE0_BLK,\r
155	\r
156	//\r
157	// X_General Purpose Event 1 Register Block\r
158	//\r
159	EFI_ACPI_5_0_SYSTEM_IO,\r
160	0x00,\r
161	0x00,\r
162	EFI_ACPI_RESERVED_BYTE,\r
163	GPE1_BLK,\r
164	\r
165	//\r
166	// Sleep Control Register Block\r
167	//\r
168	EFI_ACPI_5_0_SYSTEM_IO,\r
169	0x08,\r
170	0x00,\r
171	EFI_ACPI_RESERVED_BYTE,\r
172	0,\r
173	\r
174	//\r
175	// Sleep Status Register Block\r
176	//\r
177	EFI_ACPI_5_0_SYSTEM_IO,\r
178	0x08,\r
179	0x00,\r
180	EFI_ACPI_RESERVED_BYTE,\r
181	0,\r
182	};\r
183	\r
184	VOID*\r
185	ReferenceAcpiTable (\r
186	VOID\r
187	)\r
188	{\r
189	//\r
190	// Reference the table being generated to prevent the optimizer from\r
191	// removing the data structure from the executable\r
192	//\r
193	return (VOID*)&FACP;\r
194	}\r