projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /**************************************************************************;\r |
| 2 | ;* *;\r | |
| 3 | ;* *;\r | |
| 4 | ;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r | |
| 5 | ;* Family of Customer Reference Boards. *;\r | |
| 6 | ;* *;\r | |
| 7 | ;* *;\r | |
| aa44e98d | 8 | ;* Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved *;\r |
| 3cbfba02 | 9 | ;\r |
| 7ede8060 | 10 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 3cbfba02 DW |
11 | ;\r |
| 12 | ;* *;\r | |
| 13 | ;* *;\r | |
| 14 | ;**************************************************************************/\r | |
| 15 | \r | |
| 16 | \r | |
| 17 | \r | |
| 18 | // Define a Global region of ACPI NVS Region that may be used for any\r | |
| 19 | // type of implementation. The starting offset and size will be fixed\r | |
| 20 | // up by the System BIOS during POST. Note that the Size must be a word\r | |
| 21 | // in size to be fixed up correctly.\r | |
| 22 | \r | |
| 23 | OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55)\r | |
| 24 | Field(GNVS,AnyAcc,Lock,Preserve)\r | |
| 25 | {\r | |
| 26 | Offset(0), // Miscellaneous Dynamic Registers:\r | |
| 27 | OSYS, 16, // (00) Operating System\r | |
| 28 | , 8, // (02)\r | |
| 29 | , 8, // (03)\r | |
| 30 | , 8, // (04)\r | |
| 31 | , 8, // (05)\r | |
| 32 | , 8, // (06)\r | |
| 33 | , 8, // (07)\r | |
| 34 | , 8, // (08)\r | |
| 35 | , 8, // (09)\r | |
| 36 | , 8, // (10)\r | |
| 37 | P80D, 32, // (11) Port 80 Debug Port Value\r | |
| 38 | LIDS, 8, // (15) Lid State (Lid Open = 1)\r | |
| 39 | , 8, // (16)\r | |
| 40 | , 8, // (17)\r | |
| 41 | Offset(18), // Thermal Policy Registers:\r | |
| 42 | , 8, // (18)\r | |
| 43 | , 8, // (19)\r | |
| 44 | ACTT, 8, // (20) Active Trip Point\r | |
| 45 | PSVT, 8, // (21) Passive Trip Point\r | |
| 46 | TC1V, 8, // (22) Passive Trip Point TC1 Value\r | |
| 47 | TC2V, 8, // (23) Passive Trip Point TC2 Value\r | |
| 48 | TSPV, 8, // (24) Passive Trip Point TSP Value\r | |
| 49 | CRTT, 8, // (25) Critical Trip Point\r | |
| 50 | DTSE, 8, // (26) Digital Thermal Sensor Enable\r | |
| 51 | DTS1, 8, // (27) Digital Thermal Sensor 1 Reading\r | |
| 52 | DTS2, 8, // (28) Digital Thermal Sensor 2 Reading\r | |
| 53 | DTSF, 8, // (29) DTS SMI Function Call\r | |
| 54 | Offset(30), // Battery Support Registers:\r | |
| 55 | , 8, // (30)\r | |
| 56 | , 8, // (31)\r | |
| 57 | , 8, // (32)\r | |
| 58 | , 8, // (33)\r | |
| 59 | , 8, // (34)\r | |
| 60 | , 8, // (35)\r | |
| 61 | , 8, // (36)\r | |
| 62 | Offset(40), // CPU Identification Registers:\r | |
| 63 | APIC, 8, // (40) APIC Enabled by SBIOS (APIC Enabled = 1)\r | |
| 64 | MPEN, 8, // (41) Number of Logical Processors if MP Enabled != 0\r | |
| 65 | , 8, // (42)\r | |
| 66 | , 8, // (43)\r | |
| 67 | , 8, // (44)\r | |
| 68 | , 32, // (45)\r | |
| 69 | Offset(50), // SIO CMOS Configuration Registers:\r | |
| 70 | , 8, // (50)\r | |
| 71 | , 8, // (51)\r | |
| 72 | , 8, // (52)\r | |
| 73 | , 8, // (53)\r | |
| 74 | , 8, // (54)\r | |
| 75 | , 8, // (55)\r | |
| 76 | , 8, // (56)\r | |
| 77 | , 8, // (57)\r | |
| 78 | , 8, // (58)\r | |
| 79 | Offset(60), // Internal Graphics Registers:\r | |
| 80 | , 8, // (60)\r | |
| 81 | , 8, // (61)\r | |
| 82 | CADL, 8, // (62) Current Attached Device List\r | |
| 83 | , 8, // (63)\r | |
| 84 | CSTE, 16, // (64) Current Display State\r | |
| 85 | NSTE, 16, // (66) Next Display State\r | |
| 86 | , 16, // (68)\r | |
| 87 | NDID, 8, // (70) Number of Valid Device IDs\r | |
| 88 | DID1, 32, // (71) Device ID 1\r | |
| 89 | DID2, 32, // (75) Device ID 2\r | |
| 90 | DID3, 32, // (79) Device ID 3\r | |
| 91 | DID4, 32, // (83) Device ID 4\r | |
| 92 | DID5, 32, // (87) Device ID 5\r | |
| 93 | , 32, // (91)\r | |
| 94 | , 8, // (95) Fifth byte of AKSV (mannufacturing mode)\r | |
| 95 | Offset(103), // Backlight Control Registers:\r | |
| 96 | , 8, // (103)\r | |
| 97 | BRTL, 8, // (104) Brightness Level Percentage\r | |
| 98 | Offset(105), // Ambiant Light Sensor Registers:\r | |
| 99 | , 8, // (105)\r | |
| 100 | , 8, // (106)\r | |
| 101 | LLOW, 8, // (107) LUX Low Value\r | |
| 102 | , 8, // (108)\r | |
| 103 | Offset(110), // EMA Registers:\r | |
| 104 | , 8, // (110)\r | |
| 105 | , 16, // (111)\r | |
| 106 | , 16, // (113)\r | |
| 107 | Offset(116), // MEF Registers:\r | |
| 108 | , 8, // (116) MEF Enable\r | |
| 109 | Offset(117), // PCIe Dock:\r | |
| 110 | , 8, // (117)\r | |
| 111 | Offset(120), // TPM Registers:\r | |
| 112 | , 8, // (120)\r | |
| 113 | , 8, // (121)\r | |
| 114 | , 8, // (122)\r | |
| 115 | , 8, // (123)\r | |
| 116 | , 32, // (124)\r | |
| 117 | , 8, // (125)\r | |
| 118 | , 8, // (129)\r | |
| 119 | Offset(130), //\r | |
| 120 | , 56, // (130)\r | |
| 121 | , 56, // (137)\r | |
| 122 | , 8, // (144)\r | |
| 123 | , 56, // (145)\r | |
| 124 | Offset(170), // IGD OpRegion/Software SCI base address\r | |
| 125 | ASLB, 32, // (170) IGD OpRegion base address\r | |
| 126 | Offset(174), // IGD OpRegion/Software SCI shared data\r | |
| 127 | IBTT, 8, // (174) IGD Boot Display Device\r | |
| 128 | IPAT, 8, // (175) IGD Panel Type CMOs option\r | |
| 129 | ITVF, 8, // (176) IGD TV Format CMOS option\r | |
| 130 | ITVM, 8, // (177) IGD TV Minor Format CMOS option\r | |
| 131 | IPSC, 8, // (178) IGD Panel Scaling\r | |
| 132 | IBLC, 8, // (179) IGD BLC Configuration\r | |
| 133 | IBIA, 8, // (180) IGD BIA Configuration\r | |
| 134 | ISSC, 8, // (181) IGD SSC Configuration\r | |
| 135 | I409, 8, // (182) IGD 0409 Modified Settings Flag\r | |
| 136 | I509, 8, // (183) IGD 0509 Modified Settings Flag\r | |
| 137 | I609, 8, // (184) IGD 0609 Modified Settings Flag\r | |
| 138 | I709, 8, // (185) IGD 0709 Modified Settings Flag\r | |
| 139 | IDMM, 8, // (186) IGD DVMT Mode\r | |
| 140 | IDMS, 8, // (187) IGD DVMT Memory Size\r | |
| 141 | IF1E, 8, // (188) IGD Function 1 Enable\r | |
| 142 | HVCO, 8, // (189) HPLL VCO\r | |
| 143 | NXD1, 32, // (190) Next state DID1 for _DGS\r | |
| 144 | NXD2, 32, // (194) Next state DID2 for _DGS\r | |
| 145 | NXD3, 32, // (198) Next state DID3 for _DGS\r | |
| 146 | NXD4, 32, // (202) Next state DID4 for _DGS\r | |
| 147 | NXD5, 32, // (206) Next state DID5 for _DGS\r | |
| 148 | NXD6, 32, // (210) Next state DID6 for _DGS\r | |
| 149 | NXD7, 32, // (214) Next state DID7 for _DGS\r | |
| 150 | NXD8, 32, // (218) Next state DID8 for _DGS\r | |
| 151 | GSMI, 8, // (222) GMCH SMI/SCI mode (0=SCI)\r | |
| 152 | PAVP, 8, // (223) IGD PAVP data\r | |
| 153 | Offset(225),\r | |
| 154 | OSCC, 8, // (225) PCIE OSC Control\r | |
| 155 | NEXP, 8, // (226) Native PCIE Setup Value\r | |
| 156 | Offset(235), // Global Variables\r | |
| 157 | DSEN, 8, // (235) _DOS Display Support Flag.\r | |
| 158 | ECON, 8, // (236) Embedded Controller Availability Flag.\r | |
| 159 | GPIC, 8, // (237) Global IOAPIC/8259 Interrupt Mode Flag.\r | |
| 160 | CTYP, 8, // (238) Global Cooling Type Flag.\r | |
| 161 | L01C, 8, // (239) Global L01 Counter.\r | |
| 162 | VFN0, 8, // (240) Virtual Fan0 Status.\r | |
| 163 | VFN1, 8, // (241) Virtual Fan1 Status.\r | |
| 164 | Offset(256),\r | |
| 165 | NVGA, 32, // (256) NVIG opregion address\r | |
| 166 | NVHA, 32, // (260) NVHM opregion address\r | |
| 167 | AMDA, 32, // (264) AMDA opregion address\r | |
| 168 | DID6, 32, // (268) Device ID 6\r | |
| 169 | DID7, 32, // (272) Device ID 7\r | |
| 170 | DID8, 32, // (276) Device ID 8\r | |
| 171 | Offset(332),\r | |
| 172 | USEL, 8, // (332) UART Selection\r | |
| 173 | PU1E, 8, // (333) PCU UART 1 Enabled\r | |
| 174 | PU2E, 8, // (334) PCU UART 2 Enabled\r | |
| 175 | \r | |
| 176 | LPE0, 32, // (335) LPE Bar0\r | |
| 177 | LPE1, 32, // (339) LPE Bar1\r | |
| 178 | LPE2, 32, // (343) LPE Bar2\r | |
| 179 | \r | |
| 180 | Offset(347),\r | |
| 181 | , 8, // (347)\r | |
| 182 | , 8, // (348)\r | |
| 183 | PFLV, 8, // (349) Platform Flavor\r | |
| 184 | \r | |
| 185 | Offset(351),\r | |
| 186 | ICNF, 8, // (351) ISCT / AOAC Configuration\r | |
| 187 | XHCI, 8, // (352) xHCI controller mode\r | |
| 188 | PMEN, 8, // (353) PMIC enable/disable\r | |
| 189 | \r | |
| 190 | LPEE, 8, // (354) LPE enable/disable\r | |
| 191 | ISPA, 32, // (355) ISP Base Addr\r | |
| 192 | ISPD, 8, // (359) ISP Device Selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3\r | |
| 193 | \r | |
| 194 | offset(360), // ((4+8+6)*4+2)*4=296\r | |
| 195 | //\r | |
| 196 | // Lpss controllers\r | |
| 197 | //\r | |
| 198 | PCIB, 32,\r | |
| 199 | PCIT, 32,\r | |
| 200 | D10A, 32, //DMA1\r | |
| 201 | D10L, 32,\r | |
| 202 | D11A, 32,\r | |
| 203 | D11L, 32,\r | |
| 204 | P10A, 32, // PWM1\r | |
| 205 | P10L, 32,\r | |
| 206 | P11A, 32,\r | |
| 207 | P11L, 32,\r | |
| 208 | P20A, 32, // PWM2\r | |
| 209 | P20L, 32,\r | |
| 210 | P21A, 32,\r | |
| 211 | P21L, 32,\r | |
| 212 | U10A, 32, // UART1\r | |
| 213 | U10L, 32,\r | |
| 214 | U11A, 32,\r | |
| 215 | U11L, 32,\r | |
| 216 | U20A, 32, // UART2\r | |
| 217 | U20L, 32,\r | |
| 218 | U21A, 32,\r | |
| 219 | U21L, 32,\r | |
| 220 | SP0A, 32, // SPI\r | |
| 221 | SP0L, 32,\r | |
| 222 | SP1A, 32,\r | |
| 223 | SP1L, 32,\r | |
| 224 | \r | |
| 225 | D20A, 32, //DMA2\r | |
| 226 | D20L, 32,\r | |
| 227 | D21A, 32,\r | |
| 228 | D21L, 32,\r | |
| 229 | I10A, 32, // I2C1\r | |
| 230 | I10L, 32,\r | |
| 231 | I11A, 32,\r | |
| 232 | I11L, 32,\r | |
| 233 | I20A, 32, // I2C2\r | |
| 234 | I20L, 32,\r | |
| 235 | I21A, 32,\r | |
| 236 | I21L, 32,\r | |
| 237 | I30A, 32, // I2C3\r | |
| 238 | I30L, 32,\r | |
| 239 | I31A, 32,\r | |
| 240 | I31L, 32,\r | |
| 241 | I40A, 32, // I2C4\r | |
| 242 | I40L, 32,\r | |
| 243 | I41A, 32,\r | |
| 244 | I41L, 32,\r | |
| 245 | I50A, 32, // I2C5\r | |
| 246 | I50L, 32,\r | |
| 247 | I51A, 32,\r | |
| 248 | I51L, 32,\r | |
| 249 | I60A, 32, // I2C6\r | |
| 250 | I60L, 32,\r | |
| 251 | I61A, 32,\r | |
| 252 | I61L, 32,\r | |
| 253 | I70A, 32, // I2C7\r | |
| 254 | I70L, 32,\r | |
| 255 | I71A, 32,\r | |
| 256 | I71L, 32,\r | |
| 257 | //\r | |
| 258 | // Scc controllers\r | |
| 259 | //\r | |
| 260 | eM0A, 32, // EMMC\r | |
| 261 | eM0L, 32,\r | |
| 262 | eM1A, 32,\r | |
| 263 | eM1L, 32,\r | |
| 264 | SI0A, 32, // SDIO\r | |
| 265 | SI0L, 32,\r | |
| 266 | SI1A, 32,\r | |
| 267 | SI1L, 32,\r | |
| 268 | SD0A, 32, // SDCard\r | |
| 269 | SD0L, 32,\r | |
| 270 | SD1A, 32,\r | |
| 271 | SD1L, 32,\r | |
| 272 | MH0A, 32, //\r | |
| 273 | MH0L, 32,\r | |
| 274 | MH1A, 32,\r | |
| 275 | MH1L, 32,\r | |
| 276 | \r | |
| 277 | offset(656),\r | |
| 278 | SDRM, 8,\r | |
| 279 | offset(657),\r | |
| 280 | HLPS, 8, //(657) Hide Devices\r | |
| 281 | offset(658),\r | |
| 282 | OSEL, 8, //(658) OS Seletion - Windows/Android\r | |
| 283 | \r | |
| 284 | offset(659), // VLV1 DPTF\r | |
| 285 | SDP1, 8, //(659) An enumerated value corresponding to SKU\r | |
| 286 | DPTE, 8, //(660) DPTF Enable\r | |
| 287 | THM0, 8, //(661) System Thermal 0\r | |
| 288 | THM1, 8, //(662) System Thermal 1\r | |
| 289 | THM2, 8, //(663) System Thermal 2\r | |
| 290 | THM3, 8, //(664) System Thermal 3\r | |
| 291 | THM4, 8, //(665) System Thermal 3\r | |
| 292 | CHGR, 8, //(666) DPTF Changer Device\r | |
| 293 | DDSP, 8, //(667) DPTF Display Device\r | |
| 294 | DSOC, 8, //(668) DPTF SoC device\r | |
| 295 | DPSR, 8, //(669) DPTF Processor device\r | |
| 296 | DPCT, 32, //(670) DPTF Processor participant critical temperature\r | |
| 297 | DPPT, 32, //(674) DPTF Processor participant passive temperature\r | |
| 298 | DGC0, 32, //(678) DPTF Generic sensor0 participant critical temperature\r | |
| 299 | DGP0, 32, //(682) DPTF Generic sensor0 participant passive temperature\r | |
| 300 | DGC1, 32, //(686) DPTF Generic sensor1 participant critical temperature\r | |
| 301 | DGP1, 32, //(690) DPTF Generic sensor1 participant passive temperature\r | |
| 302 | DGC2, 32, //(694) DPTF Generic sensor2 participant critical temperature\r | |
| 303 | DGP2, 32, //(698) DPTF Generic sensor2 participant passive temperature\r | |
| 304 | DGC3, 32, //(702) DPTF Generic sensor3 participant critical temperature\r | |
| 305 | DGP3, 32, //(706) DPTF Generic sensor3 participant passive temperature\r | |
| 306 | DGC4, 32, //(710)DPTF Generic sensor3 participant critical temperature\r | |
| 307 | DGP4, 32, //(714)DPTF Generic sensor3 participant passive temperature\r | |
| 308 | DLPM, 8, //(718) DPTF Current low power mode setting\r | |
| 309 | DSC0, 32, //(719) DPTF Critical threshold0 for SCU\r | |
| 310 | DSC1, 32, //(723) DPTF Critical threshold1 for SCU\r | |
| 311 | DSC2, 32, //(727) DPTF Critical threshold2 for SCU\r | |
| 312 | DSC3, 32, //(731) DPTF Critical threshold3 for SCU\r | |
| 313 | DSC4, 32, //(735) DPTF Critical threshold3 for SCU\r | |
| 314 | DDBG, 8, //(739) DPTF Super Debug option. 0 - Disabled, 1 - Enabled\r | |
| 315 | LPOE, 32, //(740) DPTF LPO Enable\r | |
| 316 | LPPS, 32, //(744) P-State start index\r | |
| 317 | LPST, 32, //(748) Step size\r | |
| 318 | LPPC, 32, //(752) Power control setting\r | |
| 319 | LPPF, 32, //(756) Performance control setting\r | |
| 320 | DPME, 8, //(760) DPTF DPPM enable/disable\r | |
| 321 | BCSL, 8, //(761) Battery charging solution 0-CLV 1-ULPMC\r | |
| 322 | NFCS, 8, //(762) NFCx Select 1: NFC1 2:NFC2\r | |
| 323 | PCIM, 8, //(763) EMMC device 0-ACPI mode, 1-PCI mode\r | |
| 324 | TPMA, 32, //(764)\r | |
| 325 | TPML, 32, //(768)\r | |
| 326 | ITSA, 8, //(772) I2C Touch Screen Address\r | |
| 327 | S0IX, 8, //(773) S0ix status\r | |
| 328 | SDMD, 8, //(774) SDIO Mode\r | |
| 329 | EMVR, 8, //(775) eMMC controller version\r | |
| 330 | BMBD, 32, //(776) BM Bound\r | |
| 331 | FSAS, 8, //(780) FSA Status\r | |
| 332 | BDID, 8, //(781) Board ID\r | |
| 333 | FBID, 8, //(782) FAB ID\r | |
| 334 | OTGM, 8, //(783) OTG mode\r | |
| 335 | STEP, 8, //(784) Stepping ID\r | |
| 336 | WITT, 8, //(785) Enable Test Device connected to I2C for WHCK test.\r | |
| 337 | SOCS, 8, //(786) provide the SoC stepping infomation\r | |
| 338 | AMTE, 8, //(787) Ambient Trip point change\r | |
| 339 | UTS, 8, //(788) Enable Test Device connected to URT for WHCK test.\r | |
| 340 | SCPE, 8, //(789) Allow higher performance on AC/USB - Enable/Disable\r | |
| 341 | Offset(792),\r | |
| 342 | EDPV, 8, //(792) Check for eDP display device\r | |
| 343 | DIDX, 32, //(793) Device ID for eDP device\r | |
| 52a99493 | 344 | IOT, 8, //(794) MinnowBoard Max JP1 is configured for MSFT IOT project.\r |
| a0f3b028 | 345 | BATT, 8, //(795) The Flag of RTC Battery Prensent.\r |
| aa44e98d | 346 | LPAD, 8, //(796)\r |
| 3cbfba02 DW |
347 | }\r |
| 348 | \r |