Vlv2DeviceRefCodePkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / Vlv2DeviceRefCodePkg / AcpiTablesPCAT / Platform.asl

/**************************************************************************;\r
;*                                                                        *;\r
;*                                                                        *;\r
;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
;*    Family of Customer Reference Boards.                                *;\r
;*                                                                        *;\r
;*                                                                        *;\r
;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;\r
;\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
;*                                                                        *;\r
;*                                                                        *;\r
;**************************************************************************/\r
\r
\r
// Define the following External variables to prevent a WARNING when\r
// using ASL.EXE and an ERROR when using IASL.EXE.\r
\r
External(PDC0)\r
External(PDC1)\r
External(PDC2)\r
External(PDC3)\r
External(CFGD)\r
External(\_PR.CPU0._PPC, IntObj)\r
External(\_SB.PCI0.LPCB.TPM.PTS, MethodObj)\r
External(\_SB.STR3, DeviceObj)\r
External(\_SB.I2C1.BATC, DeviceObj)\r
External(\_SB.DPTF, DeviceObj)\r
External(\_SB.TCHG, DeviceObj)\r
External(\_SB.IAOE.PTSL)\r
External(\_SB.IAOE.WKRS)\r
\r
//\r
// Create a Global MUTEX.\r
//\r
Mutex(MUTX,0)\r
\r
\r
\r
// Port 80h Update:\r
//              Update 8 bits of the 32-bit Port 80h.\r
//\r
//      Arguments:\r
//              Arg0:   0 = Write Port 80h, Bits 7:0 Only.\r
//                      1 = Write Port 80h, Bits 15:8 Only.\r
//                      2 = Write Port 80h, Bits 23:16 Only.\r
//                      3 = Write Port 80h, Bits 31:24 Only.\r
//              Arg1:   8-bit Value to write\r
//\r
//      Return Value:\r
//              None\r
\r
Method(P8XH,2,Serialized)\r
{\r
  If(LEqual(Arg0,0))            // Write Port 80h, Bits 7:0.\r
  {\r
    Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D)\r
  }\r
\r
  If(LEqual(Arg0,1))            // Write Port 80h, Bits 15:8.\r
  {\r
    Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D)\r
  }\r
\r
  If(LEqual(Arg0,2))            // Write Port 80h, Bits 23:16.\r
  {\r
    Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D)\r
  }\r
\r
  If(LEqual(Arg0,3))            // Write Port 80h, Bits 31:24.\r
  {\r
    Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D)\r
  }\r
\r
}\r
\r
//\r
// Define SW SMI port as an ACPI Operating Region to use for generate SW SMI.\r
//\r
OperationRegion (SPRT, SystemIO, 0xB2, 2)\r
Field (SPRT, ByteAcc, Lock, Preserve)\r
{\r
  SSMP, 8\r
}\r
\r
// The _PIC Control Method is optional for ACPI design.  It allows the\r
// OS to inform the ASL code which interrupt controller is being used,\r
// the 8259 or APIC.  The reference code in this document will address\r
// PCI IRQ Routing and resource allocation for both cases.\r
//\r
// The values passed into _PIC are:\r
//       0 = 8259\r
//       1 = IOAPIC\r
\r
Method(\_PIC,1)\r
{\r
  Store(Arg0,GPIC)\r
  Store(Arg0,PICM)\r
}\r
\r
OperationRegion(SWC0, SystemIO, 0x610, 0x0F)\r
Field(SWC0, ByteAcc, NoLock, Preserve)\r
{\r
  G1S, 8,      //SWC GPE1_STS\r
  Offset(0x4),\r
  G1E, 8,\r
  Offset(0xA),\r
  G1S2, 8,     //SWC GPE1_STS_2\r
  G1S3, 8      //SWC GPE1_STS_3\r
}\r
\r
OperationRegion (SWC1, SystemIO, \PMBS, 0x2C)\r
Field(SWC1, DWordAcc, NoLock, Preserve)\r
{\r
  Offset(0x20),\r
  G0S, 32,      //GPE0_STS\r
  Offset(0x28),\r
  G0EN, 32      //GPE0_EN\r
}\r
\r
// Prepare to Sleep.  The hook is called when the OS is about to\r
// enter a sleep state.  The argument passed is the numeric value of\r
// the Sx state.\r
\r
Method(_PTS,1)\r
{\r
  Store(0,P80D)         // Zero out the entire Port 80h DWord.\r
  P8XH(0,Arg0)          // Output Sleep State to Port 80h, Byte 0.\r
\r
  //clear the 3 SWC status bits\r
  Store(Ones, G1S3)\r
  Store(Ones, G1S2)\r
  Store(1, G1S)\r
\r
  //set SWC GPE1_EN\r
  Store(1,G1E)\r
\r
  //clear GPE0_STS\r
  Store(Ones, G0S)\r
\r
\r
  If(LEqual(Arg0,3))   // If S3 Suspend\r
  {\r
    //\r
    // Disable Digital Thermal Sensor function when doing S3 suspend\r
    //\r
    If(CondRefOf(DTSE))\r
    {\r
      If(LGreaterEqual(DTSE, 0x01))\r
      {\r
        Store(30, DTSF) // DISABLE_UPDATE_DTS_EVERY_SMI\r
        Store(0xD0, SSMP) // DTS SW SMI\r
      }\r
    }\r
  }\r
}\r
\r
// Wake.  This hook is called when the OS is about to wake from a\r
// sleep state.  The argument passed is the numeric value of the\r
// sleep state the system is waking from.\r
Method(_WAK,1,Serialized)\r
{\r
  P8XH(1,0xAB) // Beginning of _WAK.\r
\r
  Notify(\_SB.PWRB,0x02)\r
\r
  If(NEXP)\r
  {\r
    // Reinitialize the Native PCI Express after resume\r
    If(And(OSCC,0x02))\r
    {\r
      \_SB.PCI0.NHPG()\r
    }\r
\r
    If(And(OSCC,0x04))   // PME control granted?\r
    {\r
      \_SB.PCI0.NPME()\r
    }\r
  }\r
\r
  If(LOr(LEqual(Arg0,3), LEqual(Arg0,4)))   // If S3 or S4 Resume\r
  {\r
\r
\r
    // If CMP is enabled, we may need to restore the C-State and/or\r
    // P-State configuration, as it may have been saved before the\r
    // configuration was finalized based on OS/driver support.\r
    //\r
    //   CFGD[24]  = Two or more cores enabled\r
    //\r
    If(And(CFGD,0x01000000))\r
    {\r
      //\r
      // If CMP and the OSYS is WinXP SP1, we will enable C1-SMI if\r
      // C-States are enabled.\r
      //\r
      //   CFGD[7:4] = C4, C3, C2, C1 Capable/Enabled\r
      //\r
      //\r
    }\r
\r
    // Windows XP SP2 does not properly restore the P-State\r
    // upon resume from S4 or S3 with degrade modes enabled.\r
    // Use the existing _PPC methods to cycle the available\r
    // P-States such that the processor ends up running at\r
    // the proper P-State.\r
    //\r
    // Note:  For S4, another possible W/A is to always boot\r
    // the system in LFM.\r
    //\r
    If(LEqual(OSYS,2002))\r
    {\r
      If(And(CFGD,0x01))\r
      {\r
        If(LGreater(\_PR.CPU0._PPC,0))\r
        {\r
          Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)\r
          PNOT()\r
          Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)\r
          PNOT()\r
        }\r
        Else\r
        {\r
          Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)\r
          PNOT()\r
          Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)\r
          PNOT()\r
        }\r
      }\r
    }\r
  }\r
  Return(Package() {0,0})\r
}\r
\r
// Power Notification:\r
//              Perform all needed OS notifications during a\r
//              Power Switch.\r
//\r
//      Arguments:\r
//              None\r
//\r
//      Return Value:\r
//              None\r
\r
Method(PNOT,0,Serialized)\r
{\r
  // If MP enabled and driver support is present, notify all\r
  // processors.\r
\r
  If(MPEN)\r
  {\r
    If(And(PDC0,0x0008))\r
    {\r
      Notify(\_PR.CPU0,0x80)    // Eval CPU0 _PPC.\r
\r
      If(And(PDC0,0x0010))\r
      {\r
        Sleep(100)\r
        Notify(\_PR.CPU0,0x81)  // Eval _CST.\r
      }\r
    }\r
\r
    If(And(PDC1,0x0008))\r
    {\r
      Notify(\_PR.CPU1,0x80)    // Eval CPU1 _PPC.\r
\r
      If(And(PDC1,0x0010))\r
      {\r
        Sleep(100)\r
        Notify(\_PR.CPU1,0x81)  // Eval _CST.\r
      }\r
    }\r
\r
    If(And(PDC2,0x0008))\r
    {\r
      Notify(\_PR.CPU2,0x80)    // Eval CPU2 _PPC.\r
\r
      If(And(PDC2,0x0010))\r
      {\r
        Sleep(100)\r
        Notify(\_PR.CPU2,0x81)  // Eval _CST.\r
      }\r
    }\r
\r
    If(And(PDC3,0x0008))\r
    {\r
      Notify(\_PR.CPU3,0x80)    // Eval CPU3 _PPC.\r
\r
      If(And(PDC3,0x0010))\r
      {\r
        Sleep(100)\r
        Notify(\_PR.CPU3,0x81)  // Eval _CST.\r
      }\r
    }\r
  }\r
  Else\r
  {\r
    Notify(\_PR.CPU0,0x80)      // Eval _PPC.\r
    Sleep(100)\r
    Notify(\_PR.CPU0,0x81)      // Eval _CST\r
  }\r
}\r
\r
//\r
// System Bus\r
//\r
Scope(\_SB)\r
{\r
  Name(CRTT, 110) // Processor critical temperature\r
  Name(ACTT, 77)  // Active temperature limit for processor participant\r
  Name(GCR0, 70)  // Critical temperature for Generic participant 0 in degree celsius\r
  Name(GCR1, 70)  // Critical temperature for Generic participant 1 in degree celsius\r
  Name(GCR2, 70)  // Critical temperature for Generic participant 2 in degree celsius\r
  Name(GCR3, 70)  // Critical temperature for Generic participant 3 in degree celsius\r
  Name(GCR4, 70)  // Critical temperature for Generic participant 4 in degree celsius\r
  Name(GCR5, 70)  // Critical temperature for Generic participant 5 in degree celsius\r
  Name(GCR6, 70)  // Critical temperature for Generic participant 6 in degree celsius\r
  Name(PST0, 60)  // Passive temperature limit for Generic Participant 0 in degree celsius\r
  Name(PST1, 60)  // Passive temperature limit for Generic Participant 1 in degree celsius\r
  Name(PST2, 60)  // Passive temperature limit for Generic Participant 2 in degree celsius\r
  Name(PST3, 60)  // Passive temperature limit for Generic Participant 3 in degree celsius\r
  Name(PST4, 60)  // Passive temperature limit for Generic Participant 4 in degree celsius\r
  Name(PST5, 60)  // Passive temperature limit for Generic Participant 5 in degree celsius\r
  Name(PST6, 60)  // Passive temperature limit for Generic Participant 6 in degree celsius\r
  Name(LPMV, 3)\r
  Name(PDBG, 0)   // DPTF Super debug option\r
  Name(PDPM, 1)   // DPTF DPPM enable\r
  Name(PDBP, 1)   // DPTF DBPT enable (dynamic battery protection technology)\r
  Name(DLPO, Package()\r
  {\r
    0x1, // Revision\r
    0x1, // LPO Enable\r
    0x1, // LPO StartPState\r
    25,  // LPO StepSize\r
    0x1, //\r
    0x1, //\r
  })\r
  Name(BRQD, 0x00) // This is used to determine if DPTF display participant requested Brightness level change\r
  // or it is from Graphics driver. Value of 1 is for DPTF else it is 0\r
\r
  Method(_INI,0)\r
  {\r
    // NVS has stale DTS data.  Get and update the values\r
    // with current temperatures.   Note that this will also\r
    // re-arm any AP Thermal Interrupts.\r
    // Read temperature settings from global NVS\r
    Store(DPCT, CRTT)\r
    Store(Subtract(DPPT, 8), ACTT)                      // Active Trip point = Passive trip point - 8\r
    Store(DGC0, GCR0)\r
    Store(DGC0, GCR1)\r
    Store(DGC1, GCR2)\r
    Store(DGC1, GCR3)\r
    Store(DGC1, GCR4)\r
    Store(DGC2, GCR5)\r
    Store(DGC2, GCR6)\r
    Store(DGP0, PST0)\r
    Store(DGP0, PST1)\r
    Store(DGP1, PST2)\r
    Store(DGP1, PST3)\r
    Store(DGP1, PST4)\r
    Store(DGP2, PST5)\r
    Store(DGP2, PST6)\r
    // Read Current low power mode setting from global NVS\r
    Store(DLPM, LPMV)\r
\r
\r
    // Update DPTF Super Debug option\r
    Store(DDBG, PDBG)\r
\r
\r
    // Update DPTF LPO Options\r
    Store(LPOE, Index(DLPO,1))\r
    Store(LPPS, Index(DLPO,2))\r
    Store(LPST, Index(DLPO,3))\r
    Store(LPPC, Index(DLPO,4))\r
    Store(LPPF, Index(DLPO,5))\r
    Store(DPME, PDPM)\r
  }\r
\r
  // Define a (Control Method) Power Button.\r
  Device(PWRB)\r
  {\r
    Name(_HID,EISAID("PNP0C0C"))\r
\r
    // GPI_SUS0 = GPE16 = Waketime SCI.  The PRW isn't working when\r
    // placed in any of the logical locations ( PS2K, PS2M),\r
    // so a Power Button Device was created specifically\r
    // for the WAKETIME_SCI PRW.\r
\r
    Name(_PRW, Package() {16,4})\r
  }\r
\r
  Device(SLPB)\r
  {\r
    Name(_HID, EISAID("PNP0C0E"))\r
  } // END SLPB\r
\r
  Scope(PCI0)\r
  {\r
    Method(_INI,0)\r
    {\r
      // Determine the OS and store the value, where:\r
      //\r
      //   OSYS = 2009 = Windows 7 and Windows Server 2008 R2.\r
      //   OSYS = 2012 = Windows 8 and Windows Server 2012.\r
      //\r
      // Assume Windows 7 at a minimum.\r
\r
      Store(2009,OSYS)\r
\r
      // Check for a specific OS which supports _OSI.\r
\r
      If(CondRefOf(\_OSI,Local0))\r
      {\r
        // Linux returns _OSI = TRUE for numerous Windows\r
        // strings so that it is fully compatible with\r
        // BIOSes available in the market today.  There are\r
        // currently 2 known exceptions to this model:\r
        //      1) Video Repost - Linux supports S3 without\r
        //              requireing a Driver, meaning a Video\r
        //              Repost will be required.\r
        //      2) On-Screen Branding - a full CMT Logo\r
        //              is limited to the WIN2K and WINXP\r
        //              Operating Systems only.\r
\r
        // Use OSYS for Windows Compatibility.\r
        If(\_OSI("Windows 2009"))   // Windows 7 or Windows Server 2008 R2\r
        {\r
          Store(2009,OSYS)\r
        }\r
        If(\_OSI("Windows 2012"))   // Windows 8 or Windows Server 2012\r
        {\r
          Store(2012,OSYS)\r
        }\r
        If(\_OSI("Windows 2013"))   //Windows Blue\r
        {\r
          Store(2013,OSYS)\r
        }\r
\r
        //\r
        // If CMP is enabled, enable SMM C-State\r
        // coordination.  SMM C-State coordination\r
        // will be disabled in _PDC if driver support\r
        // for independent C-States deeper than C1\r
        // is indicated.\r
      }\r
    }\r
\r
    Method(NHPG,0,Serialized)\r
    {\r
\r
    }\r
\r
    Method(NPME,0,Serialized)\r
    {\r
\r
    }\r
  } // end Scope(PCI0)\r
\r
  Device (GPED)   //virtual GPIO device for ASL based AC/Battery/Expection notification\r
  {\r
    Name (_ADR, 0)\r
    Name (_HID, "INT0002")\r
    Name (_CID, "INT0002")\r
    Name (_DDN, "Virtual GPIO controller" )\r
    Name (_UID, 1)\r
\r
    Method (_CRS, 0x0, Serialized)\r
    {\r
      Name (RBUF, ResourceTemplate ()\r
      {\r
        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x9} // Was 9\r
      })\r
      Return (RBUF)\r
    }\r
\r
    Method (_STA, 0x0, NotSerialized)\r
    {\r
      Return(0x0)\r
    }\r
\r
    Method (_AEI, 0x0, Serialized)\r
    {\r
      Name(RBUF, ResourceTemplate()\r
      {\r
        GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullDown,,"\\_SB.GPED",) {2} //pin 2\r
      })\r
      Return(RBUF)\r
    }\r
\r
    Method(_E02)   // _Exx method will be called when interrupt is raised\r
    {\r
      If (LEqual (PWBS, 1))\r
      {\r
        Store (1, PWBS)      //Clear PowerButton Status\r
      }\r
      If (LEqual (PMEB, 1))\r
      {\r
        Store (1, PMEB)      //Clear PME_B0_STS\r
      }\r
      If (LEqual (\_SB.PCI0.SATA.PMES, 1))\r
      {\r
        Store (1, \_SB.PCI0.SATA.PMES)\r
        Notify (\_SB.PCI0.SATA, 0x02)\r
      }\r
      //\r
      // eMMC 4.41\r
      //\r
      If (LAnd(LEqual (\_SB.PCI0.EM41.PMES, 1), LEqual(PCIM, 1)))\r
      {\r
        Store (1, \_SB.PCI0.EM41.PMES)\r
        Notify (\_SB.PCI0.EM41, 0x02)\r
      }\r
\r
      //\r
      // eMMC 4.5\r
      //\r
      If (LAnd(LEqual (\_SB.PCI0.EM45.PMES, 1), LEqual(PCIM, 1)))\r
      {\r
        Store (1, \_SB.PCI0.EM45.PMES)\r
        Notify (\_SB.PCI0.EM45, 0x02)\r
      }\r
\r
      If (LEqual(HDAD, 0))\r
      {\r
        If (LEqual (\_SB.PCI0.HDEF.PMES, 1))\r
        {\r
          Store (1, \_SB.PCI0.HDEF.PMES)\r
          Notify (\_SB.PCI0.HDEF, 0x02)\r
        }\r
      }\r
\r
      If (LEqual (\_SB.PCI0.EHC1.PMES, 1))\r
      {\r
        Store (1, \_SB.PCI0.EHC1.PMES)\r
        Notify (\_SB.PCI0.EHC1, 0x02)\r
      }\r
      If (LEqual (\_SB.PCI0.XHC1.PMES, 1))\r
      {\r
        Store (1, \_SB.PCI0.XHC1.PMES)\r
        Notify (\_SB.PCI0.XHC1, 0x02)\r
      }\r
      If (LEqual (\_SB.PCI0.SEC0.PMES, 1))\r
      {\r
        Or (\_SB.PCI0.SEC0.PMES, Zero, \_SB.PCI0.SEC0.PMES)\r
        Notify (\_SB.PCI0.SEC0, 0x02)\r
      }\r
    }\r
  } //  Device (GPED)\r
\r
  //--------------------\r
  //  GPIO\r
  //--------------------\r
  Device (GPO0)\r
  {\r
    Name (_ADR, 0)\r
    Name (_HID, "INT33FC")\r
    Name (_CID, "INT33B2")\r
    Name (_DDN, "ValleyView2 General Purpose Input/Output (GPIO) controller" )\r
    Name (_UID, 1)\r
    Method (_CRS, 0x0, Serialized)\r
    {\r
      Name (RBUF, ResourceTemplate ()\r
      {\r
        Memory32Fixed (ReadWrite, 0x0FED0C000, 0x00001000)\r
        Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {49}\r
\r
      })\r
      Return (RBUF)\r
    }\r
\r
    Method (_STA, 0x0, NotSerialized)\r
    {\r
      //\r
      // GPO driver will report present if any of below New IO bus exist\r
      //\r
      If (LOr(LEqual(L11D, 0), LEqual(L12D, 0))) // LPIO1 PWM #1 or #2 exist\r
      { Return(0xF) }\r
      If (LOr(LEqual(L13D, 0), LEqual(L14D, 0))) // LPIO1 HS-UART #1 or #2 exist\r
      { Return(0xF) }\r
      If (LOr(LEqual(L15D, 0), LEqual(SD1D, 0))) // LPIO1 SPI or SCC SDIO #1 exist\r
      { Return(0xF) }\r
      If (LOr(LEqual(SD2D, 0), LEqual(SD3D, 0))) // SCC SDIO #2 or #3 exist\r
      { Return(0xF) }\r
      If (LOr(LEqual(L21D, 0), LEqual(L22D, 0))) // LPIO2 I2C #1 or #2 exist\r
      { Return(0xF) }\r
      If (LOr(LEqual(L23D, 0), LEqual(L24D, 0))) // LPIO2 I2C #3 or #4 exist\r
      { Return(0xF) }\r
      If (LOr(LEqual(L25D, 0), LEqual(L26D, 0))) // LPIO2 I2C #5 or #6 exist\r
      { Return(0xF) }\r
      If (LEqual(L27D, 0))                       // LPIO2 I2C #7 exist\r
      { Return(0xF) }\r
\r
      Return(0x0)\r
    }\r
\r
    // Track status of GPIO OpRegion availability for this controller\r
    Name(AVBL, 0)\r
    Method(_REG,2)\r
    {\r
      If (Lequal(Arg0, 8))\r
      {\r
        Store(Arg1, ^AVBL)\r
      }\r
    }\r
\r
    OperationRegion(GPOP, SystemIo, \GPBS, 0x50)\r
      Field(GPOP, ByteAcc, NoLock, Preserve) {\r
      Offset(0x28), // cfio_ioreg_SC_GP_LVL_63_32_ - [GPIO_BASE_ADDRESS] + 28h\r
          ,  21,\r
      BTD3,  1,     //This field is not used. Pin not defined in schematics. Closest is GPIO_S5_35 - COMBO_BT_WAKEUP\r
      Offset(0x48), // cfio_ioreg_SC_GP_LVL_95_64_ - [GPIO_BASE_ADDRESS] + 48h\r
          ,  30,\r
      SHD3,  1      //GPIO_S0_SC_95 - SENS_HUB_RST_N\r
    }\r
\r
\r
\r
  }   //  Device (GPO0)\r
\r
  Device (GPO1)\r
  {\r
    Name (_ADR, 0)\r
    Name (_HID, "INT33FC")\r
    Name (_CID, "INT33B2")\r
    Name (_DDN, "ValleyView2 GPNCORE controller" )\r
    Name (_UID, 2)\r
    Method (_CRS, 0x0, Serialized)\r
    {\r
      Name (RBUF, ResourceTemplate ()\r
      {\r
        Memory32Fixed (ReadWrite, 0x0FED0D000, 0x00001000)\r
        Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {48}\r
      })\r
      Return (RBUF)\r
    }\r
\r
    Method (_STA, 0x0, NotSerialized)\r
    {\r
      Return(\_SB.GPO0._STA)\r
    }\r
  }   //  Device (GPO1)\r
\r
  Device (GPO2)\r
  {\r
    Name (_ADR, 0)\r
    Name (_HID, "INT33FC")\r
    Name (_CID, "INT33B2")\r
    Name (_DDN, "ValleyView2 GPSUS controller" )\r
    Name (_UID, 3)\r
    Method (_CRS, 0x0, Serialized)\r
    {\r
      Name (RBUF, ResourceTemplate ()\r
      {\r
        Memory32Fixed (ReadWrite, 0x0FED0E000, 0x00001000)\r
        Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {50}\r
      })\r
      Return (RBUF)\r
    }\r
\r
    Method (_STA, 0x0, NotSerialized)\r
    {\r
      Return(^^GPO0._STA)\r
    }\r
\r
    // Track status of GPIO OpRegion availability for this controller\r
    Name(AVBL, 0)\r
    Method(_REG,2)\r
    {\r
      If (Lequal(Arg0, 8))\r
      {\r
        Store(Arg1, ^AVBL)\r
      }\r
    }\r
    //Manipulate GPIO line using GPIO operation regions.\r
    Name (GMOD, ResourceTemplate ()     //One method of creating a Connection for OpRegion accesses in Field definitions\r
    {\r
      //is creating a named object that refers to the connection attributes\r
      GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2") {21}  //sus 21+128 BT+WLAN_ENABLE\r
    })\r
\r
  OperationRegion(GPOP, SystemIo, \GPBS, 0x100)\r
  Field(GPOP, ByteAcc, NoLock, Preserve) {\r
      Offset(0x88),  // cfio_ioreg_SUS_GP_LVL_31_0_ - [GPIO_BASE_ADDRESS] + 88h\r
          ,  20,\r
      WFD3,  1\r
    }\r
\r
\r
  }   //  Device (GPO2)\r
  include ("PchScc.asl")\r
  include ("PchLpss.asl")\r
\r
         Scope(I2C7)\r
  {\r
\r
  } //End Scope(I2C7)\r
\r
} // end Scope(\_SB)\r
\r
Name(PICM, 0)   // Global Name, returns current Interrupt controller mode; updated from _PIC control method\r
\r