Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Platform.asl

   1 /**************************************************************************;
   2 ;*                                                                        *;
   3 ;*                                                                        *;
   4 ;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
   5 ;*    Family of Customer Reference Boards.                                *;
   6 ;*                                                                        *;
   7 ;*                                                                        *;
   8 ;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;
   9 ;
  10 ; SPDX-License-Identifier: BSD-2-Clause-Patent
  11 ;
  12 ;*                                                                        *;
  13 ;*                                                                        *;
  14 ;**************************************************************************/
  15
  16
  17 // Define the following External variables to prevent a WARNING when
  18 // using ASL.EXE and an ERROR when using IASL.EXE.
  19
  20 External(PDC0)
  21 External(PDC1)
  22 External(PDC2)
  23 External(PDC3)
  24 External(CFGD)
  25 External(\_PR.CPU0._PPC, IntObj)
  26 External(\_SB.PCI0.LPCB.TPM.PTS, MethodObj)
  27 External(\_SB.STR3, DeviceObj)
  28 External(\_SB.I2C1.BATC, DeviceObj)
  29 External(\_SB.DPTF, DeviceObj)
  30 External(\_SB.TCHG, DeviceObj)
  31 External(\_SB.IAOE.PTSL)
  32 External(\_SB.IAOE.WKRS)
  33
  34 //
  35 // Create a Global MUTEX.
  36 //
  37 Mutex(MUTX,0)
  38
  39
  40
  41 // Port 80h Update:
  42 //              Update 8 bits of the 32-bit Port 80h.
  43 //
  44 //      Arguments:
  45 //              Arg0:   0 = Write Port 80h, Bits 7:0 Only.
  46 //                      1 = Write Port 80h, Bits 15:8 Only.
  47 //                      2 = Write Port 80h, Bits 23:16 Only.
  48 //                      3 = Write Port 80h, Bits 31:24 Only.
  49 //              Arg1:   8-bit Value to write
  50 //
  51 //      Return Value:
  52 //              None
  53
  54 Method(P8XH,2,Serialized)
  55 {
  56   If(LEqual(Arg0,0))            // Write Port 80h, Bits 7:0.
  57   {
  58     Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D)
  59   }
  60
  61   If(LEqual(Arg0,1))            // Write Port 80h, Bits 15:8.
  62   {
  63     Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D)
  64   }
  65
  66   If(LEqual(Arg0,2))            // Write Port 80h, Bits 23:16.
  67   {
  68     Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D)
  69   }
  70
  71   If(LEqual(Arg0,3))            // Write Port 80h, Bits 31:24.
  72   {
  73     Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D)
  74   }
  75
  76 }
  77
  78 //
  79 // Define SW SMI port as an ACPI Operating Region to use for generate SW SMI.
  80 //
  81 OperationRegion (SPRT, SystemIO, 0xB2, 2)
  82 Field (SPRT, ByteAcc, Lock, Preserve)
  83 {
  84   SSMP, 8
  85 }
  86
  87 // The _PIC Control Method is optional for ACPI design.  It allows the
  88 // OS to inform the ASL code which interrupt controller is being used,
  89 // the 8259 or APIC.  The reference code in this document will address
  90 // PCI IRQ Routing and resource allocation for both cases.
  91 //
  92 // The values passed into _PIC are:
  93 //       0 = 8259
  94 //       1 = IOAPIC
  95
  96 Method(\_PIC,1)
  97 {
  98   Store(Arg0,GPIC)
  99   Store(Arg0,PICM)
 100 }
 101
 102 OperationRegion(SWC0, SystemIO, 0x610, 0x0F)
 103 Field(SWC0, ByteAcc, NoLock, Preserve)
 104 {
 105   G1S, 8,      //SWC GPE1_STS
 106   Offset(0x4),
 107   G1E, 8,
 108   Offset(0xA),
 109   G1S2, 8,     //SWC GPE1_STS_2
 110   G1S3, 8      //SWC GPE1_STS_3
 111 }
 112
 113 OperationRegion (SWC1, SystemIO, \PMBS, 0x2C)
 114 Field(SWC1, DWordAcc, NoLock, Preserve)
 115 {
 116   Offset(0x20),
 117   G0S, 32,      //GPE0_STS
 118   Offset(0x28),
 119   G0EN, 32      //GPE0_EN
 120 }
 121
 122 // Prepare to Sleep.  The hook is called when the OS is about to
 123 // enter a sleep state.  The argument passed is the numeric value of
 124 // the Sx state.
 125
 126 Method(_PTS,1)
 127 {
 128   Store(0,P80D)         // Zero out the entire Port 80h DWord.
 129   P8XH(0,Arg0)          // Output Sleep State to Port 80h, Byte 0.
 130
 131   //clear the 3 SWC status bits
 132   Store(Ones, G1S3)
 133   Store(Ones, G1S2)
 134   Store(1, G1S)
 135
 136   //set SWC GPE1_EN
 137   Store(1,G1E)
 138
 139   //clear GPE0_STS
 140   Store(Ones, G0S)
 141
 142
 143   If(LEqual(Arg0,3))   // If S3 Suspend
 144   {
 145     //
 146     // Disable Digital Thermal Sensor function when doing S3 suspend
 147     //
 148     If(CondRefOf(DTSE))
 149     {
 150       If(LGreaterEqual(DTSE, 0x01))
 151       {
 152         Store(30, DTSF) // DISABLE_UPDATE_DTS_EVERY_SMI
 153         Store(0xD0, SSMP) // DTS SW SMI
 154       }
 155     }
 156   }
 157 }
 158
 159 // Wake.  This hook is called when the OS is about to wake from a
 160 // sleep state.  The argument passed is the numeric value of the
 161 // sleep state the system is waking from.
 162 Method(_WAK,1,Serialized)
 163 {
 164   P8XH(1,0xAB) // Beginning of _WAK.
 165
 166   Notify(\_SB.PWRB,0x02)
 167
 168   If(NEXP)
 169   {
 170     // Reinitialize the Native PCI Express after resume
 171     If(And(OSCC,0x02))
 172     {
 173       \_SB.PCI0.NHPG()
 174     }
 175
 176     If(And(OSCC,0x04))   // PME control granted?
 177     {
 178       \_SB.PCI0.NPME()
 179     }
 180   }
 181
 182   If(LOr(LEqual(Arg0,3), LEqual(Arg0,4)))   // If S3 or S4 Resume
 183   {
 184
 185
 186     // If CMP is enabled, we may need to restore the C-State and/or
 187     // P-State configuration, as it may have been saved before the
 188     // configuration was finalized based on OS/driver support.
 189     //
 190     //   CFGD[24]  = Two or more cores enabled
 191     //
 192     If(And(CFGD,0x01000000))
 193     {
 194       //
 195       // If CMP and the OSYS is WinXP SP1, we will enable C1-SMI if
 196       // C-States are enabled.
 197       //
 198       //   CFGD[7:4] = C4, C3, C2, C1 Capable/Enabled
 199       //
 200       //
 201     }
 202
 203     // Windows XP SP2 does not properly restore the P-State
 204     // upon resume from S4 or S3 with degrade modes enabled.
 205     // Use the existing _PPC methods to cycle the available
 206     // P-States such that the processor ends up running at
 207     // the proper P-State.
 208     //
 209     // Note:  For S4, another possible W/A is to always boot
 210     // the system in LFM.
 211     //
 212     If(LEqual(OSYS,2002))
 213     {
 214       If(And(CFGD,0x01))
 215       {
 216         If(LGreater(\_PR.CPU0._PPC,0))
 217         {
 218           Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)
 219           PNOT()
 220           Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)
 221           PNOT()
 222         }
 223         Else
 224         {
 225           Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)
 226           PNOT()
 227           Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)
 228           PNOT()
 229         }
 230       }
 231     }
 232   }
 233   Return(Package() {0,0})
 234 }
 235
 236 // Power Notification:
 237 //              Perform all needed OS notifications during a
 238 //              Power Switch.
 239 //
 240 //      Arguments:
 241 //              None
 242 //
 243 //      Return Value:
 244 //              None
 245
 246 Method(PNOT,0,Serialized)
 247 {
 248   // If MP enabled and driver support is present, notify all
 249   // processors.
 250
 251   If(MPEN)
 252   {
 253     If(And(PDC0,0x0008))
 254     {
 255       Notify(\_PR.CPU0,0x80)    // Eval CPU0 _PPC.
 256
 257       If(And(PDC0,0x0010))
 258       {
 259         Sleep(100)
 260         Notify(\_PR.CPU0,0x81)  // Eval _CST.
 261       }
 262     }
 263
 264     If(And(PDC1,0x0008))
 265     {
 266       Notify(\_PR.CPU1,0x80)    // Eval CPU1 _PPC.
 267
 268       If(And(PDC1,0x0010))
 269       {
 270         Sleep(100)
 271         Notify(\_PR.CPU1,0x81)  // Eval _CST.
 272       }
 273     }
 274
 275     If(And(PDC2,0x0008))
 276     {
 277       Notify(\_PR.CPU2,0x80)    // Eval CPU2 _PPC.
 278
 279       If(And(PDC2,0x0010))
 280       {
 281         Sleep(100)
 282         Notify(\_PR.CPU2,0x81)  // Eval _CST.
 283       }
 284     }
 285
 286     If(And(PDC3,0x0008))
 287     {
 288       Notify(\_PR.CPU3,0x80)    // Eval CPU3 _PPC.
 289
 290       If(And(PDC3,0x0010))
 291       {
 292         Sleep(100)
 293         Notify(\_PR.CPU3,0x81)  // Eval _CST.
 294       }
 295     }
 296   }
 297   Else
 298   {
 299     Notify(\_PR.CPU0,0x80)      // Eval _PPC.
 300     Sleep(100)
 301     Notify(\_PR.CPU0,0x81)      // Eval _CST
 302   }
 303 }
 304
 305 //
 306 // System Bus
 307 //
 308 Scope(\_SB)
 309 {
 310   Name(CRTT, 110) // Processor critical temperature
 311   Name(ACTT, 77)  // Active temperature limit for processor participant
 312   Name(GCR0, 70)  // Critical temperature for Generic participant 0 in degree celsius
 313   Name(GCR1, 70)  // Critical temperature for Generic participant 1 in degree celsius
 314   Name(GCR2, 70)  // Critical temperature for Generic participant 2 in degree celsius
 315   Name(GCR3, 70)  // Critical temperature for Generic participant 3 in degree celsius
 316   Name(GCR4, 70)  // Critical temperature for Generic participant 4 in degree celsius
 317   Name(GCR5, 70)  // Critical temperature for Generic participant 5 in degree celsius
 318   Name(GCR6, 70)  // Critical temperature for Generic participant 6 in degree celsius
 319   Name(PST0, 60)  // Passive temperature limit for Generic Participant 0 in degree celsius
 320   Name(PST1, 60)  // Passive temperature limit for Generic Participant 1 in degree celsius
 321   Name(PST2, 60)  // Passive temperature limit for Generic Participant 2 in degree celsius
 322   Name(PST3, 60)  // Passive temperature limit for Generic Participant 3 in degree celsius
 323   Name(PST4, 60)  // Passive temperature limit for Generic Participant 4 in degree celsius
 324   Name(PST5, 60)  // Passive temperature limit for Generic Participant 5 in degree celsius
 325   Name(PST6, 60)  // Passive temperature limit for Generic Participant 6 in degree celsius
 326   Name(LPMV, 3)
 327   Name(PDBG, 0)   // DPTF Super debug option
 328   Name(PDPM, 1)   // DPTF DPPM enable
 329   Name(PDBP, 1)   // DPTF DBPT enable (dynamic battery protection technology)
 330   Name(DLPO, Package()
 331   {
 332     0x1, // Revision
 333     0x1, // LPO Enable
 334     0x1, // LPO StartPState
 335     25,  // LPO StepSize
 336     0x1, //
 337     0x1, //
 338   })
 339   Name(BRQD, 0x00) // This is used to determine if DPTF display participant requested Brightness level change
 340   // or it is from Graphics driver. Value of 1 is for DPTF else it is 0
 341
 342   Method(_INI,0)
 343   {
 344     // NVS has stale DTS data.  Get and update the values
 345     // with current temperatures.   Note that this will also
 346     // re-arm any AP Thermal Interrupts.
 347     // Read temperature settings from global NVS
 348     Store(DPCT, CRTT)
 349     Store(Subtract(DPPT, 8), ACTT)                      // Active Trip point = Passive trip point - 8
 350     Store(DGC0, GCR0)
 351     Store(DGC0, GCR1)
 352     Store(DGC1, GCR2)
 353     Store(DGC1, GCR3)
 354     Store(DGC1, GCR4)
 355     Store(DGC2, GCR5)
 356     Store(DGC2, GCR6)
 357     Store(DGP0, PST0)
 358     Store(DGP0, PST1)
 359     Store(DGP1, PST2)
 360     Store(DGP1, PST3)
 361     Store(DGP1, PST4)
 362     Store(DGP2, PST5)
 363     Store(DGP2, PST6)
 364     // Read Current low power mode setting from global NVS
 365     Store(DLPM, LPMV)
 366
 367
 368     // Update DPTF Super Debug option
 369     Store(DDBG, PDBG)
 370
 371
 372     // Update DPTF LPO Options
 373     Store(LPOE, Index(DLPO,1))
 374     Store(LPPS, Index(DLPO,2))
 375     Store(LPST, Index(DLPO,3))
 376     Store(LPPC, Index(DLPO,4))
 377     Store(LPPF, Index(DLPO,5))
 378     Store(DPME, PDPM)
 379   }
 380
 381   // Define a (Control Method) Power Button.
 382   Device(PWRB)
 383   {
 384     Name(_HID,EISAID("PNP0C0C"))
 385
 386     // GPI_SUS0 = GPE16 = Waketime SCI.  The PRW isn't working when
 387     // placed in any of the logical locations ( PS2K, PS2M),
 388     // so a Power Button Device was created specifically
 389     // for the WAKETIME_SCI PRW.
 390
 391     Name(_PRW, Package() {16,4})
 392   }
 393
 394   Device(SLPB)
 395   {
 396     Name(_HID, EISAID("PNP0C0E"))
 397   } // END SLPB
 398
 399   Scope(PCI0)
 400   {
 401     Method(_INI,0)
 402     {
 403       // Determine the OS and store the value, where:
 404       //
 405       //   OSYS = 2009 = Windows 7 and Windows Server 2008 R2.
 406       //   OSYS = 2012 = Windows 8 and Windows Server 2012.
 407       //
 408       // Assume Windows 7 at a minimum.
 409
 410       Store(2009,OSYS)
 411
 412       // Check for a specific OS which supports _OSI.
 413
 414       If(CondRefOf(\_OSI,Local0))
 415       {
 416         // Linux returns _OSI = TRUE for numerous Windows
 417         // strings so that it is fully compatible with
 418         // BIOSes available in the market today.  There are
 419         // currently 2 known exceptions to this model:
 420         //      1) Video Repost - Linux supports S3 without
 421         //              requireing a Driver, meaning a Video
 422         //              Repost will be required.
 423         //      2) On-Screen Branding - a full CMT Logo
 424         //              is limited to the WIN2K and WINXP
 425         //              Operating Systems only.
 426
 427         // Use OSYS for Windows Compatibility.
 428         If(\_OSI("Windows 2009"))   // Windows 7 or Windows Server 2008 R2
 429         {
 430           Store(2009,OSYS)
 431         }
 432         If(\_OSI("Windows 2012"))   // Windows 8 or Windows Server 2012
 433         {
 434           Store(2012,OSYS)
 435         }
 436         If(\_OSI("Windows 2013"))   //Windows Blue
 437         {
 438           Store(2013,OSYS)
 439         }
 440
 441         //
 442         // If CMP is enabled, enable SMM C-State
 443         // coordination.  SMM C-State coordination
 444         // will be disabled in _PDC if driver support
 445         // for independent C-States deeper than C1
 446         // is indicated.
 447       }
 448     }
 449
 450     Method(NHPG,0,Serialized)
 451     {
 452
 453     }
 454
 455     Method(NPME,0,Serialized)
 456     {
 457
 458     }
 459   } // end Scope(PCI0)
 460
 461   Device (GPED)   //virtual GPIO device for ASL based AC/Battery/Expection notification
 462   {
 463     Name (_ADR, 0)
 464     Name (_HID, "INT0002")
 465     Name (_CID, "INT0002")
 466     Name (_DDN, "Virtual GPIO controller" )
 467     Name (_UID, 1)
 468
 469     Method (_CRS, 0x0, Serialized)
 470     {
 471       Name (RBUF, ResourceTemplate ()
 472       {
 473         Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x9} // Was 9
 474       })
 475       Return (RBUF)
 476     }
 477
 478     Method (_STA, 0x0, NotSerialized)
 479     {
 480       Return(0x0)
 481     }
 482
 483     Method (_AEI, 0x0, Serialized)
 484     {
 485       Name(RBUF, ResourceTemplate()
 486       {
 487         GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullDown,,"\\_SB.GPED",) {2} //pin 2
 488       })
 489       Return(RBUF)
 490     }
 491
 492     Method(_E02)   // _Exx method will be called when interrupt is raised
 493     {
 494       If (LEqual (PWBS, 1))
 495       {
 496         Store (1, PWBS)      //Clear PowerButton Status
 497       }
 498       If (LEqual (PMEB, 1))
 499       {
 500         Store (1, PMEB)      //Clear PME_B0_STS
 501       }
 502       If (LEqual (\_SB.PCI0.SATA.PMES, 1))
 503       {
 504         Store (1, \_SB.PCI0.SATA.PMES)
 505         Notify (\_SB.PCI0.SATA, 0x02)
 506       }
 507       //
 508       // eMMC 4.41
 509       //
 510       If (LAnd(LEqual (\_SB.PCI0.EM41.PMES, 1), LEqual(PCIM, 1)))
 511       {
 512         Store (1, \_SB.PCI0.EM41.PMES)
 513         Notify (\_SB.PCI0.EM41, 0x02)
 514       }
 515
 516       //
 517       // eMMC 4.5
 518       //
 519       If (LAnd(LEqual (\_SB.PCI0.EM45.PMES, 1), LEqual(PCIM, 1)))
 520       {
 521         Store (1, \_SB.PCI0.EM45.PMES)
 522         Notify (\_SB.PCI0.EM45, 0x02)
 523       }
 524
 525       If (LEqual(HDAD, 0))
 526       {
 527         If (LEqual (\_SB.PCI0.HDEF.PMES, 1))
 528         {
 529           Store (1, \_SB.PCI0.HDEF.PMES)
 530           Notify (\_SB.PCI0.HDEF, 0x02)
 531         }
 532       }
 533
 534       If (LEqual (\_SB.PCI0.EHC1.PMES, 1))
 535       {
 536         Store (1, \_SB.PCI0.EHC1.PMES)
 537         Notify (\_SB.PCI0.EHC1, 0x02)
 538       }
 539       If (LEqual (\_SB.PCI0.XHC1.PMES, 1))
 540       {
 541         Store (1, \_SB.PCI0.XHC1.PMES)
 542         Notify (\_SB.PCI0.XHC1, 0x02)
 543       }
 544       If (LEqual (\_SB.PCI0.SEC0.PMES, 1))
 545       {
 546         Or (\_SB.PCI0.SEC0.PMES, Zero, \_SB.PCI0.SEC0.PMES)
 547         Notify (\_SB.PCI0.SEC0, 0x02)
 548       }
 549     }
 550   } //  Device (GPED)
 551
 552   //--------------------
 553   //  GPIO
 554   //--------------------
 555   Device (GPO0)
 556   {
 557     Name (_ADR, 0)
 558     Name (_HID, "INT33FC")
 559     Name (_CID, "INT33B2")
 560     Name (_DDN, "ValleyView2 General Purpose Input/Output (GPIO) controller" )
 561     Name (_UID, 1)
 562     Method (_CRS, 0x0, Serialized)
 563     {
 564       Name (RBUF, ResourceTemplate ()
 565       {
 566         Memory32Fixed (ReadWrite, 0x0FED0C000, 0x00001000)
 567         Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {49}
 568
 569       })
 570       Return (RBUF)
 571     }
 572
 573     Method (_STA, 0x0, NotSerialized)
 574     {
 575       //
 576       // GPO driver will report present if any of below New IO bus exist
 577       //
 578       If (LOr(LEqual(L11D, 0), LEqual(L12D, 0))) // LPIO1 PWM #1 or #2 exist
 579       { Return(0xF) }
 580       If (LOr(LEqual(L13D, 0), LEqual(L14D, 0))) // LPIO1 HS-UART #1 or #2 exist
 581       { Return(0xF) }
 582       If (LOr(LEqual(L15D, 0), LEqual(SD1D, 0))) // LPIO1 SPI or SCC SDIO #1 exist
 583       { Return(0xF) }
 584       If (LOr(LEqual(SD2D, 0), LEqual(SD3D, 0))) // SCC SDIO #2 or #3 exist
 585       { Return(0xF) }
 586       If (LOr(LEqual(L21D, 0), LEqual(L22D, 0))) // LPIO2 I2C #1 or #2 exist
 587       { Return(0xF) }
 588       If (LOr(LEqual(L23D, 0), LEqual(L24D, 0))) // LPIO2 I2C #3 or #4 exist
 589       { Return(0xF) }
 590       If (LOr(LEqual(L25D, 0), LEqual(L26D, 0))) // LPIO2 I2C #5 or #6 exist
 591       { Return(0xF) }
 592       If (LEqual(L27D, 0))                       // LPIO2 I2C #7 exist
 593       { Return(0xF) }
 594
 595       Return(0x0)
 596     }
 597
 598     // Track status of GPIO OpRegion availability for this controller
 599     Name(AVBL, 0)
 600     Method(_REG,2)
 601     {
 602       If (Lequal(Arg0, 8))
 603       {
 604         Store(Arg1, ^AVBL)
 605       }
 606     }
 607
 608     OperationRegion(GPOP, SystemIo, \GPBS, 0x50)
 609       Field(GPOP, ByteAcc, NoLock, Preserve) {
 610       Offset(0x28), // cfio_ioreg_SC_GP_LVL_63_32_ - [GPIO_BASE_ADDRESS] + 28h
 611           ,  21,
 612       BTD3,  1,     //This field is not used. Pin not defined in schematics. Closest is GPIO_S5_35 - COMBO_BT_WAKEUP
 613       Offset(0x48), // cfio_ioreg_SC_GP_LVL_95_64_ - [GPIO_BASE_ADDRESS] + 48h
 614           ,  30,
 615       SHD3,  1      //GPIO_S0_SC_95 - SENS_HUB_RST_N
 616     }
 617
 618
 619
 620   }   //  Device (GPO0)
 621
 622   Device (GPO1)
 623   {
 624     Name (_ADR, 0)
 625     Name (_HID, "INT33FC")
 626     Name (_CID, "INT33B2")
 627     Name (_DDN, "ValleyView2 GPNCORE controller" )
 628     Name (_UID, 2)
 629     Method (_CRS, 0x0, Serialized)
 630     {
 631       Name (RBUF, ResourceTemplate ()
 632       {
 633         Memory32Fixed (ReadWrite, 0x0FED0D000, 0x00001000)
 634         Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {48}
 635       })
 636       Return (RBUF)
 637     }
 638
 639     Method (_STA, 0x0, NotSerialized)
 640     {
 641       Return(\_SB.GPO0._STA)
 642     }
 643   }   //  Device (GPO1)
 644
 645   Device (GPO2)
 646   {
 647     Name (_ADR, 0)
 648     Name (_HID, "INT33FC")
 649     Name (_CID, "INT33B2")
 650     Name (_DDN, "ValleyView2 GPSUS controller" )
 651     Name (_UID, 3)
 652     Method (_CRS, 0x0, Serialized)
 653     {
 654       Name (RBUF, ResourceTemplate ()
 655       {
 656         Memory32Fixed (ReadWrite, 0x0FED0E000, 0x00001000)
 657         Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {50}
 658       })
 659       Return (RBUF)
 660     }
 661
 662     Method (_STA, 0x0, NotSerialized)
 663     {
 664       Return(^^GPO0._STA)
 665     }
 666
 667     // Track status of GPIO OpRegion availability for this controller
 668     Name(AVBL, 0)
 669     Method(_REG,2)
 670     {
 671       If (Lequal(Arg0, 8))
 672       {
 673         Store(Arg1, ^AVBL)
 674       }
 675     }
 676     //Manipulate GPIO line using GPIO operation regions.
 677     Name (GMOD, ResourceTemplate ()     //One method of creating a Connection for OpRegion accesses in Field definitions
 678     {
 679       //is creating a named object that refers to the connection attributes
 680       GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2") {21}  //sus 21+128 BT+WLAN_ENABLE
 681     })
 682
 683   OperationRegion(GPOP, SystemIo, \GPBS, 0x100)
 684   Field(GPOP, ByteAcc, NoLock, Preserve) {
 685       Offset(0x88),  // cfio_ioreg_SUS_GP_LVL_31_0_ - [GPIO_BASE_ADDRESS] + 88h
 686           ,  20,
 687       WFD3,  1
 688     }
 689
 690
 691   }   //  Device (GPO2)
 692   include ("PchScc.asl")
 693   include ("PchLpss.asl")
 694
 695          Scope(I2C7)
 696   {
 697
 698   } //End Scope(I2C7)
 699
 700 } // end Scope(\_SB)
 701
 702 Name(PICM, 0)   // Global Name, returns current Interrupt controller mode; updated from _PIC control method
 703