[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / CPU / PowerManagement / AcpiTables / Ssdt / ApTst.asl

/*-----------------------------------------------------------------------------\r
-------------------------------------------------------------------------------\r
\r
\r
 Intel Platform Processor Power Management BIOS Reference Code\r
\r
 Copyright (c) 2007  - 2014, Intel Corporation\r
\r
  This program and the accompanying materials are licensed and made available under\r
  the terms and conditions of the BSD License that accompanies this distribution.\r
  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
\r
 Filename:      APTST.ASL\r
\r
 Revision:      Refer to Readme\r
\r
 Date:          Refer to Readme\r
\r
--------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------\r
\r
 This Processor Power Management BIOS Source Code is furnished under license\r
 and may only be used or copied in accordance with the terms of the license.\r
 The information in this document is furnished for informational use only, is\r
 subject to change without notice, and should not be construed as a commitment\r
 by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
 for any errors or inaccuracies that may appear in this document or any\r
 software that may be provided in association with this document.\r
\r
 Except as permitted by such license, no part of this document may be\r
 reproduced, stored in a retrieval system, or transmitted in any form or by\r
 any means without the express written consent of Intel Corporation.\r
\r
 WARNING: You are authorized and licensed to install and use this BIOS code\r
 ONLY on an IST PC. This utility may damage any system that does not\r
 meet these requirements.\r
\r
        An IST PC is a computer which\r
        (1) Is capable of seamlessly and automatically transitioning among\r
        multiple performance states (potentially operating at different\r
        efficiency ratings) based upon power source changes, END user\r
        preference, processor performance demand, and thermal conditions; and\r
        (2) Includes an Intel Pentium II processors, Intel Pentium III\r
        processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
        Processor-M, Intel Pentium M Processor, or any other future Intel\r
        processors that incorporates the capability to transition between\r
        different performance states by altering some, or any combination of,\r
        the following processor attributes: core voltage, core frequency, bus\r
        frequency, number of processor cores available, or any other attribute\r
        that changes the efficiency (instructions/unit time-power) at which the\r
        processor operates.\r
\r
-------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------\r
\r
NOTES:\r
        (1) <TODO> - IF the trap range and port definitions do not match those\r
        specified by this reference code, this file must be modified IAW the\r
        individual implmentation.\r
\r
--------------------------------------------------------------------------------\r
------------------------------------------------------------------------------*/\r
\r
\r
DefinitionBlock(\r
        "APTST.aml",\r
        "SSDT",\r
        0x01,\r
        "PmRef",\r
        "ApTst",\r
        0x3000\r
        )\r
{\r
        External(\_PR.CPU1, DeviceObj)\r
        External(\_PR.CPU2, DeviceObj)\r
        External(\_PR.CPU3, DeviceObj)\r
        External(\_PR.CPU0._PTC)\r
        External(\_PR.CPU0._TSS)\r
        External(PDC0)\r
        External(CFGD)\r
        External(MPEN)\r
\r
        Scope(\_PR.CPU1)\r
        {\r
                Name(_TPC, 0)   // All T-States are available\r
\r
                //\r
                // T-State Control/Status interface\r
                //\r
                Method(_PTC, 0)\r
                {\r
                        Return(\_PR.CPU0._PTC)\r
                }\r
\r
                Method(_TSS, 0)\r
                {\r
                        Return(\_PR.CPU0._TSS)\r
                }\r
\r
                //\r
                // T-State Dependency\r
                //\r
                Method(_TSD, 0)\r
                {\r
                        //\r
                        // IF four cores are supported/enabled && !(direct access to MSR)\r
                        //    Report 4 processors and SW_ANY as the coordination\r
                        // IF two cores are supported/enabled && !(direct access to MSR)\r
                        //    Report 2 processors and SW_ANY as the coordination type\r
                        //  ELSE\r
                        //    Report 1 processor and SW_ALL as the coordination type (domain 1)\r
                        //\r
                        //  CFGD[23] = Four cores enabled\r
                        //  CFGD[24] = Two or more cores enabled\r
                        //  PDCx[2] = OSPM is capable of direct access to On\r
                        //              Demand throttling MSR\r
                        //\r
\r
                If(LNot(And(PDC0,4)))\r
                {\r
                                Return(Package(){       // SW_ANY\r
                                        Package(){\r
                                                5,                // # entries.\r
                                                0,                // Revision.\r
                                                0,                // Domain #.\r
                                                0xFD,           // Coord Type- SW_ANY\r
                                                MPEN          // # processors.\r
                                        }\r
                                })\r
                }\r
                Return(Package(){               // SW_ALL\r
                        Package(){\r
                                5,                        // # entries.\r
                                0,                        // Revision.\r
                                1,                        // Domain #.\r
                                0xFC,                   // Coord Type- SW_ALL\r
                                1               // # processors.\r
                        }\r
                })\r
                }\r
        }  // End of CPU1\r
\r
        Scope(\_PR.CPU2)\r
        {\r
                Name(_TPC, 0)   // All T-States are available\r
\r
                //\r
                // T-State Control/Status interface\r
                //\r
                Method(_PTC, 0)\r
                {\r
                        Return(\_PR.CPU0._PTC)\r
                }\r
\r
                Method(_TSS, 0)\r
                {\r
                        Return(\_PR.CPU0._TSS)\r
                }\r
\r
                //\r
                // T-State Dependency\r
                //\r
                Method(_TSD, 0)\r
                {\r
                        //\r
                        // IF four cores are supported/enabled && !(direct access to MSR)\r
                        //    Report 4 processors and SW_ANY as the coordination\r
                        // IF two cores are supported/enabled && !(direct access to MSR)\r
                        //    Report 2 processors and SW_ANY as the coordination type\r
                        //  ELSE\r
                        //    Report 1 processor and SW_ALL as the coordination type (domain 1)\r
                        //\r
                        //  CFGD[23] = Four cores enabled\r
                        //  CFGD[24] = Two or more cores enabled\r
                        //  PDCx[2] = OSPM is capable of direct access to On\r
                        //              Demand throttling MSR\r
                        //\r
\r
                If(LNot(And(PDC0,4)))\r
                {\r
                                Return(Package(){       // SW_ANY\r
                                        Package(){\r
                                                5,                // # entries.\r
                                                0,                // Revision.\r
                                                0,                // Domain #.\r
                                                0xFD,           // Coord Type- SW_ANY\r
                                                MPEN          // # processors.\r
                                        }\r
                                })\r
                }\r
                Return(Package(){               // SW_ALL\r
                        Package(){\r
                                5,                        // # entries.\r
                                0,                        // Revision.\r
                                1,                        // Domain #.\r
                                0xFC,                   // Coord Type- SW_ALL\r
                                1                // # processors.\r
                        }\r
                })\r
                }\r
        }  // End of CPU2\r
\r
        Scope(\_PR.CPU3)\r
        {\r
                Name(_TPC, 0)   // All T-States are available\r
\r
                //\r
                // T-State Control/Status interface\r
                //\r
                Method(_PTC, 0)\r
                {\r
                        Return(\_PR.CPU0._PTC)\r
                }\r
\r
                Method(_TSS, 0)\r
                {\r
                        Return(\_PR.CPU0._TSS)\r
                }\r
\r
                //\r
                // T-State Dependency\r
                //\r
                Method(_TSD, 0)\r
                {\r
                        //\r
                        // IF four cores are supported/enabled && !(direct access to MSR)\r
                        //    Report 4 processors and SW_ANY as the coordination\r
                        // IF two cores are supported/enabled && !(direct access to MSR)\r
                        //    Report 2 processors and SW_ANY as the coordination type\r
                        //  ELSE\r
                        //    Report 1 processor and SW_ALL as the coordination type (domain 1)\r
                        //\r
                        //  CFGD[23] = Four cores enabled\r
                        //  CFGD[24] = Two or more cores enabled\r
                        //  PDCx[2] = OSPM is capable of direct access to On\r
                        //              Demand throttling MSR\r
                        //\r
\r
                If(LNot(And(PDC0,4)))\r
                {\r
                                Return(Package(){       // SW_ANY\r
                                        Package(){\r
                                                5,                // # entries.\r
                                                0,                // Revision.\r
                                                0,                // Domain #.\r
                                                0xFD,           // Coord Type- SW_ANY\r
                                                MPEN          // # processors.\r
                                        }\r
                                })\r
                }\r
                Return(Package(){               // SW_ALL\r
                        Package(){\r
                                5,                        // # entries.\r
                                0,                        // Revision.\r
                                1,                        // Domain #.\r
                                0xFC,                   // Coord Type- SW_ALL\r
                                1                // # processors.\r
                        }\r
                })\r
                }\r
        }  // End of CPU3\r
} // End of Definition Block\r
\r
Commit	Line	Data
3cbfba02 DW	1	/*-----------------------------------------------------------------------------\r
	2	-------------------------------------------------------------------------------\r
	3	\r
	4	\r
	5	Intel Platform Processor Power Management BIOS Reference Code\r
	6	\r
	7	Copyright (c) 2007 - 2014, Intel Corporation\r
	8	\r
	9	This program and the accompanying materials are licensed and made available under\r
	10	the terms and conditions of the BSD License that accompanies this distribution.\r
	11	The full text of the license may be found at\r
	12	http://opensource.org/licenses/bsd-license.php.\r
	13	\r
	14	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	15	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	16	\r
	17	\r
	18	Filename: APTST.ASL\r
	19	\r
	20	Revision: Refer to Readme\r
	21	\r
	22	Date: Refer to Readme\r
	23	\r
	24	--------------------------------------------------------------------------------\r
	25	-------------------------------------------------------------------------------\r
	26	\r
	27	This Processor Power Management BIOS Source Code is furnished under license\r
	28	and may only be used or copied in accordance with the terms of the license.\r
	29	The information in this document is furnished for informational use only, is\r
	30	subject to change without notice, and should not be construed as a commitment\r
	31	by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
	32	for any errors or inaccuracies that may appear in this document or any\r
	33	software that may be provided in association with this document.\r
	34	\r
	35	Except as permitted by such license, no part of this document may be\r
	36	reproduced, stored in a retrieval system, or transmitted in any form or by\r
	37	any means without the express written consent of Intel Corporation.\r
	38	\r
	39	WARNING: You are authorized and licensed to install and use this BIOS code\r
	40	ONLY on an IST PC. This utility may damage any system that does not\r
	41	meet these requirements.\r
	42	\r
	43	An IST PC is a computer which\r
	44	(1) Is capable of seamlessly and automatically transitioning among\r
	45	multiple performance states (potentially operating at different\r
	46	efficiency ratings) based upon power source changes, END user\r
	47	preference, processor performance demand, and thermal conditions; and\r
	48	(2) Includes an Intel Pentium II processors, Intel Pentium III\r
	49	processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
	50	Processor-M, Intel Pentium M Processor, or any other future Intel\r
	51	processors that incorporates the capability to transition between\r
	52	different performance states by altering some, or any combination of,\r
	53	the following processor attributes: core voltage, core frequency, bus\r
	54	frequency, number of processor cores available, or any other attribute\r
	55	that changes the efficiency (instructions/unit time-power) at which the\r
	56	processor operates.\r
	57	\r
	58	-------------------------------------------------------------------------------\r
	59	-------------------------------------------------------------------------------\r
	60	\r
	61	NOTES:\r
	62	(1) <TODO> - IF the trap range and port definitions do not match those\r
	63	specified by this reference code, this file must be modified IAW the\r
	64	individual implmentation.\r
65	\r
66	--------------------------------------------------------------------------------\r
67	------------------------------------------------------------------------------*/\r
68	\r
69	\r
70	DefinitionBlock(\r
71	"APTST.aml",\r
72	"SSDT",\r
73	0x01,\r
74	"PmRef",\r
75	"ApTst",\r
76	0x3000\r
77	)\r
78	{\r
79	External(\_PR.CPU1, DeviceObj)\r
80	External(\_PR.CPU2, DeviceObj)\r
81	External(\_PR.CPU3, DeviceObj)\r
82	External(\_PR.CPU0._PTC)\r
83	External(\_PR.CPU0._TSS)\r
84	External(PDC0)\r
85	External(CFGD)\r
86	External(MPEN)\r
87	\r
88	Scope(\_PR.CPU1)\r
89	{\r
90	Name(_TPC, 0) // All T-States are available\r
91	\r
92	//\r
93	// T-State Control/Status interface\r
94	//\r
95	Method(_PTC, 0)\r
96	{\r
97	Return(\_PR.CPU0._PTC)\r
98	}\r
99	\r
100	Method(_TSS, 0)\r
101	{\r
102	Return(\_PR.CPU0._TSS)\r
103	}\r
104	\r
105	//\r
106	// T-State Dependency\r
107	//\r
108	Method(_TSD, 0)\r
109	{\r
110	//\r
111	// IF four cores are supported/enabled && !(direct access to MSR)\r
112	// Report 4 processors and SW_ANY as the coordination\r
113	// IF two cores are supported/enabled && !(direct access to MSR)\r
114	// Report 2 processors and SW_ANY as the coordination type\r
115	// ELSE\r
116	// Report 1 processor and SW_ALL as the coordination type (domain 1)\r
117	//\r
118	// CFGD[23] = Four cores enabled\r
119	// CFGD[24] = Two or more cores enabled\r
120	// PDCx[2] = OSPM is capable of direct access to On\r
121	// Demand throttling MSR\r
122	//\r
123	\r
124	If(LNot(And(PDC0,4)))\r
125	{\r
126	Return(Package(){ // SW_ANY\r
127	Package(){\r
128	5, // # entries.\r
129	0, // Revision.\r
130	0, // Domain #.\r
131	0xFD, // Coord Type- SW_ANY\r
132	MPEN // # processors.\r
133	}\r
134	})\r
135	}\r
136	Return(Package(){ // SW_ALL\r
137	Package(){\r
138	5, // # entries.\r
139	0, // Revision.\r
140	1, // Domain #.\r
141	0xFC, // Coord Type- SW_ALL\r
142	1 // # processors.\r
143	}\r
144	})\r
145	}\r
146	} // End of CPU1\r
147	\r
148	Scope(\_PR.CPU2)\r
149	{\r
150	Name(_TPC, 0) // All T-States are available\r
151	\r
152	//\r
153	// T-State Control/Status interface\r
154	//\r
155	Method(_PTC, 0)\r
156	{\r
157	Return(\_PR.CPU0._PTC)\r
158	}\r
159	\r
160	Method(_TSS, 0)\r
161	{\r
162	Return(\_PR.CPU0._TSS)\r
163	}\r
164	\r
165	//\r
166	// T-State Dependency\r
167	//\r
168	Method(_TSD, 0)\r
169	{\r
170	//\r
171	// IF four cores are supported/enabled && !(direct access to MSR)\r
172	// Report 4 processors and SW_ANY as the coordination\r
173	// IF two cores are supported/enabled && !(direct access to MSR)\r
174	// Report 2 processors and SW_ANY as the coordination type\r
175	// ELSE\r
176	// Report 1 processor and SW_ALL as the coordination type (domain 1)\r
177	//\r
178	// CFGD[23] = Four cores enabled\r
179	// CFGD[24] = Two or more cores enabled\r
180	// PDCx[2] = OSPM is capable of direct access to On\r
181	// Demand throttling MSR\r
182	//\r
183	\r
184	If(LNot(And(PDC0,4)))\r
185	{\r
186	Return(Package(){ // SW_ANY\r
187	Package(){\r
188	5, // # entries.\r
189	0, // Revision.\r
190	0, // Domain #.\r
191	0xFD, // Coord Type- SW_ANY\r
192	MPEN // # processors.\r
193	}\r
194	})\r
195	}\r
196	Return(Package(){ // SW_ALL\r
197	Package(){\r
198	5, // # entries.\r
199	0, // Revision.\r
200	1, // Domain #.\r
201	0xFC, // Coord Type- SW_ALL\r
202	1 // # processors.\r
203	}\r
204	})\r
205	}\r
206	} // End of CPU2\r
207	\r
208	Scope(\_PR.CPU3)\r
209	{\r
210	Name(_TPC, 0) // All T-States are available\r
211	\r
212	//\r
213	// T-State Control/Status interface\r
214	//\r
215	Method(_PTC, 0)\r
216	{\r
217	Return(\_PR.CPU0._PTC)\r
218	}\r
219	\r
220	Method(_TSS, 0)\r
221	{\r
222	Return(\_PR.CPU0._TSS)\r
223	}\r
224	\r
225	//\r
226	// T-State Dependency\r
227	//\r
228	Method(_TSD, 0)\r
229	{\r
230	//\r
231	// IF four cores are supported/enabled && !(direct access to MSR)\r
232	// Report 4 processors and SW_ANY as the coordination\r
233	// IF two cores are supported/enabled && !(direct access to MSR)\r
234	// Report 2 processors and SW_ANY as the coordination type\r
235	// ELSE\r
236	// Report 1 processor and SW_ALL as the coordination type (domain 1)\r
237	//\r
238	// CFGD[23] = Four cores enabled\r
239	// CFGD[24] = Two or more cores enabled\r
240	// PDCx[2] = OSPM is capable of direct access to On\r
241	// Demand throttling MSR\r
242	//\r
243	\r
244	If(LNot(And(PDC0,4)))\r
245	{\r
246	Return(Package(){ // SW_ANY\r
247	Package(){\r
248	5, // # entries.\r
249	0, // Revision.\r
250	0, // Domain #.\r
251	0xFD, // Coord Type- SW_ANY\r
252	MPEN // # processors.\r
253	}\r
254	})\r
255	}\r
256	Return(Package(){ // SW_ALL\r
257	Package(){\r
258	5, // # entries.\r
259	0, // Revision.\r
260	1, // Domain #.\r
261	0xFC, // Coord Type- SW_ALL\r
262	1 // # processors.\r
263	}\r
264	})\r
265	}\r
266	} // End of CPU3\r
267	} // End of Definition Block\r
268	\r