[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / CPU / PowerManagement / AcpiTables / Ssdt / Cpu0Cst.asl

\r
/*-----------------------------------------------------------------------------\r
-------------------------------------------------------------------------------\r
\r
\r
 Intel Silvermont Processor Power Management BIOS Reference Code\r
\r
 Copyright (c) 2006 - 2014, Intel Corporation\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
\r
 Filename:    CPU0CST.ASL\r
\r
 Revision:    Refer to Readme\r
\r
 Date:        Refer to Readme\r
\r
--------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------\r
\r
 This Processor Power Management BIOS Source Code is furnished under license\r
 and may only be used or copied in accordance with the terms of the license.\r
 The information in this document is furnished for informational use only, is\r
 subject to change without notice, and should not be construed as a commitment\r
 by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
 for any errors or inaccuracies that may appear in this document or any\r
 software that may be provided in association with this document.\r
\r
 Except as permitted by such license, no part of this document may be\r
 reproduced, stored in a retrieval system, or transmitted in any form or by\r
 any means without the express written consent of Intel Corporation.\r
\r
 WARNING: You are authorized and licensed to install and use this BIOS code\r
 ONLY on an IST PC. This utility may damage any system that does not\r
 meet these requirements.\r
\r
    An IST PC is a computer which\r
    (1) Is capable of seamlessly and automatically transitioning among\r
    multiple performance states (potentially operating at different\r
    efficiency ratings) based upon power source changes, END user\r
    preference, processor performance demand, and thermal conditions; and\r
    (2) Includes an Intel Pentium II processors, Intel Pentium III\r
    processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
    Processor-M, Intel Pentium M Processor, or any other future Intel\r
    processors that incorporates the capability to transition between\r
    different performance states by altering some, or any combination of,\r
    the following processor attributes: core voltage, core frequency, bus\r
    frequency, number of processor cores available, or any other attribute\r
    that changes the efficiency (instructions/unit time-power) at which the\r
    processor operates.\r
\r
-------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------\r
\r
NOTES:\r
    (1) <TODO> - IF the trap range and port definitions do not match those\r
    specified by this reference code, this file must be modified IAW the\r
    individual implmentation.\r
\r
--------------------------------------------------------------------------------\r
------------------------------------------------------------------------------*/\r
\r
\r
DefinitionBlock (\r
    "CPU0CST.aml",\r
    "SSDT",\r
    1,\r
    "PmRef",\r
    "Cpu0Cst",\r
    0x3001\r
    )\r
{\r
    External(\_PR.CPU0, DeviceObj)\r
    External(PWRS)\r
    External(CFGD)\r
    External(PDC0)\r
\r
    Scope(\_PR.CPU0)\r
    {\r
        OperationRegion (DEB0, SystemIO, 0x80, 1)    //DBG\r
        Field (DEB0, ByteAcc,NoLock,Preserve)        //DBG\r
        { DBG8, 8,}                    //DBG\r
\r
        Method (_CST, 0)\r
        {\r
            Store(0x60,DBG8) //DBG\r
\r
            // IF CMP is supported, but independent C-States beyond C1 are\r
            // not supported; return C1 Halt and rely on BIOS based software\r
            // coordination\r
            //\r
            //   CFGD[24] = CMP support\r
            //   PDCx[4]  = 0 - OS does not support ind. C2/C3 in MP systems\r
            //\r
            // Note:  SMI will be generated when both processor enter the\r
            // Halt state.\r
            //\r
            If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))\r
            {\r
                Store(0x61,DBG8) //DBG\r
                Return(Package() {\r
                    1,\r
                    Package()\r
                    {   // C1 halt, but with BIOS coordination\r
                        ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r
                        1,\r
                        157,\r
                        1000\r
                    }\r
                })\r
            }\r
\r
            // IF MWAIT extensions are supported, use them.\r
            //\r
            //  IF C6 capable/enabled AND Battery\r
            //        Report MWAIT C1, C2, C6 w/ BM_STS avoidance\r
            //  ELSE IF C4 capable/enabled AND Battery\r
            //        Report MWAIT C1, C2, C4 w/ BM_STS avoidance\r
            //  ELSE IF C3 capable/enabled\r
            //      Report MWAIT C1, C2, C3 w/ BM_STS avoidance\r
            //  ELSE IF C2 capable/enabled\r
            //        Report MWAIT C1, C2\r
            //  ELSE\r
            //        Report MWAIT C1\r
            //\r
            //   CFGD[21] = 1 - MWAIT extensions supported\r
            //   CFGD[13] = 1 - C7  Capable/Enabled\r
            //   CFGD[12] = 1 - C6S Capable/Enabled\r
            //   CFGD[11] = 1 - C6  Capable/Enabled\r
            //   CFGD[7]  = 1 - C4  Capable/Enabled\r
            //   CFGD[5]  = 1 - C3  Capable/Enabled\r
            //   PDCx[9]  = 1 - OS  supports MWAIT extensions\r
            //   PDCx[8]  = 1 - OS  supports MWAIT for C1\r
            //            (Inferred from PDCx[9] = 1.)\r
            //   PDCx[4]  = 1 - OS supports independent C2/C3 in MP systems\r
            //    or\r
            //   NOT CMP  (Inferred from previous check.)\r
            //\r
            If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))\r
            {\r
                //\r
                // <TODO> The implementor may wish to only report C1-C2\r
                // when on AC power.  In this case, the IF clause below can\r
                // be modified to something like:\r
                //\r
                // "If(LAnd(And(CFGD,0x200), LNot(PWRS)))"\r
                //\r
                // Which uses the power state of the system (PWRS) to\r
                // determine whether to allow deepers states.\r
                //\r
                //   IF C7 supported AND on battery\r
                //    report MWAIT C1, C6, C7\r
                //\r
                //   CFGD[13] = C7  Capable/Enabled\r
                //   CFGD[11] = C6  Capable/Enabled\r
                //\r
              If(LAnd(And(CFGD,0x2000),And(CFGD,0x40000000)))\r
                {\r
                    Store(0x77,DBG8) //DBG\r
                    Return( Package()\r
                    {\r
                        3,\r
                        Package()\r
                        {   // C1, MWAIT\r
                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
                            1,\r
                            1,\r
                            1000\r
                        },\r
                        Package()\r
                        {\r
                            // C6, MWAIT Extension with Incremental L2 Shrink\r
                            // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
                            // C6, MWAIT Extension with No L2 Shrink\r
                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
                            2,\r
                            500,\r
                            10\r
                        },\r
                        Package()\r
                        {\r
                            // C7, MWAIT Extension with Full L2 Shrink\r
                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x64, 1)},\r
                            3,\r
                            1500,   //PnP setting, 1.5 ms for worst-case exit latency\r
                            10\r
                        }\r
                    })\r
                }\r
\r
\r
             If(LAnd(And(CFGD,0x2000),LNot(And(CFGD,0x40000000))))\r
                {\r
                    Store(0x67,DBG8) //DBG\r
                    Return( Package()\r
                    {\r
                        3,\r
                        Package()\r
                        {   // C1, MWAIT\r
                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
                            1,\r
                            1,\r
                            1000\r
                        },\r
                        Package()\r
                        {\r
                            // C6, MWAIT Extension with Incremental L2 Shrink\r
                            // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
                            // C6 = C6NS, MWAIT Extension with No L2 Shrink\r
                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
                            2,\r
                            500,\r
                            10\r
                        },\r
                        Package()\r
                        {\r
\r
                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x52, 1)},\r
                            3,\r
                            1500,   //PnP setting, 1.5 ms for worst-case exit latency\r
                            10\r
                        }\r
                    })\r
                }\r
\r
                If(And(CFGD,0x800)) // Setup Max C-State = C6\r
                {\r
                    Store(0x76,DBG8) //DBG\r
                    Return( Package()\r
                    {\r
                        2,\r
                        Package()\r
                        {   // C1, MWAIT\r
                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
                            1,\r
                            1,\r
                            1000\r
                        },\r
                        Package()\r
                        {\r
                            // C6, MWAIT Extension with Incremental L2 Shrink\r
                            // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
                            // C6, MWAIT Extension with No L2 Shrink\r
                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
                            2,\r
                            500,\r
                            10\r
                        }\r
                    })\r
                }\r
                //\r
                // IF no deeper C-States are supported; report MWAIT C1.\r
                //\r
                Store(0x71,DBG8) //DBG\r
                Return(Package()\r
                {\r
                    1,\r
                    Package()\r
                    {   // C1, MWAIT\r
                        ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
                        1,\r
                        1,\r
                        1000\r
                    }\r
                })\r
            }\r
\r
\r
        }\r
    }\r
}\r
\r
\r
Commit	Line	Data
3cbfba02 DW	1	\r
	2	/*-----------------------------------------------------------------------------\r
	3	-------------------------------------------------------------------------------\r
	4	\r
	5	\r
	6	Intel Silvermont Processor Power Management BIOS Reference Code\r
	7	\r
	8	Copyright (c) 2006 - 2014, Intel Corporation\r
	9	\r
7ede8060	10	SPDX-License-Identifier: BSD-2-Clause-Patent\r
3cbfba02 DW	11	\r
	12	\r
	13	Filename: CPU0CST.ASL\r
	14	\r
	15	Revision: Refer to Readme\r
	16	\r
	17	Date: Refer to Readme\r
	18	\r
	19	--------------------------------------------------------------------------------\r
	20	-------------------------------------------------------------------------------\r
	21	\r
	22	This Processor Power Management BIOS Source Code is furnished under license\r
	23	and may only be used or copied in accordance with the terms of the license.\r
	24	The information in this document is furnished for informational use only, is\r
	25	subject to change without notice, and should not be construed as a commitment\r
	26	by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
	27	for any errors or inaccuracies that may appear in this document or any\r
	28	software that may be provided in association with this document.\r
	29	\r
	30	Except as permitted by such license, no part of this document may be\r
	31	reproduced, stored in a retrieval system, or transmitted in any form or by\r
	32	any means without the express written consent of Intel Corporation.\r
	33	\r
	34	WARNING: You are authorized and licensed to install and use this BIOS code\r
	35	ONLY on an IST PC. This utility may damage any system that does not\r
	36	meet these requirements.\r
	37	\r
	38	An IST PC is a computer which\r
	39	(1) Is capable of seamlessly and automatically transitioning among\r
	40	multiple performance states (potentially operating at different\r
	41	efficiency ratings) based upon power source changes, END user\r
	42	preference, processor performance demand, and thermal conditions; and\r
	43	(2) Includes an Intel Pentium II processors, Intel Pentium III\r
	44	processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
	45	Processor-M, Intel Pentium M Processor, or any other future Intel\r
	46	processors that incorporates the capability to transition between\r
	47	different performance states by altering some, or any combination of,\r
	48	the following processor attributes: core voltage, core frequency, bus\r
	49	frequency, number of processor cores available, or any other attribute\r
	50	that changes the efficiency (instructions/unit time-power) at which the\r
	51	processor operates.\r
	52	\r
	53	-------------------------------------------------------------------------------\r
	54	-------------------------------------------------------------------------------\r
	55	\r
	56	NOTES:\r
	57	(1) <TODO> - IF the trap range and port definitions do not match those\r
	58	specified by this reference code, this file must be modified IAW the\r
	59	individual implmentation.\r
	60	\r
	61	--------------------------------------------------------------------------------\r
	62	------------------------------------------------------------------------------*/\r
	63	\r
	64	\r
	65	DefinitionBlock (\r
	66	"CPU0CST.aml",\r
	67	"SSDT",\r
	68	1,\r
	69	"PmRef",\r
	70	"Cpu0Cst",\r
	71	0x3001\r
	72	)\r
	73	{\r
	74	External(\_PR.CPU0, DeviceObj)\r
75	External(PWRS)\r
76	External(CFGD)\r
77	External(PDC0)\r
78	\r
79	Scope(\_PR.CPU0)\r
80	{\r
81	OperationRegion (DEB0, SystemIO, 0x80, 1) //DBG\r
82	Field (DEB0, ByteAcc,NoLock,Preserve) //DBG\r
83	{ DBG8, 8,} //DBG\r
84	\r
85	Method (_CST, 0)\r
86	{\r
87	Store(0x60,DBG8) //DBG\r
88	\r
89	// IF CMP is supported, but independent C-States beyond C1 are\r
90	// not supported; return C1 Halt and rely on BIOS based software\r
91	// coordination\r
92	//\r
93	// CFGD[24] = CMP support\r
94	// PDCx[4] = 0 - OS does not support ind. C2/C3 in MP systems\r
95	//\r
96	// Note: SMI will be generated when both processor enter the\r
97	// Halt state.\r
98	//\r
99	If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))\r
100	{\r
101	Store(0x61,DBG8) //DBG\r
102	Return(Package() {\r
103	1,\r
104	Package()\r
105	{ // C1 halt, but with BIOS coordination\r
106	ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r
107	1,\r
108	157,\r
109	1000\r
110	}\r
111	})\r
112	}\r
113	\r
114	// IF MWAIT extensions are supported, use them.\r
115	//\r
116	// IF C6 capable/enabled AND Battery\r
117	// Report MWAIT C1, C2, C6 w/ BM_STS avoidance\r
118	// ELSE IF C4 capable/enabled AND Battery\r
119	// Report MWAIT C1, C2, C4 w/ BM_STS avoidance\r
120	// ELSE IF C3 capable/enabled\r
121	// Report MWAIT C1, C2, C3 w/ BM_STS avoidance\r
122	// ELSE IF C2 capable/enabled\r
123	// Report MWAIT C1, C2\r
124	// ELSE\r
125	// Report MWAIT C1\r
126	//\r
127	// CFGD[21] = 1 - MWAIT extensions supported\r
128	// CFGD[13] = 1 - C7 Capable/Enabled\r
129	// CFGD[12] = 1 - C6S Capable/Enabled\r
130	// CFGD[11] = 1 - C6 Capable/Enabled\r
131	// CFGD[7] = 1 - C4 Capable/Enabled\r
132	// CFGD[5] = 1 - C3 Capable/Enabled\r
133	// PDCx[9] = 1 - OS supports MWAIT extensions\r
134	// PDCx[8] = 1 - OS supports MWAIT for C1\r
135	// (Inferred from PDCx[9] = 1.)\r
136	// PDCx[4] = 1 - OS supports independent C2/C3 in MP systems\r
137	// or\r
138	// NOT CMP (Inferred from previous check.)\r
139	//\r
140	If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))\r
141	{\r
142	//\r
143	// <TODO> The implementor may wish to only report C1-C2\r
144	// when on AC power. In this case, the IF clause below can\r
145	// be modified to something like:\r
146	//\r
147	// "If(LAnd(And(CFGD,0x200), LNot(PWRS)))"\r
148	//\r
149	// Which uses the power state of the system (PWRS) to\r
150	// determine whether to allow deepers states.\r
151	//\r
152	// IF C7 supported AND on battery\r
153	// report MWAIT C1, C6, C7\r
154	//\r
155	// CFGD[13] = C7 Capable/Enabled\r
156	// CFGD[11] = C6 Capable/Enabled\r
157	//\r
158	If(LAnd(And(CFGD,0x2000),And(CFGD,0x40000000)))\r
159	{\r
160	Store(0x77,DBG8) //DBG\r
161	Return( Package()\r
162	{\r
163	3,\r
164	Package()\r
165	{ // C1, MWAIT\r
166	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
167	1,\r
168	1,\r
169	1000\r
170	},\r
171	Package()\r
172	{\r
173	// C6, MWAIT Extension with Incremental L2 Shrink\r
174	// ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
175	// C6, MWAIT Extension with No L2 Shrink\r
176	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
177	2,\r
178	500,\r
179	10\r
180	},\r
181	Package()\r
182	{\r
183	// C7, MWAIT Extension with Full L2 Shrink\r
184	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x64, 1)},\r
185	3,\r
186	1500, //PnP setting, 1.5 ms for worst-case exit latency\r
187	10\r
188	}\r
189	})\r
190	}\r
191	\r
192	\r
193	If(LAnd(And(CFGD,0x2000),LNot(And(CFGD,0x40000000))))\r
194	{\r
195	Store(0x67,DBG8) //DBG\r
196	Return( Package()\r
197	{\r
198	3,\r
199	Package()\r
200	{ // C1, MWAIT\r
201	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
202	1,\r
203	1,\r
204	1000\r
205	},\r
206	Package()\r
207	{\r
208	// C6, MWAIT Extension with Incremental L2 Shrink\r
209	// ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
210	// C6 = C6NS, MWAIT Extension with No L2 Shrink\r
211	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
212	2,\r
213	500,\r
214	10\r
215	},\r
216	Package()\r
217	{\r
218	\r
219	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x52, 1)},\r
220	3,\r
221	1500, //PnP setting, 1.5 ms for worst-case exit latency\r
222	10\r
223	}\r
224	})\r
225	}\r
226	\r
227	If(And(CFGD,0x800)) // Setup Max C-State = C6\r
228	{\r
229	Store(0x76,DBG8) //DBG\r
230	Return( Package()\r
231	{\r
232	2,\r
233	Package()\r
234	{ // C1, MWAIT\r
235	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
236	1,\r
237	1,\r
238	1000\r
239	},\r
240	Package()\r
241	{\r
242	// C6, MWAIT Extension with Incremental L2 Shrink\r
243	// ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
244	// C6, MWAIT Extension with No L2 Shrink\r
245	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
246	2,\r
247	500,\r
248	10\r
249	}\r
250	})\r
251	}\r
252	//\r
253	// IF no deeper C-States are supported; report MWAIT C1.\r
254	//\r
255	Store(0x71,DBG8) //DBG\r
256	Return(Package()\r
257	{\r
258	1,\r
259	Package()\r
260	{ // C1, MWAIT\r
261	ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
262	1,\r
263	1,\r
264	1000\r
265	}\r
266	})\r
267	}\r
268	\r
269	\r
270	}\r
271	}\r
272	}\r
273	\r
274	\r