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1 | /*++\r |
2 | \r | |
3 | Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r | |
4 | \r | |
5 | This program and the accompanying materials are licensed and made available under\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution.\r | |
7 | The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php.\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | \r | |
14 | --*/\r | |
15 | \r | |
16 | \r | |
17 | /*++\r | |
18 | \r | |
19 | Module Name:\r | |
20 | \r | |
21 | MMC.h\r | |
22 | \r | |
23 | Abstract:\r | |
24 | \r | |
25 | Header file for Industry MMC 4.2 spec.\r | |
26 | \r | |
27 | --*/\r | |
28 | \r | |
29 | #ifndef _MMC_H\r | |
30 | #define _MMC_H\r | |
31 | \r | |
32 | #pragma pack(1)\r | |
33 | //\r | |
34 | //Command definition\r | |
35 | //\r | |
36 | \r | |
37 | #define CMD0 0\r | |
38 | #define CMD1 1\r | |
39 | #define CMD2 2\r | |
40 | #define CMD3 3\r | |
41 | #define CMD4 4\r | |
42 | #define CMD6 6\r | |
43 | #define CMD7 7\r | |
44 | #define CMD8 8\r | |
45 | #define CMD9 9\r | |
46 | #define CMD10 10\r | |
47 | #define CMD11 11\r | |
48 | #define CMD12 12\r | |
49 | #define CMD13 13\r | |
50 | #define CMD14 14\r | |
51 | #define CMD15 15\r | |
52 | #define CMD16 16\r | |
53 | #define CMD17 17\r | |
54 | #define CMD18 18\r | |
55 | #define CMD19 19\r | |
56 | #define CMD20 20\r | |
57 | #define CMD23 23\r | |
58 | #define CMD24 24\r | |
59 | #define CMD25 25\r | |
60 | #define CMD26 26\r | |
61 | #define CMD27 27\r | |
62 | #define CMD28 28\r | |
63 | #define CMD29 29\r | |
64 | #define CMD30 30\r | |
65 | #define CMD35 35\r | |
66 | #define CMD36 36\r | |
67 | #define CMD38 38\r | |
68 | #define CMD39 39\r | |
69 | #define CMD40 40\r | |
70 | #define CMD42 42\r | |
71 | #define CMD55 55\r | |
72 | #define CMD56 56\r | |
73 | \r | |
74 | \r | |
75 | \r | |
76 | #define GO_IDLE_STATE CMD0\r | |
77 | #define SEND_OP_COND CMD1\r | |
78 | #define ALL_SEND_CID CMD2\r | |
79 | #define SET_RELATIVE_ADDR CMD3\r | |
80 | #define SET_DSR CMD4\r | |
81 | #define SWITCH CMD6\r | |
82 | #define SELECT_DESELECT_CARD CMD7\r | |
83 | #define SEND_EXT_CSD CMD8\r | |
84 | #define SEND_CSD CMD9\r | |
85 | #define SEND_CID CMD10\r | |
86 | #define READ_DAT_UNTIL_STOP CMD11\r | |
87 | #define STOP_TRANSMISSION CMD12\r | |
88 | #define SEND_STATUS CMD13\r | |
89 | #define BUSTEST_R CMD14\r | |
90 | #define GO_INACTIVE_STATE CMD15\r | |
91 | #define SET_BLOCKLEN CMD16\r | |
92 | #define READ_SINGLE_BLOCK CMD17\r | |
93 | #define READ_MULTIPLE_BLOCK CMD18\r | |
94 | #define BUSTEST_W CMD19\r | |
95 | #define WRITE_DAT_UNTIL_STOP CMD20\r | |
96 | #define SET_BLOCK_COUNT CMD23\r | |
97 | #define WRITE_BLOCK CMD24\r | |
98 | #define WRITE_MULTIPLE_BLOCK CMD25\r | |
99 | #define PROGRAM_CID CMD26\r | |
100 | #define PROGRAM_CSD CMD27\r | |
101 | #define SET_WRITE_PROT CMD28\r | |
102 | #define CLR_WRITE_PROT CMD29\r | |
103 | #define SEND_WRITE_PROT CMD30\r | |
104 | #define ERASE_GROUP_START CMD35\r | |
105 | #define ERASE_GROUP_END CMD36\r | |
106 | #define ERASE CMD38\r | |
107 | #define FAST_IO CMD39\r | |
108 | #define GO_IRQ_STATE CMD40\r | |
109 | #define LOCK_UNLOCK CMD42\r | |
110 | #define APP_CMD CMD55\r | |
111 | #define GEN_CMD CMD56\r | |
112 | \r | |
113 | #define B_PERM_WP_DIS 0x10\r | |
114 | #define B_PWR_WP_EN 0x01\r | |
115 | #define US_PERM_WP_DIS 0x10\r | |
116 | #define US_PWR_WP_EN 0x01\r | |
117 | \r | |
118 | #define FREQUENCY_OD (400 * 1000)\r | |
119 | #define FREQUENCY_MMC_PP (26 * 1000 * 1000)\r | |
120 | #define FREQUENCY_MMC_PP_HIGH (52 * 1000 * 1000)\r | |
121 | \r | |
122 | #define DEFAULT_DSR_VALUE 0x404\r | |
123 | \r | |
124 | //\r | |
125 | //Registers definition\r | |
126 | //\r | |
127 | \r | |
128 | typedef struct {\r | |
129 | UINT32 Reserved0: 7; // 0\r | |
130 | UINT32 V170_V195: 1; // 1.70V - 1.95V\r | |
131 | UINT32 V200_V260: 7; // 2.00V - 2.60V\r | |
132 | UINT32 V270_V360: 9; // 2.70V - 3.60V\r | |
133 | UINT32 Reserved1: 5; // 0\r | |
134 | UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)\r | |
135 | UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine\r | |
136 | } OCR;\r | |
137 | \r | |
138 | \r | |
139 | typedef struct {\r | |
140 | UINT8 NotUsed: 1; // 1\r | |
141 | UINT8 CRC: 7; // CRC7 checksum\r | |
142 | UINT8 MDT; // Manufacturing date\r | |
143 | UINT32 PSN; // Product serial number\r | |
144 | UINT8 PRV; // Product revision\r | |
145 | UINT8 PNM[6]; // Product name\r | |
146 | UINT16 OID; // OEM/Application ID\r | |
147 | UINT8 MID; // Manufacturer ID\r | |
148 | } CID;\r | |
149 | \r | |
150 | \r | |
151 | typedef struct {\r | |
152 | UINT8 NotUsed: 1; // 1 [0:0]\r | |
153 | UINT8 CRC: 7; // CRC [7:1]\r | |
154 | UINT8 ECC: 2; // ECC code [9:8]\r | |
155 | UINT8 FILE_FORMAT: 2; // File format [11:10]\r | |
156 | UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]\r | |
157 | UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]\r | |
158 | UINT8 COPY: 1; // Copy flag (OTP) [14:14]\r | |
159 | UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]\r | |
160 | UINT16 CONTENT_PROT_APP: 1; // Content protection application [16:16]\r | |
161 | UINT16 Reserved0: 4; // 0 [20:17]\r | |
162 | UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]\r | |
163 | UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]\r | |
164 | UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]\r | |
165 | UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29]\r | |
166 | UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]\r | |
167 | UINT32 WP_GRP_SIZE: 5; // Write protect group size [36:32]\r | |
168 | UINT32 ERASE_GRP_MULT: 5; // Erase group size multiplier [41:37]\r | |
169 | UINT32 ERASE_GRP_SIZE: 5; // Erase group size [46:42]\r | |
170 | UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]\r | |
171 | UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]\r | |
172 | UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]\r | |
173 | UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]\r | |
174 | UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]\r | |
175 | UINT32 C_SIZELow2: 2;// Device size [73:62]\r | |
176 | UINT32 C_SIZEHigh10: 10;// Device size [73:62]\r | |
177 | UINT32 Reserved1: 2; // 0 [75:74]\r | |
178 | UINT32 DSR_IMP: 1; // DSR implemented [76:76]\r | |
179 | UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]\r | |
180 | UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]\r | |
181 | UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]\r | |
182 | UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]\r | |
183 | UINT32 CCC: 12;// Card command classes [95:84]\r | |
184 | UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]\r | |
185 | UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r | |
186 | UINT8 TAAC ; // Data read access-time 1 [119:112]\r | |
187 | UINT8 Reserved2: 2; // 0 [121:120]\r | |
188 | UINT8 SPEC_VERS: 4; // System specification version [125:122]\r | |
189 | UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]\r | |
190 | } CSD;\r | |
191 | \r | |
192 | typedef struct {\r | |
193 | UINT8 Reserved133_0[134]; // [133:0] 0\r | |
194 | UINT8 SEC_BAD_BLOCK_MGMNT; // [134] Bad Block Management mode\r | |
195 | UINT8 Reserved135; // [135] 0\r | |
196 | UINT8 ENH_START_ADDR[4]; // [139:136] Enhanced User Data Start Address\r | |
197 | UINT8 ENH_SIZE_MULT[3]; // [142:140] Enhanced User Data Start Size\r | |
198 | UINT8 GP_SIZE_MULT_1[3]; // [145:143] GPP1 Size\r | |
199 | UINT8 GP_SIZE_MULT_2[3]; // [148:146] GPP2 Size\r | |
200 | UINT8 GP_SIZE_MULT_3[3]; // [151:149] GPP3 Size\r | |
201 | UINT8 GP_SIZE_MULT_4[3]; // [154:152] GPP4 Size\r | |
202 | UINT8 PARTITION_SETTING_COMPLETED; // [155] Partitioning Setting\r | |
203 | UINT8 PARTITIONS_ATTRIBUTES; // [156] Partitions attributes\r | |
204 | UINT8 MAX_ENH_SIZE_MULT[3]; // [159:157] GPP4 Start Size\r | |
205 | UINT8 PARTITIONING_SUPPORT; // [160] Partitioning Support\r | |
206 | UINT8 HPI_MGMT; // [161] HPI management\r | |
207 | UINT8 RST_n_FUNCTION; // [162] H/W reset function\r | |
208 | UINT8 BKOPS_EN; // [163] Enable background operations handshake\r | |
209 | UINT8 BKOPS_START; // [164] Manually start background operations\r | |
210 | UINT8 Reserved165; // [165] 0\r | |
211 | UINT8 WR_REL_PARAM; // [166] Write reliability parameter register\r | |
212 | UINT8 WR_REL_SET; // [167] Write reliability setting register\r | |
213 | UINT8 RPMB_SIZE_MULT; // [168] RPMB Size\r | |
214 | UINT8 FW_CONFIG; // [169] FW configuration\r | |
215 | UINT8 Reserved170; // [170] 0\r | |
216 | UINT8 USER_WP; // [171] User area write protection\r | |
217 | UINT8 Reserved172; // [172] 0\r | |
218 | UINT8 BOOT_WP; // [173] Boot area write protection\r | |
219 | UINT8 Reserved174; // [174] 0\r | |
220 | UINT8 ERASE_GROUP_DEF; // [175] High density erase group definition\r | |
221 | UINT8 Reserved176; // [176] 0\r | |
222 | UINT8 BOOT_BUS_WIDTH; // [177] Boot bus width\r | |
223 | UINT8 BOOT_CONFIG_PROT; // [178] Boot config protection\r | |
224 | UINT8 PARTITION_CONFIG; // [179] Partition config\r | |
225 | UINT8 Reserved180; // [180] 0\r | |
226 | UINT8 ERASED_MEM_CONT; // [181] Erased Memory Content\r | |
227 | UINT8 Reserved182; // [182] 0\r | |
228 | UINT8 BUS_WIDTH; // [183] Bus Width Mode\r | |
229 | UINT8 Reserved184; // [184] 0\r | |
230 | UINT8 HS_TIMING; // [185] High Speed Interface Timing\r | |
231 | UINT8 Reserved186; // [186] 0\r | |
232 | UINT8 POWER_CLASS; // [187] Power Class\r | |
233 | UINT8 Reserved188; // [188] 0\r | |
234 | UINT8 CMD_SET_REV; // [189] Command Set Revision\r | |
235 | UINT8 Reserved190; // [190] 0\r | |
236 | UINT8 CMD_SET; // [191] Command Set\r | |
237 | UINT8 EXT_CSD_REV; // [192] Extended CSD Revision\r | |
238 | UINT8 Reserved193; // [193] 0\r | |
239 | UINT8 CSD_STRUCTURE; // [194] CSD Structure Version\r | |
240 | UINT8 Reserved195; // [195] 0\r | |
241 | UINT8 CARD_TYPE; // [196] Card Type\r | |
242 | UINT8 Reserved197; // [197] 0\r | |
243 | UINT8 OUT_OF_INTERRUPT_TIME; // [198] Out-of-interrupt busy timing\r | |
244 | UINT8 PARTITION_SWITCH_TIME; // [199] Partition switching timing\r | |
245 | UINT8 PWR_CL_52_195; // [200] Power Class for 52MHz @ 1.95V\r | |
246 | UINT8 PWR_CL_26_195; // [201] Power Class for 26MHz @ 1.95V\r | |
247 | UINT8 PWR_CL_52_360; // [202] Power Class for 52MHz @ 3.6V\r | |
248 | UINT8 PWR_CL_26_360; // [203] Power Class for 26MHz @ 3.6V\r | |
249 | UINT8 Reserved204; // [204] 0\r | |
250 | UINT8 MIN_PERF_R_4_26; // [205] Minimum Read Performance for 4bit @26MHz\r | |
251 | UINT8 MIN_PERF_W_4_26; // [206] Minimum Write Performance for 4bit @26MHz\r | |
252 | UINT8 MIN_PERF_R_8_26_4_52; // [207] Minimum Read Performance for 8bit @26MHz/4bit @52MHz\r | |
253 | UINT8 MIN_PERF_W_8_26_4_52; // [208] Minimum Write Performance for 8bit @26MHz/4bit @52MHz\r | |
254 | UINT8 MIN_PERF_R_8_52; // [209] Minimum Read Performance for 8bit @52MHz\r | |
255 | UINT8 MIN_PERF_W_8_52; // [210] Minimum Write Performance for 8bit @52MHz\r | |
256 | UINT8 Reserved211; // [211] 0\r | |
257 | UINT8 SEC_COUNT[4]; // [215:212] Sector Count\r | |
258 | UINT8 Reserved216; // [216] 0\r | |
259 | UINT8 S_A_TIMEOUT; // [217] Sleep/awake timeout\r | |
260 | UINT8 Reserved218; // [218] 0\r | |
261 | UINT8 S_C_VCCQ; // [219] Sleep current (VCCQ)\r | |
262 | UINT8 S_C_VCC; // [220] Sleep current (VCC)\r | |
263 | UINT8 HC_WP_GRP_SIZE; // [221] High-capacity write protect group size\r | |
264 | UINT8 REL_WR_SEC_C; // [222] Reliable write sector count\r | |
265 | UINT8 ERASE_TIMEOUT_MULT; // [223] High-capacity erase timeout\r | |
266 | UINT8 HC_ERASE_GRP_SIZE; // [224] High-capacity erase unit size\r | |
267 | UINT8 ACC_SIZE; // [225] Access size\r | |
268 | UINT8 BOOT_SIZE_MULTI; // [226] Boot partition size\r | |
269 | UINT8 Reserved227; // [227] 0\r | |
270 | UINT8 BOOT_INFO; // [228] Boot information\r | |
271 | UINT8 SEC_TRIM_MULT; // [229] Secure TRIM Multiplier\r | |
272 | UINT8 SEC_ERASE_MULT; // [230] Secure Erase Multiplier\r | |
273 | UINT8 SEC_FEATURE_SUPPORT; // [231] Secure Feature support\r | |
274 | UINT8 TRIM_MULT; // [232] TRIM Multiplier\r | |
275 | UINT8 Reserved233; // [233] 0\r | |
276 | UINT8 MIN_PERF_DDR_R_8_52; // [234] Min Read Performance for 8-bit @ 52MHz\r | |
277 | UINT8 MIN_PERF_DDR_W_8_52; // [235] Min Write Performance for 8-bit @ 52MHz\r | |
278 | UINT8 Reserved237_236[2]; // [237:236] 0\r | |
279 | UINT8 PWR_CL_DDR_52_195; // [238] Power class for 52MHz, DDR at 1.95V\r | |
280 | UINT8 PWR_CL_DDR_52_360; // [239] Power class for 52MHz, DDR at 3.6V\r | |
281 | UINT8 Reserved240; // [240] 0\r | |
282 | UINT8 INI_TIMEOUT_AP; // [241] 1st initialization time after partitioning\r | |
283 | UINT8 CORRECTLY_PRG_SECTORS_NUM[4]; // [245:242] Number of correctly programmed sectors\r | |
284 | UINT8 BKOPS_STATUS; // [246] Background operations status\r | |
285 | UINT8 Reserved501_247[255]; // [501:247] 0\r | |
286 | UINT8 BKOPS_SUPPORT; // [502] Background operations support\r | |
287 | UINT8 HPI_FEATURES; // [503] HPI features\r | |
288 | UINT8 S_CMD_SET; // [504] Sector Count\r | |
289 | UINT8 Reserved511_505[7]; // [511:505] Sector Count\r | |
290 | } EXT_CSD;\r | |
291 | \r | |
292 | \r | |
293 | //\r | |
294 | //Card Status definition\r | |
295 | //\r | |
296 | typedef struct {\r | |
297 | UINT32 Reserved0: 2; //Reserved for Manufacturer Test Mode\r | |
298 | UINT32 Reserved1: 2; //Reserved for Application Specific commands\r | |
299 | UINT32 Reserved2: 1; //\r | |
300 | UINT32 SAPP_CMD: 1; //\r | |
301 | UINT32 Reserved3: 1; //Reserved\r | |
302 | UINT32 SWITCH_ERROR: 1; //\r | |
303 | UINT32 READY_FOR_DATA: 1; //\r | |
304 | UINT32 CURRENT_STATE: 4; //\r | |
305 | UINT32 ERASE_RESET: 1; //\r | |
306 | UINT32 Reserved4: 1; //Reserved\r | |
307 | UINT32 WP_ERASE_SKIP: 1; //\r | |
308 | UINT32 CID_CSD_OVERWRITE: 1; //\r | |
309 | UINT32 OVERRUN: 1; //\r | |
310 | UINT32 UNDERRUN: 1; //\r | |
311 | UINT32 ERROR: 1; //\r | |
312 | UINT32 CC_ERROR: 1; //\r | |
313 | UINT32 CARD_ECC_FAILED: 1; //\r | |
314 | UINT32 ILLEGAL_COMMAND: 1; //\r | |
315 | UINT32 COM_CRC_ERROR: 1; //\r | |
316 | UINT32 LOCK_UNLOCK_FAILED: 1; //\r | |
317 | UINT32 CARD_IS_LOCKED: 1; //\r | |
318 | UINT32 WP_VIOLATION: 1; //\r | |
319 | UINT32 ERASE_PARAM: 1; //\r | |
320 | UINT32 ERASE_SEQ_ERROR: 1; //\r | |
321 | UINT32 BLOCK_LEN_ERROR: 1; //\r | |
322 | UINT32 ADDRESS_MISALIGN: 1; //\r | |
323 | UINT32 ADDRESS_OUT_OF_RANGE:1; //\r | |
324 | } CARD_STATUS;\r | |
325 | \r | |
326 | typedef struct {\r | |
327 | UINT32 CmdSet: 3;\r | |
328 | UINT32 Reserved0: 5;\r | |
329 | UINT32 Value: 8;\r | |
330 | UINT32 Index: 8;\r | |
331 | UINT32 Access: 2;\r | |
332 | UINT32 Reserved1: 6;\r | |
333 | } SWITCH_ARGUMENT;\r | |
334 | \r | |
335 | #define CommandSet_Mode 0\r | |
336 | #define SetBits_Mode 1\r | |
337 | #define ClearBits_Mode 2\r | |
338 | #define WriteByte_Mode 3\r | |
339 | \r | |
340 | \r | |
341 | #define Idle_STATE 0\r | |
342 | #define Ready_STATE 1\r | |
343 | #define Ident_STATE 2\r | |
344 | #define Stby_STATE 3\r | |
345 | #define Tran_STATE 4\r | |
346 | #define Data_STATE 5\r | |
347 | #define Rcv_STATE 6\r | |
348 | #define Prg_STATE 7\r | |
349 | #define Dis_STATE 8\r | |
350 | #define Btst_STATE 9\r | |
351 | \r | |
352 | \r | |
353 | \r | |
354 | #pragma pack()\r | |
355 | #endif\r |