Vlv2DeviceRefCodePkg/ValleyView2Soc: Remove the unused code
[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / SouthCluster / Include / Library / I2CLib.h
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1/*++\r
2\r
3Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
4\r
5 This program and the accompanying materials are licensed and made available under\r
6 the terms and conditions of the BSD License that accompanies this distribution.\r
7 The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php.\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13\r
14\r
15Module Name:\r
16\r
17 I2CRegs.h\r
18\r
19Abstract:\r
20\r
21 Register Definitions for I2C Driver/PEIM.\r
22\r
23--*/\r
24#include <Uefi.h>\r
25#include <Library/IoLib.h>\r
26\r
27#ifndef I2C_REGS_A0_H\r
28#define I2C_REGS_A0_H\r
29\r
30//\r
31// FIFO write workaround value.\r
32//\r
33#define FIFO_WRITE_DELAY 2\r
34\r
35//\r
36// MMIO Register Definitions\r
37//\r
38#define R_IC_CON ( 0x00) // I2C Control\r
39#define B_IC_RESTART_EN BIT5\r
40#define B_IC_SLAVE_DISABLE BIT6\r
41#define V_SPEED_STANDARD 0x02\r
42#define V_SPEED_FAST 0x04\r
43#define V_SPEED_HIGH 0x06\r
44#define B_MASTER_MODE BIT0\r
45\r
46#define R_IC_TAR ( 0x04) // I2C Target Address\r
47#define IC_TAR_10BITADDR_MASTER BIT12\r
48\r
49#define R_IC_SAR ( 0x08) // I2C Slave Address\r
50#define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code Address\r
51#define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and Command\r
52\r
53#define B_READ_CMD BIT8 // 1 = read, 0 = write\r
54#define B_CMD_STOP BIT9 // 1 = STOP\r
55#define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN\r
56\r
57#define V_WRITE_CMD_MASK ( 0xFF)\r
58\r
59#define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock SCL High Count\r
60#define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock SCL Low Count\r
61#define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL High Count\r
62#define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL Low Count\r
63#define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL High Count\r
64#define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL Low Count\r
65#define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status\r
66#define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask\r
67#define I2C_INTR_GEN_CALL BIT11 // General call received\r
68#define I2C_INTR_START_DET BIT10\r
69#define I2C_INTR_STOP_DET BIT9\r
70#define I2C_INTR_ACTIVITY BIT8\r
71#define I2C_INTR_TX_ABRT BIT6 // Set on NACK\r
72#define I2C_INTR_TX_EMPTY BIT4\r
73#define I2C_INTR_TX_OVER BIT3\r
74#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold\r
75#define I2C_INTR_RX_OVER BIT1\r
76#define I2C_INTR_RX_UNDER BIT0\r
77#define R_IC_RAW_INTR_STAT ( 0x34) // I2C Raw Interrupt Status\r
78#define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold\r
79#define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold\r
80#define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts\r
81#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt\r
82#define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt\r
83#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt\r
84#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt\r
85#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt\r
86#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt\r
87#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt\r
88#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt\r
89#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt\r
90#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt\r
91#define R_IC_ENABLE ( 0x6C) // I2C Enable\r
92#define R_IC_STATUS ( 0x70) // I2C Status\r
93\r
94#define R_IC_SDA_HOLD ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits\r
95\r
96#define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status.\r
97#define STAT_RFF BIT4 // RX FIFO is completely full\r
98#define STAT_RFNE BIT3 // RX FIFO is not empty\r
99#define STAT_TFE BIT2 // TX FIFO is completely empty\r
100#define STAT_TFNF BIT1 // TX FIFO is not full\r
101\r
102#define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register\r
103#define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register\r
104#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort Status Register\r
105#define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate SLV_DATA_NACK Register\r
106#define R_IC_DMA_CR ( 0x88) // DMA Control Register\r
107#define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level\r
108#define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level\r
109#define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register\r
110#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call Register\r
111#define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status Register\r
112#define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register\r
113#define R_IC_COMP_VERSION ( 0xF8) // Component Version ID\r
114#define R_IC_COMP_TYPE ( 0xFC) // Component Type\r
115\r
116#define R_IC_CLK_GATE ( 0xC0) // Clock Gate\r
117\r
118#define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD\r
119#define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4\r
120#define I2C_FS_SCL_HCNT_VALUE_100M 0x54\r
121#define I2C_FS_SCL_LCNT_VALUE_100M 0x9a\r
122#define I2C_HS_SCL_HCNT_VALUE_100M 0x7\r
123#define I2C_HS_SCL_LCNT_VALUE_100M 0xE\r
124\r
125#define IC_TAR_10BITADDR_MASTER BIT12\r
126#define FIFO_SIZE 32\r
127#define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status\r
128#define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask\r
129#define I2C_INTR_GEN_CALL BIT11 // General call received\r
130#define I2C_INTR_START_DET BIT10\r
131#define I2C_INTR_STOP_DET BIT9\r
132#define I2C_INTR_ACTIVITY BIT8\r
133#define I2C_INTR_TX_ABRT BIT6 // Set on NACK\r
134#define I2C_INTR_TX_EMPTY BIT4\r
135#define I2C_INTR_TX_OVER BIT3\r
136#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold\r
137#define I2C_INTR_RX_OVER BIT1\r
138#define I2C_INTR_RX_UNDER BIT0\r
139\r
140EFI_STATUS ProgramPciLpssI2C (\r
141 IN UINT8 BusNo\r
142 );\r
143EFI_STATUS ByteReadI2C_Basic(\r
144 IN UINT8 BusNo,\r
145 IN UINT8 SlaveAddress,\r
146 IN UINTN ReadBytes,\r
147 OUT UINT8 *ReadBuffer,\r
148 IN UINT8 Start,\r
149 IN UINT8 End\r
150 );\r
151EFI_STATUS ByteWriteI2C_Basic(\r
152 IN UINT8 BusNo,\r
153 IN UINT8 SlaveAddress,\r
154 IN UINTN WriteBytes,\r
155 IN UINT8 *WriteBuffer,\r
156 IN UINT8 Start,\r
157 IN UINT8 End\r
158 );\r
159\r
160EFI_STATUS ByteReadI2C(\r
161 IN UINT8 BusNo,\r
162 IN UINT8 SlaveAddress,\r
163 IN UINT8 Offset,\r
164 IN UINTN ReadBytes,\r
165 OUT UINT8 *ReadBuffer\r
166 );\r
167EFI_STATUS ByteWriteI2C(\r
168 IN UINT8 BusNo,\r
169 IN UINT8 SlaveAddress,\r
170 IN UINT8 Offset,\r
171 IN UINTN WriteBytes,\r
172 IN UINT8 *WriteBuffer\r
173 );\r
174\r
175#endif // I2C_REGS_A0_H\r