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Vlv2DeviceRefCodePkg: Replace BSD License with BSD+Patent License
[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / SouthCluster / Include / Ppi / PchPlatformPolicy.h
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3cbfba02
DW		 1/**\r
2**/\r
3/**\r
4\r
5Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r
6\r
7ede8060 7 SPDX-License-Identifier: BSD-2-Clause-Patent\r
3cbfba02
DW		 8\r
9\r
10\r
11 @file\r
12 PchPlatformPolicy.h\r
13\r
14 @brief\r
15 PCH policy PPI produced by a platform driver specifying various\r
16 expected PCH settings. This PPI is consumed by the PCH PEI modules.\r
17\r
18**/\r
19#ifndef PCH_PLATFORM_POLICY_H_\r
20#define PCH_PLATFORM_POLICY_H_\r
21//\r
22// External include files do NOT need to be explicitly specified in real EDKII\r
23// environment\r
24//\r
25\r
26\r
27#include "PchRegs.h"\r
28\r
29//\r
30#define PCH_PLATFORM_POLICY_PPI_GUID \\r
31 { \\r
32 0x15344673, 0xd365, 0x4be2, 0x85, 0x13, 0x14, 0x97, 0xcc, 0x7, 0x61, 0x1d \\r
33 }\r
34\r
35extern EFI_GUID gPchPlatformPolicyPpiGuid;\r
36\r
37///\r
38/// Forward reference for ANSI C compatibility\r
39///\r
40typedef struct _PCH_PLATFORM_POLICY_PPI PCH_PLATFORM_POLICY_PPI;\r
41\r
42///\r
43/// PPI revision number\r
44/// Any backwards compatible changes to this PPI will result in an update in the revision number\r
45/// Major changes will require publication of a new PPI\r
46///\r
47/// Revision 1: Original version\r
48///\r
49#define PCH_PLATFORM_POLICY_PPI_REVISION_1 1\r
50#define PCH_PLATFORM_POLICY_PPI_REVISION_2 2\r
51#define PCH_PLATFORM_POLICY_PPI_REVISION_3 3\r
52#define PCH_PLATFORM_POLICY_PPI_REVISION_4 4\r
53#define PCH_PLATFORM_POLICY_PPI_REVISION_5 5\r
54//\r
55// Generic definitions for device enabling/disabling used by PCH code.\r
56//\r
57#define PCH_DEVICE_ENABLE 1\r
58#define PCH_DEVICE_DISABLE 0\r
59\r
60typedef struct {\r
61 UINT8 ThermalDataReportEnable : 1; // OBSOLETE from Revision 5 !!! DO NOT USE !!!\r
62 UINT8 MchTempReadEnable : 1;\r
63 UINT8 PchTempReadEnable : 1;\r
64 UINT8 CpuEnergyReadEnable : 1;\r
65 UINT8 CpuTempReadEnable : 1;\r
66 UINT8 Cpu2TempReadEnable : 1;\r
67 UINT8 TsOnDimmEnable : 1;\r
68 UINT8 Dimm1TempReadEnable : 1;\r
69\r
70 UINT8 Dimm2TempReadEnable : 1;\r
71 UINT8 Dimm3TempReadEnable : 1;\r
72 UINT8 Dimm4TempReadEnable : 1;\r
73 UINT8 Rsvdbits : 5;\r
74} PCH_THERMAL_REPORT_CONTROL;\r
75//\r
76// ---------------------------- HPET Config -----------------------------\r
77//\r
78typedef struct {\r
79 BOOLEAN Enable; /// Determines if enable HPET function\r
80 UINT32 Base; /// The HPET base address\r
81} PCH_HPET_CONFIG;\r
82\r
83\r
84///\r
85/// ---------------------------- SATA Config -----------------------------\r
86///\r
87typedef enum {\r
88 PchSataModeIde,\r
89 PchSataModeAhci,\r
90 PchSataModeRaid,\r
91 PchSataModeMax\r
92} PCH_SATA_MODE;\r
93\r
94///\r
95/// ---------------------------- PCI Express Config -----------------------------\r
96///\r
97typedef enum {\r
98 PchPcieAuto,\r
99 PchPcieGen1,\r
100 PchPcieGen2\r
101} PCH_PCIE_SPEED;\r
102\r
103typedef struct {\r
104 PCH_PCIE_SPEED PcieSpeed[PCH_PCIE_MAX_ROOT_PORTS];\r
105} PCH_PCIE_CONFIG;\r
106\r
107///\r
108/// ---------------------------- IO APIC Config -----------------------------\r
109///\r
110typedef struct {\r
111 UINT8 IoApicId;\r
112} PCH_IOAPIC_CONFIG;\r
113\r
114///\r
115/// --------------------- Low Power Input Output Config ------------------------\r
116///\r
117typedef struct {\r
118 UINT8 LpssPciModeEnabled : 1; /// Determines if LPSS PCI Mode enabled\r
119 UINT8 Dma0Enabled : 1; /// Determines if LPSS DMA1 enabled\r
120 UINT8 Dma1Enabled : 1; /// Determines if LPSS DMA2 enabled\r
121 UINT8 I2C0Enabled : 1; /// Determines if LPSS I2C #1 enabled\r
122 UINT8 I2C1Enabled : 1; /// Determines if LPSS I2C #2 enabled\r
123 UINT8 I2C2Enabled : 1; /// Determines if LPSS I2C #3 enabled\r
124 UINT8 I2C3Enabled : 1; /// Determines if LPSS I2C #4 enabled\r
125 UINT8 I2C4Enabled : 1; /// Determines if LPSS I2C #5 enabled\r
126 UINT8 I2C5Enabled : 1; /// Determines if LPSS I2C #6 enabled\r
127 UINT8 I2C6Enabled : 1; /// Determines if LPSS I2C #7 enabled\r
128 UINT8 Pwm0Enabled : 1; /// Determines if LPSS PWM #1 enabled\r
129 UINT8 Pwm1Enabled : 1; /// Determines if LPSS PWM #2 enabled\r
130 UINT8 Hsuart0Enabled : 1; /// Determines if LPSS HSUART #1 enabled\r
131 UINT8 Hsuart1Enabled : 1; /// Determines if LPSS HSUART #2 enabled\r
132 UINT8 SpiEnabled : 1; /// Determines if LPSS SPI enabled\r
133 UINT8 Rsvdbits : 2;\r
134} PEI_PCH_LPSS_CONFIG;\r
135\r
136///\r
137/// ------------ General PCH Platform Policy PPI definition ------------\r
138///\r
139struct _PCH_PLATFORM_POLICY_PPI {\r
140 UINT8 Revision;\r
141 UINT8 BusNumber; // Bus Number of the PCH device\r
142 UINT32 SpiBase; // SPI Base Address.\r
143 UINT32 PmcBase; // PMC Base Address.\r
144 UINT32 SmbmBase; // SMB Memory Base Address.\r
145 UINT32 IoBase; // IO Base Address.\r
146 UINT32 IlbBase; // Intel Legacy Block Base Address.\r
147 UINT32 PUnitBase; // PUnit Base Address.\r
148 UINT32 Rcba; // Root Complex Base Address.\r
149 UINT32 MphyBase; // MPHY Base Address.\r
150 UINT16 AcpiBase; // ACPI I/O Base address.\r
151 UINT16 GpioBase; // GPIO Base address\r
152 PCH_HPET_CONFIG *HpetConfig;\r
153 PCH_SATA_MODE SataMode;\r
154 PCH_PCIE_CONFIG *PcieConfig;\r
155 PCH_IOAPIC_CONFIG *IoApicConfig;\r
156 PEI_PCH_LPSS_CONFIG *LpssConfig;\r
157 BOOLEAN EnableRmh; // Determines if enable USB RMH function\r
158 BOOLEAN EhciPllCfgEnable;\r
159};\r
160\r
161#endif\r
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