]>
Commit | Line | Data |
---|---|---|
3cbfba02 DW |
1 | ;\r |
2 | ; This file contains an 'Intel Sample Driver' and is\r | |
3 | ; licensed for Intel CPUs and chipsets under the terms of your\r | |
4 | ; license agreement with Intel or your vendor. This file may\r | |
5 | ; be modified by the user, subject to additional terms of the\r | |
6 | ; license agreement\r | |
7 | ;\r | |
8 | ;\r | |
9 | ; Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r | |
10 | ; \r\r | |
11 | ; This program and the accompanying materials are licensed and made available under\r\r | |
12 | ; the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
13 | ; The full text of the license may be found at \r\r | |
14 | ; http://opensource.org/licenses/bsd-license.php. \r\r | |
15 | ; \r\r | |
16 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
17 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
18 | ; \r\r | |
19 | ;\r | |
20 | \r | |
21 | ;Module Name:\r | |
22 | ;\r | |
23 | ; CpuIA32.c\r | |
24 | ;\r | |
25 | ;Abstract:\r | |
26 | ;\r | |
27 | ;--*/\r | |
28 | \r | |
29 | ;#include "CpuIA32.h"\r | |
30 | \r | |
31 | ;---------------------------------------------------------------------------\r | |
32 | .586p\r | |
33 | .model flat,C\r | |
34 | .code\r | |
35 | \r | |
36 | ;---------------------------------------------------------------------------\r | |
37 | ;VOID\r | |
38 | ;EfiHalt (\r | |
39 | ; VOID\r | |
40 | ;)\r | |
41 | EfiHalt PROC C PUBLIC\r | |
42 | hlt\r | |
43 | ret\r | |
44 | EfiHalt ENDP\r | |
45 | \r | |
46 | ;VOID\r | |
47 | ;EfiWbinvd (\r | |
48 | ; VOID\r | |
49 | ;)\r | |
50 | EfiWbinvd PROC C PUBLIC\r | |
51 | wbinvd\r | |
52 | ret\r | |
53 | EfiWbinvd ENDP\r | |
54 | \r | |
55 | ;VOID\r | |
56 | ;EfiInvd (\r | |
57 | ; VOID\r | |
58 | ;)\r | |
59 | EfiInvd PROC C PUBLIC\r | |
60 | invd\r | |
61 | ret\r | |
62 | EfiInvd ENDP\r | |
63 | \r | |
64 | ;VOID\r | |
65 | ;EfiCpuid (IN UINT32 RegisterInEax,\r | |
66 | ; OUT EFI_CPUID_REGISTER *Reg OPTIONAL)\r | |
67 | EfiCpuid PROC C PUBLIC\r | |
68 | push ebp\r | |
69 | mov ebp, esp\r | |
70 | push ebx\r | |
71 | push esi\r | |
72 | push edi\r | |
73 | pushad\r | |
74 | \r | |
75 | mov eax, dword ptr[ebp + 8] ;egisterInEax\r | |
76 | cpuid\r | |
77 | cmp dword ptr[ebp + 0Ch], 0 ; Reg\r | |
78 | je @F\r | |
79 | mov edi,dword ptr [ebp+0Ch] ; Reg\r | |
80 | \r | |
81 | mov dword ptr [edi],eax ; Reg->RegEax\r | |
82 | mov dword ptr [edi+4],ebx ; Reg->RegEbx\r | |
83 | mov dword ptr [edi+8],ecx ; Reg->RegEcx\r | |
84 | mov dword ptr [edi+0Ch],edx ; Reg->RegEdx\r | |
85 | \r | |
86 | @@:\r | |
87 | popad\r | |
88 | pop edi\r | |
89 | pop esi\r | |
90 | pop ebx\r | |
91 | pop ebp\r | |
92 | \r | |
93 | ret\r | |
94 | EfiCpuid ENDP\r | |
95 | \r | |
96 | \r | |
97 | ;UINT64\r | |
98 | ;EfiReadMsr (\r | |
99 | ; IN UINT32 Index\r | |
100 | ; );\r | |
101 | EfiReadMsr PROC C PUBLIC\r | |
102 | mov ecx, dword ptr [esp + 4]; Index\r | |
103 | rdmsr\r | |
104 | ret\r | |
105 | EfiReadMsr ENDP\r | |
106 | \r | |
107 | ;VOID\r | |
108 | ;EfiWriteMsr (\r | |
109 | ; IN UINT32 Index,\r | |
110 | ; IN UINT64 Value\r | |
111 | ; );\r | |
112 | EfiWriteMsr PROC C PUBLIC\r | |
113 | mov ecx, dword ptr [esp+4]; Index\r | |
114 | mov eax, dword ptr [esp+8]; DWORD PTR Value[0]\r | |
115 | mov edx, dword ptr [esp+0Ch]; DWORD PTR Value[4]\r | |
116 | wrmsr\r | |
117 | ret\r | |
118 | EfiWriteMsr ENDP\r | |
119 | \r | |
120 | ;UINT64\r | |
121 | ;EfiReadTsc (\r | |
122 | ; VOID\r | |
123 | ; )\r | |
124 | EfiReadTsc PROC C PUBLIC\r | |
125 | rdtsc\r | |
126 | ret\r | |
127 | EfiReadTsc ENDP\r | |
128 | \r | |
129 | ;VOID\r | |
130 | ;EfiDisableCache (\r | |
131 | ; VOID\r | |
132 | ;)\r | |
133 | EfiDisableCache PROC C PUBLIC\r | |
134 | mov eax, cr0\r | |
135 | bswap eax\r | |
136 | and al, 60h\r | |
137 | cmp al, 60h\r | |
138 | je @F\r | |
139 | mov eax, cr0\r | |
140 | or eax, 060000000h\r | |
141 | mov cr0, eax\r | |
142 | wbinvd\r | |
143 | @@:\r | |
144 | ret\r | |
145 | EfiDisableCache ENDP\r | |
146 | \r | |
147 | ;VOID\r | |
148 | ;EfiEnableCache (\r | |
149 | ; VOID\r | |
150 | ; )\r | |
151 | EfiEnableCache PROC C PUBLIC\r | |
152 | wbinvd\r | |
153 | mov eax, cr0\r | |
154 | and eax, 09fffffffh\r | |
155 | mov cr0, eax\r | |
156 | ret\r | |
157 | EfiEnableCache ENDP\r | |
158 | \r | |
159 | ;UINT32\r | |
160 | ;EfiGetEflags (\r | |
161 | ; VOID\r | |
162 | ; )\r | |
163 | EfiGetEflags PROC C PUBLIC\r | |
164 | pushfd\r | |
165 | pop eax\r | |
166 | ret\r | |
167 | EfiGetEflags ENDP\r | |
168 | \r | |
169 | ;VOID\r | |
170 | ;EfiDisableInterrupts (\r | |
171 | ; VOID\r | |
172 | ; )\r | |
173 | EfiDisableInterrupts PROC C PUBLIC\r | |
174 | cli\r | |
175 | ret\r | |
176 | EfiDisableInterrupts ENDP\r | |
177 | \r | |
178 | ;VOID\r | |
179 | ;EfiEnableInterrupts (\r | |
180 | ; VOID\r | |
181 | ; )\r | |
182 | EfiEnableInterrupts PROC C PUBLIC\r | |
183 | sti\r | |
184 | ret\r | |
185 | EfiEnableInterrupts ENDP\r | |
186 | \r | |
187 | ;VOID\r | |
188 | ;EfiCpuidExt (\r | |
189 | ; IN UINT32 RegisterInEax,\r | |
190 | ; IN UINT32 CacheLevel,\r | |
191 | ; OUT EFI_CPUID_REGISTER *Regs\r | |
192 | ; )\r | |
193 | EfiCpuidExt PROC C PUBLIC USES ebx edi esi\r | |
194 | pushad\r | |
195 | \r | |
196 | mov eax, dword ptr [esp + 30h] ; RegisterInEax\r | |
197 | mov ecx, dword ptr [esp + 34h] ; CacheLevel\r | |
198 | cpuid\r | |
199 | mov edi, dword ptr [esp + 38h] ; DWORD PTR Regs\r | |
200 | \r | |
201 | mov dword ptr [edi], eax ; Reg->RegEax\r | |
202 | mov dword ptr [edi + 4], ebx ; Reg->RegEbx\r | |
203 | mov dword ptr [edi + 8], ecx ; Reg->RegEcx\r | |
204 | mov dword ptr [edi + 0Ch], edx ; Reg->RegEdx\r | |
205 | \r | |
206 | popad\r | |
207 | ret\r | |
208 | EfiCpuidExt ENDP\r | |
209 | \r | |
210 | END\r | |
211 | \r |