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Vlv2TbltDevicePkg/FlashDeviceLib: Add DXE flash device lib.
[mirror_edk2.git] / Vlv2TbltDevicePkg / Library / FlashDeviceLib / SpiChipDefinitions.h
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7a0a32f1
JY		 1/** @file\r
2\r
3 Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>\r
4\r
5 This program and the accompanying materials are licensed and made available under\r
6 the terms and conditions of the BSD License that accompanies this distribution.\r
7 The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php.\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
3cbfba02 12\r
3cbfba02
DW		 13\r
14\r
15**/\r
16\r
17#include <Library/SpiFlash.H>\r
18\r
7a0a32f1 19#define FLASH_SIZE 0x400000\r
3cbfba02
DW		 20\r
21//\r
22// Serial Flash device initialization data table provided to the\r
23// Intel(R) SPI Host Controller Compatibility Interface.\r
24//\r
25SPI_INIT_TABLE mInitTable[] = {\r
26 {\r
27 SF_VENDOR_ID_WINBOND, // VendorId\r
28 SF_DEVICE_ID0_W25QXX, // DeviceId 0\r
29 SF_DEVICE_ID1_W25Q64, // DeviceId 1\r
30 {\r
31 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
32 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
33 },\r
34 {\r
35 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
36 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
37 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
38 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
39 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
40 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
41 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
42 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
43 },\r
44\r
45 //\r
46 // The offset of the start of the BIOS image in flash. This value is platform specific\r
47 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
48 //\r
49 ((WINBOND_W25Q64_SIZE >= FLASH_SIZE) ? WINBOND_W25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
50\r
51 //\r
52 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
53 //\r
54 FLASH_SIZE\r
55 },\r
56 {\r
57 SF_VENDOR_ID_ATMEL, // VendorId\r
58 SF_DEVICE_ID0_AT25DF321A, // DeviceId 0\r
59 SF_DEVICE_ID1_AT25DF321A, // DeviceId 1\r
60 {\r
61 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
62 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
63 },\r
64 {\r
65 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
66 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
67 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
68 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
69 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
70 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)\r
71 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
72 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
73 },\r
74\r
75 //\r
76 // The offset of the start of the BIOS image in flash. This value is platform specific\r
77 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
78 //\r
79 ((ATMEL_AT25DF321A_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF321A_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
80\r
81 //\r
82 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
83 //\r
84 FLASH_SIZE\r
85 },\r
86 {\r
87 SF_VENDOR_ID_ATMEL, // VendorId\r
88 SF_DEVICE_ID0_AT26DF321, // DeviceId 0\r
89 SF_DEVICE_ID1_AT26DF321, // DeviceId 1\r
90 {\r
91 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
92 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
93 },\r
94 {\r
95 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
96 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
97 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
98 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
99 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
100 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)\r
101 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
102 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
103 },\r
104\r
105 //\r
106 // The offset of the start of the BIOS image in flash. This value is platform specific\r
107 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
108 //\r
109 ((ATMEL_AT26DF321_SIZE >= FLASH_SIZE) ? ATMEL_AT26DF321_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
110\r
111 //\r
112 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
113 //\r
114 FLASH_SIZE\r
115 },\r
116 {\r
117 SF_VENDOR_ID_ATMEL, // VendorId\r
118 SF_DEVICE_ID0_AT25DF641, // DeviceId 0\r
119 SF_DEVICE_ID1_AT25DF641, // DeviceId 1\r
120 {\r
121 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
122 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
123 },\r
124 {\r
125 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
126 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
127 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
128 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
129 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
130 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)\r
131 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
132 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
133 },\r
134\r
135 //\r
136 // The offset of the start of the BIOS image in flash. This value is platform specific\r
137 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
138 //\r
139 ((ATMEL_AT25DF641_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF641_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
140\r
141 //\r
142 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
143 //\r
144 FLASH_SIZE\r
145 },\r
146 {\r
147 SF_VENDOR_ID_WINBOND, // VendorId\r
148 SF_DEVICE_ID0_W25QXX, // DeviceId 0\r
149 SF_DEVICE_ID1_W25Q16, // DeviceId 1\r
150 {\r
151 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
152 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
153 },\r
154 {\r
155 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
156 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
157 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
158 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
159 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
160 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
161 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
162 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
163 },\r
164\r
165 //\r
166 // The offset of the start of the BIOS image in flash. This value is platform specific\r
167 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
168 //\r
169 ((WINBOND_W25Q16_SIZE >= FLASH_SIZE) ? WINBOND_W25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
170\r
171 //\r
172 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
173 //\r
174 FLASH_SIZE\r
175 },\r
176 {\r
177 SF_VENDOR_ID_WINBOND, // VendorId\r
178 SF_DEVICE_ID0_W25QXX, // DeviceId 0\r
179 SF_DEVICE_ID1_W25Q32, // DeviceId 1\r
180 {\r
181 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
182 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register.\r
183 },\r
184 {\r
185 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
186 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
187 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
188 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
189 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
190 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
191 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
192 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
193 },\r
194\r
195 //\r
196 // The offset of the start of the BIOS image in flash. This value is platform specific\r
197 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
198 //\r
199 ((WINBOND_W25Q32_SIZE >= FLASH_SIZE) ? WINBOND_W25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
200\r
201 //\r
202 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
203 //\r
204 FLASH_SIZE\r
205 },\r
206 {\r
207 SF_VENDOR_ID_WINBOND, // VendorId\r
208 SF_DEVICE_ID0_W25XXX, // DeviceId 0\r
209 SF_DEVICE_ID1_W25X32, // DeviceId 1\r
210 {\r
211 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
212 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
213 },\r
214 {\r
215 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
216 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
217 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
218 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
219 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
220 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
221 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
222 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
223 },\r
224\r
225 //\r
226 // The offset of the start of the BIOS image in flash. This value is platform specific\r
227 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
228 //\r
229 ((WINBOND_W25X32_SIZE >= FLASH_SIZE) ? WINBOND_W25X32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
230\r
231 //\r
232 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
233 //\r
234 FLASH_SIZE\r
235 },\r
236 {\r
237 SF_VENDOR_ID_WINBOND, // VendorId\r
238 SF_DEVICE_ID0_W25XXX, // DeviceId 0\r
239 SF_DEVICE_ID1_W25X64, // DeviceId 1\r
240 {\r
241 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
242 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
243 },\r
244 {\r
245 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
246 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
247 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
248 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
249 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
250 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
251 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
252 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
253 },\r
254\r
255 //\r
256 // The offset of the start of the BIOS image in flash. This value is platform specific\r
257 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
258 //\r
259 ((WINBOND_W25X64_SIZE >= FLASH_SIZE) ? WINBOND_W25X64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
260\r
261 //\r
262 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
263 //\r
264 FLASH_SIZE\r
265 },\r
266 {\r
267 SF_VENDOR_ID_WINBOND, // VendorId\r
268 SF_DEVICE_ID0_W25QXX, // DeviceId 0\r
269 SF_DEVICE_ID1_W25Q128, // DeviceId 1\r
270 {\r
271 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
272 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
273 },\r
274 {\r
275 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
276 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
277 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
278 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
279 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
280 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
281 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
282 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
283 },\r
284\r
285 //\r
286 // The offset of the start of the BIOS image in flash. This value is platform specific\r
287 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
288 //\r
289 ((WINBOND_W25Q128_SIZE >= FLASH_SIZE) ? WINBOND_W25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
290\r
291 //\r
292 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
293 //\r
294 FLASH_SIZE\r
295 },\r
296 {\r
297 SF_VENDOR_ID_MACRONIX, // VendorId\r
298 SF_DEVICE_ID0_MX25LXX, // DeviceId 0\r
299 SF_DEVICE_ID1_MX25L16, // DeviceId 1\r
300 {\r
301 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
302 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
303 },\r
304 {\r
305 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
306 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
307 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
308 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
309 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
310 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
311 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
312 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
313 },\r
314\r
315 //\r
316 // The offset of the start of the BIOS image in flash. This value is platform specific\r
317 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
318 //\r
319 ((MACRONIX_MX25L16_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
320\r
321 //\r
322 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
323 //\r
324 FLASH_SIZE\r
325 },\r
326 {\r
327 SF_VENDOR_ID_MACRONIX, // VendorId\r
328 SF_DEVICE_ID0_MX25LXX, // DeviceId 0\r
329 SF_DEVICE_ID1_MX25L32, // DeviceId 1\r
330 {\r
331 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
332 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
333 },\r
334 {\r
335 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
336 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
337 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
338 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
339 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
340 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
341 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
342 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
343 },\r
344\r
345 //\r
346 // The offset of the start of the BIOS image in flash. This value is platform specific\r
347 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
348 //\r
349 ((MACRONIX_MX25L32_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
350\r
351 //\r
352 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
353 //\r
354 FLASH_SIZE\r
355 },\r
356 {\r
357 SF_VENDOR_ID_MACRONIX, // VendorId\r
358 SF_DEVICE_ID0_MX25LXX, // DeviceId 0\r
359 SF_DEVICE_ID1_MX25L64, // DeviceId 1\r
360 {\r
361 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
362 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
363 },\r
364 {\r
365 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
366 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
367 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
368 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
369 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
370 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
371 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
372 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
373 },\r
374\r
375 //\r
376 // The offset of the start of the BIOS image in flash. This value is platform specific\r
377 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
378 //\r
379 ((MACRONIX_MX25L64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
380\r
381 //\r
382 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
383 //\r
384 FLASH_SIZE\r
385 },\r
386 {\r
387 SF_VENDOR_ID_MACRONIX, // VendorId\r
388 SF_DEVICE_ID0_MX25LXX, // DeviceId 0\r
389 SF_DEVICE_ID1_MX25L128, // DeviceId 1\r
390 {\r
391 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
392 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
393 },\r
394 {\r
395 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
396 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
397 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
398 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
399 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
400 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
401 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
402 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
403 },\r
404\r
405 //\r
406 // The offset of the start of the BIOS image in flash. This value is platform specific\r
407 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
408 //\r
409 ((MACRONIX_MX25L128_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L128_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
410\r
411 //\r
412 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
413 //\r
414 FLASH_SIZE\r
415 },\r
416 {\r
417 SF_VENDOR_ID_MACRONIX, // VendorId\r
418 SF_DEVICE_ID0_MX25UXX, // DeviceId 0\r
419 SF_DEVICE_ID1_MX25U6435F, // DeviceId 1\r
420 {\r
421 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
422 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
423 },\r
424 {\r
425 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
426 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
427 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
428 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
429 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
430 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
431 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
432 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
433 },\r
434\r
435 //\r
436 // The offset of the start of the BIOS image in flash. This value is platform specific\r
437 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
438 //\r
439 ((MACRONIX_MX25U64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25U64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
440\r
441 //\r
442 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
443 //\r
444 FLASH_SIZE\r
445 },\r
446 {\r
447 SF_VENDOR_ID_SST, // VendorId\r
448 SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0\r
449 SF_DEVICE_ID1_SST25VF016B,// DeviceId 1\r
450 {\r
451 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
452 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
453 },\r
454 {\r
455 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
456 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
457 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
458 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
459 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
460 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)\r
461 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
462 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
463 },\r
464\r
465 //\r
466 // The offset of the start of the BIOS image in flash. This value is platform specific\r
467 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
468 //\r
469 ((SST_SST25VF016B_SIZE >= FLASH_SIZE) ? SST_SST25VF016B_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
470\r
471 //\r
472 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
473 //\r
474 FLASH_SIZE\r
475 },\r
476 {\r
477 SF_VENDOR_ID_SST, // VendorId\r
478 SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0\r
479 SF_DEVICE_ID1_SST25VF064C,// DeviceId 1\r
480 {\r
481 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
482 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
483 },\r
484 {\r
485 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
486 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
487 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
488 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
489 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
490 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)\r
491 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
492 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
493 },\r
494\r
495 //\r
496 // The offset of the start of the BIOS image in flash. This value is platform specific\r
497 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
498 //\r
499 ((SST_SST25VF064C_SIZE >= FLASH_SIZE) ? SST_SST25VF064C_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
500\r
501 //\r
502 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
503 //\r
504 FLASH_SIZE\r
505 },\r
506 {\r
507 //\r
508 // Minnow2 SPI type\r
509 //\r
510 SF_VENDOR_ID_NUMONYX, // VendorId\r
511 SF_DEVICE_ID0_N25Q064, // DeviceId 0\r
512 SF_DEVICE_ID1_N25Q064, // DeviceId 1\r
513 {\r
514 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
515 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
516 },\r
517 {\r
518 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle20MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
519 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
520 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle20MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
521 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle20MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
522 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle20MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
523 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle20MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
524 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle20MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
525 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle20MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
526 },\r
527\r
528 //\r
529 // The offset of the start of the BIOS image in flash. This value is platform specific\r
530 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
531 //\r
532 ((NUMONYX_N25Q064_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q064_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
533\r
534 //\r
535 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
536 //\r
537 FLASH_SIZE\r
538 },\r
539 {\r
540 SF_VENDOR_ID_NUMONYX, // VendorId\r
541 SF_DEVICE_ID0_M25PXXX, // DeviceId 0\r
542 SF_DEVICE_ID1_M25PX16, // DeviceId 1\r
543 {\r
544 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
545 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
546 },\r
547 {\r
548 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
549 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
550 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
551 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
552 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
553 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
554 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
555 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
556 },\r
557\r
558 //\r
559 // The offset of the start of the BIOS image in flash. This value is platform specific\r
560 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
561 //\r
562 ((NUMONYX_M25PX16_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
563\r
564 //\r
565 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
566 //\r
567 FLASH_SIZE\r
568 },\r
569 {\r
570 SF_VENDOR_ID_NUMONYX, // VendorId\r
571 SF_DEVICE_ID0_N25QXXX, // DeviceId 0\r
572 SF_DEVICE_ID1_N25Q032, // DeviceId 1\r
573 {\r
574 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
575 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
576 },\r
577 {\r
578 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
579 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
580 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
581 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
582 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
583 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
584 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
585 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
586 },\r
587\r
588 //\r
589 // The offset of the start of the BIOS image in flash. This value is platform specific\r
590 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
591 //\r
592 ((NUMONYX_N25Q032_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q032_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
593\r
594 //\r
595 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
596 //\r
597 FLASH_SIZE\r
598 },\r
599 {\r
600 SF_VENDOR_ID_NUMONYX, // VendorId\r
601 SF_DEVICE_ID0_M25PXXX, // DeviceId 0\r
602 SF_DEVICE_ID1_M25PX32, // DeviceId 1\r
603 {\r
604 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
605 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
606 },\r
607 {\r
608 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
609 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
610 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
611 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
612 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
613 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
614 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
615 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
616 },\r
617\r
618 //\r
619 // The offset of the start of the BIOS image in flash. This value is platform specific\r
620 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
621 //\r
622 ((NUMONYX_M25PX32_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
623\r
624 //\r
625 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
626 //\r
627 FLASH_SIZE\r
628 },\r
629 {\r
630 SF_VENDOR_ID_NUMONYX, // VendorId\r
631 SF_DEVICE_ID0_M25PXXX, // DeviceId 0\r
632 SF_DEVICE_ID1_M25PX64, // DeviceId 1\r
633 {\r
634 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
635 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
636 },\r
637 {\r
638 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
639 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
640 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
641 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
642 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
643 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
644 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
645 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
646 },\r
647\r
648 //\r
649 // The offset of the start of the BIOS image in flash. This value is platform specific\r
650 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
651 //\r
652 ((NUMONYX_M25PX64_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
653\r
654 //\r
655 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
656 //\r
657 FLASH_SIZE\r
658 },\r
659 {\r
660 SF_VENDOR_ID_NUMONYX, // VendorId\r
661 SF_DEVICE_ID0_N25QXXX, // DeviceId 0\r
662 SF_DEVICE_ID1_N25Q128, // DeviceId 1\r
663 {\r
664 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
665 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
666 },\r
667 {\r
668 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
669 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
670 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
671 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
672 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
673 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
674 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
675 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
676 },\r
677\r
678 //\r
679 // The offset of the start of the BIOS image in flash. This value is platform specific\r
680 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
681 //\r
682 ((NUMONYX_N25Q128_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
683\r
684 //\r
685 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
686 //\r
687 FLASH_SIZE\r
688 },\r
689 {\r
690 SF_VENDOR_ID_EON, // VendorId\r
691 SF_DEVICE_ID0_EN25QXX, // DeviceId 0\r
692 SF_DEVICE_ID1_EN25Q16, // DeviceId 1\r
693 {\r
694 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
695 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
696 },\r
697 {\r
698 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
699 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
700 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
701 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
702 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
703 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
704 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
705 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
706 },\r
707\r
708 //\r
709 // The offset of the start of the BIOS image in flash. This value is platform specific\r
710 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
711 //\r
712 ((EON_EN25Q16_SIZE >= FLASH_SIZE) ? EON_EN25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
713\r
714 //\r
715 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
716 //\r
717 FLASH_SIZE\r
718 },\r
719 {\r
720 SF_VENDOR_ID_EON, // VendorId\r
721 SF_DEVICE_ID0_EN25QXX, // DeviceId 0\r
722 SF_DEVICE_ID1_EN25Q32, // DeviceId 1\r
723 {\r
724 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
725 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
726 },\r
727 {\r
728 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
729 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
730 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
731 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
732 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
733 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
734 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
735 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
736 },\r
737\r
738 //\r
739 // The offset of the start of the BIOS image in flash. This value is platform specific\r
740 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
741 //\r
742 ((EON_EN25Q32_SIZE >= FLASH_SIZE) ? EON_EN25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
743\r
744 //\r
745 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
746 //\r
747 FLASH_SIZE\r
748 },\r
749 {\r
750 SF_VENDOR_ID_EON, // VendorId\r
751 SF_DEVICE_ID0_EN25QXX, // DeviceId 0\r
752 SF_DEVICE_ID1_EN25Q64, // DeviceId 1\r
753 {\r
754 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
755 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
756 },\r
757 {\r
758 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
759 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
760 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
761 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
762 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
763 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
764 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
765 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
766 },\r
767\r
768 //\r
769 // The offset of the start of the BIOS image in flash. This value is platform specific\r
770 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
771 //\r
772 ((EON_EN25Q64_SIZE >= FLASH_SIZE) ? EON_EN25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
773\r
774 //\r
775 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
776 //\r
777 FLASH_SIZE\r
778 },\r
779 {\r
780 SF_VENDOR_ID_EON, // VendorId\r
781 SF_DEVICE_ID0_EN25QXX, // DeviceId 0\r
782 SF_DEVICE_ID1_EN25Q128, // DeviceId 1\r
783 {\r
784 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
785 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
786 },\r
787 {\r
788 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
789 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
790 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
791 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
792 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
793 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
794 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
795 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
796 },\r
797\r
798 //\r
799 // The offset of the start of the BIOS image in flash. This value is platform specific\r
800 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
801 //\r
802 ((EON_EN25Q128_SIZE >= FLASH_SIZE) ? EON_EN25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
803\r
804 //\r
805 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
806 //\r
807 FLASH_SIZE\r
808 },\r
809 {\r
810 SF_VENDOR_ID_AMIC, // VendorId\r
811 SF_DEVICE_ID0_A25L016, // DeviceId 0\r
812 SF_DEVICE_ID1_A25L016, // DeviceId 1\r
813 {\r
814 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
815 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
816 },\r
817 {\r
818 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
819 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
820 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
821 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
822 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
823 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
824 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
825 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
826 },\r
827\r
828 //\r
829 // The offset of the start of the BIOS image in flash. This value is platform specific\r
830 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
831 //\r
832 ((AMIC_A25L16_SIZE >= FLASH_SIZE) ? AMIC_A25L16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
833\r
834 //\r
835 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
836 //\r
837 FLASH_SIZE\r
838 }\r
839};\r
7a0a32f1 840\r
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