Vlv2TbltDevicePkg/Library/FlashDeviceLib/SpiChipDefinitions.h

   1 /** @file
   2
   3   Copyright (c) 2004  - 2016, Intel Corporation. All rights reserved.<BR>
   4
   5   This program and the accompanying materials are licensed and made available under
   6   the terms and conditions of the BSD License that accompanies this distribution.
   7   The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14
  15 **/
  16
  17 #include <Library/SpiFlash.H>
  18
  19 #define FLASH_SIZE  0x400000
  20
  21 //
  22 // Serial Flash device initialization data table provided to the
  23 // Intel(R) SPI Host Controller Compatibility Interface.
  24 //
  25 SPI_INIT_TABLE  mInitTable[] = {
  26   {
  27   SF_VENDOR_ID_WINBOND,     // VendorId
  28   SF_DEVICE_ID0_W25QXX,     // DeviceId 0
  29   SF_DEVICE_ID1_W25Q64,     // DeviceId 1
  30   {
  31     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
  32     SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register
  33   },
  34   {
  35     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
  36     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
  37     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
  38     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
  39     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
  40     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (64KB
  41     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
  42     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
  43   },
  44
  45   //
  46   // The offset of the start of the BIOS image in flash. This value is platform specific
  47   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
  48   //
  49   ((WINBOND_W25Q64_SIZE >= FLASH_SIZE) ? WINBOND_W25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),
  50
  51   //
  52   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
  53   //
  54   FLASH_SIZE
  55   },
  56   {
  57   SF_VENDOR_ID_ATMEL,       // VendorId
  58   SF_DEVICE_ID0_AT25DF321A,  // DeviceId 0
  59   SF_DEVICE_ID1_AT25DF321A, // DeviceId 1
  60   {
  61     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
  62     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
  63   },
  64   {
  65     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
  66     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
  67     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
  68     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable      },     // Opcode 3: Write Disable
  69     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
  70     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (32KB)
  71     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
  72     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
  73   },
  74
  75   //
  76   // The offset of the start of the BIOS image in flash. This value is platform specific
  77   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
  78   //
  79   ((ATMEL_AT25DF321A_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF321A_SIZE - FLASH_SIZE : (UINTN) (-1)),
  80
  81   //
  82   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
  83   //
  84   FLASH_SIZE
  85   },
  86   {
  87   SF_VENDOR_ID_ATMEL,       // VendorId
  88   SF_DEVICE_ID0_AT26DF321,  // DeviceId 0
  89   SF_DEVICE_ID1_AT26DF321,  // DeviceId 1
  90   {
  91     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
  92     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
  93   },
  94   {
  95     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
  96     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
  97     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
  98     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable      },     // Opcode 3: Write Disable
  99     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
 100     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (32KB)
 101     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 102     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
 103   },
 104
 105   //
 106   // The offset of the start of the BIOS image in flash. This value is platform specific
 107   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 108   //
 109   ((ATMEL_AT26DF321_SIZE >= FLASH_SIZE) ? ATMEL_AT26DF321_SIZE - FLASH_SIZE : (UINTN) (-1)),
 110
 111   //
 112   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 113   //
 114   FLASH_SIZE
 115   },
 116   {
 117   SF_VENDOR_ID_ATMEL,       // VendorId
 118   SF_DEVICE_ID0_AT25DF641,  // DeviceId 0
 119   SF_DEVICE_ID1_AT25DF641,  // DeviceId 1
 120   {
 121     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 122     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
 123   },
 124   {
 125     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
 126     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
 127     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
 128     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable      },     // Opcode 3: Write Disable
 129     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
 130     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (32KB)
 131     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 132     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
 133   },
 134
 135   //
 136   // The offset of the start of the BIOS image in flash. This value is platform specific
 137   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 138   //
 139   ((ATMEL_AT25DF641_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF641_SIZE - FLASH_SIZE : (UINTN) (-1)),
 140
 141   //
 142   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 143   //
 144   FLASH_SIZE
 145   },
 146   {
 147   SF_VENDOR_ID_WINBOND,     // VendorId
 148   SF_DEVICE_ID0_W25QXX,     // DeviceId 0
 149   SF_DEVICE_ID1_W25Q16,     // DeviceId 1
 150   {
 151     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 152     SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register
 153   },
 154   {
 155     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
 156     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
 157     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
 158     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 159     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
 160     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (64KB
 161     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 162     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
 163   },
 164
 165   //
 166   // The offset of the start of the BIOS image in flash. This value is platform specific
 167   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 168   //
 169   ((WINBOND_W25Q16_SIZE >= FLASH_SIZE) ? WINBOND_W25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),
 170
 171   //
 172   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 173   //
 174   FLASH_SIZE
 175   },
 176   {
 177   SF_VENDOR_ID_WINBOND,     // VendorId
 178   SF_DEVICE_ID0_W25QXX,     // DeviceId 0
 179   SF_DEVICE_ID1_W25Q32,     // DeviceId 1
 180   {
 181     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 182     SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register.
 183   },
 184   {
 185     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
 186     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
 187     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
 188     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 189     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
 190     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (64KB
 191     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 192     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
 193   },
 194
 195   //
 196   // The offset of the start of the BIOS image in flash. This value is platform specific
 197   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 198   //
 199   ((WINBOND_W25Q32_SIZE >= FLASH_SIZE) ? WINBOND_W25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),
 200
 201   //
 202   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 203   //
 204   FLASH_SIZE
 205   },
 206   {
 207   SF_VENDOR_ID_WINBOND,     // VendorId
 208   SF_DEVICE_ID0_W25XXX,     // DeviceId 0
 209   SF_DEVICE_ID1_W25X32,     // DeviceId 1
 210   {
 211     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 212     SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register
 213   },
 214   {
 215     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
 216     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
 217     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
 218     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 219     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
 220     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (64KB
 221     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 222     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
 223   },
 224
 225   //
 226   // The offset of the start of the BIOS image in flash. This value is platform specific
 227   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 228   //
 229   ((WINBOND_W25X32_SIZE >= FLASH_SIZE) ? WINBOND_W25X32_SIZE - FLASH_SIZE : (UINTN) (-1)),
 230
 231   //
 232   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 233   //
 234   FLASH_SIZE
 235   },
 236   {
 237   SF_VENDOR_ID_WINBOND,     // VendorId
 238   SF_DEVICE_ID0_W25XXX,     // DeviceId 0
 239   SF_DEVICE_ID1_W25X64,     // DeviceId 1
 240   {
 241     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 242     SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register
 243   },
 244   {
 245     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },     // Opcode 0: Read ID
 246     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData      },     // Opcode 1: Read
 247     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },     // Opcode 2: Read Status Register
 248     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 249     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },     // Opcode 4: Sector Erase (4KB)
 250     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },     // Opcode 5: Block Erase (64KB
 251     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},    // Opcode 6: Byte Program
 252     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },     // Opcode 7: Write Status Register
 253   },
 254
 255   //
 256   // The offset of the start of the BIOS image in flash. This value is platform specific
 257   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 258   //
 259   ((WINBOND_W25X64_SIZE >= FLASH_SIZE) ? WINBOND_W25X64_SIZE - FLASH_SIZE : (UINTN) (-1)),
 260
 261   //
 262   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 263   //
 264   FLASH_SIZE
 265   },
 266   {
 267   SF_VENDOR_ID_WINBOND,     // VendorId
 268   SF_DEVICE_ID0_W25QXX,     // DeviceId 0
 269   SF_DEVICE_ID1_W25Q128,    // DeviceId 1
 270   {
 271     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 272     SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register
 273   },
 274   {
 275     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
 276     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
 277     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
 278     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 279     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
 280     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (64KB
 281     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 282     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
 283   },
 284
 285   //
 286   // The offset of the start of the BIOS image in flash. This value is platform specific
 287   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 288   //
 289   ((WINBOND_W25Q128_SIZE >= FLASH_SIZE) ? WINBOND_W25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),
 290
 291   //
 292   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 293   //
 294   FLASH_SIZE
 295   },
 296   {
 297   SF_VENDOR_ID_MACRONIX,    // VendorId
 298   SF_DEVICE_ID0_MX25LXX,    // DeviceId 0
 299   SF_DEVICE_ID1_MX25L16,    // DeviceId 1
 300   {
 301     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 302     SF_INST_EWSR            // Prefix Opcode 1:  Write Enable (this part doesn't support EWSR).
 303   },
 304   {
 305     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 306     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 307     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 308     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 309     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 310     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 311     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 312     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 313   },
 314
 315   //
 316   // The offset of the start of the BIOS image in flash. This value is platform specific
 317   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 318   //
 319   ((MACRONIX_MX25L16_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L16_SIZE - FLASH_SIZE : (UINTN) (-1)),
 320
 321   //
 322   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 323   //
 324   FLASH_SIZE
 325   },
 326   {
 327   SF_VENDOR_ID_MACRONIX,    // VendorId
 328   SF_DEVICE_ID0_MX25LXX,    // DeviceId 0
 329   SF_DEVICE_ID1_MX25L32,    // DeviceId 1
 330   {
 331     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 332     SF_INST_EWSR            // Prefix Opcode 1:  Write Enable (this part doesn't support EWSR).
 333   },
 334   {
 335     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 336     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 337     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 338     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 339     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 340     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 341     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 342     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 343   },
 344
 345   //
 346   // The offset of the start of the BIOS image in flash. This value is platform specific
 347   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 348   //
 349   ((MACRONIX_MX25L32_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L32_SIZE - FLASH_SIZE : (UINTN) (-1)),
 350
 351   //
 352   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 353   //
 354   FLASH_SIZE
 355   },
 356   {
 357   SF_VENDOR_ID_MACRONIX,    // VendorId
 358   SF_DEVICE_ID0_MX25LXX,    // DeviceId 0
 359   SF_DEVICE_ID1_MX25L64,    // DeviceId 1
 360   {
 361     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 362     SF_INST_EWSR            // Prefix Opcode 1:  Write Enable (this part doesn't support EWSR)
 363   },
 364   {
 365     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 366     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 367     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 368     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 369     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 370     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 371     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 372     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 373   },
 374
 375   //
 376   // The offset of the start of the BIOS image in flash. This value is platform specific
 377   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 378   //
 379   ((MACRONIX_MX25L64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L64_SIZE - FLASH_SIZE : (UINTN) (-1)),
 380
 381   //
 382   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 383   //
 384   FLASH_SIZE
 385   },
 386   {
 387   SF_VENDOR_ID_MACRONIX,    // VendorId
 388   SF_DEVICE_ID0_MX25LXX,    // DeviceId 0
 389   SF_DEVICE_ID1_MX25L128,   // DeviceId 1
 390   {
 391     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 392     SF_INST_EWSR            // Prefix Opcode 1:  Write Enable (this part doesn't support EWSR)
 393   },
 394   {
 395     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 396     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 397     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 398     {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters
 399     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 400     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 401     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 402     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 403   },
 404
 405   //
 406   // The offset of the start of the BIOS image in flash. This value is platform specific
 407   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 408   //
 409   ((MACRONIX_MX25L128_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L128_SIZE - FLASH_SIZE : (UINTN) (-1)),
 410
 411   //
 412   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 413   //
 414   FLASH_SIZE
 415   },
 416   {
 417   SF_VENDOR_ID_MACRONIX,          // VendorId
 418   SF_DEVICE_ID0_MX25UXX,          // DeviceId 0
 419   SF_DEVICE_ID1_MX25U6435F,   // DeviceId 1
 420   {
 421     SF_INST_WREN,                     // Prefix Opcode 0: Write Enable
 422     SF_INST_EWSR                          // Prefix Opcode 1:  Write Enable (this part doesn't support EWSR)
 423   },
 424   {
 425     {EnumSpiOpcodeReadNoAddr,   SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId              },              // Opcode 0: Read ID
 426     {EnumSpiOpcodeRead,                 SF_INST_READ,                   EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 427     {EnumSpiOpcodeReadNoAddr,   SF_INST_RDSR,                   EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 428     {EnumSpiOpcodeRead,                 SF_INST_SFDP,                   EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},        // Opcode 3: Serial Flash Discovery Parameters
 429     {EnumSpiOpcodeWrite,                SF_INST_SERASE,                 EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 430     {EnumSpiOpcodeWrite,                SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 431     {EnumSpiOpcodeWrite,                SF_INST_PROG,                   EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},         // Opcode 6: Byte Program
 432     {EnumSpiOpcodeWriteNoAddr,  SF_INST_WRSR,                   EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 433   },
 434
 435   //
 436   // The offset of the start of the BIOS image in flash. This value is platform specific
 437   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 438   //
 439   ((MACRONIX_MX25U64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25U64_SIZE - FLASH_SIZE : (UINTN) (-1)),
 440
 441   //
 442   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 443   //
 444   FLASH_SIZE
 445   },
 446   {
 447   SF_VENDOR_ID_SST,         // VendorId
 448   SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0
 449   SF_DEVICE_ID1_SST25VF016B,// DeviceId 1
 450   {
 451     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 452     SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register
 453   },
 454   {
 455     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
 456     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle20MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
 457     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
 458     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable      },     // Opcode 3: Write Disable
 459     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
 460     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (32KB)
 461     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 462     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
 463   },
 464
 465   //
 466   // The offset of the start of the BIOS image in flash. This value is platform specific
 467   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 468   //
 469   ((SST_SST25VF016B_SIZE >= FLASH_SIZE) ? SST_SST25VF016B_SIZE - FLASH_SIZE : (UINTN) (-1)),
 470
 471   //
 472   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 473   //
 474   FLASH_SIZE
 475   },
 476   {
 477   SF_VENDOR_ID_SST,         // VendorId
 478   SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0
 479   SF_DEVICE_ID1_SST25VF064C,// DeviceId 1
 480   {
 481     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 482     SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register
 483   },
 484   {
 485     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID
 486     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle20MHz, EnumSpiOperationReadData          },     // Opcode 1: Read
 487     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register
 488     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable      },     // Opcode 3: Write Disable
 489     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)
 490     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (32KB)
 491     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 492     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register
 493   },
 494
 495   //
 496   // The offset of the start of the BIOS image in flash. This value is platform specific
 497   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 498   //
 499   ((SST_SST25VF064C_SIZE >= FLASH_SIZE) ? SST_SST25VF064C_SIZE - FLASH_SIZE : (UINTN) (-1)),
 500
 501   //
 502   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 503   //
 504   FLASH_SIZE
 505   },
 506   {
 507         //
 508         // Minnow2 SPI type
 509         //
 510   SF_VENDOR_ID_NUMONYX,     // VendorId
 511   SF_DEVICE_ID0_N25Q064,    // DeviceId 0
 512   SF_DEVICE_ID1_N25Q064,    // DeviceId 1
 513   {
 514     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 515     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
 516   },
 517   {
 518     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle20MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 519     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle20MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 520     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle20MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 521     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle20MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 522     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle20MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 523     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle20MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 524     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle20MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 525     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle20MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 526   },
 527
 528   //
 529   // The offset of the start of the BIOS image in flash. This value is platform specific
 530   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 531   //
 532   ((NUMONYX_N25Q064_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q064_SIZE - FLASH_SIZE : (UINTN) (-1)),
 533
 534   //
 535   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 536   //
 537   FLASH_SIZE
 538   },
 539   {
 540   SF_VENDOR_ID_NUMONYX,     // VendorId
 541   SF_DEVICE_ID0_M25PXXX,    // DeviceId 0
 542   SF_DEVICE_ID1_M25PX16,    // DeviceId 1
 543   {
 544     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 545     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
 546   },
 547   {
 548     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 549     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 550     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 551     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 552     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 553     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 554     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 555     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 556   },
 557
 558   //
 559   // The offset of the start of the BIOS image in flash. This value is platform specific
 560   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 561   //
 562   ((NUMONYX_M25PX16_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX16_SIZE - FLASH_SIZE : (UINTN) (-1)),
 563
 564   //
 565   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 566   //
 567   FLASH_SIZE
 568   },
 569   {
 570   SF_VENDOR_ID_NUMONYX,     // VendorId
 571   SF_DEVICE_ID0_N25QXXX,    // DeviceId 0
 572   SF_DEVICE_ID1_N25Q032,    // DeviceId 1
 573   {
 574     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 575     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
 576   },
 577   {
 578     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },        // Opcode 0: Read ID
 579     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },        // Opcode 1: Read
 580     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },        // Opcode 2: Read Status Register
 581     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 582     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 583     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 584     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},   // Opcode 6: Byte Program
 585     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 586   },
 587
 588   //
 589   // The offset of the start of the BIOS image in flash. This value is platform specific
 590   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 591   //
 592   ((NUMONYX_N25Q032_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q032_SIZE - FLASH_SIZE : (UINTN) (-1)),
 593
 594   //
 595   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 596   //
 597   FLASH_SIZE
 598   },
 599   {
 600   SF_VENDOR_ID_NUMONYX,     // VendorId
 601   SF_DEVICE_ID0_M25PXXX,    // DeviceId 0
 602   SF_DEVICE_ID1_M25PX32,    // DeviceId 1
 603   {
 604     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 605     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
 606   },
 607   {
 608     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 609     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 610     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 611     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 612     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 613     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 614     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 615     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 616   },
 617
 618   //
 619   // The offset of the start of the BIOS image in flash. This value is platform specific
 620   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 621   //
 622   ((NUMONYX_M25PX32_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX32_SIZE - FLASH_SIZE : (UINTN) (-1)),
 623
 624   //
 625   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 626   //
 627   FLASH_SIZE
 628   },
 629   {
 630   SF_VENDOR_ID_NUMONYX,     // VendorId
 631   SF_DEVICE_ID0_M25PXXX,    // DeviceId 0
 632   SF_DEVICE_ID1_M25PX64,    // DeviceId 1
 633   {
 634     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 635     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
 636   },
 637   {
 638     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 639     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 640     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 641     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 642     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 643     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 644     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 645     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 646   },
 647
 648   //
 649   // The offset of the start of the BIOS image in flash. This value is platform specific
 650   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 651   //
 652   ((NUMONYX_M25PX64_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX64_SIZE - FLASH_SIZE : (UINTN) (-1)),
 653
 654   //
 655   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 656   //
 657   FLASH_SIZE
 658   },
 659   {
 660   SF_VENDOR_ID_NUMONYX,     // VendorId
 661   SF_DEVICE_ID0_N25QXXX,    // DeviceId 0
 662   SF_DEVICE_ID1_N25Q128,    // DeviceId 1
 663   {
 664     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 665     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
 666   },
 667   {
 668     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 669     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 670     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 671     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 672     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 673     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 674     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 675     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 676   },
 677
 678   //
 679   // The offset of the start of the BIOS image in flash. This value is platform specific
 680   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 681   //
 682   ((NUMONYX_N25Q128_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),
 683
 684   //
 685   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 686   //
 687   FLASH_SIZE
 688   },
 689   {
 690   SF_VENDOR_ID_EON,         // VendorId
 691   SF_DEVICE_ID0_EN25QXX,    // DeviceId 0
 692   SF_DEVICE_ID1_EN25Q16,    // DeviceId 1
 693   {
 694     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 695     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
 696   },
 697   {
 698     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 699     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 700     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 701     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 702     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 703     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 704     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 705     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 706   },
 707
 708   //
 709   // The offset of the start of the BIOS image in flash. This value is platform specific
 710   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 711   //
 712   ((EON_EN25Q16_SIZE >= FLASH_SIZE) ? EON_EN25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),
 713
 714   //
 715   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 716   //
 717   FLASH_SIZE
 718   },
 719   {
 720   SF_VENDOR_ID_EON,         // VendorId
 721   SF_DEVICE_ID0_EN25QXX,    // DeviceId 0
 722   SF_DEVICE_ID1_EN25Q32,    // DeviceId 1
 723   {
 724     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 725     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
 726   },
 727   {
 728     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 729     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 730     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 731     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 732     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 733     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 734     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 735     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 736   },
 737
 738   //
 739   // The offset of the start of the BIOS image in flash. This value is platform specific
 740   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 741   //
 742   ((EON_EN25Q32_SIZE >= FLASH_SIZE) ? EON_EN25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),
 743
 744   //
 745   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 746   //
 747   FLASH_SIZE
 748   },
 749   {
 750   SF_VENDOR_ID_EON,         // VendorId
 751   SF_DEVICE_ID0_EN25QXX,    // DeviceId 0
 752   SF_DEVICE_ID1_EN25Q64,    // DeviceId 1
 753   {
 754     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 755     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).
 756   },
 757   {
 758     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 759     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 760     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 761     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 762     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 763     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 764     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 765     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 766   },
 767
 768   //
 769   // The offset of the start of the BIOS image in flash. This value is platform specific
 770   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 771   //
 772   ((EON_EN25Q64_SIZE >= FLASH_SIZE) ? EON_EN25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),
 773
 774   //
 775   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 776   //
 777   FLASH_SIZE
 778   },
 779   {
 780   SF_VENDOR_ID_EON,         // VendorId
 781   SF_DEVICE_ID0_EN25QXX,    // DeviceId 0
 782   SF_DEVICE_ID1_EN25Q128,   // DeviceId 1
 783   {
 784     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 785     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
 786   },
 787   {
 788     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 789     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 790     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 791     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 792     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 793     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 794     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 795     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 796   },
 797
 798   //
 799   // The offset of the start of the BIOS image in flash. This value is platform specific
 800   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 801   //
 802   ((EON_EN25Q128_SIZE >= FLASH_SIZE) ? EON_EN25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),
 803
 804   //
 805   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 806   //
 807   FLASH_SIZE
 808   },
 809   {
 810   SF_VENDOR_ID_AMIC,        // VendorId
 811   SF_DEVICE_ID0_A25L016,    // DeviceId 0
 812   SF_DEVICE_ID1_A25L016,    // DeviceId 1
 813   {
 814     SF_INST_WREN,           // Prefix Opcode 0: Write Enable
 815     SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)
 816   },
 817   {
 818     {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID
 819     {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData      },      // Opcode 1: Read
 820     {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register
 821     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable
 822     {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)
 823     {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB
 824     {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program
 825     {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register
 826   },
 827
 828   //
 829   // The offset of the start of the BIOS image in flash. This value is platform specific
 830   // and depends on the system flash map. If BIOS size is bigger than flash return -1.
 831   //
 832   ((AMIC_A25L16_SIZE >= FLASH_SIZE) ? AMIC_A25L16_SIZE - FLASH_SIZE : (UINTN) (-1)),
 833
 834   //
 835   // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.
 836   //
 837   FLASH_SIZE
 838   }
 839 };
 840