projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /*++\r |
| 2 | \r | |
| 3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
| 4 | \r\r | |
| 5 | This program and the accompanying materials are licensed and made available under\r\r | |
| 6 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
| 7 | The full text of the license may be found at \r\r | |
| 8 | http://opensource.org/licenses/bsd-license.php. \r\r | |
| 9 | \r\r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
| 12 | \r\r | |
| 13 | \r | |
| 14 | Module Name:\r | |
| 15 | \r | |
| 16 | Configuration.h\r | |
| 17 | \r | |
| 18 | Abstract:\r | |
| 19 | \r | |
| 20 | Driver configuration include file\r | |
| 21 | \r | |
| 22 | \r | |
| 23 | --*/\r | |
| 24 | \r | |
| 25 | #ifndef _CONFIGURATION_H\r | |
| 26 | #define _CONFIGURATION_H\r | |
| 27 | \r | |
| 28 | #define EFI_NON_DEVICE_CLASS 0x00\r | |
| 29 | #define EFI_DISK_DEVICE_CLASS 0x01\r | |
| 30 | #define EFI_VIDEO_DEVICE_CLASS 0x02\r | |
| 31 | #define EFI_NETWORK_DEVICE_CLASS 0x04\r | |
| 32 | #define EFI_INPUT_DEVICE_CLASS 0x08\r | |
| 33 | #define EFI_ON_BOARD_DEVICE_CLASS 0x10\r | |
| 34 | #define EFI_OTHER_DEVICE_CLASS 0x20\r | |
| 35 | \r | |
| 36 | //\r | |
| 37 | // Processor labels\r | |
| 38 | //\r | |
| 39 | #define PROCESSOR_HT_MODE 0x0100\r | |
| 40 | #define PROCESSOR_FSB_MULTIPLIER 0x0101\r | |
| 41 | #define PROCESSOR_MULTIPLIER_OVERRIDE_CONTROL 0x0211\r | |
| 42 | \r | |
| 43 | //\r | |
| 44 | // Memory labels\r | |
| 45 | //\r | |
| 46 | #define MEMORY_SLOT1_SPEED 0x0200\r | |
| 47 | #define MEMORY_SLOT2_SPEED 0x0201\r | |
| 48 | #define MEMORY_SLOT3_SPEED 0x0202\r | |
| 49 | #define MEMORY_SLOT4_SPEED 0x0203\r | |
| 50 | #define END_MEMORY_SLOT_SPEED 0x020F\r | |
| 51 | #define PERFORMANCE_MEMORY_PROFILE_CONTROL 0x0210\r | |
| 52 | #define UCLK_RATIO_CONTROL 0x0212\r | |
| 53 | \r | |
| 54 | //\r | |
| 55 | // Language label\r | |
| 56 | //\r | |
| 57 | #define FRONT_PAGE_ITEM_LANGUAGE 0x300\r | |
| 58 | \r | |
| 59 | //\r | |
| 60 | // Boot Labels\r | |
| 61 | //\r | |
| 62 | #define BOOT_DEVICE_PRIORITY_BEGIN 0x0400\r | |
| 63 | #define BOOT_DEVICE_PRIORITY_END 0x0401\r | |
| 64 | #define BOOT_OPTICAL_DEVICE_BEGIN 0x0410\r | |
| 65 | #define BOOT_OPTICAL_DEVICE_END 0x0411\r | |
| 66 | #define BOOT_REMOVABLE_DEVICE_BEGIN 0x0420\r | |
| 67 | #define BOOT_REMOVABLE_DEVICE_END 0x0421\r | |
| 68 | #define BOOT_PXE_DEVICE_BEGIN 0x0430\r | |
| 69 | #define BOOT_PXE_DEVICE_END 0x0431\r | |
| 70 | #define BOOT_MENU_TYPE_BEGIN 0x0440\r | |
| 71 | #define BOOT_MENU_TYPE_END 0x0441\r | |
| 72 | #define BOOT_USB_DEVICE_BEGIN 0x0450\r | |
| 73 | #define BOOT_USB_DEVICE_END 0x0451\r | |
| 74 | #define BOOT_USB_FIRST_BEGIN 0x0460\r | |
| 75 | #define BOOT_USB_FIRST_END 0x0461\r | |
| 76 | #define BOOT_UEFI_BEGIN 0x0470\r | |
| 77 | #define BOOT_UEFI_END 0x0471\r | |
| 78 | #define BOOT_USB_UNAVAILABLE_BEGIN 0x0480\r | |
| 79 | #define BOOT_USB_UNAVAILABLE_END 0x0481\r | |
| 80 | #define BOOT_CD_UNAVAILABLE_BEGIN 0x0490\r | |
| 81 | #define BOOT_CD_UNAVAILABLE_END 0x0491\r | |
| 82 | #define BOOT_FDD_UNAVAILABLE_BEGIN 0x04A0\r | |
| 83 | #define BOOT_FDD_UNAVAILABLE_END 0x04A1\r | |
| 84 | #define BOOT_DEVICE_PRIORITY_DEFAULT_BEGIN 0x04B0\r | |
| 85 | #define BOOT_DEVICE_PRIORITY_DEFAULT_END 0x04B1\r | |
| 86 | #define BOOT_USB_OPT_LABEL_BEGIN 0x04C0\r | |
| 87 | #define BOOT_USB_OPT_LABEL_END 0x04C1\r | |
| 88 | \r | |
| 89 | #define VAR_EQ_ADMIN_NAME 0x0041 // A\r | |
| 90 | #define VAR_EQ_ADMIN_DECIMAL_NAME L"65"\r | |
| 91 | #define VAR_EQ_VIEW_ONLY_NAME 0x0042 // B\r | |
| 92 | #define VAR_EQ_VIEW_ONLY_DECIMAL_NAME L"66"\r | |
| 93 | #define VAR_EQ_CONFIG_MODE_NAME 0x0043 // C\r | |
| 94 | #define VAR_EQ_CONFIG_MODE_DECIMAL_NAME L"67"\r | |
| 95 | #define VAR_EQ_CPU_EE_NAME 0x0045 // E\r | |
| 96 | #define VAR_EQ_CPU_EE_DECIMAL_NAME L"69"\r | |
| 97 | #define VAR_EQ_FLOPPY_MODE_NAME 0x0046 // F\r | |
| 98 | #define VAR_EQ_FLOPPY_MODE_DECIMAL_NAME L"70"\r | |
| 99 | #define VAR_EQ_HT_MODE_NAME 0x0048 // H\r | |
| 100 | #define VAR_EQ_HT_MODE_DECIMAL_NAME L"72"\r | |
| 101 | #define VAR_EQ_AHCI_MODE_NAME 0x0049 // I\r | |
| 102 | #define VAR_EQ_AHCI_MODE_DECIMAL_NAME L"73"\r | |
| 103 | #define VAR_EQ_CPU_LOCK_NAME 0x004C // L\r | |
| 104 | #define VAR_EQ_CPU_LOCK_DECIMAL_NAME L"76"\r | |
| 105 | #define VAR_EQ_NX_MODE_NAME 0x004E // N\r | |
| 106 | #define VAR_EQ_NX_MODE_DECIMAL_NAME L"78"\r | |
| 107 | #define VAR_EQ_RAID_MODE_NAME 0x0052 // R\r | |
| 108 | #define VAR_EQ_RAID_MODE_DECIMAL_NAME L"82"\r | |
| 109 | #define VAR_EQ_1394_MODE_NAME 0x0054 // T\r | |
| 110 | #define VAR_EQ_1394_MODE_DECIMAL_NAME L"84"\r | |
| 111 | #define VAR_EQ_USER_NAME 0x0055 // U\r | |
| 112 | #define VAR_EQ_USER_DECIMAL_NAME L"85"\r | |
| 113 | #define VAR_EQ_VIDEO_MODE_NAME 0x0056 // V\r | |
| 114 | #define VAR_EQ_VIDEO_MODE_DECIMAL_NAME L"86"\r | |
| 115 | #define VAR_EQ_LEGACY_FP_AUDIO_NAME 0x0057 // W\r | |
| 116 | #define VAR_EQ_LEGACY_FP_AUDIO_DECIMAL_NAME L"87"\r | |
| 117 | #define VAR_EQ_EM64T_CAPABLE_NAME 0x0058 // X\r | |
| 118 | #define VAR_EQ_EM64T_CAPABLE_DECIMAL_NAME L"88"\r | |
| 119 | #define VAR_EQ_BOARD_FORMFACTOR_NAME 0x0059 // Y\r | |
| 120 | #define VAR_EQ_BOARD_FORMFACTOR_DECIMAL_NAME L"89"\r | |
| 121 | #define VAR_EQ_UNCON_CPU_NAME 0x005B // ??\r | |
| 122 | #define VAR_EQ_UNCON_CPU_DECIMAL_NAME L"91"\r | |
| 123 | #define VAR_EQ_VAR_HIDE_NAME 0x005C // ??\r | |
| 124 | #define VAR_EQ_VAR_HIDE_DECIMAL_NAME L"92"\r | |
| 125 | #define VAR_EQ_ENERGY_LAKE_NAME 0x005D // ??\r | |
| 126 | #define VAR_EQ_ENERGY_LAKE_DECIMAL_NAME L"93"\r | |
| 127 | #define VAR_EQ_TPM_MODE_NAME 0x005E // ^\r | |
| 128 | #define VAR_EQ_TPM_MODE_DECIMAL_NAME L"94"\r | |
| 129 | #define VAR_EQ_DISCRETE_SATA_NAME 0x005F // ??\r | |
| 130 | #define VAR_EQ_DISCRETE_SATA_DECIMAL_NAME L"95"\r | |
| 131 | #define VAR_EQ_ROEM_SKU_NAME 0x0060 // ??\r | |
| 132 | #define VAR_EQ_ROEM_SKU_DECIMAL_NAME L"96"\r | |
| 133 | #define VAR_EQ_AMTSOL_MODE_NAME 0x0061 // ??\r | |
| 134 | #define VAR_EQ_AMTSOL_MODE_DECIMAL_NAME L"97"\r | |
| 135 | #define VAR_EQ_NO_PEG_MODE_NAME 0x0062 // ??\r | |
| 136 | #define VAR_EQ_NO_PEG_MODE_DECIMAL_NAME L"98"\r | |
| 137 | #define VAR_EQ_SINGLE_PROCESSOR_MODE_NAME 0x0063 // ??\r | |
| 138 | #define VAR_EQ_SINGLE_PROCESSOR_MODE_DECIMAL_NAME L"99"\r | |
| 139 | #define VAR_EQ_FLOPPY_HIDE_NAME 0x0064 // ??\r | |
| 140 | #define VAR_EQ_FLOPPY_HIDE_DECIMAL_NAME L"100"\r | |
| 141 | #define VAR_EQ_SERIAL_HIDE_NAME 0x0065 // ??\r | |
| 142 | #define VAR_EQ_SERIAL_HIDE_DECIMAL_NAME L"101"\r | |
| 143 | #define VAR_EQ_GV3_CAPABLE_NAME 0x0066 // f\r | |
| 144 | #define VAR_EQ_GV3_CAPABLE_DECIMAL_NAME L"102"\r | |
| 145 | #define VAR_EQ_2_MEMORY_NAME 0x0067 // ??\r | |
| 146 | #define VAR_EQ_2_MEMORY_DECIMAL_NAME L"103"\r | |
| 147 | #define VAR_EQ_2_SATA_NAME 0x0068 // ??\r | |
| 148 | #define VAR_EQ_2_SATA_DECIMAL_NAME L"104"\r | |
| 149 | #define VAR_EQ_NEC_SKU_NAME 0x0069 // ??\r | |
| 150 | #define VAR_EQ_NEC_SKU_DECIMAL_NAME L"105"\r | |
| 151 | #define VAR_EQ_AMT_MODE_NAME 0x006A // ??\r | |
| 152 | #define VAR_EQ_AMT_MODE_DECIMAL_NAME L"106"\r | |
| 153 | #define VAR_EQ_LCLX_SKU_NAME 0x006B // ??\r | |
| 154 | #define VAR_EQ_LCLX_SKU_DECIMAL_NAME L"107"\r | |
| 155 | #define VAR_EQ_VT_NAME 0x006C\r | |
| 156 | #define VAR_EQ_VT_DECIMAL_NAME L"108"\r | |
| 157 | #define VAR_EQ_LT_NAME 0x006D\r | |
| 158 | #define VAR_EQ_LT_DECIMAL_NAME L"109"\r | |
| 159 | #define VAR_EQ_ITK_BIOS_MOD_NAME 0x006E // ??\r | |
| 160 | #define VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME L"110"\r | |
| 161 | #define VAR_EQ_HPET_NAME 0x006F\r | |
| 162 | #define VAR_EQ_HPET_DECIMAL_NAME L"111"\r | |
| 163 | #define VAR_EQ_ADMIN_INSTALLED_NAME 0x0070 // ??\r | |
| 164 | #define VAR_EQ_ADMIN_INSTALLED_DECIMAL_NAME L"112"\r | |
| 165 | #define VAR_EQ_USER_INSTALLED_NAME 0x0071 // ??\r | |
| 166 | #define VAR_EQ_USER_INSTALLED_DECIMAL_NAME L"113"\r | |
| 167 | #define VAR_EQ_CPU_CMP_NAME 0x0072\r | |
| 168 | #define VAR_EQ_CPU_CMP_DECIMAL_NAME L"114"\r | |
| 169 | #define VAR_EQ_LAN_MAC_ADDR_NAME 0x0073 // ??\r | |
| 170 | #define VAR_EQ_LAN_MAC_ADDR_DECIMAL_NAME L"115"\r | |
| 171 | #define VAR_EQ_PARALLEL_HIDE_NAME 0x0074 // ??\r | |
| 172 | #define VAR_EQ_PARALLEL_HIDE_DECIMAL_NAME L"116"\r | |
| 173 | #define VAR_EQ_AFSC_SETUP_NAME 0x0075\r | |
| 174 | #define VAR_EQ_AFSC_SETUP_DECIMAL_NAME L"117"\r | |
| 175 | #define VAR_EQ_MINICARD_MODE_NAME 0x0076 //\r | |
| 176 | #define VAR_EQ_MINICARD_MODE_DECIMAL_NAME L"118"\r | |
| 177 | #define VAR_EQ_VIDEO_IGD_NAME 0x0077 //\r | |
| 178 | #define VAR_EQ_VIDEO_IGD_DECIMAL_NAME L"119"\r | |
| 179 | #define VAR_EQ_ALWAYS_ENABLE_LAN_NAME 0x0078 //\r | |
| 180 | #define VAR_EQ_ALWAYS_ENABLE_LAN_DECIMAL_NAME L"120"\r | |
| 181 | #define VAR_EQ_LEGACY_FREE_NAME 0x0079 //\r | |
| 182 | #define VAR_EQ_LEGACY_FREE_DECIMAL_NAME L"121"\r | |
| 183 | #define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_NAME 0x007A\r | |
| 184 | #define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_DECIMAL_NAME L"122"\r | |
| 185 | #define VAR_EQ_CPU_FSB_NAME 0x007B //\r | |
| 186 | #define VAR_EQ_CPU_FSB_DECIMAL_NAME L"123"\r | |
| 187 | #define VAR_EQ_SATA0_DEVICE_NAME 0x007C //\r | |
| 188 | #define VAR_EQ_SATA0_DVICE_DECIMAL_NAME L"124"\r | |
| 189 | #define VAR_EQ_SATA1_DEVICE_NAME 0x007D //\r | |
| 190 | #define VAR_EQ_SATA1_DVICE_DECIMAL_NAME L"125"\r | |
| 191 | #define VAR_EQ_SATA2_DEVICE_NAME 0x007E //\r | |
| 192 | #define VAR_EQ_SATA2_DVICE_DECIMAL_NAME L"126"\r | |
| 193 | #define VAR_EQ_SATA3_DEVICE_NAME 0x007F //\r | |
| 194 | #define VAR_EQ_SATA3_DVICE_DECIMAL_NAME L"127"\r | |
| 195 | #define VAR_EQ_SATA4_DEVICE_NAME 0x0080 //\r | |
| 196 | #define VAR_EQ_SATA4_DVICE_DECIMAL_NAME L"128"\r | |
| 197 | #define VAR_EQ_SATA5_DEVICE_NAME 0x0081 //\r | |
| 198 | #define VAR_EQ_SATA5_DVICE_DECIMAL_NAME L"129"\r | |
| 199 | #define VAR_EQ_TPM_STATUS_NAME 0x0082 // To indicate if TPM is enabled\r | |
| 200 | #define VAR_EQ_TPM_STATUS_DECIMAL_NAME L"130"\r | |
| 201 | #define VAR_EQ_HECETA6E_PECI_CPU_NAME 0x0083\r | |
| 202 | #define VAR_EQ_HECETA6E_PECI_CPU_DECIMAL_NAME L"131"\r | |
| 203 | #define VAR_EQ_USB_2_NAME 0x0084 //\r | |
| 204 | #define VAR_EQ_USB_2_DECIMAL_NAME L"132"\r | |
| 205 | #define VAR_EQ_RVP_NAME 0x0085 //\r | |
| 206 | #define VAR_EQ_RVP_DECIMAL_NAME L"133"\r | |
| 207 | #define VAR_EQ_ECIR_NAME 0x0086\r | |
| 208 | #define VAR_EQ_ECIR_DECIMAL_NAME L"134"\r | |
| 209 | #define VAR_EQ_WAKONS5KB_NAME 0x0087\r | |
| 210 | #define VAR_EQ_WAKONS5KB_DECIMAL_NAME L"135"\r | |
| 211 | #define VAR_EQ_HDAUDIOLINKBP_NAME 0x0088\r | |
| 212 | #define VAR_EQ_HDAUDIOLINKBP_DECIMAL_NAME L"136"\r | |
| 213 | #define VAR_EQ_FINGERPRINT_NAME 0x0089\r | |
| 214 | #define VAR_EQ_FINGERPRINT_DECIMAL_NAME L"137"\r | |
| 215 | #define VAR_EQ_BLUETOOTH_NAME 0x008A\r | |
| 216 | #define VAR_EQ_BLUETOOTH_DECIMAL_NAME L"138"\r | |
| 217 | #define VAR_EQ_WLAN_NAME 0x008B\r | |
| 218 | #define VAR_EQ_WLAN_DECIMAL_NAME L"139"\r | |
| 219 | #define VAR_EQ_1_PATA_NAME 0x008C\r | |
| 220 | #define VAR_EQ_1_PATA_DECIMAL_NAME L"140"\r | |
| 221 | #define VAR_EQ_ACTIVE_PROCESSOR_CORE_NAME 0x008D\r | |
| 222 | #define VAR_EQ_ACTIVE_PROCESSOR_CORE_DECIMAL_NAME L"141"\r | |
| 223 | #define VAR_EQ_TURBO_MODE_CAP_NAME 0x008E\r | |
| 224 | #define VAR_EQ_TURBO_MODE_CAP_DECIMAL_NAME L"142"\r | |
| 225 | #define VAR_EQ_XE_MODE_CAP_NAME 0x008F\r | |
| 226 | #define VAR_EQ_XE_MODE_CAP_DECIMAL_NAME L"143"\r | |
| 227 | #define VAR_EQ_NPI_QPI_VOLTAGE_NAME 0x0090\r | |
| 228 | #define VAR_EQ_NPI_QPI_VOLTAGE_DECIMAL_NAME L"144"\r | |
| 229 | #define VAR_EQ_PRE_PROD_NON_XE_NAME 0x0091\r | |
| 230 | #define VAR_EQ_PRE_PROD_NON_XE_DECIMAL_NAME L"145"\r | |
| 231 | #define VAR_EQ_2_C0_MEMORY_NAME 0x0092 // ??\r | |
| 232 | #define VAR_EQ_2_C0_MEMORY_DECIMAL_NAME L"146"\r | |
| 233 | #define VAR_EQ_LVDS_NAME 0x0093\r | |
| 234 | #define VAR_EQ_LVDS_DECIMAL_NAME L"147"\r | |
| 235 | #define VAR_EQ_USB_OPTION_SHOW_NAME 0x0094\r | |
| 236 | #define VAR_EQ_USB_OPTION_SHOW_DECIMAL_NAME L"148"\r | |
| 237 | #define VAR_EQ_HDD_MASTER_INSTALLED_NAME 0x0095\r | |
| 238 | #define VAR_EQ_HDD_MASTER_INSTALLED_DECIMAL_NAME L"149"\r | |
| 239 | #define VAR_EQ_HDD_USER_INSTALLED_NAME 0x0096\r | |
| 240 | #define VAR_EQ_HDD_USER_INSTALLED_DECIMAL_NAME L"150"\r | |
| 241 | #define VAR_EQ_PS2_HIDE_NAME 0x0097 // ??\r | |
| 242 | #define VAR_EQ_PS2_HIDE_DECIMAL_NAME L"151"\r | |
| 243 | #define VAR_EQ_VIDEO_SLOT_NAME 0x0098\r | |
| 244 | #define VAR_EQ_VIDEO_SLOT_DECIMAL_NAME L"152"\r | |
| 245 | #define VAR_EQ_HDMI_SLOT_NAME 0x0099\r | |
| 246 | #define VAR_EQ_HDMI_SLOT_DECIMAL_NAME L"153"\r | |
| 247 | #define VAR_EQ_SERIAL2_HIDE_NAME 0x009a\r | |
| 248 | #define VAR_EQ_SERIAL2_HIDE_DECIMAL_NAME L"154"\r | |
| 249 | \r | |
| 250 | \r | |
| 251 | #define VAR_EQ_LVDS_WARNING_HIDE_NAME 0x009e\r | |
| 252 | #define VAR_EQ_LVDS_WARNING_HIDE_DECIMAL_NAME L"158"\r | |
| 253 | \r | |
| 254 | \r | |
| 255 | #define VAR_EQ_MSATA_HIDE_NAME 0x009f\r | |
| 256 | #define VAR_EQ_MSATA_HIDE_DECIMAL_NAME L"159"\r | |
| 257 | \r | |
| 258 | \r | |
| 259 | #define VAR_EQ_PCI_SLOT1_NAME 0x00a0\r | |
| 260 | #define VAR_EQ_PCI_SLOT1_DECIMAL_NAME L"160"\r | |
| 261 | #define VAR_EQ_PCI_SLOT2_NAME 0x00a1\r | |
| 262 | #define VAR_EQ_PCI_SLOT2_DECIMAL_NAME L"161"\r | |
| 263 | \r | |
| 264 | //\r | |
| 265 | // Generic Form Ids\r | |
| 266 | //\r | |
| 267 | #define ROOT_FORM_ID 1\r | |
| 268 | \r | |
| 269 | //\r | |
| 270 | // Advance Page. Do not have to be sequential but have to be unique\r | |
| 271 | //\r | |
| 272 | #define CONFIGURATION_ROOT_FORM_ID 2\r | |
| 273 | #define BOOT_CONFIGURATION_ID 3\r | |
| 274 | #define ONBOARDDEVICE_CONFIGURATION_ID 4\r | |
| 275 | #define DRIVE_CONFIGURATION_ID 5\r | |
| 276 | #define FLOPPY_CONFIGURATION_ID 6\r | |
| 277 | #define EVENT_LOG_CONFIGURATION_ID 7\r | |
| 278 | #define VIDEO_CONFIGURATION_ID 8\r | |
| 279 | #define USB_CONFIGURATION_ID 9\r | |
| 280 | #define HARDWARE_MONITOR_CONFIGURATION_ID 10\r | |
| 281 | #define VIEW_EVENT_LOG_CONFIGURATION_ID 11\r | |
| 282 | #define MEMORY_OVERRIDE_ID 12\r | |
| 283 | #define CHIPSET_CONFIGURATION_ID 13\r | |
| 284 | #define BURN_IN_MODE_ID 14\r | |
| 285 | #define PCI_EXPRESS_ID 15\r | |
| 286 | #define MANAGEMENT_CONFIGURATION_ID 16\r | |
| 287 | #define CPU_CONFIGURATION_ID 17\r | |
| 288 | #define PCI_CONFIGURATION_ID 18\r | |
| 289 | #define SECURITY_CONFIGURATION_ID 19\r | |
| 290 | #define ZIP_CONFIGURATION_ID 20\r | |
| 291 | #define AFSC_FAN_CONTROL_ID 21\r | |
| 292 | #define VFR_FORMID_CSI 22\r | |
| 293 | #define VFR_FORMID_MEMORY 23\r | |
| 294 | #define VFR_FORMID_IOH 24\r | |
| 295 | #define VFR_FORMID_CPU_CSI 25\r | |
| 296 | #define VFR_FORMID_IOH_CONFIG 26\r | |
| 297 | #define VFR_FORMID_VTD 27\r | |
| 298 | #define VFR_FORMID_PCIE_P0 28\r | |
| 299 | #define VFR_FORMID_PCIE_P1 29\r | |
| 300 | #define VFR_FORMID_PCIE_P2 30\r | |
| 301 | #define VFR_FORMID_PCIE_P3 31\r | |
| 302 | #define VFR_FORMID_PCIE_P4 32\r | |
| 303 | #define VFR_FORMID_PCIE_P5 33\r | |
| 304 | #define VFR_FORMID_PCIE_P6 34\r | |
| 305 | #define VFR_FORMID_PCIE_P7 35\r | |
| 306 | #define VFR_FORMID_PCIE_P8 36\r | |
| 307 | #define VFR_FORMID_PCIE_P9 37\r | |
| 308 | #define VFR_FORMID_PCIE_P10 38\r | |
| 309 | #define VFR_FID_SKT0 39\r | |
| 310 | #define VFR_FID_IOH0 40\r | |
| 311 | #define VFR_FID_IOH_DEV_HIDE 41\r | |
| 312 | #define PROCESSOR_OVERRIDES_FORM_ID 42\r | |
| 313 | #define BUS_OVERRIDES_FORM_ID 43\r | |
| 314 | #define REF_OVERRIDES_FORM_ID 44\r | |
| 315 | #define MEMORY_INFORMATION_ID 45\r | |
| 316 | #define LVDS_WARNING_ID 46\r | |
| 317 | #define LVDS_CONFIGURATION_ID 47\r | |
| 318 | #define PCI_SLOT_CONFIGURATION_ID 48\r | |
| 319 | #define HECETA_CONFIGURATION_ID 49\r | |
| 320 | #define LVDS_EXPERT_CONFIGURATION_ID 50\r | |
| 321 | #define PCI_SLOT_7_ID 51\r | |
| 322 | #define PCI_SLOT_6_ID 52\r | |
| 323 | #define PCI_SLOT_5_ID 53\r | |
| 324 | #define PCI_SLOT_4_ID 54\r | |
| 325 | #define PCI_SLOT_3_ID 55\r | |
| 326 | #define PCI_SLOT_2_ID 56\r | |
| 327 | #define PCI_SLOT_1_ID 57\r | |
| 328 | #define BOOT_DISPLAY_ID 58\r | |
| 329 | #define CPU_PWR_CONFIGURATION_ID 59\r | |
| 330 | \r | |
| 331 | #define FSC_CONFIGURATION_ID 60\r | |
| 332 | #define FSC_CPU_TEMPERATURE_FORM_ID 61\r | |
| 333 | #define FSC_VTT_VOLTAGE_FORM_ID 62\r | |
| 334 | #define FSC_FEATURES_CONTROL_ID 63\r | |
| 335 | #define FSC_FAN_CONFIGURATION_ID 64\r | |
| 336 | #define FSC_PROCESSOR_FAN_CONFIGURATION_ID 65\r | |
| 337 | #define FSC_FRONT_FAN_CONFIGURATION_ID 66\r | |
| 338 | #define FSC_REAR_FAN_CONFIGURATION_ID 67\r | |
| 339 | #define FSC_AUX_FAN_CONFIGURATION_ID 68\r | |
| 340 | #define FSC_12_VOLTAGE_FORM_ID 69\r | |
| 341 | #define FSC_5_VOLTAGE_FORM_ID 70\r | |
| 342 | #define FSC_3P3_VOLTAGE_FORM_ID 71\r | |
| 343 | #define FSC_2P5_VOLTAGE_FORM_ID 72\r | |
| 344 | #define FSC_VCC_VOLTAGE_FORM_ID 73\r | |
| 345 | #define FSC_PCH_TEMPERATURE_FORM_ID 74\r | |
| 346 | #define FSC_MEM_TEMPERATURE_FORM_ID 75\r | |
| 347 | #define FSC_VR_TEMPERATURE_FORM_ID 76\r | |
| 348 | #define FSC_3P3STANDBY_VOLTAGE_FORM_ID 77\r | |
| 349 | #define FSC_5BACKUP_VOLTAGE_FORM_ID 78\r | |
| 350 | #define ROOT_MAIN_FORM_ID 79\r | |
| 351 | #define ROOT_BOOT_FORM_ID 80\r | |
| 352 | #define ROOT_MAINTENANCE_ID 81\r | |
| 353 | #define ROOT_POWER_FORM_ID 82\r | |
| 354 | #define ROOT_SECURITY_FORM_ID 83\r | |
| 355 | #define ROOT_PERFORMANCE_FORM_ID 84\r | |
| 356 | #define ROOT_SYSTEM_SETUP_FORM_ID 85\r | |
| 357 | \r | |
| 358 | #define ADDITIONAL_SYSTEM_INFO_FORM_ID 86\r | |
| 359 | \r | |
| 360 | #define THERMAL_CONFIG_FORM_ID 87\r | |
| 361 | \r | |
| 362 | #define PCI_SLOT_CONFIG_LABEL_ID_1 0x300A\r | |
| 363 | #define PCI_SLOT_CONFIG_LABEL_ID_2 0x300B\r | |
| 364 | #define PCI_SLOT_CONFIG_LABEL_ID_3 0x300C\r | |
| 365 | #define PCI_SLOT_CONFIG_LABEL_ID_4 0x300D\r | |
| 366 | #define PCI_SLOT_CONFIG_LABEL_ID_5 0x300E\r | |
| 367 | #define PCI_SLOT_CONFIG_LABEL_ID_6 0x300F\r | |
| 368 | #define PCI_SLOT_CONFIG_LABEL_ID_7 0x3010\r | |
| 369 | #define PCI_SLOT_CONFIG_LABEL_ID_8 0x3011\r | |
| 370 | \r | |
| 371 | //\r | |
| 372 | // Advance Hardware Monitor Callback Keys. Do not have to be sequential but have to be unique\r | |
| 373 | //\r | |
| 374 | #define CONFIGURATION_HARDWARE_CALLBACK_KEY 0x2000\r | |
| 375 | #define ADVANCE_VIDEO_CALLBACK_KEY 0x2001\r | |
| 376 | #define CONFIGURATION_FSC_CALLBACK_KEY 0x2002\r | |
| 377 | #define CONFIGURATION_RESTORE_FAN_CONTROL_CALLBACK_KEY 0x2003\r | |
| 378 | #define CONFIGURATION_LVDS_CALLBACK_KEY 0x2004\r | |
| 379 | #define CONFIGURATION_PREDEFINED_EDID_CALLBACK_KEY 0x2005\r | |
| 380 | #define ADVANCE_LVDS_CALLBACK_KEY 0x2010\r | |
| 381 | \r | |
| 382 | //\r | |
| 383 | // Main Callback Keys. Do not have to be sequential but have to be unique\r | |
| 384 | //\r | |
| 385 | #define MAIN_LANGUAGE_CALLBACK_KEY 0x3000\r | |
| 386 | \r | |
| 387 | //\r | |
| 388 | // Power Hardware Monitor Callback Keys. Do not have to be sequential but have to be unique\r | |
| 389 | //\r | |
| 390 | #define POWER_HARDWARE_CALLBACK_KEY 0x4000\r | |
| 391 | \r | |
| 392 | //\r | |
| 393 | // Performance Callback Keys. Do not have to be sequential but have to be unique\r | |
| 394 | //\r | |
| 395 | #define PROCESSOR_OVERRIDES_CALLBACK_KEY 0x5000\r | |
| 396 | #define PERFORMANCE_CALLBACK_KEY 0x5001\r | |
| 397 | #define BUS_OVERRIDES_CALLBACK_KEY 0x5002\r | |
| 398 | #define MEMORY_CFG_CALLBACK_KEY 0x5003\r | |
| 399 | #define PERFORMANCE_STATUS_CALLBACK_KEY 0x5004\r | |
| 400 | #define MEMORY_RATIO_CALLBACK_KEY 0x5005\r | |
| 401 | #define MEMORY_MODE_CALLBACK_KEY 0x5006\r | |
| 402 | \r | |
| 403 | //\r | |
| 404 | // Security Callback Keys. Do not have to be sequential but have to be unique\r | |
| 405 | //\r | |
| 406 | #define SECURITY_SUPERVISOR_CALLBACK_KEY 0x1000\r | |
| 407 | #define SECURITY_USER_CALLBACK_KEY 0x1001\r | |
| 408 | #define SECURITY_CLEAR_ALL_CALLBACK_KEY 0x1002\r | |
| 409 | #define SECURITY_CLEAR_USER_CALLBACK_KEY 0x1004\r | |
| 410 | #define SECURITY_RESET_AMT_CALLBACK_KEY 0x1008\r | |
| 411 | #define SECURITY_CHANGE_VT_CALLBACK_KEY 0x1010\r | |
| 412 | #define SECURITY_MASTER_HDD_CALLBACK_KEY 0x1020\r | |
| 413 | #define SECURITY_USER_HDD_CALLBACK_KEY 0x1040\r | |
| 414 | \r | |
| 415 | //\r | |
| 416 | // Boot Callback Keys. Do not have to be sequential but have to be unique\r | |
| 417 | //\r | |
| 418 | #define BOOT_HYPERBOOT_CALLBACK_KEY 0x6003\r | |
| 419 | #define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE 0x6004\r | |
| 420 | #define BOOT_HYPERBOOT_CALLBACK_KEY_USB 0x6005\r | |
| 421 | #define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE_USB_OPT 0x6006\r | |
| 422 | \r | |
| 423 | //\r | |
| 424 | // IDCC/Setup FSB Frequency Override Range\r | |
| 425 | //\r | |
| 426 | #define EFI_IDCC_FSB_MIN 133\r | |
| 427 | #define EFI_IDCC_FSB_MAX 240\r | |
| 428 | #define EFI_IDCC_FSB_STEP 1\r | |
| 429 | \r | |
| 430 | //\r | |
| 431 | // Reference voltage\r | |
| 432 | //\r | |
| 433 | #define EFI_REF_DAC_MIN 0\r | |
| 434 | #define EFI_REF_DAC_MAX 255\r | |
| 435 | #define EFI_GTLREF_DEF 170\r | |
| 436 | #define EFI_DDRREF_DEF 128\r | |
| 437 | #define EFI_DIMMREF_DEF 128\r | |
| 438 | \r | |
| 439 | //\r | |
| 440 | // Setup FSB Frequency Override Range\r | |
| 441 | //\r | |
| 442 | #define EFI_FSB_MIN 133\r | |
| 443 | #define EFI_FSB_MAX 240\r | |
| 444 | #define EFI_FSB_STEP 1\r | |
| 445 | #define EFI_FSB_AUTOMATIC 0\r | |
| 446 | #define EFI_FSB_MANUAL 1\r | |
| 447 | #define FSB_FREQ_ENTRY_COUNT ((EFI_FSB_MAX - EFI_FSB_MIN)/EFI_FSB_STEP) + 1\r | |
| 448 | #define FSB_FREQ_ENTRY_TYPE UINT16_TYPE\r | |
| 449 | \r | |
| 450 | //\r | |
| 451 | // Setup processor multiplier range\r | |
| 452 | //\r | |
| 453 | #define EFI_PROC_MULT_MIN 5\r | |
| 454 | #define EFI_PROC_MULT_MAX 40\r | |
| 455 | #define EFI_PROC_MULT_STEP 1\r | |
| 456 | #define EFI_PROC_AUTOMATIC 0\r | |
| 457 | #define EFI_PROC_MANUAL 1\r | |
| 458 | #define PROC_MULT_ENTRY_COUNT ((EFI_PROC_MULT_MAX - EFI_PROC_MULT_MIN)/EFI_PROC_MULT_STEP) + 1\r | |
| 459 | #define PROC_MULT_ENTRY_TYPE UINT8_TYPE\r | |
| 460 | \r | |
| 461 | //\r | |
| 462 | // PCI Express Definitions\r | |
| 463 | //\r | |
| 464 | #define EFI_PCIE_FREQ_DEF 0x0\r | |
| 465 | \r | |
| 466 | #define PCIE_FREQ_ENTRY_TYPE UINT8_TYPE\r | |
| 467 | #define PCIE_FREQ_ENTRY_7 0x7\r | |
| 468 | #define PCIE_FREQ_ENTRY_6 0x6\r | |
| 469 | #define PCIE_FREQ_ENTRY_5 0x5\r | |
| 470 | #define PCIE_FREQ_ENTRY_4 0x4\r | |
| 471 | #define PCIE_FREQ_ENTRY_3 0x3\r | |
| 472 | #define PCIE_FREQ_ENTRY_2 0x2\r | |
| 473 | #define PCIE_FREQ_ENTRY_1 0x1\r | |
| 474 | #define PCIE_FREQ_ENTRY_0 0x0\r | |
| 475 | \r | |
| 476 | #define PCIE_FREQ_TRANSLATION_TABLE_ENTRIES 8\r | |
| 477 | #define PCIE_FREQ_TRANSLATION_TABLE { PCIE_FREQ_ENTRY_0, \\r | |
| 478 | PCIE_FREQ_ENTRY_1, \\r | |
| 479 | PCIE_FREQ_ENTRY_2, \\r | |
| 480 | PCIE_FREQ_ENTRY_3, \\r | |
| 481 | PCIE_FREQ_ENTRY_4, \\r | |
| 482 | PCIE_FREQ_ENTRY_5, \\r | |
| 483 | PCIE_FREQ_ENTRY_6, \\r | |
| 484 | PCIE_FREQ_ENTRY_7 }\r | |
| 485 | \r | |
| 486 | \r | |
| 487 | #define PCIE_FREQ_PRECISION 2\r | |
| 488 | #define PCIE_FREQ_VALUE_7 10924\r | |
| 489 | #define PCIE_FREQ_VALUE_6 10792\r | |
| 490 | #define PCIE_FREQ_VALUE_5 10660\r | |
| 491 | #define PCIE_FREQ_VALUE_4 10528\r | |
| 492 | #define PCIE_FREQ_VALUE_3 10396\r | |
| 493 | #define PCIE_FREQ_VALUE_2 10264\r | |
| 494 | #define PCIE_FREQ_VALUE_1 10132\r | |
| 495 | #define PCIE_FREQ_VALUE_0 10000\r | |
| 496 | \r | |
| 497 | #define PCIE_FREQ_VALUES { PCIE_FREQ_VALUE_0, \\r | |
| 498 | PCIE_FREQ_VALUE_1, \\r | |
| 499 | PCIE_FREQ_VALUE_2, \\r | |
| 500 | PCIE_FREQ_VALUE_3, \\r | |
| 501 | PCIE_FREQ_VALUE_4, \\r | |
| 502 | PCIE_FREQ_VALUE_5, \\r | |
| 503 | PCIE_FREQ_VALUE_6, \\r | |
| 504 | PCIE_FREQ_VALUE_7 }\r | |
| 505 | \r | |
| 506 | //\r | |
| 507 | // Memory Frequency Definitions\r | |
| 508 | //\r | |
| 509 | #define MEMORY_REF_FREQ_ENTRY_DEF 0x08\r | |
| 510 | \r | |
| 511 | #define MEMORY_REF_FREQ_ENTRY_TYPE UINT8_TYPE\r | |
| 512 | #define MEMORY_REF_FREQ_ENTRY_3 0x04\r | |
| 513 | #define MEMORY_REF_FREQ_ENTRY_2 0x00\r | |
| 514 | #define MEMORY_REF_FREQ_ENTRY_1 0x02\r | |
| 515 | #define MEMORY_REF_FREQ_ENTRY_0 0x01\r | |
| 516 | \r | |
| 517 | #define MEMORY_REF_FREQ_TRANSLATION_TABLE_ENTRIES 4\r | |
| 518 | #define MEMORY_REF_FREQ_TRANSLATION_TABLE { MEMORY_REF_FREQ_ENTRY_0, \\r | |
| 519 | MEMORY_REF_FREQ_ENTRY_1, \\r | |
| 520 | MEMORY_REF_FREQ_ENTRY_2, \\r | |
| 521 | MEMORY_REF_FREQ_ENTRY_3 }\r | |
| 522 | \r | |
| 523 | #define MEMORY_REF_FREQ_PRECISION 0\r | |
| 524 | #define MEMORY_REF_FREQ_VALUE_3 333\r | |
| 525 | #define MEMORY_REF_FREQ_VALUE_2 267\r | |
| 526 | #define MEMORY_REF_FREQ_VALUE_1 200\r | |
| 527 | #define MEMORY_REF_FREQ_VALUE_0 133\r | |
| 528 | \r | |
| 529 | #define MEMORY_REF_FREQ_VALUES { MEMORY_REF_FREQ_VALUE_0, \\r | |
| 530 | MEMORY_REF_FREQ_VALUE_1, \\r | |
| 531 | MEMORY_REF_FREQ_VALUE_2, \\r | |
| 532 | MEMORY_REF_FREQ_VALUE_3 }\r | |
| 533 | \r | |
| 534 | \r | |
| 535 | //\r | |
| 536 | // Memory Reference Frequency Definitions\r | |
| 537 | //\r | |
| 538 | \r | |
| 539 | #define MEMORY_FREQ_ENTRY_TYPE UINT8_TYPE\r | |
| 540 | #define MEMORY_FREQ_ENTRY_3 0x4\r | |
| 541 | #define MEMORY_FREQ_ENTRY_2 0x3\r | |
| 542 | #define MEMORY_FREQ_ENTRY_1 0x2\r | |
| 543 | #define MEMORY_FREQ_ENTRY_0 0x1\r | |
| 544 | \r | |
| 545 | #define MEMORY_FREQ_TRANSLATION_TABLE_ENTRIES 4\r | |
| 546 | #define MEMORY_FREQ_TRANSLATION_TABLE { MEMORY_FREQ_ENTRY_0, \\r | |
| 547 | MEMORY_FREQ_ENTRY_1, \\r | |
| 548 | MEMORY_FREQ_ENTRY_2, \\r | |
| 549 | MEMORY_FREQ_ENTRY_3 }\r | |
| 550 | \r | |
| 551 | \r | |
| 552 | #define MEMORY_FREQ_MULT_PRECISION 2\r | |
| 553 | #define MEMORY_FREQ_MULT_333MHZ_VALUE_3 240\r | |
| 554 | #define MEMORY_FREQ_MULT_333MHZ_VALUE_2 200\r | |
| 555 | #define MEMORY_FREQ_MULT_333MHZ_VALUE_1 160\r | |
| 556 | #define MEMORY_FREQ_MULT_333MHZ_VALUE_0 120\r | |
| 557 | \r | |
| 558 | #define MEMORY_FREQ_MULT_266MHZ_VALUE_3 300\r | |
| 559 | #define MEMORY_FREQ_MULT_266MHZ_VALUE_2 250\r | |
| 560 | #define MEMORY_FREQ_MULT_266MHZ_VALUE_1 200\r | |
| 561 | #define MEMORY_FREQ_MULT_266MHZ_VALUE_0 150\r | |
| 562 | \r | |
| 563 | #define MEMORY_FREQ_MULT_200MHZ_VALUE_3 400\r | |
| 564 | #define MEMORY_FREQ_MULT_200MHZ_VALUE_2 333\r | |
| 565 | #define MEMORY_FREQ_MULT_200MHZ_VALUE_1 267\r | |
| 566 | #define MEMORY_FREQ_MULT_200MHZ_VALUE_0 200\r | |
| 567 | \r | |
| 568 | #define MEMORY_FREQ_MULT_133MHZ_VALUE_3 600\r | |
| 569 | #define MEMORY_FREQ_MULT_133MHZ_VALUE_2 500\r | |
| 570 | #define MEMORY_FREQ_MULT_133MHZ_VALUE_1 400\r | |
| 571 | #define MEMORY_FREQ_MULT_133MHZ_VALUE_0 300\r | |
| 572 | \r | |
| 573 | #define MEMORY_FREQ_MULT_333MHZ_VALUES { MEMORY_FREQ_MULT_333MHZ_VALUE_0, \\r | |
| 574 | MEMORY_FREQ_MULT_333MHZ_VALUE_1, \\r | |
| 575 | MEMORY_FREQ_MULT_333MHZ_VALUE_2, \\r | |
| 576 | MEMORY_FREQ_MULT_333MHZ_VALUE_3 }\r | |
| 577 | \r | |
| 578 | #define MEMORY_FREQ_MULT_266MHZ_VALUES { MEMORY_FREQ_MULT_266MHZ_VALUE_0, \\r | |
| 579 | MEMORY_FREQ_MULT_266MHZ_VALUE_1, \\r | |
| 580 | MEMORY_FREQ_MULT_266MHZ_VALUE_2, \\r | |
| 581 | MEMORY_FREQ_MULT_266MHZ_VALUE_3 }\r | |
| 582 | \r | |
| 583 | #define MEMORY_FREQ_MULT_200MHZ_VALUES { MEMORY_FREQ_MULT_200MHZ_VALUE_0, \\r | |
| 584 | MEMORY_FREQ_MULT_200MHZ_VALUE_1, \\r | |
| 585 | MEMORY_FREQ_MULT_200MHZ_VALUE_2, \\r | |
| 586 | MEMORY_FREQ_MULT_200MHZ_VALUE_3 }\r | |
| 587 | \r | |
| 588 | #define MEMORY_FREQ_MULT_133MHZ_VALUES { MEMORY_FREQ_MULT_133MHZ_VALUE_0, \\r | |
| 589 | MEMORY_FREQ_MULT_133MHZ_VALUE_1, \\r | |
| 590 | MEMORY_FREQ_MULT_133MHZ_VALUE_2, \\r | |
| 591 | MEMORY_FREQ_MULT_133MHZ_VALUE_3 }\r | |
| 592 | \r | |
| 593 | //\r | |
| 594 | // CAS Memory Timing Definitions\r | |
| 595 | //\r | |
| 596 | \r | |
| 597 | #define MEMORY_TCL_ENTRY_TYPE UINT8_TYPE\r | |
| 598 | #define MEMORY_TCL_ENTRY_3 0x2\r | |
| 599 | #define MEMORY_TCL_ENTRY_2 0x1\r | |
| 600 | #define MEMORY_TCL_ENTRY_1 0x0\r | |
| 601 | #define MEMORY_TCL_ENTRY_0 0x3\r | |
| 602 | \r | |
| 603 | #define MEMORY_TCL_TRANSLATION_TABLE_ENTRIES 4\r | |
| 604 | #define MEMORY_TCL_TRANSLATION_TABLE { MEMORY_TCL_ENTRY_0, \\r | |
| 605 | MEMORY_TCL_ENTRY_1, \\r | |
| 606 | MEMORY_TCL_ENTRY_2, \\r | |
| 607 | MEMORY_TCL_ENTRY_3 }\r | |
| 608 | \r | |
| 609 | \r | |
| 610 | #define MEMORY_TCL_PRECISION 0\r | |
| 611 | #define MEMORY_TCL_VALUE_3 3\r | |
| 612 | #define MEMORY_TCL_VALUE_2 4\r | |
| 613 | #define MEMORY_TCL_VALUE_1 5\r | |
| 614 | #define MEMORY_TCL_VALUE_0 6\r | |
| 615 | \r | |
| 616 | #define MEMORY_TCL_VALUES { MEMORY_TCL_VALUE_0, \\r | |
| 617 | MEMORY_TCL_VALUE_1, \\r | |
| 618 | MEMORY_TCL_VALUE_2, \\r | |
| 619 | MEMORY_TCL_VALUE_3 }\r | |
| 620 | \r | |
| 621 | \r | |
| 622 | //\r | |
| 623 | // TRCD Memory Timing Definitions\r | |
| 624 | //\r | |
| 625 | \r | |
| 626 | #define MEMORY_TRCD_ENTRY_TYPE UINT8_TYPE\r | |
| 627 | #define MEMORY_TRCD_ENTRY_3 0x0\r | |
| 628 | #define MEMORY_TRCD_ENTRY_2 0x1\r | |
| 629 | #define MEMORY_TRCD_ENTRY_1 0x2\r | |
| 630 | #define MEMORY_TRCD_ENTRY_0 0x3\r | |
| 631 | \r | |
| 632 | #define MEMORY_TRCD_TRANSLATION_TABLE_ENTRIES 4\r | |
| 633 | #define MEMORY_TRCD_TRANSLATION_TABLE { MEMORY_TRCD_ENTRY_0, \\r | |
| 634 | MEMORY_TRCD_ENTRY_1, \\r | |
| 635 | MEMORY_TRCD_ENTRY_2, \\r | |
| 636 | MEMORY_TRCD_ENTRY_3 }\r | |
| 637 | \r | |
| 638 | \r | |
| 639 | #define MEMORY_TRCD_PRECISION 0\r | |
| 640 | #define MEMORY_TRCD_VALUE_3 2\r | |
| 641 | #define MEMORY_TRCD_VALUE_2 3\r | |
| 642 | #define MEMORY_TRCD_VALUE_1 4\r | |
| 643 | #define MEMORY_TRCD_VALUE_0 5\r | |
| 644 | \r | |
| 645 | #define MEMORY_TRCD_VALUES { MEMORY_TRCD_VALUE_0, \\r | |
| 646 | MEMORY_TRCD_VALUE_1, \\r | |
| 647 | MEMORY_TRCD_VALUE_2, \\r | |
| 648 | MEMORY_TRCD_VALUE_3 }\r | |
| 649 | \r | |
| 650 | \r | |
| 651 | //\r | |
| 652 | // TRP Memory Timing Definitions\r | |
| 653 | //\r | |
| 654 | \r | |
| 655 | #define MEMORY_TRP_ENTRY_TYPE UINT8_TYPE\r | |
| 656 | #define MEMORY_TRP_ENTRY_3 0x0\r | |
| 657 | #define MEMORY_TRP_ENTRY_2 0x1\r | |
| 658 | #define MEMORY_TRP_ENTRY_1 0x2\r | |
| 659 | #define MEMORY_TRP_ENTRY_0 0x3\r | |
| 660 | \r | |
| 661 | #define MEMORY_TRP_TRANSLATION_TABLE_ENTRIES 4\r | |
| 662 | #define MEMORY_TRP_TRANSLATION_TABLE { MEMORY_TRP_ENTRY_0, \\r | |
| 663 | MEMORY_TRP_ENTRY_1, \\r | |
| 664 | MEMORY_TRP_ENTRY_2, \\r | |
| 665 | MEMORY_TRP_ENTRY_3 }\r | |
| 666 | \r | |
| 667 | \r | |
| 668 | #define MEMORY_TRP_PRECISION 0\r | |
| 669 | #define MEMORY_TRP_VALUE_3 2\r | |
| 670 | #define MEMORY_TRP_VALUE_2 3\r | |
| 671 | #define MEMORY_TRP_VALUE_1 4\r | |
| 672 | #define MEMORY_TRP_VALUE_0 5\r | |
| 673 | \r | |
| 674 | #define MEMORY_TRP_VALUES { MEMORY_TRP_VALUE_0, \\r | |
| 675 | MEMORY_TRP_VALUE_1, \\r | |
| 676 | MEMORY_TRP_VALUE_2, \\r | |
| 677 | MEMORY_TRP_VALUE_3 }\r | |
| 678 | \r | |
| 679 | \r | |
| 680 | //\r | |
| 681 | // TRAS Memory Timing Definitions\r | |
| 682 | //\r | |
| 683 | #define MEMORY_TRAS_MIN 4\r | |
| 684 | #define MEMORY_TRAS_MAX 18\r | |
| 685 | #define MEMORY_TRAS_STEP 1\r | |
| 686 | #define MEMORY_TRAS_DEFAULT 13\r | |
| 687 | #define MEMORY_TRAS_COUNT ((MEMORY_TRAS_MAX - MEMORY_TRAS_MIN)/MEMORY_TRAS_STEP) + 1\r | |
| 688 | #define MEMORY_TRAS_TYPE UINT8_TYPE\r | |
| 689 | \r | |
| 690 | //\r | |
| 691 | // Uncore Multiplier Definitions\r | |
| 692 | //\r | |
| 693 | #define UCLK_RATIO_MIN 12\r | |
| 694 | #define UCLK_RATIO_MAX 30\r | |
| 695 | #define UCLK_RATIO_DEFAULT 20\r | |
| 696 | \r | |
| 697 | #endif // #ifndef _CONFIGURATION_H\r |