Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to

[mirror_edk2.git] / Vlv2TbltDevicePkg / PlatformDxe / IchTcoReset.c

/** @file\r
\r
  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
                                                                                   \r\r
  This program and the accompanying materials are licensed and made available under\r\r
  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
  The full text of the license may be found at                                     \r\r
  http://opensource.org/licenses/bsd-license.php.                                  \r\r
                                                                                   \r\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
                                                                                   \r\r
\r
Module Name:\r
\r
\r
  IchTcoReset.c\r
\r
Abstract:\r
  Implements the programming of events in TCO Reset\r
\r
\r
--*/\r
\r
#include "PlatformDxe.h"\r
#include <Protocol/TcoReset.h>\r
#include <Protocol/HwWatchdogTimer.h>\r
\r
\r
EFI_STATUS\r
EFIAPI\r
EnableTcoReset (\r
  IN      UINT32            *RcrbGcsSaveValue\r
  );\r
  \r
EFI_STATUS\r
EFIAPI\r
DisableTcoReset (\r
  OUT     UINT32    RcrbGcsRestoreValue\r
  );\r
\r
EFI_TCO_RESET_PROTOCOL  mTcoResetProtocol = {\r
  EnableTcoReset,\r
  DisableTcoReset\r
};\r
\r
/**\r
\r
  Enables the TCO timer to reset the system in case of a system hang.  This is\r
  used when writing the clock registers.\r
\r
  @param RcrbGcsSaveValue   This is the value of the RCRB GCS register before it is\r
                            changed by this procedure.  This will be used to restore\r
                            the settings of this register in PpiDisableTcoReset.\r
\r
  @retval  EFI_STATUS\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
EnableTcoReset (\r
  IN      UINT32            *RcrbGcsSaveValue\r
  )\r
{\r
  UINT16          TmpWord;\r
  UINT16          AcpiBase;\r
  EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL  *WatchdogTimerProtocol;\r
  EFI_STATUS          Status;\r
  UINTN           PbtnDisableInterval = 4;  //Default value\r
\r
  //\r
  // Get Watchdog Timer protocol.\r
  //\r
  Status = gBS->LocateProtocol (\r
                  &gEfiWatchdogTimerDriverProtocolGuid,\r
                  NULL,\r
                  (VOID **)&WatchdogTimerProtocol\r
                  );\r
\r
  //\r
  // If the protocol is present, shut off the Timer as we enter BDS\r
  //\r
  if (!EFI_ERROR(Status)) {\r
    WatchdogTimerProtocol->RestartWatchdogTimer();\r
    WatchdogTimerProtocol->AllowKnownReset(TRUE);\r
  }\r
\r
  if (*RcrbGcsSaveValue == 0) {\r
    PbtnDisableInterval = PcdGet32(PcdPBTNDisableInterval);\r
  } else {\r
    PbtnDisableInterval = *RcrbGcsSaveValue * 10 / 6;\r
  }\r
\r
  //\r
  // Read ACPI Base Address\r
  //\r
  AcpiBase = PchLpcPciCfg16(R_PCH_LPC_ACPI_BASE) & B_PCH_LPC_ACPI_BASE_BAR;\r
\r
  //\r
  // Stop TCO if not already stopped\r
  //\r
  TmpWord = IoRead16(AcpiBase + R_PCH_TCO_CNT);\r
  TmpWord |= B_PCH_TCO_CNT_TMR_HLT;\r
  IoWrite16(AcpiBase + R_PCH_TCO_CNT, TmpWord);\r
\r
  //\r
  // Clear second TCO status\r
  //\r
  IoWrite32(AcpiBase + R_PCH_TCO_STS, B_PCH_TCO_STS_SECOND_TO);\r
\r
  //\r
  // Enable reboot on TCO timeout\r
  //\r
  *RcrbGcsSaveValue = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG);\r
  MmioAnd8 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG, (UINT8) ~B_PCH_PMC_PM_CFG_NO_REBOOT);\r
\r
  //\r
  // Set TCO reload value (interval *.6s)\r
  //\r
  IoWrite32(AcpiBase + R_PCH_TCO_TMR, (UINT32)(PbtnDisableInterval<<16));\r
\r
  //\r
  // Force TCO to load new value\r
  //\r
  IoWrite8(AcpiBase + R_PCH_TCO_RLD, 4);\r
\r
  //\r
  // Clear second TCO status\r
  //\r
  IoWrite32(AcpiBase + R_PCH_TCO_STS, B_PCH_TCO_STS_SECOND_TO);\r
\r
  //\r
  // Start TCO timer running\r
  //\r
  TmpWord = IoRead16(AcpiBase + R_PCH_TCO_CNT);\r
  TmpWord &= ~(B_PCH_TCO_CNT_TMR_HLT);\r
  IoWrite16(AcpiBase + R_PCH_TCO_CNT, TmpWord);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Disables the TCO timer.  This is used after writing the clock registers.\r
\r
  @param RcrbGcsRestoreValue   Value saved in PpiEnableTcoReset so that it can\r
                               restored.\r
\r
  @retval EFI_STATUS\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
DisableTcoReset (\r
  OUT     UINT32    RcrbGcsRestoreValue\r
  )\r
{\r
  UINT16          TmpWord;\r
  UINT16          AcpiBase;\r
  EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL  *WatchdogTimerProtocol;\r
  EFI_STATUS          Status;\r
\r
  //\r
  // Read ACPI Base Address\r
  //\r
  AcpiBase = PchLpcPciCfg16(R_PCH_LPC_ACPI_BASE) & B_PCH_LPC_ACPI_BASE_BAR;\r
\r
  //\r
  // Stop the TCO timer\r
  //\r
  TmpWord = IoRead16(AcpiBase + R_PCH_TCO_CNT);\r
  TmpWord |= B_PCH_TCO_CNT_TMR_HLT;\r
  IoWrite16(AcpiBase + R_PCH_TCO_CNT, TmpWord);\r
\r
  //\r
  // Get Watchdog Timer protocol.\r
  //\r
  Status = gBS->LocateProtocol (\r
                  &gEfiWatchdogTimerDriverProtocolGuid,\r
                  NULL,\r
                  (VOID **)&WatchdogTimerProtocol\r
                  );\r
\r
  //\r
  // If the protocol is present, shut off the Timer as we enter BDS\r
  //\r
  if (!EFI_ERROR(Status)) {\r
    WatchdogTimerProtocol->AllowKnownReset(FALSE);\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
\r
  Updates the feature policies according to the setup variable.\r
\r
  @retval Returns   VOID\r
\r
**/\r
VOID\r
InitTcoReset (\r
  )\r
{\r
  EFI_HANDLE                        Handle;\r
  EFI_STATUS                        Status;\r
\r
  Handle = NULL;\r
  Status = gBS->InstallProtocolInterface (\r
                  &Handle,\r
                  &gEfiTcoResetProtocolGuid,\r
                  EFI_NATIVE_INTERFACE,\r
                  &mTcoResetProtocol\r
                  );\r
  ASSERT_EFI_ERROR(Status);\r
\r
}\r