Add code to protect the whole BIOS region on SPI flash, except UEFI Variable region.

[mirror_edk2.git] / Vlv2TbltDevicePkg / PlatformDxe / PlatformDxe.inf

#/*++\r
#\r
#  Copyright (c)  1999  - 2015, Intel Corporation. All rights reserved\r
#                                                                                  \r
# This program and the accompanying materials are licensed and made available under\r
# the terms and conditions of the BSD License that accompanies this distribution.  \r
# The full text of the license may be found at                                     \r
# http://opensource.org/licenses/bsd-license.php.                                  \r
#                                                                                  \r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r
#                                                                                  \r
#\r
#  Module Name:\r
#\r
#    PlatformBB.inf\r
#\r
#  Abstract:\r
#\r
#    Component description file for platform DXE driver\r
#  ------------------------------------------------------------------------------\r
#  Rev   Date<MM/DD/YYYY>    Name    Description\r
#  ------------------------------------------------------------------------------\r
#  R01     <04/22/2011>       LB     Update code for SIO83627UHG support.\r
#  ------------------------------------------------------------------------------\r
#\r
#--*/\r
\r
[defines]\r
  INF_VERSION                    = 0x00010005\r
  BASE_NAME                      = PlatformDxe\r
  FILE_GUID                      = 056E7324-A718-465b-9A84-228F06642B4F\r
  MODULE_TYPE                    = DXE_DRIVER\r
  VERSION_STRING                 = 1.0\r
  PI_SPECIFICATION_VERSION       = 0x0001000A\r
  ENTRY_POINT                    = InitializePlatform\r
\r
[sources.common]\r
  BoardId.c\r
  BoardIdDecode.c\r
  ClockControl.c\r
  Platform.c\r
  IchRegTable.c\r
  IdccInfo.c\r
  SioPlatformPolicy.c\r
  IchPlatformPolicy.c\r
  PciDevice.c\r
  SlotConfig.c\r
  IchTcoReset.c\r
  SensorVar.c\r
  LegacySpeaker.c\r
  Observable/Observable.c\r
  ExI.c\r
  Rtc.c\r
\r
[Packages]\r
  MdePkg/MdePkg.dec\r
  MdeModulePkg/MdeModulePkg.dec\r
  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
  IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
  Vlv2TbltDevicePkg/PlatformPkg.dec\r
  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
  SecurityPkg/SecurityPkg.dec\r
  CryptoPkg/CryptoPkg.dec\r
  IntelFspWrapperPkg/IntelFspWrapperPkg.dec\r
\r
[LibraryClasses]\r
  BaseLib\r
  BaseMemoryLib\r
  MemoryAllocationLib\r
  UefiBootServicesTableLib\r
  UefiDriverEntryPoint\r
  UefiRuntimeServicesTableLib\r
  DxeServicesTableLib\r
  PchPlatformLib\r
\r
  DebugLib\r
  HiiLib\r
  PrintLib\r
  UefiLib\r
  S3BootScriptLib\r
  ReportStatusCodeLib\r
  EfiRegTableLib\r
  BiosIdLib\r
  BaseCryptLib\r
\r
[Guids]\r
  gEfiBiosIdGuid\r
  gEfiPlatformBootModeGuid\r
  gEfiBoardFeaturesGuid\r
  gItkDataVarGuid\r
  gDmiDataGuid\r
  gIdccDataHubGuid\r
  gEfiPciLanInfoGuid\r
  gEfiNormalSetupGuid\r
  gEfiGlobalVariableGuid\r
  gEfiEventExitBootServicesGuid\r
  gEfiVlv2VariableGuid\r
  gEfiSecureBootEnableDisableGuid\r
\r
[Protocols]\r
  gEfiPciRootBridgeIoProtocolGuid    # CONSUMES  ## GUID\r
  gEfiVariableArchProtocolGuid\r
  gEfiVariableWriteArchProtocolGuid\r
  gEfiHiiConfigAccessProtocolGuid\r
  gEfiBootScriptSaveProtocolGuid\r
  gEfiCpuIoProtocolGuid\r
  gEfiDevicePathProtocolGuid\r
  gEfiDiskInfoProtocolGuid\r
  gEfiPs2PolicyProtocolGuid\r
  gEfiIsaAcpiProtocolGuid\r
  gEfiDataHubProtocolGuid\r
  gEfiPciIoProtocolGuid\r
  gDxePchPlatformPolicyProtocolGuid\r
  gEfiTpmMpDriverProtocolGuid\r
  gEfiLpcWpce791PolicyProtocolGuid\r
  gUsbPolicyGuid\r
  gEfiSpeakerInterfaceProtocolGuid\r
  gDxeVlvPlatformPolicyGuid\r
  gEfiSmbiosSlotPopulationGuid\r
  gObservableProtocolGuid\r
  gEfiCk505ClockPlatformInfoGuid\r
  gEfiLpcWpc83627PolicyProtocolGuid\r
  gEfiTcoResetProtocolGuid\r
  gEfiWatchdogTimerDriverProtocolGuid\r
  gEfiPlatformIdeInitProtocolGuid\r
  gEfiGlobalNvsAreaProtocolGuid\r
  gEfiCpuIo2ProtocolGuid\r
  gIgdOpRegionProtocolGuid\r
  gExitPmAuthProtocolGuid\r
\r
[Pcd.common]\r
  gPlatformModuleTokenSpaceGuid.PcdPBTNDisableInterval\r
  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
  gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress\r
  gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress\r
  gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeSize\r
  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection\r
  gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase\r
  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase\r
  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize\r
  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase\r
  \r
\r
[Depex]\r
  gEfiPciRootBridgeIoProtocolGuid     AND\r
  gEfiVariableArchProtocolGuid        AND\r
  gEfiVariableWriteArchProtocolGuid   AND\r
  gEfiBootScriptSaveProtocolGuid      AND\r
  gEfiCpuIoProtocolGuid               AND\r
  gDxePchPlatformPolicyProtocolGuid   AND\r
  gEfiGlobalNvsAreaProtocolGuid\r
\r
\r